CN101604248A - A kind of embedded system and its implementation of revising program in the ROM (read-only memory) - Google Patents
A kind of embedded system and its implementation of revising program in the ROM (read-only memory) Download PDFInfo
- Publication number
- CN101604248A CN101604248A CNA2009100890055A CN200910089005A CN101604248A CN 101604248 A CN101604248 A CN 101604248A CN A2009100890055 A CNA2009100890055 A CN A2009100890055A CN 200910089005 A CN200910089005 A CN 200910089005A CN 101604248 A CN101604248 A CN 101604248A
- Authority
- CN
- China
- Prior art keywords
- rom
- program
- address
- otp
- embedded system
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Stored Programmes (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The present invention relates to embedded system, relate in particular to embedded system and its implementation of a kind of modified R OM program.This embedded system comprises processor, ROM, OTP, supervisory circuit, alternative controller etc.Main body of the present invention adopts the ROM storage, and adopt OTP that erroneous procedures among the ROM is revised, and OTP and ROM shared address line, and by the address on this address wire of monitor circuit monitors, the instruction that the alternative controller selects program among the ROM or selection to jump to OTP according to the control of this address that monitors.System and method of the present invention has solved the problem that embedded system chip ROM can not revise, and has saved cost when reducing the embedded system chip risk, therefore has important use and is worth.
Description
Technical field
The present invention relates to embedded system, relate in particular to the ROM (read-only memory) in the embedded system.
Background technology
Embedded system is a kind of controlled device dedicated computer system inner and that design for application-specific that is embedded into, it is characterized by that system kernel is little, specificity is strong, software solid-state storage etc., is widely used in each field such as home intelligent management, information household appliances, traffic administration, Industry Control, POS network and ecommerce.
The core of embedded system parts are embedded microprocessor (Micro Processor Unit, MPU) or embedded microcontroller (Microcontroller Unit, MCU) or the DSP embedded processor (Embedded Digital Signal Processor, EDSP).MPU, MCU, EDSP are operated in in the designed system of particular group, and it is integrated in chip internal with many being finished by integrated circuit board of tasks in the universal cpu, thereby make system design be tending towards miniaturization and have higher efficient and reliability.
Embedded system mainly contains three kinds of storage meanss at present, be respectively and utilize special external chip to store, utilize interior One Time Programmable (the one time programmable of master chip, hereinafter to be referred as OTP) module stores, utilizes the ROM (read-only memory) (Read Only Memory is hereinafter to be referred as ROM) in the master chip to store.
The method of utilizing special external chip to store is applicable to the embedded system that procedure quantity is bigger, is characterized in flexibly, easily changes, and cost is lower when procedure quantity is big, if but the less cost of procedure quantity is higher on the contrary.The method of utilizing the OTP module in the master chip to store is the OTP inside that program is written to chip at the production final tache.The method of utilizing the ROM in the master chip to store is in the chip production process program Solidification to be arrived chip internal.
Under the identical situation of capacity, use the cost of the embedded system of ROM to be lower than the embedded system cost that adopts OTP, therefore for the embedded system to the cost requirement strictness, using ROM is better choice.Yet traditional ROM storage mode in the embedded product production run just with program Solidification in ROM, program can not be revised flexibly.If therefore only adopt the ROM mode to store, in case going wrong, program causes throwing again sheet probably, risk is very high.
In sum, in embedded system, only adopt ROM storage meeting to bring risk to embedded product, and only adopting OTP storage can improve the embedded product cost, therefore a kind of embedded system and its implementation with low cost and can modified R OM program have important practical value.
Summary of the invention
The invention provides embedded system and its implementation of the modified R OM program that can overcome the above problems.
In first aspect, the invention provides a kind of embedded system of modified R OM program, this system comprises processor and the ROM that links to each other by address wire with this processor, so that processor is to the ROM write address.This embedded system comprises OTP, supervisory circuit, alternative controller.OTP and ROM shared address line, and this OTP is used to store the ROM program of correction.Supervisory circuit is positioned on the described address wire, is used to monitor the address on this address wire.The address that the alternative controller arrives according to monitor circuit monitors, the instruction that program among the control selection ROM or selection jump to OTP.
In second aspect, the invention provides the method for modified R OM program in a kind of embedded system, wherein this embedded system comprises processor and ROM, processor is to the ROM write address.This method comprises: at first monitor described address contents; Judge then whether this address satisfies trigger condition; When described trigger condition is satisfied in this address, send the instruction that jumps to OTP, and this instruction that jumps to OTP is sent to processor, wherein the ROM program of OTP and ROM shared address line and storage correction; Last processor is carried out corresponding operating according to the data that receive.
Embedded system main body of the present invention adopts the ROM storage, by the OTP storage mode erroneous procedures among the ROM is revised, and system and method for the present invention has been saved cost when reducing the embedded product risk, therefore has important practical value.
Description of drawings
Below with reference to accompanying drawings specific embodiments of the present invention is described in detail, in the accompanying drawings:
Fig. 1 is the embedded system block diagram of modified R OM program;
Fig. 2 is the storage format of supervisory circuit register;
Fig. 3 is the process flow diagram of modified R OM program in the embedded system.
Embodiment
After embedded chip production is finished, system program is cured among the ROM fully, and can not make any modification, and this moment is if mistake appears in some program among the ROM of finding, embedded chip is scrapped possibly, and then brings very big risk for the production of embedded product.The present invention is in order to remedy this kind defective, and the final tache of producing at embedded product is burnt to the revision program of ROM erroneous procedures among the OTP, makes a mistake so that revise the systemic-function that is caused by the ROM erroneous procedures.Described embedded chip such as MP3 chip, embedded product such as MP3.
Fig. 1 is the embedded system block diagram of modified R OM program, and this embedded system comprises processor 110, ROM120, OTP130, supervisory circuit 140, alternative controller 150.Wherein, processor 110 is MPU, MCU or EDSP etc., and especially, native system is fit to use breathe out the not processor of structure more.
ROM120 is used to store the main program of embedded system, and in the embedded chip production run this main program is all solidified.OTP130 is used to store revision program so that the erroneous procedures among the modified R OM, and then finish erroneous procedures among the ROM the function that should finish originally.
The stored program hardware of embedded system is finished jointly by ROM120 and OTP130, and ROM120 and OTP130 use same set of address space, and selects by the high low level in address.For example as the address on the address wire high four to be 1111 be the OTP130 address, otherwise be the ROM120 address.This is finished embedded stored program hardware jointly be called ROM/OTP.Because the modification content of embedded system program is less with respect to total program of embedded system, so OTP130 memory capacity is less with respect to ROM120.
Supervisory circuit 140 is positioned on the address wire of processor 110 and ROM/OTP, be used to monitor the content on this address wire, content on monitoring this address wire transmits control signal when being the address of ROM120 erroneous procedures and jumps to instruction among the OTP, so that processor 110 is no longer carried out the erroneous procedures among the ROM120, and the revision program among the execution OTP130.
Supervisory circuit 140 comprises one group of register, and Fig. 2 is the storage format of supervisory circuit register.The temporary content of this register comprises trigger condition and replacement content, and described trigger condition is the entry address of ROM120 erroneous procedures, and the program of this misaddress correspondence is the erroneous procedures that processor 110 is carried out ROM120.Described replacement content is the entry address that jumps to the corresponding revision program of OTP130, and this instruction comprises the specific address that jumps among the OTP130, and this address obtains in the process by design OTP130 when finding the ROM120 program error.
When trigger condition is satisfied in the address that supervisory circuit 140 monitors, promptly this monitored address be the ROM120 program make mistakes the entry address time, this supervisory circuit 140 transmits control signal and sends the instruction that jumps to OTP130 by data line two.
Alternative controller 150 links to each other with supervisory circuit 140 with data line two by control signal, and links to each other with the ROM/OTP storage organization by data line one, links to each other with processor 110 by data line three.
The address that alternative controller 150 monitors according to supervisory circuit 140, program or selection jump to the instruction of OTP130 among the control selection ROM120.Particularly, alternative controller 150 is when the control signal that receives from supervisory circuit 140, select the instruction among the OTP of jumping in the data line two, otherwise select the ROM program in the data line one, and these data that receive are sent to processor 110 by data line three.
Processor 110 is carried out the program of ROM or the instruction that execution jumps to OTP according to the data content in the data line three.
Need to prove that Fig. 1 just schematically describes address wire and data line, in fact other designs of number of address lines and data line quantity and embedded system are relevant, are not subjected to qualification of the present invention.
Fig. 3 is the process flow diagram of modified R OM program in the embedded system.
In step 310, send in the process of address the address on this processor 110 of supervisory circuit 140 monitoring and the ROM/OTP address wire to ROM/OTP at processor 110.
In step 320, judge whether the address that supervisory circuit 140 monitors satisfies trigger condition, and described trigger condition is the address of ROM120 erroneous procedures.
In step 330, when not satisfying trigger condition in the address that supervisory circuit 140 monitors, the data that alternative controller 150 is selected in the data line one are just selected the program among the ROM/OTP, and this ROM program are sent to processor 110 by data line three.
In step 331, processor receives the ROM/OTP program in the data line three, carries out corresponding operating according to this contents of program.
In step 340, when satisfying trigger condition in the address that supervisory circuit 140 monitors, supervisory circuit 140 transmits control signal and sends the instruction that jumps to OTP by data line two to alternative controller 150.
In step 341, alternative controller 150 receives from this control signal of supervisory circuit 140 and chooses and jumps to the instruction that OTP formulates the position in the data two.
In step 342, this jump instruction that alternative controller 150 will receive is sent to processor 110 by data line three.Described jump instruction comprises the specific address that jumps among the OTP, so that processor 110 can correctly jump to relevant position among the OTP.
In step 343, processor 110 jumps in the corresponding revision program of OTP according to the address of OTP in this jump instruction, thereby begins to carry out the corresponding revision program among the OTP, and then finishes the correction to the ROM erroneous procedures.
Obviously, under the prerequisite that does not depart from true spirit of the present invention and scope, the present invention described here can have many variations.Therefore, the change that all it will be apparent to those skilled in the art that all should be included within the scope that these claims contain.The present invention's scope required for protection is only limited by described claims.
Claims (11)
1. the embedded system of a modified R OM program comprises processor (110) and the ROM (120) that links to each other by address wire with this processor, so that processor (110) is to ROM (120) write address;
It is characterized in that described embedded system comprises OTP (130), supervisory circuit (140), alternative controller (150);
Described OTP (130) and ROM (120) shared address line, and this OTP (130) is used to store ROM (120) program of correction;
Described supervisory circuit (140) is positioned on the described address wire, is used to monitor the address on this address wire;
The address that described alternative controller (150) monitors according to supervisory circuit (140), the instruction that program among the control selection ROM (120) or selection jump to OTP (130).
2. the embedded system of a kind of modified R OM program as claimed in claim 1 is characterized in that, described OTP (130) and described ROM (120) choose by the high low level in address, and OTP (130) memory capacity is less than the memory capacity of ROM (120).
3. the embedded system of a kind of modified R OM program as claimed in claim 1 is characterized in that, described supervisory circuit (140) comprises register, and this register is used to store the instruction of trigger condition and the described OTP of jumping to (130);
Described trigger condition is the entry address of wrong ROM (120) program.
4. the embedded system of a kind of modified R OM program as claimed in claim 3, it is characterized in that, satisfy under the described trigger condition situation address that supervisory circuit (140) monitors, and transmits control signal and jump to the instruction of OTP (130) to alternative controller (150).
5. the embedded system of a kind of modified R OM program as claimed in claim 4 is characterized in that, described alternative controller (150) is selected the described instruction that jumps to OTP (130) after receiving described control signal.
6. the embedded system of a kind of modified R OM program as claimed in claim 1 is characterized in that, described processor (110) is in embedded microprocessor device, embedded microcontroller, the DSP embedded processor.
7. the method for modified R OM program in the embedded system, wherein this embedded system comprises processor (110) and ROM (120), processor is to ROM (120) write address; Described method comprises:
Step 1 is monitored described address contents;
Step 2 judges whether described address satisfies trigger condition;
Step 3 when described trigger condition is satisfied in described address, sends the instruction that jumps to OTP (130), and this instruction that jumps to OTP (130) is sent to processor (110); Wherein, described OTP (130) and ROM (120) shared address line, and ROM (120) program of storage correction;
Step 4, processor (110) is carried out corresponding operating according to the data that receive.
8. the method for modified R OM program is characterized in that in step 2 in a kind of embedded system as claimed in claim 7, when judging that described trigger condition is not satisfied in described address, the program among the ROM (120) is sent to processor (110)
9. the method for modified R OM program is characterized in that in step 3 in a kind of embedded system as claimed in claim 7, judges that described address is satisfied after the trigger condition and transmits control signal when sending the described OTP of jumping to (130) instruction.
10. the method for modified R OM program is characterized in that in a kind of embedded system as claimed in claim 7, and described trigger condition is the entry address of wrong ROM (120) program.
11. the method for modified R OM program is characterized in that in a kind of embedded system as claimed in claim 7, described OTP (130) and described ROM (120) choose by the high low level in address, and OTP (130) memory capacity is less than the memory capacity of ROM (120).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910089005A CN101604248B (en) | 2009-07-20 | 2009-07-20 | Embedded system for correcting programs in read only memory and realization method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910089005A CN101604248B (en) | 2009-07-20 | 2009-07-20 | Embedded system for correcting programs in read only memory and realization method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101604248A true CN101604248A (en) | 2009-12-16 |
| CN101604248B CN101604248B (en) | 2012-09-26 |
Family
ID=41469991
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200910089005A Expired - Fee Related CN101604248B (en) | 2009-07-20 | 2009-07-20 | Embedded system for correcting programs in read only memory and realization method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101604248B (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102129486A (en) * | 2010-10-20 | 2011-07-20 | 杭州晟元芯片技术有限公司 | Novel OTP implementation method |
| CN103927195A (en) * | 2013-12-17 | 2014-07-16 | 记忆科技(深圳)有限公司 | Method for upgrading one time programmable (OTP) chip |
| CN104598408A (en) * | 2015-02-05 | 2015-05-06 | 深圳芯邦科技股份有限公司 | Data burning method of one-time programmable read-only memory (OTP ROM) |
| CN105512560A (en) * | 2015-11-27 | 2016-04-20 | 深圳国微技术有限公司 | Disposable programmable storage chip and control method thereof |
| CN106598660A (en) * | 2016-12-08 | 2017-04-26 | 深圳市博巨兴实业发展有限公司 | Program memory management device used for microcontroller |
| CN107133066A (en) * | 2017-04-01 | 2017-09-05 | 深圳市博巨兴实业发展有限公司 | A kind of storage multiplexed control system in MCU chip |
| CN110058951A (en) * | 2019-04-24 | 2019-07-26 | 核芯互联科技(青岛)有限公司 | A kind of method and apparatus for repairing low volume data mistake inside ROM |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1254129A (en) * | 1998-11-12 | 2000-05-24 | 英业达集团(西安)电子技术有限公司 | Device for safely updating read-only memory and its method |
| JP3750494B2 (en) * | 1999-08-31 | 2006-03-01 | 松下電器産業株式会社 | Semiconductor device |
| JP4404625B2 (en) * | 2003-12-25 | 2010-01-27 | パナソニック株式会社 | Information processing apparatus and ROM image generation apparatus for the apparatus |
| US7594135B2 (en) * | 2003-12-31 | 2009-09-22 | Sandisk Corporation | Flash memory system startup operation |
| CN1920777A (en) * | 2006-09-15 | 2007-02-28 | 中山大学 | System software upgrading method for digital household appliances and updated system |
-
2009
- 2009-07-20 CN CN200910089005A patent/CN101604248B/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102129486A (en) * | 2010-10-20 | 2011-07-20 | 杭州晟元芯片技术有限公司 | Novel OTP implementation method |
| CN103927195A (en) * | 2013-12-17 | 2014-07-16 | 记忆科技(深圳)有限公司 | Method for upgrading one time programmable (OTP) chip |
| CN103927195B (en) * | 2013-12-17 | 2017-10-20 | 记忆科技(深圳)有限公司 | One Time Programmable chip OTP upgrade method |
| CN104598408A (en) * | 2015-02-05 | 2015-05-06 | 深圳芯邦科技股份有限公司 | Data burning method of one-time programmable read-only memory (OTP ROM) |
| CN105512560A (en) * | 2015-11-27 | 2016-04-20 | 深圳国微技术有限公司 | Disposable programmable storage chip and control method thereof |
| CN105512560B (en) * | 2015-11-27 | 2018-11-16 | 深圳国微技术有限公司 | A kind of disposable programmable memory chip and and its control method |
| CN106598660A (en) * | 2016-12-08 | 2017-04-26 | 深圳市博巨兴实业发展有限公司 | Program memory management device used for microcontroller |
| CN107133066A (en) * | 2017-04-01 | 2017-09-05 | 深圳市博巨兴实业发展有限公司 | A kind of storage multiplexed control system in MCU chip |
| CN110058951A (en) * | 2019-04-24 | 2019-07-26 | 核芯互联科技(青岛)有限公司 | A kind of method and apparatus for repairing low volume data mistake inside ROM |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101604248B (en) | 2012-09-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101604248B (en) | Embedded system for correcting programs in read only memory and realization method thereof | |
| US9471435B2 (en) | Information processing device, information processing method, and computer program | |
| CN104461657B (en) | A kind of startup method and device of active and standby boot loader | |
| CN101329632B (en) | Method and apparatus for starting CPU by BOOT | |
| CN102388366B (en) | Method and device for realizing compatibility of different processors | |
| CN101699402B (en) | Multi-mode startup embedded system | |
| CN107704285B (en) | Multi-version configuration chip, system and method for field programmable gate array | |
| CN108228244A (en) | The recognition methods of light rail board and system | |
| CN103116511A (en) | Double-booting method based on single FLASH storage chip | |
| CN105677398A (en) | Universal embedded computer software on-line upgrading method | |
| CN109388526B (en) | Control circuit and reset operation method | |
| US20110302393A1 (en) | Control systems and data processing method | |
| CN107861764A (en) | For the program upgrade system of cooking appliance, method and cooking appliance | |
| CN103530215B (en) | A kind of self checking method of internal integrated circuit main frame, device and main frame | |
| CN104881312A (en) | FPGA (Field Programmable Gate Array) logic code iterable upgrading method and circuit | |
| CN109800032A (en) | BOOTROM multicore loading method and device | |
| JP6175788B2 (en) | Electronic devices that can update microprograms | |
| CN105528314B (en) | A kind of data processing method and control equipment | |
| CN108132899A (en) | A kind of transmission mode configuration method, apparatus and system | |
| CN114691573A (en) | Hardware identification circuit, method and related equipment | |
| CN112328528A (en) | Clock chip compatible method, device and equipment based on Feiteng processor | |
| CN110673894A (en) | Automatic loading method for BOB module ED of home gateway | |
| CN116300780B (en) | Component configuration method, device, electronic equipment and storage medium | |
| CN100449498C (en) | Data storage device | |
| CN110442364A (en) | Processing method, processing system, display device and its electronic equipment of register |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120926 Termination date: 20180720 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |