CN101378259A - Phase selection programmable frequency divider - Google Patents
Phase selection programmable frequency divider Download PDFInfo
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- CN101378259A CN101378259A CNA2007100940534A CN200710094053A CN101378259A CN 101378259 A CN101378259 A CN 101378259A CN A2007100940534 A CNA2007100940534 A CN A2007100940534A CN 200710094053 A CN200710094053 A CN 200710094053A CN 101378259 A CN101378259 A CN 101378259A
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Abstract
The invention discloses a phase selection programmable frequency divider, only an accumulator is needed in a phase selection generating circuit, thus simplifying the producing process of phase selection logic, improving the stability of the whole frequency divider, avoiding the generation of burrs in the phase selection process, and reducing the error possibility of the whole frequency divider; meanwhile, by pre-obtaining four signals working at the actual system working frequency and with the phase difference of 90 degrees, and causing the phase selection generating circuit to output a switching control signal used for controlling the phase selection switching circuit to be switched from the signal of one phase into the signal of another phase under the control of a trigger signal output by the M frequency divider, the frequency dividing value with the minimum value of 0.25 is realized, thus causing reference clock frequency to be improved to be four times of the prior one, namely, the sampling frequency of a Sigma-Delta modulator is improved to be four times of the prior one, thereby effectively reducing the in-band phase noise of a phase-locking loop and improving the entire phase noise of a frequency synthesizer.
Description
Technical field
The present invention relates to a kind of frequency synthesizer, relate in particular to a kind of based on the phase selection programmable frequency divider in the frequency synthesizer of phase-locked loop based on phase-locked loop.
Background technology
As everyone knows, programmable frequency divider is based on one of the component units of the frequency synthesizer of phase-locked loop structures, and frequency synthesizer is widely used in as being used in the receiver and produces local oscillation signal or be used to produce the carrier frequency local oscillation signal in the transmitter the inside.
The fractional divider (fractional-N) that (retiming) control phase was selected when existing programmable frequency divider was mainly minimum frequency division and can only resets for the integer frequency divider (integer-N) of integer and employing, but these two kinds of programmable frequency dividers all exist certain shortcoming.Wherein, adopt the phase-locked loop structures of integral frequency divisioil number to have two potential problems: the first, when selectable reference clock frequency and pll output signal frequency did not exist integral multiple to concern, this phase-locked loop can't use, and just frequency accuracy is very limited; The second, in a lot of the application, adopt the phase-locked loop of integer frequency divider often will choose a very low reference clock frequency, make the loop bandwidth of this class programmable phase-locked loop can not select very greatly, thereby can increase the locking time of phase-locked loop.Compare integer frequency divider, the fractional divider with decimal precision does not just have above-mentioned restriction.Yet the fractional divider that adopts (retiming) control phase selection when resetting can produce such as burr phenomenons such as (glitch) when real work, and too complicated control logic also causes the unstable of whole frequency divider easily or causes logical mistake.
Summary of the invention
Technical problem to be solved by this invention provides a kind of phase selection programmable frequency divider, can simplify the production process that phase place is selected control logic, and can avoid the generation of burr, thereby reduces the probability of makeing mistakes of whole programmable frequency divider; In addition, can also realize the fractional frequency division value, can increase the frequency of reference clock simultaneously, improve the phase noise of frequency synthesizer.
For solving the problems of the technologies described above, the invention provides a kind of phase selection programmable frequency divider, comprising: 2 frequency dividing circuits, phase place selected on-off circuit, M frequency dividing circuit and phase place select to produce circuit;
Described 2 frequency dividing circuits, for having 2 frequency dividing circuits of quadrature output characteristic, the frequency of its input signal is 2 times of system's actual operating frequency, and the signals of its output signal to be 4 phase differences be 90 degree;
Described phase place selected on-off circuit, be used under the control of switch-over control signal Sel_0, the Sel_90, Sel_180 and the Sel_270 that are selected the generation circuit to export by described phase place, described 4 phase differences of selection output are that in 90 signals of spending exports;
Described M frequency dividing circuit is used to receive the output signal fSEL of described phase place selected on-off circuit, and with this signal f
SELCarry out exporting behind the M frequency division, and after whenever finishing M frequency division, control output triggers control signal f
FBSelect to produce circuit for described phase place;
Described phase place is selected to produce circuit, is used at described triggering control signal f
FBControl under, send 0～3 switch-over control signal Sel_0, Sel_90, Sel_180 and Sel_270 to described phase place selected on-off circuit continuously, realize that minimum is 0.25 frequency division value.
The present invention is owing to adopted technique scheme, has such beneficial effect, promptly select to produce and only need an accumulator in the circuit in phase place, thereby simplified the production process of phase place selection logic, improved the stability of whole frequency divider, and avoided the generation of burr in the phase place selection course, greatly reduced the probability that whole frequency divider is made mistakes; Simultaneously, the signal of four phase phasic differences, 90 degree by obtaining being operated in system's actual operating frequency in advance, and allow described phase place select to produce circuit under the control of the triggering signal that the M frequency divider is exported, output is used for the control phase selected on-off circuit and is switched to the switch-over control signal of another phase signal by the signal of a phase place, thereby realized that minimum is 0.25 frequency division value, promptly be equivalent to reference clock frequency has been brought up to original 4 times, the sample frequency that is equivalent to the Sigma-Delta modulator has been brought up to original 4 times, thereby effectively reduce phase noise in the band of phase-locked loop, improved the whole phase noise of frequency synthesizer greatly.
Description of drawings
The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:
Fig. 1 is the structured flowchart of phase selection programmable frequency divider of the present invention;
Fig. 2 is a structured flowchart of selecting to produce circuit according to phase place of the present invention;
Fig. 3 is the sequential logic figure when M is 2 in the M frequency divider according to the present invention.
Embodiment
In one embodiment, as shown in Figure 1, phase selection programmable frequency divider of the present invention comprises that 2 frequency dividing circuits, phase place selected on-off circuit, phase place selection produce circuit and M frequency dividing circuit.
Described 2 frequency dividing circuits are one to have 2 frequency dividing circuits of quadrature output characteristic, and in the present invention, the frequency of the input signal of this 2 frequency dividing circuit is 2 times of system's actual operating frequency, i.e. 2*f
L0, its output signal is that 4 phase differences are the signal f of 90 degree
P0, f
P90, f
P180And f
P270, the general staff of this area should know, these 4 output signal frequency are identical with the system actual operating frequency.
Described phase place selected on-off circuit, be used under the control of switch-over control signal Sel_0, the Sel_90, Sel_180 and the Sel_270 that are selected the generation circuit to export by described phase place, described 4 phase differences of selection output are that in 90 signals of spending exports.In the embodiment shown in fig. 1, when Sel_0 was 1, this phase place selected on-off circuit was selected the signal f of output
SELBe f
P0When Sel_90 is 1, the signal f of the selection of this phase place selected on-off circuit output
SELBe f
P90When Sel_180 was 1, this phase place selected on-off circuit was selected the signal f of output
SELBe f
P180When Sel_270 was 1, this phase place selected on-off circuit was selected the signal f of output
SELBe f
P270
Described M frequency dividing circuit receives the output signal f of described phase place selected on-off circuit
SEL, and with this signal f
SELCarry out output signal f behind the M frequency division
PFD, and at signal f
SELWhenever after finishing M frequency division, all can control one of output and trigger control signal f
FBSelect to produce circuit for described phase place, switch to start phase place.Wherein M can be arbitrarily more than or equal to 2 integer.
Described phase place is selected to produce circuit, is used at described triggering control signal f
FBControl under, send 0～3 switch-over control signal Sel_0, Sel_90, Sel_180 and Sel_270 to described phase place selected on-off circuit continuously, be 0.25 frequency division value to realize minimum.Wherein, among switch-over control signal Sel_0, Sel_90, Sel_180 and the Sel_270 that at every turn sends, the value of having only a signal is 1.As shown in Figure 2, this described phase place selects the generation circuit to comprise: delay circuit, 2 bit accumulators and decoding circuit.Described delay circuit is used for receiving triggering control signal f
FBThe time, produce 0～3 delay pulse, promptly be equivalent to produce 0～3 and trigger clock, thereby determined receiving triggering control signal f at every turn to described 2 bit accumulators
FBThe time, the accumulative frequency of described 2 bit accumulators (0,1,2 or 3 time).In the present embodiment, the number of described delay pulse can be provided with by postponing signalization according to actual operating position.Described 2 bit accumulators are used under the control of described delay circuit output signal, whenever receive a delay pulse, promptly add 1 accumulation calculating forward, then 2 accumulation result are exported to described decoding circuit.In the present embodiment, the initial value of described 2 bit accumulators can be provided with by the initial setting up position.Described decoding circuit is used for its received described 2 cumulative signals are decoded into 4 switch-over control signal Sel_0, Sel_90, Sel_180 and Sel_270.In the present invention, owing to only need in the generation circuit to select one 2 bit accumulator in this phase place, and whenever this 2 bit accumulator whenever adds forward at 1 o'clock, phase place is selected just to carry out once, choose next 1/4 signal that postpones, constantly move in circles then, therefore this simple logic has been simplified complexity and the difficulty that phase selection programmable frequency divider of the present invention is realized greatly, thereby has increased its stability and reliability.
According to top description, one of ordinary skill in the art should be understood that in phase selection programmable frequency divider of the present invention, the output signal (f of described phase place selected on-off circuit
SEL) period ratio do not carry out many at least 1/4 cycles of signal before phase place is selected, after promptly being equivalent to select through a phase place, signal f
SELFrequency reduced 0.25 with respect to the operating frequency of system's reality.This signal f
SELBy pre-removing, just can realize the function of (M+0.25) again to behind the frequency divider of M.And whenever receive a triggering control signal f by being controlled at
FBThe time, control is to the accumulative frequency of 2 bit accumulators in the described phase place selection generation circuit, and (frequency is f in a long period
PFD) can realize 0～3 phase place selection output, therefore just can realize that frequency is the frequency programmable dividing function of M, M+0.25, M+2 * 0.25 and M+3 * 0.25.Description according to preamble, because phase selection programmable frequency division of the present invention has realized that minimum is 0.25 frequency division value, this precision for the frequency divider that the frequency division precision is integer has improved 4 times, this is equivalent to reference clock frequency has been brought up to original 4 times, the sample frequency that is equivalent to the Sigma-Delta modulator has been brought up to original 4 times, thereby effectively reduce phase noise in the band of phase-locked loop, improved the whole phase noise of frequency synthesizer.
In order to be illustrated more clearly in above-mentioned principle, by application example shown in Figure 3, illustrate when the M frequency divider is 2 frequency dividers, the sequential logic of each coherent signal, the signal change procedure in the time of can being clear that by this figure programmable frequency divider of the present invention is realized the branch yupin effect of M+0.25 and M+2 * 0.25.
Claims (3)
1, a kind of phase selection programmable frequency divider is characterized in that, comprising: 2 frequency dividing circuits, phase place selected on-off circuit, M frequency dividing circuit and phase place select to produce circuit;
Described 2 frequency dividing circuits, for having 2 frequency dividing circuits of quadrature output characteristic, the frequency of its input signal is 2 times of system's actual operating frequency, and the signals of its output signal to be 4 phase differences be 90 degree;
Described phase place selected on-off circuit, be used under the control of switch-over control signal Sel_0, the Sel_90, Sel_180 and the Sel_270 that are selected the generation circuit to export by described phase place, described 4 phase differences of selection output are that in 90 signals of spending exports;
Described M frequency dividing circuit is used to receive the output signal f of described phase place selected on-off circuit
SEL, and with this signal f
SELCarry out exporting behind the M frequency division, and after whenever finishing M frequency division, control output triggers control signal f
FBSelect to produce circuit for described phase place;
Described phase place is selected to produce circuit, is used at described triggering control signal f
FBControl under, send 0～3 switch-over control signal Sel_0, Sel_90, Sel_180 and Sel_270 to described phase place selected on-off circuit continuously, realize that minimum is 0.25 frequency division value.
2, phase selection programmable frequency divider according to claim 1 is characterized in that, described phase place is selected to produce circuit and comprised: delay circuit, 2 bit accumulators and decoding circuit;
Described delay circuit is used for receiving triggering control signal f
FBThe time, realize 0～3 delay pulse;
Described 2 bit accumulators are used for whenever receiving a delay pulse under the control of described delay circuit output signal, promptly add 1 accumulation calculating forward, then 2 accumulation result are exported to described decoding circuit;
Described decoding circuit is used for its received described 2 cumulative signals are decoded into 4 switch-over control signal Sel_0, Sel_90, Sel_180 and Sel_270.
3, phase selection programmable frequency divider according to claim 1 and 2 is characterized in that, the M in the described M frequency dividing circuit can be arbitrarily more than or equal to 2 integer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007100940534A CN101378259A (en) | 2007-08-31 | 2007-08-31 | Phase selection programmable frequency divider |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007100940534A CN101378259A (en) | 2007-08-31 | 2007-08-31 | Phase selection programmable frequency divider |
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| CN101378259A true CN101378259A (en) | 2009-03-04 |
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102811038A (en) * | 2011-06-03 | 2012-12-05 | 瑞鼎科技股份有限公司 | Non-integer frequency clock pulse generating circuit and method thereof |
| CN103098377A (en) * | 2010-07-29 | 2013-05-08 | 马维尔国际贸易有限公司 | Modular frequency divider and mixer configuration |
| CN104363015A (en) * | 2014-10-08 | 2015-02-18 | 四川和芯微电子股份有限公司 | Fractional frequency divider circuit |
| CN105811967A (en) * | 2014-12-31 | 2016-07-27 | 北京华大九天软件有限公司 | Circuit for generating fractional frequency-division clock based on HDMI standard |
| CN105915216A (en) * | 2016-04-06 | 2016-08-31 | 上海交通大学 | Medium high frequency multi-mode frequency dividing ratio adjustable LO fractional divider |
| CN107005230A (en) * | 2014-12-09 | 2017-08-01 | 高通股份有限公司 | Apparatus and method for giving birth to the reference clock that quadruples from single-ended crystal oscillator |
| CN107294531A (en) * | 2017-06-21 | 2017-10-24 | 上海兆芯集成电路有限公司 | Phase-locked loop and frequency divider |
| CN108964660A (en) * | 2018-07-19 | 2018-12-07 | 重庆湃芯入微科技有限公司 | A kind of high-resolution low-power consumption spread spectrum control circuit based on phase delay compensation |
| CN113852385A (en) * | 2021-10-20 | 2021-12-28 | 中电科思仪科技股份有限公司 | Method and system for optimizing phase noise of receiver |
| CN114204937A (en) * | 2022-02-16 | 2022-03-18 | 山东兆通微电子有限公司 | Frequency divider circuit and frequency synthesizer |
| WO2024119995A1 (en) * | 2022-12-08 | 2024-06-13 | 晶晨半导体(上海)股份有限公司 | Clock signal noise reduction apparatus, noise reduction method, and multi-phase delay-locked loop |
-
2007
- 2007-08-31 CN CNA2007100940534A patent/CN101378259A/en active Pending
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103098377A (en) * | 2010-07-29 | 2013-05-08 | 马维尔国际贸易有限公司 | Modular frequency divider and mixer configuration |
| CN103098377B (en) * | 2010-07-29 | 2015-08-26 | 马维尔国际贸易有限公司 | Module frequency divider and mixer configuration |
| CN102811038A (en) * | 2011-06-03 | 2012-12-05 | 瑞鼎科技股份有限公司 | Non-integer frequency clock pulse generating circuit and method thereof |
| CN104363015A (en) * | 2014-10-08 | 2015-02-18 | 四川和芯微电子股份有限公司 | Fractional frequency divider circuit |
| CN107005230A (en) * | 2014-12-09 | 2017-08-01 | 高通股份有限公司 | Apparatus and method for giving birth to the reference clock that quadruples from single-ended crystal oscillator |
| CN107005230B (en) * | 2014-12-09 | 2021-03-09 | 高通股份有限公司 | Apparatus and method for generating a quad reference clock from a single-ended crystal oscillator |
| CN105811967A (en) * | 2014-12-31 | 2016-07-27 | 北京华大九天软件有限公司 | Circuit for generating fractional frequency-division clock based on HDMI standard |
| CN105811967B (en) * | 2014-12-31 | 2018-08-07 | 北京华大九天软件有限公司 | Circuit in HDMI standard for generating fractional frequency division clock |
| CN105915216B (en) * | 2016-04-06 | 2019-01-25 | 上海交通大学 | LO decimal frequency divider is adjusted in medium-high frequency multimode frequency dividing ratio |
| CN105915216A (en) * | 2016-04-06 | 2016-08-31 | 上海交通大学 | Medium high frequency multi-mode frequency dividing ratio adjustable LO fractional divider |
| CN107294531A (en) * | 2017-06-21 | 2017-10-24 | 上海兆芯集成电路有限公司 | Phase-locked loop and frequency divider |
| CN107294531B (en) * | 2017-06-21 | 2020-09-11 | 上海兆芯集成电路有限公司 | Phase locked loop and frequency divider |
| CN108964660A (en) * | 2018-07-19 | 2018-12-07 | 重庆湃芯入微科技有限公司 | A kind of high-resolution low-power consumption spread spectrum control circuit based on phase delay compensation |
| CN108964660B (en) * | 2018-07-19 | 2024-02-06 | 重庆湃芯创智微电子有限公司 | High-resolution low-power-consumption spread spectrum control circuit based on phase delay compensation |
| CN113852385A (en) * | 2021-10-20 | 2021-12-28 | 中电科思仪科技股份有限公司 | Method and system for optimizing phase noise of receiver |
| CN114204937A (en) * | 2022-02-16 | 2022-03-18 | 山东兆通微电子有限公司 | Frequency divider circuit and frequency synthesizer |
| WO2024119995A1 (en) * | 2022-12-08 | 2024-06-13 | 晶晨半导体(上海)股份有限公司 | Clock signal noise reduction apparatus, noise reduction method, and multi-phase delay-locked loop |
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Open date: 20090304 |