CN206135882U

CN206135882U - Jump frequency source soon with low stray low phase noise

Info

Publication number: CN206135882U
Application number: CN201621185882.4U
Authority: CN
Inventors: 王瑞耀; 张敬
Original assignee: Hebei Hong Jie Electronic Technology Co Ltd
Current assignee: Hebei Hong Jie Electronic Technology Co Ltd
Priority date: 2016-11-04
Filing date: 2016-11-04
Publication date: 2017-04-26
Anticipated expiration: 2026-11-04

Abstract

The utility model discloses a jump frequency source soon with low stray low phase noise belongs to the communications field, and it includes 2 and above frequency phase lock ring unit and the FPGA controller that is used for controlling each frequency phase lock ring unit, the input of FPGA controller inserts the frequency hopping control code, the output of FPGA controller connects the control input end of each frequency phase lock ring unit, each respectively each period number end of select switch K, warp are connected to the output of frequency phase lock ring unit select switch K's selection end output frequency hopping signal. The utility model has the advantages that when satisfying quick frequency hopping and require, avoided instantaneous system performance appearing and worsening with last trading beginning frequently, just solved when using single frequency phase lock ring unit the shortcoming that locking time is long, be difficult to realize fast frequency agility, the advantage of utilizing frequency phase lock ring unit simultaneously reaches low strayly, low phase noise's frequency hopping output index.

Description

A kind of fast frequency hopping rate source with low spurious Low phase noise

Technical field

This utility model is related to a kind of fast frequency hopping rate source with low spurious Low phase noise, belongs to the communications field, main to apply In frequency-hopping communication system.

Background technology

Frequency hopping communications is a kind of carrier frequency with the communication technology of Hopping frequencies controller pseudorandom saltus step, the technology from See on frequency domain, transmission information frequency band is extended to very wide frequency band range, belong to a branch of spread spectrum technic, with expansion The advantage of frequency communication.Frequency hopping communications is good with its anti-interference, anti-intercepting and capturing ability is strong, good confidentiality the advantages of be widely used in army In various occasions such as thing secret communication, radar and satellite navigation.In frequency hopping communications, Chief technology has two：One be it is pseudo- with The carrier jumping frequency source of machine saltus step；One is the Frequency Hopping Synchronization Techniques for being capable of simultaneous upload wave frequency pseudorandom saltus step, both mutually auxiliary phases Into indispensable.Important component part of the frequency hopping synthesizer as frequency-hopping communication system, so its performance indications is to whole frequency hopping communications It is all which that system has extremely important impact, the low spurious of frequency hopping synthesizer, low phase noise, frequency handover ability of fast and stable etc. Make great efforts the direction of research.The implementation in fast frequency hopping rate source mainly has at present：Based on Direct Digital frequency device DDS methods, it is based on The method that phase-locked loop pll method and DDS+PLL combinations are realized, but this several scheme has respective pluses and minuses：Based on DDS shapes The frequency source hop rate of formula is fast but spuious big, and power consumption is high；Frequency source based on PLL forms is spuious low, and phase noise is low but is difficult to reality Existing fast frequency agility.Therefore need a kind of scheme that frequency source can be made to realize low spurious, low phase noise, altofrequency switching rate Performance indications.

Utility model content

Technical problem to be solved in the utility model there is provided a kind of good stability, frequency conversion and quickly have low spurious The fast frequency hopping rate source of Low phase noise.

The technical solution of the utility model is as follows：

A kind of fast frequency hopping rate source with low spurious Low phase noise, which includes the frequency phase lock ring element of 2 and above quantity With for controlling the FPGA controller of each frequency phase lock ring element；The input of the FPGA controller accesses frequency hopping control Code, the outfan of the FPGA controller connect the control signal of each frequency phase lock ring element respectively, each described frequency locker The outfan of phase ring element connects each section end of selecting switch K, the selection end output frequency hopping letter of selecting switch K described in Jing Number.

Further, the structural parameters of each frequency phase lock ring element are identical and mutually independent.

As each described, frequency phase lock ring element structural parameters are identical and mutually independent, when one it is in running order When, the output signal of the frequency phase lock ring element of another off working state is very easy to be coupled to output as spurious signal On, final output is affected, therefore the isolation between each frequency phase lock ring element is particularly important, further, described in each It is respectively provided between each section end of the outfan of frequency phase lock ring element and selecting switch K and isolates each frequency The switch S of phase locked-loop unit, increased one-level switch, and so final is spuious suppressed.

Further, the loop bandwidth of the frequency phase lock ring element is set as 250K～300K.

The beneficial effects of the utility model are as follows：

Switch switching and the data configuration of each phase locked-loop unit, switching are realized in this utility model using FPGA controller Speed is fast, adopts preset means by FPGA controller, before switching every time, first by the frequency frequency configuration for setting to One of them idle frequency phase lock ring element, the generation of such frequency are realized during another frequency works , i.e., when a frequency phase lock ring element is in running order, another frequency phase lock ring element is prewired to be set to next frequency Point, and be allowed to, in stable lock-out state, so switch repeatedly before next frequency error factor, so meeting fast frequency-hopped While requirement, it is to avoid instantaneous system performance degradation occur in the beginning for changing frequency and finally, just solve using single lock Locking time length during phase ring element, the shortcoming for being difficult to fast frequency agility, while being reached using the advantage of phase locked-loop unit low miscellaneous Dissipate, the frequency hopping output-index of Low phase noise.

Description of the drawings

Fig. 1 is structural principle block diagram of the present utility model.

Fig. 2 is to show this utility model in the phase noise curve chart that output frequency is at 3.3GHz.

Specific embodiment

Fast frequency hopping rate source of the present utility model is described in further detail with reference to Fig. 1.

As shown in figure 1, the present embodiment devises a kind of fast frequency hopping rate source with low spurious Low phase noise, it include 2 and FPGA controller with last frequency phase lock ring element and for controlling each frequency phase lock ring element；The FPGA controller Input accesses frequency hopping control code, and the outfan of the FPGA controller connects the control input of each frequency phase lock ring element respectively End, the outfan of each frequency phase lock ring element connect each section end of selecting switch K, selecting switch K described in Jing Select end output Frequency Hopping Signal.

Further, no matter the number of frequency phase lock ring element is for 2 and with last, each described frequency phase lock ring element Structural parameters it is identical and mutually independent.

As each described, frequency phase lock ring element structural parameters are identical and mutually independent, when one it is in running order When, the output signal of the frequency phase lock ring element of another off working state is very easy to be coupled to output as spurious signal On, final output is affected, therefore the isolation between each frequency phase lock ring element is particularly important, further, described in each It is respectively provided between each section end of the outfan of frequency phase lock ring element and selecting switch K and isolates each frequency The switch S of phase locked-loop unit, increased one-level switch, and so final is spuious suppressed；When frequency phase lock ring element is 2 When, selecting switch K be single-pole double-throw switch (SPDT), respectively with 2, each section end of single-pole double-throw switch (SPDT) frequency locker Increase one-level switch S between the outfan of phase ring element, it is finally spuious to be suppressed in below 70dB, the single-pole double-throw switch (SPDT) Selection end output it is unaffected.

The operation principle of the present embodiment is as follows：

The present embodiment takes the working method of table tennis to be similar to, alternately by 2 or multiple frequency phase lock ring elements frequency Rate puts out to meet fast frequency-hopped requirement, this addresses the problem and is difficult to using locking time length during single frequency phase locked-loop unit The shortcoming of frequency agility is realized, while low spurious, the output-index of Low phase noise are reached using the advantage of frequency phase lock ring element.

By arrange 2 frequency phase lock ring elements the fast frequency hopping rate source with low spurious Low phase noise as a example by illustrate as Under, the fast frequency hopping rate source with low spurious Low phase noise of multiple frequency phase lock ring elements is also suitable.

The FPGA controller receives outside frequency hopping control code and is responsible for the data configuration of 2 frequency phase lock ring elements simultaneously With switch switch operating.

In this fast frequency hopping rate source initial work, FPGA controller is responsible for advance to first frequency phase lock ring element The frequency frequency of f1 has been configured, when it is f1 that exterior arrangement needs this fast frequency hopping rate source output frequency, the FPGA controller and choosing Select switch " K " and play a part of signal shift switch, make the signal output of first frequency phase lock ring element simultaneously close off second The signal output of individual frequency phase lock ring element, makes this fast frequency hopping rate source output frequency for f1, at the same time, the FPGA controller It is responsible for next frequency f2 is pre-configured with second frequency phase lock ring element；Treat that exterior arrangement needs this fast frequency hopping rate source defeated Go out frequency for f2 when, FPGA control switching switch makes the signal output of second frequency phase lock ring element simultaneously close off the The signal output of one frequency phase lock ring element, makes this fast frequency hopping rate source output frequency for f2, at the same time, the FPGA controls Device is responsible for being pre-configured with first frequency phase lock ring element, to complete frequency hopping next time, afterwards next frequency f3 First frequency phase lock ring element and second frequency phase lock ring element this 2 phaselocked loop are repeatedly thus, rate-adaptive pacemaker alternately enters OK.As a result of preset means, the generation of frequency is realized during another frequency works, when a frequency When phase locked-loop unit is in running order, another frequency phase lock ring element is prewired to be set to next frequency, and in lower secondary frequencies It is allowed to before switching in stable lock-out state.

What such first frequency phase lock ring element and second frequency phase lock ring element were constituted similar takes table tennis Export structure be achieved that the function of fast frequency shift, simultaneously because having used switch switching, switching time<200ns, it is to avoid Change the beginning of frequency and instantaneous system performance degradation finally occur.

As a result of bicyclic design, another non-work when a frequency phase lock ring element is in running order The output signal for making the frequency phase lock ring element of state is very easy to be coupled to outfan as spurious signal, affects final defeated Go out, therefore the isolation between two frequency phase lock ring elements is particularly important.In order to increase isolation, in two frequency phase lock ring lists Increased one-level switch S, i.e., a two frequency phase lock ring element between unit and selecting switch K of controlled output again double with hilted broadsword respectively Increased one-level switch S between the double-throw end of throw switch, it is so final spuious to be suppressed in below 70dB.

In order to obtain the locking time of faster single frequency phase locked-loop unit, while phase noise is reduced as far as possible, The loop bandwidth of the frequency phase lock ring element is set to 250K～300K.

Fig. 2 shows that this utility model block jumps phase noise curve chart of the frequency source in output frequency at 3.3GHz.By Figure is visible, and frequency source can reach -105dBc/Hz@1KHz and -110dBc/Hz@10KHz poles when the frequency of 3.3GHz is exported The index of Low phase noise.

Certainly, those skilled in the art in the art are it should be appreciated that above-described embodiment is intended merely to illustrate this reality With new, and it is not used as to restriction of the present utility model, as long as in spirit of the present utility model, to above-mentioned reality Apply change, modification of example etc. will all fall in the range of this utility model claim.

Claims

1. a kind of fast frequency hopping rate source with low spurious Low phase noise, it is characterised in that：Which includes the frequency locker of 2 and above quantity Phase ring element and the FPGA controller for controlling each frequency phase lock ring element；The input of the FPGA controller is accessed jumps Frequency control code, the outfan of the FPGA controller connect the control signal of each frequency phase lock ring element respectively, described in each The outfan of frequency phase lock ring element connects each section end of selecting switch K, and the selection end output of selecting switch K described in Jing is jumped Frequency signal.

2. the fast frequency hopping rate source with low spurious Low phase noise according to claim 1, it is characterised in that：Each described frequency It is respectively provided between each section end of the outfan of phase locked-loop unit and selecting switch K and isolates each frequency phase lock The switch S of ring element.

3. the fast frequency hopping rate source with low spurious Low phase noise according to claim 2, it is characterised in that：The frequency phase lock The loop bandwidth of ring element is set as 250K～300K.

4. the fast frequency hopping rate source with low spurious Low phase noise according to claim 1, it is characterised in that：Each described frequency The structural parameters of phase locked-loop unit are identical and mutually independent.