CN103312319A - Spurious suppression phase frequency detector circuit applied to integer fractional frequency phase-locked loop - Google Patents
Spurious suppression phase frequency detector circuit applied to integer fractional frequency phase-locked loop Download PDFInfo
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Abstract
The invention discloses a phase frequency detector circuit which has a spurious suppression function and is applied to an integer fractional frequency phase-locked loop. The phase frequency detector circuit comprises two frequency-halving circuits, two phase frequency detectors (PFDs) based on dynamic triggers, a random signal generating logic circuit and a digital selecting logic circuit, wherein the two frequency-halving circuits are first used for carrying out frequency-halving operation on a reference clock signal REF_1 input by a crystal oscillator and a signal DIV_1 fed back by an integer divider in the phase-locked loop to obtain signals REF_2 and DIV_2, the two phase frequency detectors PFD1 and PFD2 are used for detecting the signals REF_1 and DIV_1 and the signals REF_2 and DIV_2 respectively to obtain corresponding clock pulses containing phase frequency information to be input into the digital selecting logic circuit; and the digital selecting logic circuit includes some selectors, and is driven by random signals output by the random signal generating logic circuit to output driven pulse signals UP_1, DN_1 and UP_2, DN_2 generated by the PFD1 and the PFD2 in a randomization way to charge pump circuits behind the digital selecting logic circuit, so that spurious signals are scattered, and further the power spectral density is reduced, and the effect of spurious suppression is realized.
Description
Technical field
The present invention relates to the analog phase-locked look field, be specifically related to a kind of phase frequency detector circuit that is applied to the spuious inhibition in the integer-N PLL.
Background technology
Phase-locked loop is an important module in the transceiver, it is used to provide the machine oscillator signal, and along with the fast development of field of wireless communication, transceiver is also more and more higher for the requirement of the various performances of phase-locked loop, especially phase noise, spuious and these 3 indexs of power consumption more and more are concerned.
The phase-locked loop of integral frequency divisioil generally is made of phase frequency detector, charge pump, loop filter, voltage controlled oscillator and divider.Wherein, phase frequency detector is used for surveying phase place and the frequency difference information between the signal that feeds back by the reference signal of crystal oscillator input with by divider, and converts the potential pulse that width do not wait to and export.Charge pump circuit converts to corresponding current impulse such as the potential pulse that the width of phase frequency detector output does not wait, and the loop filter of charge pump rear class is charged or discharges.The control voltage input end that the voltage output end of loop filter is directly received voltage controlled oscillator comes the frequency of control generator output.Divider generally is a programmable frequency dividing circuit, and it becomes low frequency signal to feed back in the phase frequency detector high frequency output signal frequency split of voltage controlled oscillator.
For the spurious signal in the phase-locked loop output, be because the noise that charge pump is introduced during switch under reference frequency causes greatly.The reference that the band appearance of output local oscillation signal both sides is larger thereby the injection noise that this frequency is identical with reference signal can cause in the output of loop filter little voltage fluctuation modulation voltage controlled oscillator is spuious.
Summary of the invention
By can guessing and know with reference to spuious generation reason, if can with loop filter output with voltage fluctuation randomization and equalization the reference signal same frequency, the output spectrum of voltage controlled oscillator is just more smooth-going has so comprised lower spuious energy.Thereby charge pump produces noise with the reference signal same frequency with reference frequency switch MOS pipe when phase-locked loop locks, if can be when phase-locked loop locks the switching frequency of randomization charge pump, then can realize the randomness of noise voltage fluctuation, thereby reach the purpose that suppresses spuious.
Thought based on randomization charge pump switches frequency, because the switch controlling signal of charge pump derives from phase frequency detector, can in phase frequency detector, introduce the random clock signal, by suitable logic control circuit, so that originally phase frequency detector output with the pulse repetition frequency randomization reference clock same frequency, the Injection Current noise frequency of charge pump has reached the randomized target of loop filter output noise voltage fluctuation also with regard to randomization like this.
For solving the above-mentioned technical problem that exists in the prior art, the present invention proposes a kind of spuious inhibition phase frequency detector circuit that is applied in the integer-N PLL, can establishment the reference on the phase-locked loop output spectrum spuious.
Design philosophy of the present invention is:
The present invention is a kind of phase frequency detector circuit with spuious inhibit feature that is applied in the integer-N PLL.This phase frequency detector circuit comprises two frequency-halving circuits, two phase-frequency detectors based on dynamic trigger (PFD), and random signal produces logical circuit and numeral is selected logical circuit.The signal DIV_1 that at first by two frequency-halving circuits integer divider feedback in the reference clock signal REF_1 of crystal oscillator input and the phase-locked loop is come carry out divide-by-two operations to signal REF_2 and DIV_2.Two-way phase-frequency detector PFD1 and PFD2 survey respectively REF_1, and DIV_1 and REF_2, DIV_2 signal draw the clock pulse that comprises accordingly phase frequency information and be input in the numeral selection logical circuit.Numeral selects logical circuit to comprise some selectors, the random signal that is produced logical circuit output by random signal drives, pulse signal UP_1 with PFD1 and PFD2 generation, DN_1 and UP_2, DN_2 randomization after overdriving outputs to charge pump circuit thereafter, with realization spurious signal is disperseed in order to reduce its power spectral density, realize the effect of spuious inhibition.
The phase frequency detector circuit that the present invention proposes has comprised two phase-frequency detector PFD, but they are operated under the different frequencies, and their operating frequency differs 2 times in the present invention.This phase-frequency detector is based on surveying the rising edge of input signal with the dynamic D trigger of reset function, and comprise the inverter of following thereafter and with door, delay cell, this phase-frequency detector is the basic composition unit of this phase frequency detector circuit.Because two phase-frequency detectors are operated under the different frequencies in this phase frequency detector circuit, this phase frequency detector circuit comprises that two output QB by dynamic D trigger terminate to the frequency-halving circuit of inputting this dynamic D trigger D end and consisting of, and provide signal to the phase-frequency detector that is operated under the lower frequency.Comprise also in this phase frequency detector circuit that a random signal produces logical circuit and produces random signal to drive the numeral selection logical circuit of rear class.Random signal produces logical circuit by 4 dynamic D triggers, an XOR gate, and a delay cell and a selector form.Selector is by the low frequency signals control of input reference signal through obtaining behind the above-mentioned frequency-halving circuit, and the connected mode of this uniqueness provides more reliable and stable random signal.Described numeral selects logical circuit to adopt three selectors, first selector is by outside input control, decide and adopt fixing reference signal or adopt random signal, the second level is the selector of 2 parallel connections, control output UP_1 by the output of first selector, DN_1 or UP_2, the DN_2 signal.In case first selector has been exported random signal, then the second level is exported UP_1 at random, DN_1 or UP_2, the DN_2 signal, randomization the switching frequency of charge pump.
Concrete technical scheme of the present invention is as follows:
A kind of spuious inhibition phase frequency detector circuit that is applied in the integer-N PLL comprises that two frequency-halving circuits, two phase-frequency detector PFD based on dynamic trigger, a random signal produce logical circuit and a numeral selection logical circuit; Numeral is selected to be connected with two drive circuits behind the logical circuit;
Random signal produces the reference clock signal REF_1 signal output part of the input connection crystal oscillator input signal of logical circuit, and random signal produces logical circuit output random signal Ran_C;
The reference clock signal REF_1 that crystal oscillator is inputted by the first frequency-halving circuit carries out two divided-frequency, obtains signal REF_2; The signal DIV_1 that integer divider feedback in the phase-locked loop is come by the second frequency-halving circuit carries out two divided-frequency, obtains signal DIV_2;
Two inputs of the first phase-frequency detector PFD1 connect respectively signal REF_1 and the signal DIV_1 output of the first frequency-halving circuit, and the first phase-frequency detector PFD1 output comprises clock pulse signal UP_1 and the signal DN_1 of phase frequency information accordingly;
Two inputs of the second phase-frequency detector PFD2 connect respectively signal REF_2 and the signal DIV_2 output of the second frequency-halving circuit, and the second phase-frequency detector PFD2 output comprises clock pulse signal UP_2 and the signal DN_2 of phase frequency information accordingly;
The operating frequency of described first frequency detector PFD1 is higher than the second phase-frequency detector PFD2;
Numeral selects signal UP_1, signal DN_1, signal UP_2 and the signal DN_2 input of logical circuit to connect respectively signal UP_1 and the signal DN_1 output of the first phase-frequency detector PFD1 and the signal UP_2 of the second phase-frequency detector PFD2 and signal DN_2 output;
Numeral is selected the control signal input of logical circuit to connect respectively random signal and is produced logical circuit signal Ran_C output and external input signal INPUT; Numeral is selected signal output part output signals UP and the DN of logical circuit; It is UPP and UPN that the UP signal obtains complementary signal through a drive circuit, but the identical electrical level polar of their frequencies is opposite; It is DNP that the DN signal obtains complementary signal through another drive circuit, DNN, but the identical electrical level polar of their frequencies is opposite.
Described first and second frequency-halving circuit is identical; Frequency-halving circuit is to be made of a d type flip flop based on true single phase clock structure that the QB end signal is fed back to D end; The Q end of d type flip flop is frequency output terminal, and the clock signal input terminal of d type flip flop is the frequency input.
Feature is that the structure of described two phase-frequency detectors is identical;
For arbitrary phase-frequency detector, its structure is to comprise two d type flip flops, the D input termination power vd D of two d type flip flops;
The clock signal input terminal of the first d type flip flop meets signal REF_1 or signal REF_2; The clock signal input terminal of the second d type flip flop meets signal DIV_1 or signal DIV_2;
The Q end of the first d type flip flop connects the two-stage inverter, and two inverters connect and compose first group of inverter successively; The Q end of the second d type flip flop connects the two-stage inverter, and two inverters connect and compose second group of inverter successively; Each inverter is identical in first and second group inverter;
The output of first and second group inverter is connected to two inputs and door, is to be connected the two-stage delay circuit with gate output terminal;
Two delay circuits all are to be made of inverter and electric capacity, and wherein, the input of inverter is as the input of delay circuit, and the output of inverter is as the output of delay circuit, and the output of inverter passes through capacity earth;
Inverter parameter in two delay circuits is identical, and the appearance value of the electric capacity in the delay circuit of the second level is 1.5 times of appearance value of the electric capacity in the delay circuit of the second level.
It is by level Four d type flip flop, a selector and the synchronizing sequential circuit that XOR gate consists of that described random signal produces logical circuit; The level Four d type flip flop connects successively;
In first three grade d type flip flop, the QB of previous stage trigger end connects the D end of next stage trigger; The QB end of afterbody trigger and the Q end of first order trigger are connected to two inputs of XOR gate, and the output of XOR gate is connected to the D end of first order trigger; The input end of clock of all d type flip flops all connects the reference clock signal REF_1 signal output part of crystal oscillator;
The Q end of described first order trigger is connected with QB and is connected respectively selector two inputs, and the control end of selector connects the output of signal REF_2, and the output of selector is the random signal Ran_C output that random signal produces logical circuit; Random signal Ran_C has high and low level signal, and the probability that high and low level produces is identical.
Described random signal produces in the logical circuit and also comprises delay cell, between the QB output of the input connection first order trigger of this delay cell and the input of selector.
Numeral selects logical circuit to comprise three selectors, is respectively first and second and three selectors;
In the first selector, the A input end grounding, the B input connects the output that random signal produces logical circuit, and the control input end connects external input signal INPUT, and the Y output connects respectively the control input end of second and third selector;
In the second selector, the A input connects the clock pulse UP_1 output of the first phase-frequency detector PFD1, and the B input connects the clock pulse DN_1 output of the first phase-frequency detector PFD1, and the Y output is the UP signal output part;
In the third selector, the A input connects the clock pulse UP_2 output of the second phase-frequency detector PFD2, and the B input connects the clock pulse DN_2 output of the second phase-frequency detector PFD2, and the Y output is the DN signal output part;
Selected by the external input signal INPUT in the described first selector: in the starting stage of phase-locked loop operation, a mode; After the phase-locked loop locking, select the b mode;
The a mode is fixedly to choose UP_1 and DN_1 select logical circuit as numeral output;
The b mode is, chooses arbitrarily UP_1 and DN_1 or UP_2 and DN_2 select logical circuit as numeral output by random signal.
Described drive circuit comprises UP signal and corresponding UP branch road and the DN branch road of DN signal of numeral selection logical circuit, and the structure of two branch roads is identical;
For arbitrary branch road, comprise inverter and a delay cell that two-way is parallel;
For signal UPP or corresponding the setting out on a journey of DNP, comprise four inverters that connect successively, wherein the input of the first inverter connects UP signal or the DN signal output part that numeral is selected logical circuit; Four inverters increase step by step; Afterbody inverter output UPP or DNP signal;
For complementary signal UPN or lower road corresponding to DNN, described MOS switch and three inverters that connect successively thereafter; The input of described MOS switch connects UP signal or the DN signal output part that numeral is selected logical circuit; Three inverters increase step by step; Afterbody inverter output UPN or DNN signal;
In upper and lower road, according to from rear to front sequence, three grades of inverters are identical in twos; The time of delay that delay cell in the lower road provides is identical with the time of delay that first order inverter in setting out on a journey causes.
Described delay cell is the MOS switch, and this MOS switch is often driven the MOS switch by what PMOS and NMOS formed.
Description of drawings
Fig. 1 is phase frequency detector overall structure block diagram of the present invention.
Fig. 2 is the circuit diagram of the two-divider of embodiment employing.
Fig. 3 is the circuit diagram that random signal produces logical circuit among the present invention.
Fig. 4 is the circuit diagram of the phase-frequency detector of embodiment employing.
Fig. 5 is the circuit diagram that numeral is selected logical circuit among the present invention.
Fig. 6 selects the logical circuit Single-end output to change into the drive circuit schematic diagram of charge pump both-end input numeral among the present invention.
Embodiment
Below in conjunction with embodiment and accompanying drawing, the present invention is described in more detail.
Phase frequency detector circuit described in the specific embodiment of the invention is innovation and the improvement of carrying out on the basis of phase-frequency detector shown in Figure 4, comprise that by two phase-frequency detectors being incorporated into one random signal produces logical circuit and numeral is selected in the system of logical circuit, be operated in lower frequency by auxiliary one of them phase-frequency detector of two frequency-halving circuits, thereby any that can drive select two phase-frequency detectors by random signal is as output, upset fixing reference frequency, suppressed with reference to spuious.
The frequency-halving circuit that the technical program adopts consists of the d type flip flop based on true single phase clock structure of QB signal feedback to the D input by one.Fig. 2 is exactly the frequency-halving circuit that utilizes dynamic D trigger to realize, the QB output feedback link of d type flip flop is to the D input, from the output of divider in the reference frequency input of crystal oscillator and the phase-locked loop, the frequency-halving circuit output signal offers the lower phase-frequency detector of operating frequency to the input of the clock of two d type flip flops respectively.
Phase-frequency detector can adopt existing phase-frequency detector, as shown in Figure 4, in the phase-frequency detector, the D input termination power vd D of d type flip flop 301 and d type flip flop 302, the clock input of d type flip flop 301 connects reference frequency signal or its two divided-frequency signal, and the clock input of d type flip flop 302 connects signal or its two divided-frequency signal of phase-locked loop divider feedback.D type flip flop 301 is connected output Q end and is all connected respectively the identical inverter of two-stage 303,310 and 309,311 with d type flip flop.The output of inverter 310 and inverter 311 be connected to 2 the input with the door 304, with gate output terminal be the two-stage delay circuit, by a dead-time problem that overcomes charge pump switches larger time of delay.Wherein inverter 305 is identical with 306 parameters in the delay circuit, and the value of electric capacity 308 is 1.5 times of electric capacity 307.
Random signal among the present invention produce logical circuit be one by 4 grades of d type flip flops and the synchronizing sequential circuit that XOR gate forms, as shown in Figure 3, front 3 grades of d type flip flops, (be trigger 201,202,203) QB output all connects the D input of next stage trigger, the QB end of trigger 204 and the Q end of trigger 201 are held by the D that an XOR gate 205 feeds back to first order trigger 201, the clock input of all d type flip flops all connects the crystal oscillator input signal, so just, realized random signal generating circuit, in order to reach the reliability and stability requirement of random signal, the output Q of first order trigger 201 and QB end are connected to one by the selector of reference signal REF_1 through the control of the signal REF_2 behind the two divided-frequency, the connected mode of this innovation can guarantee that the high-low level output probability equates, degree of randomization is higher.In order to weaken the problem of clock competition burr in the circuit, delay cell 207 is inserted into QB signal rear end, by the time of delay of reasonable adjustment delay cell 207, can effectively reduce burr.
Fig. 5 and Fig. 6 have provided respectively digital selection logical circuit and drive circuit thereafter.Numeral selects logical circuit to be made of 3 selectors 401,402,403.UP_1, DN_1 is from the phase-frequency detector of high operate frequency, UP_2, DN_2 is from the phase-frequency detector of low operating frequency, the control inputs signal IINPUT of selector 401 is inputted by the outside, and it is used for selecting is fixedly to choose UP_1, and DN_1 selects the output of logical circuit or chooses arbitrarily UP_1 by random signal as numeral, DN_1 or UP_2, DN_2 select the output of logical circuit as numeral.In the starting stage of phase-locked loop operation, can lock faster in order to guarantee phase-locked loop, can fix and select UP_1, DN_1 is as output.After the phase-locked loop locking, in order to suppress spuious, random signal just is introduced into to control selector.
For difference or with the charge pump of mirror image branch, it is inadequate that UP and DN signal only are provided, and also needs to provide their complementary signal, is labeled as UPP at this, UPN and DNP, DNN; But the identical electrical level polar of their frequency is opposite.We need to add drive circuit after numeral is selected logical circuit in order to obtain such signal, as shown in Figure 6.For the UP branch road, inverter 501,502,503,504 increase step by step; And inverter 502 and inverter 506, inverter 503 and inverter 507, inverter 504 is identical with inverter 508.505 is MOS switches of often opening that are comprised of PMOS and NMOS, be used to provide a short delay, and time of delay is identical with the delay that inverter 501 causes.The structure of DN branch road and UP branch road are identical, and UP and DN signal just can obtain the electric charge pump drive signal UPP of 2 pairs of complementations, UPN and DNP, DNN behind overdrive circuit.
Claims (7)
1. a spuious inhibition phase frequency detector circuit that is applied in the integer-N PLL is characterized in that: comprise that two frequency-halving circuits, two phase-frequency detector PFD based on dynamic trigger, a random signal produce logical circuit and a numeral selection logical circuit; Numeral is selected to be connected with two drive circuits behind the logical circuit;
Random signal produces the reference clock signal REF_1 signal output part of the input connection crystal oscillator input signal of logical circuit, and random signal produces logical circuit output random signal Ran_C;
The reference clock signal REF_1 that crystal oscillator is inputted by the first frequency-halving circuit carries out two divided-frequency, obtains signal REF_2; The signal DIV_1 that integer divider feedback in the phase-locked loop is come by the second frequency-halving circuit carries out two divided-frequency, obtains signal DIV_2;
Two inputs of the first phase-frequency detector PFD1 connect respectively signal REF_1 and the signal DIV_1 output of the first frequency-halving circuit, and the first phase-frequency detector PFD1 output comprises clock pulse signal UP_1 and the signal DN_1 of phase frequency information accordingly;
Two inputs of the second phase-frequency detector PFD2 connect respectively signal REF_2 and the signal DIV_2 output of the second frequency-halving circuit, and the second phase-frequency detector PFD2 output comprises clock pulse signal UP_2 and the signal DN_2 of phase frequency information accordingly;
The operating frequency of described first frequency detector PFD1 is higher than the second phase-frequency detector PFD2;
Numeral selects signal UP_1, signal DN_1, signal UP_2 and the signal DN_2 input of logical circuit to connect respectively signal UP_1 and the signal DN_1 output of the first phase-frequency detector PFD1 and the signal UP_2 of the second phase-frequency detector PFD2 and signal DN_2 output;
Numeral is selected the control signal input of logical circuit to connect respectively random signal and is produced logical circuit signal Ran_C output and external input signal INPUT; Numeral is selected signal output part output signals UP and the DN of logical circuit; It is UPP and UPN that the UP signal obtains complementary signal through a drive circuit, but the identical electrical level polar of their frequencies is opposite; It is DNP that the DN signal obtains complementary signal through another drive circuit, DNN, but the identical electrical level polar of their frequencies is opposite.
2. the spuious inhibition phase frequency detector circuit that is applied in the integer-N PLL according to claim 1 is characterized in that described first and second frequency-halving circuit is identical; Frequency-halving circuit is to be made of a d type flip flop based on true single phase clock structure that the QB end signal is fed back to D end; The Q end of d type flip flop is frequency output terminal, and the clock signal input terminal of d type flip flop is the frequency input;
Feature is that the structure of described two phase-frequency detectors is identical;
For arbitrary phase-frequency detector, its structure is to comprise two d type flip flops, the D input termination power vd D of two d type flip flops;
The clock signal input terminal of the first d type flip flop meets signal REF_1 or signal REF_2; The clock signal input terminal of the second d type flip flop meets signal DIV_1 or signal DIV_2;
The Q end of the first d type flip flop connects the two-stage inverter, and two inverters connect and compose first group of inverter successively; The Q end of the second d type flip flop connects the two-stage inverter, and two inverters connect and compose second group of inverter successively; Each inverter is identical in first and second group inverter;
The output of first and second group inverter is connected to two inputs and door, is to be connected the two-stage delay circuit with gate output terminal;
Two delay circuits all are to be made of inverter and electric capacity, and wherein, the input of inverter is as the input of delay circuit, and the output of inverter is as the output of delay circuit, and the output of inverter passes through capacity earth;
Inverter parameter in two delay circuits is identical, and the appearance value of the electric capacity in the delay circuit of the second level is 1.5 times of appearance value of the electric capacity in the delay circuit of the second level.
3. the spuious inhibition phase frequency detector circuit that is applied in the integer-N PLL according to claim 1 is characterized in that it is by level Four d type flip flop, a selector and the synchronizing sequential circuit that XOR gate consists of that described random signal produces logical circuit; The level Four d type flip flop connects successively;
In first three grade d type flip flop, the QB of previous stage trigger end connects the D end of next stage trigger; The QB end of afterbody trigger and the Q end of first order trigger are connected to two inputs of XOR gate, and the output of XOR gate is connected to the D end of first order trigger; The input end of clock of all d type flip flops all connects the reference clock signal REF_1 signal output part of crystal oscillator;
The Q end of described first order trigger is connected with QB and is connected respectively selector two inputs, and the control end of selector connects the output of signal REF_2, and the output of selector is the random signal Ran_C output that random signal produces logical circuit; Random signal Ran_C has high and low level signal, and the probability that high and low level produces is identical.
4. the spuious inhibition phase frequency detector circuit that is applied in the integer-N PLL according to claim 3, it is characterized in that also comprising delay cell in the described random signal generation logical circuit, between the QB output of the input connection first order trigger of this delay cell and the input of selector.
5. the spuious inhibition phase frequency detector circuit that is applied in the integer-N PLL according to claim 1 is characterized in that numeral selection logical circuit comprises three selectors, is respectively first and second and three selectors;
In the first selector, the A input end grounding, the B input connects the output that random signal produces logical circuit, and the control input end connects external input signal INPUT, and the Y output connects respectively the control input end of second and third selector;
In the second selector, the A input connects the clock pulse UP_1 output of the first phase-frequency detector PFD1, and the B input connects the clock pulse DN_1 output of the first phase-frequency detector PFD1, and the Y output is the UP signal output part;
In the third selector, the A input connects the clock pulse UP_2 output of the second phase-frequency detector PFD2, and the B input connects the clock pulse DN_2 output of the second phase-frequency detector PFD2, and the Y output is the DN signal output part;
Selected by the external input signal INPUT in the described first selector: in the starting stage of phase-locked loop operation, select a mode; After the phase-locked loop locking, select the b mode;
The a mode is fixedly to choose UP_1 and DN_1 select logical circuit as numeral output;
The b mode is, chooses arbitrarily UP_1 and DN_1 or UP_2 and DN_2 select logical circuit as numeral output by random signal.
6. the spuious inhibition phase frequency detector circuit that is applied in the integer-N PLL according to claim 5, it is characterized in that described drive circuit comprises UP signal and corresponding UP branch road and the DN branch road of DN signal of numeral selection logical circuit, the structure of two branch roads is identical;
For arbitrary branch road, comprise inverter and a delay cell that two-way is parallel;
For signal UPP or corresponding the setting out on a journey of DNP, comprise four inverters that connect successively, wherein the input of the first inverter connects UP signal or the DN signal output part that numeral is selected logical circuit; Four inverters increase step by step; Afterbody inverter output UPP or DNP signal;
For complementary signal UPN or lower road corresponding to DNN, described MOS switch and three inverters that connect successively thereafter; The input of described MOS switch connects UP signal or the DN signal output part that numeral is selected logical circuit; Three inverters increase step by step; Afterbody inverter output UPN or DNN signal;
In upper and lower road, according to from rear to front sequence, three grades of inverters are identical in twos; The time of delay that delay cell in the lower road provides is identical with the time of delay that first order inverter in setting out on a journey causes.
7. the spuious inhibition phase frequency detector circuit that is applied in the integer-N PLL according to claim 6 is characterized in that described delay cell is the MOS switch, and this MOS switch is often driven the MOS switch by what PMOS and NMOS formed.
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| CN110460328A (en) * | 2019-09-09 | 2019-11-15 | 广东华芯微特集成电路有限公司 | Arbitrary integer frequency divider and phase-locked loop systems |
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| CN110460328A (en) * | 2019-09-09 | 2019-11-15 | 广东华芯微特集成电路有限公司 | Arbitrary integer frequency divider and phase-locked loop systems |
| CN113498506A (en) * | 2020-01-19 | 2021-10-12 | 京东方科技集团股份有限公司 | Random number generation circuit, random number generation method, and electronic device |
| CN113498506B (en) * | 2020-01-19 | 2024-03-19 | 京东方科技集团股份有限公司 | Random number generation circuit, random number generation method, and electronic device |
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| CN112702043A (en) * | 2021-03-24 | 2021-04-23 | 上海海栎创科技股份有限公司 | Bidirectional deburring circuit |
| CN114421931A (en) * | 2022-01-28 | 2022-04-29 | 中国电子科技集团公司第二十四研究所 | Pseudo-random frequency division signal generating circuit and method |
| CN114421931B (en) * | 2022-01-28 | 2023-09-22 | 中国电子科技集团公司第二十四研究所 | Pseudo-random frequency division signal generating circuit and method |
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