CN101136855B - Asynchronous clock data transmission device and method - Google Patents
Asynchronous clock data transmission device and method Download PDFInfo
- Publication number
- CN101136855B CN101136855B CN2007100911527A CN200710091152A CN101136855B CN 101136855 B CN101136855 B CN 101136855B CN 2007100911527 A CN2007100911527 A CN 2007100911527A CN 200710091152 A CN200710091152 A CN 200710091152A CN 101136855 B CN101136855 B CN 101136855B
- Authority
- CN
- China
- Prior art keywords
- data
- assembling
- clock
- control unit
- frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The device includes following units: counting unit for global clock (CUGC) in use for indicating serial number of the input data in fast source clock domain; being connected to CUGC, multichannel allocation and control unit (MACU) in use for sampling the input data circularly based on serial number of data; being connected to MACU, the synchronous control unit (SCU) in use for synchronizing the sampled data with target clock domain; being connected to SCU, the word assembling unit in use for assembling the synchronized data by SCU into the assembled data. The method includes steps: indicating serial number of the input data in fast source clock domain; based on serial number of the data to sample the input data circularly through multiple data channels; synchronizing the sampled data with target clock domain; assembling the synchronized data into the assembled data and outputting the data. Features are: raising transmission efficiency, and simple control method.
Description
Technical field
The present invention relates to a kind of asynchronous clock data transmission device and method, relate in particular to a kind of from asynchronous clock data transmission device and the method when at a slow speed the target clock territory transmission data of source clock zone fast.
Background technology
In engineering design, the data that the application that great majority are correlated with transfer of data all relates to crossing clock domain move, such as Magnetic Disk Controler commonly used, network processing unit etc.When signal when a clock zone is sent to another clock zone, need be taken as asynchronous signal and handle.Handle for asynchronous signal; The most basic problem is the stability problem that solves signal; If solve badly, the asynchronous signal that then receives possibly play pendulum, such as being in metastable state; And possibly cause this labile state its spread in china in new clock zone, thereby cause the functional fault of system.Therefore, when signal passes through between asynchronous clock domain, need carry out synchronously through synchronizer usually.When single-bit signal was passed through between asynchronous clock domain, common synchronizer structure had level synchronization device, edge to detect synchronizer and impulsive synchronization device etc.
Usually, through target clock territory synchronizer synchronously after, just can solve the stability problem of asynchronous signal.In more applications, what cross over that clock transmits is not simple single-bit signal, but through data/address bus, address bus, and transmission lot of data such as control bus.These data-signals after the effect of synchronizer, have obtained stable signal equally.But because the transformation period of asynchronous signal and target clock, make that the signal that receives is not necessarily correct along the uncertainty of relation.In order to address this problem, common way is to adopt to shake hands and method such as push-up storage (First In, First Out, abbreviation FIFO) interface.
This method that employing is shaken hands, when the data of clock zone were effective in the source, transmission was given the target clock territory according to the index signal of the DSR of single-bit.The target clock territory detect this index signal effectively after, begin to receive data, and the answer signal that feedback data has received is given the source clock zone from data/address bus.The source clock zone is detecting this answer signal effectively indication and data/address bus of release data when effective.In this process; In order to solve the stability problem of asynchronous signal; The data effective index signal of source clock zone is delivered to the target clock territory; And the target clock numeric field data receives answer signal and feeds back to the source clock zone and all need pass through synchronizer and carry out Synchronous Processing, thereby greatly reduces the data transmission efficiency of this communication mode.
When using FIFO, except the extra FIFO memory space of needs, also there is control problem to FIFO as the interface of asynchronous clock transfer of data.When FIFO is full, can not in FIFO, write data again, if at this moment also continue to produce write operation, the loss of data phenomenon will appear; Similarly, at FIFO when being empty, reading of data from FIFO again, if reading of data from FIFO also at this moment, then the data of output are exactly incorrect.The judgement of the empty full state of FIFO all need compare the reading, writing address of FIFO.But they in order to compare, need through the clock zone Synchronous Processing in different clock zones.Though have now than mature technique and solve these problems; But from quick clock zone when the clock zone Data transmission at a slow speed; In this side of clock zone at a slow speed, the speed that data write is also faster than the speed of data output, at this moment uses fifo structure just must make the memory space of FIFO be set to infinity; Otherwise can cause the data stacking effect, produce the data overflow problem.
Summary of the invention
Technical problem to be solved by this invention is for a kind of asynchronous clock data transmission device and transmission method thereof are provided, and is used for during at a slow speed target clock territory transmission data, realizing the synchronization of data transmission at source clock zone fast efficiently, simply.
In order to solve the problems of the technologies described above, the present invention at first provides a kind of asynchronous clock data transmission device, comprising:
Global clock counting unit is used to indicate the sequence number of the input data that derive from the fast source clock zone;
Multichannel distributes and control unit, links to each other with said global clock counting unit, disposes a plurality of data channel, is used for each said data channel according to said data sequence number, circularly to said sampling input data;
Synchronous control unit links to each other with control unit with said multichannel distribution, is used for the said data sync that samples to the target clock territory;
The word module units links to each other with said synchronous control unit, is used for the data set of said synchronous control unit after synchronously dressed up assembling data and output.
According to above-mentioned a kind of asynchronous clock data transmission device, wherein, said each data channel in said multichannel distribution and the control unit can be carried out said sampling under enable signal effect separately.Said multichannel distributes the data channel number with control unit, can confirm according to the frequency of said source clock zone and the frequency in said target clock territory.Further, said data channel number can further adopt the emulation of Verilog language and Verilog compiling simulator to confirm.
According to above-mentioned a kind of asynchronous clock data transmission device, wherein, said synchronous control unit synchronously, can adopt two carrying out shake communication mechanism.
According to above-mentioned a kind of asynchronous clock data transmission device; Wherein, said word module units can be further used for after said each assembling data assembling is accomplished; All generate the marking signal that said assembling data assembling is accomplished, be used to indicate said assembling data assembling to accomplish.Said word module units is when carrying out said assembling, and said data set after is synchronously dressed up the number of said assembling data, can confirm according to said source clock zone frequency and said target clock territory frequency.
A kind of asynchronous clock data transmission device according to above-mentioned further comprises the digital signal processor interface unit, links to each other with said word module units, for said device provides data output interface.
On this basis, the present invention and then a kind of asynchronous clock data transmission method is provided comprises step:
(1) indication derives from the sequence number of the input data of fast source clock zone;
(2) according to said data sequence number, through a plurality of data channel circularly to said sampling input data;
(3) with the said data sync that samples to the target clock territory;
(4) said data set after is synchronously dressed up assembling data and output.
According to above-mentioned a kind of asynchronous clock data transmission method, wherein, in the said step (2), said sampling can be carried out under the enable signal control separately of said data channel.Said data channel number can be confirmed according to the frequency of said source clock zone and the frequency in said target clock territory.Further, said data channel number can further adopt the emulation of Verilog language and Verilog compiling simulator to confirm.
According to above-mentioned a kind of asynchronous clock data transmission method, wherein said synchronous in the said step (3), can adopt two carrying out shake communication mechanism.
According to above-mentioned a kind of asynchronous clock data transmission method, wherein, in the said step (4), said data set after is synchronously dressed up the number of said assembling data, can confirm according to said source clock zone frequency and said target clock territory frequency.After said each assembling data assembling after is synchronously accomplished, can further generate the marking signal that the data assembling is accomplished, indicate said assembling data assembling to accomplish.
A kind of asynchronous clock data transmission method according to above-mentioned may further include step:
(5) said assembling data output to a data output interface and supply the said assembling data of external call.
A kind of asynchronous clock data transmission device provided by the invention and method with the existing compared with techniques that adopts, have following characteristics:
1) improved efficiency of transmission;
The equipment cost of 2) practicing thrift;
3) control method is more simple.
Description of drawings
Fig. 1 is apparatus of the present invention and method design sketch map;
Fig. 2 is apparatus of the present invention example structure sketch map;
Fig. 3 is the correlation sketch map of apparatus of the present invention application implementation example multichannel control;
Fig. 4 is the inventive method embodiment schematic flow sheet.
Embodiment
Below in conjunction with accompanying drawing and embodiment the present invention is further specified.
Referring to Fig. 1, thinking of the present invention is: the source aiming field is the data sequence D1 of quick clock zone, behind the counting through a counter, is input in the middle of the corresponding asynchronous clock data transmission circuit.This transmission circuit carries out the data assembling with the sequence number that the data of source aiming field provide according to counter, such as number one data and No. second data set are dressed up data, No. three data and Di Si data set is dressed up data, by that analogy.Certainly, according to concrete needs, also can adopt other assemble methods.Data sequence D2 after transmission circuit will be assembled, the cpu i/f through digital signal processor (DigitalSignal Processor is called for short DSP) sends to the target clock territory promptly at a slow speed in the clock zone on the relevant data processing unit again.Asynchronous clock data transmission device based on this thought realizes is assembled into data sequence D2 with data sequence D1, not only can improve the efficient of transfer of data, nor can produce the problem that data are overflowed.
As shown in Figure 2, asynchronous clock data transmission device of the present invention comprises that mainly global clock counting unit 201, multichannel distribute and control unit 202, synchronous control unit 203, word module units 204, and dsp interface unit 205, wherein:
Global clock counting unit 201 is equivalent to a global clock counter, is used to indicate derive from the sequence number that quick clock zone is the input data of source clock zone.The data that global clock counting unit 201 produces are sent in multichannel distribution and the control unit 202.
Multichannel distributes and control unit 202; Link to each other with global clock counting unit 201; Dispose a plurality of data channel, each passage under enable signal effect separately, the data sequence number of being exported according to global clock counting unit 201; Circularly to the output of global clock counting unit 201, carry out data sampling continuously.Synchronization has only an enable signal to be in effective status.These passages constitute a passage winding under the Collaborative Control of multichannel distribution and control unit 202 and synchronous control unit 203.Can sample the circularly continuously data of quick clock zone output of this passage winding.Each channel sample in multichannel distribution and the control unit 202 is sent into synchronous control unit 203 after the data of each self-corresponding quick clock zone.
The number of data channel in multichannel distribution and the control unit 202; Be also to be also i.e. clock frequency at a slow speed of quick clock frequency and target clock territory according to the source clock zone; The hardware of ALT-CH alternate channel is described with the Verilog language; After predefine passage number is some numerical value M, confirm the value of predefine port number M through Verilog compiling simulator (Verilog Compiled Simulator is called for short VCS) emulation.
f
1×n≥f
2＜f
1×(n+1) (1)
Wherein, f
1Be the clock frequency of clock at a slow speed, n is for distributing the passage number that channel data is assembled in control unit 202, f with multichannel
2Clock frequency for quick clock.Also i.e. clock frequency f at a slow speed
1Be multiplied by the passage number n that need be assembled into together, should be more than or equal to quick clock frequency f
2Its reason is to let the data of adjacent several passages carry out after the data assembling, carries out data sampling at clock zone at a slow speed again.The data that so just can not lose the source clock zone are accomplished the accurate of transfer of data.
Supposing that total number of channels is M in distribution and the control unit 202, is n according to the determined assembling number of words of expression formula (1), and word module units 204 need be followed certain assembling principle when carrying out the data assembling.If M can just be divided exactly by n, then M channel data just is assembled into M/n assembling data; If M can not be divided exactly by n; Then M channel data need be assembled into [M/n]+1 an assembling data, and [M/n] wherein is the integer part of M/n, and assemble method is to n the data of preceding [M/n] * in M the data; Assemble successively; Being assembled into [M/n] individual assembling data altogether, also is the data in n passage of M-[M/n] * to remaining part, is assembled into assembling data; To these data of last assembling, its figure place insufficient section can be changed to the data with certain sense with its high-order perhaps low level, and is complete zero such as being changed to, or is changed to other significant data etc.
According to assembling principle and the mode that apparatus of the present invention provide, the data after the assembling do not need to carry out other again and handle, and the data of 205 outputs are in proper order promptly in full accord with the order of clock zone data input fast from the dsp interface unit.
Below with 61.44 megahertzes as the data input clock, be application implementation example with 50 megahertzes as data output clock, come apparatus of the present invention are further specified.The operating frequency that also is the source clock zone is 61.44 megahertzes, and the operating frequency in target clock territory is 50 megahertzes.Apparatus of the present invention suppose further that also the data width of 61.44 megahertz clock zones input is 32bits.
Global clock counting unit 201 is equivalent to produce the global clock counter of one 32 bit width signals.Data at a 32bits of each clock generating; Be the data definition of this 32bits in the present embodiment: bit0～bit4 is the sample count value; Bit5～bit16 is the chip count value, and bit17～bit20 is the time slot count value, and bit21～bit31 is a frame count value.According to concrete application, also it can be defined as other implication.The data of input are the 32bits data of Cycle by Cycle output, change at the rising edge of 61.44 megahertz clocks, at the rising edge of 61.44 megahertz clocks data are sampled equally.The counting unit of this 32bits is made up of four sub-counters, and wherein, bit0～bit4 is the sample count value, and bit5～bit16 is the chip count value, and bit17～bit20 is the time slot count value, and bit21～bit31 is a frame count value.In the present embodiment, the data of input can be the 32bits random numbers of Cycle by Cycle output.Certainly, also can just test count value itself as the input data.
Multichannel distributes a plurality of data channel that disposed with control unit 202, under the Collaborative Control of synchronous control unit 203, constitutes a passage winding.Each passage in the passage winding is under enable signal effect separately, and the data of the 61.44 megahertz clock generating of circularly global clock counting unit 201 being exported are continuously sampled.Synchronization has only an enable signal to be in effective status.In the present embodiment, come the clock data of transmission sources clock zone 61.44 megahertzes, need 11 passages with the clock of target clock territory 50 megahertzes.Each passage all has the enable signal of a sampled data and this sampled data accordingly.When the enable signal trailing edge of each passage, this corresponding passage just carries out data sampling.These 11 passages constitute a winding under the Collaborative Control of multichannel distribution and control unit 202 and synchronous control unit 203, thus the 32bits random number that the source clock zone 61.44 megahertz clocks of can sampling are circularly continuously produced.
Should use among the embodiment; Multichannel distributes 11 passages with control unit 202; Be according to clock frequency 61.44 megahertzes and clock frequency 50 megahertzes fast at a slow speed, describe the hardware of ALT-CH alternate channel with the Verilog language, and confirm through VCS emulation.
These 11 passages are when depositing the input data of 61.44 megahertzes; Adopt following mode: first 32bit data of the random data that first channel sample is effectively imported continuously; Second 32bit data of the random data of second continuous input of channel sample; By that analogy, the 11 32bit data of the random data of the 11 the continuous input of passage.The data sampling of adjacency channel enables control signal and differs a clock cycle, and the correlation of passage is as shown in Figure 3.
Clk_61.44 among Fig. 3 representes the clock frequency of source clock zone, and what gcc2 [31:0] represented is the sequence number that the source clock zone need be sent to the data in target clock territory; And ch1_data [31:0], ch2_data [31:0] ..., ch11_data [31:0] is respectively the sampled data of these 11 passages, ch1_en, ch2_en ..., ch11_en is respectively the sampled data enable signal of 11 passages.
In this application implementation example of the present invention; Because source clock zone frequency is 61.44 megahertzes, target clock territory frequency is 50 megahertzes, according to expression formula (1); Can draw n is 2, also is that word module units 204 need be dressed up double-word data with synchronous control unit 203 data set after synchronously.Assembling principle according to above-mentioned can be learnt; The data of number one passage and No. second passage are assembled into a double-word data; The data of No. three passage and No. four passage are assembled into a double-word data, by that analogy, in a circulation with the data of last passage also assembled.Concrete assembling mode can be selected the data of number one passage are placed on low level, and the data of No. second passage are placed on a high position; Also can reverse, also be that the data of number one passage are placed on a high position, and the data of No. second passage are placed on low level.Certainly, the method that two data is assembled into data also has a lot, does not enumerate one by one at this.But this of apparatus of the present invention proposition preferably is placed on low level with the data of number one passage, and the data of No. second passage are placed on high-order this mode, are a kind of more excellent common methods.
Should use among the embodiment, multichannel distributes in the passage winding that constitutes with control unit 202 and includes 11 passages, also is that port number is an odd number.In loop control, last passage in these 11 passages is the ride on Bus No. 11 passage also, and the data that it samples maybe be identical with the number one channel data of source next clock cycle of clock zone, also maybe be inequality, should handle respectively both of these case.If ride on Bus No. 11 passage and number one channel sample are not then exported this channel data to the data of the same sequence number of source clock zone, also be about to the rejection of data of this last passage, and get into next circulation; If this last passage and number one channel sample be to the data that are not the same sequence number of source clock zone, then the data of this number passage and other same bit-width and data set with certain sense are dressed up a double-word data.Data with certain sense are such as comprising complete zero perhaps specified sign property data etc.Low 32bit is provided with the data of this passage, and high 32bi correspondingly is set to this data with certain sense.
When port number was even number, the data of just per two passages were assembled into a double-word data.Concrete assembling mode is the description of odd number situation with reference to above-mentioned port number.Word module units 204 also correspondingly generates the marking signal that the data assembling is accomplished after the data in the passage all are assembled into double-word data.
As can be seen from Figure 3, the data that the ride on Bus No. 11 channel sample arrives, the data that sampled with next clock cycle number one passage are identical.Therefore when carrying out the double word assembling, with this ride on Bus No. 11 channel sample to data abandon, directly carry out number one passage and the assembling of No. second channel data in next circulation.
Double-word data through word module units 204 assembles is transferred to other data processing units of system through dsp interface unit 205.
The present invention and then provides a kind of asynchronous clock data transmission method on the basis of foregoing invention system, be used for from source clock zone fast realizing the data sync transmission efficiently, simply when at a slow speed the target clock territory transmission data.Referring to Fig. 4, the inventive method mainly comprises the steps:
Step 401: at first through global clock counting unit 201, the data sequence as the quick clock zone of source clock zone is counted, indication derives from the sequence number of the input data of source clock zone.The transfer of data that global clock counting unit 201 finishes counting to multichannel distribute with control unit 202 in.
Step 402: multichannel distributes and control unit 202 disposes a plurality of data channel.The input data sequence number of being exported according to said global clock counting unit 201; Under the Collaborative Control of multichannel distribution and control unit 202 and synchronous control unit 203; According to enable signal separately, the data that all data channel are imported the clock zone from the source are sampled continuously circularly.
Step 403: synchronous control unit 203 with multichannel distribute with each channel sample of control unit 202 to the data of source clock zone be synchronized to the target clock territory respectively.Synchronizing process adopts two carrying out shake communication mechanism, and is reliable to guarantee the data security that target clock samples, and eliminates metastable state.
Step 404: word module units 204 carries out the data assembling with synchronous control unit 203 data after synchronously, and after each assembling data assembling is accomplished, correspondingly generates data assembling complement mark signal.When carrying out the data assembling; The assembling principle of being followed supposes that total number of channels is M in distribution and the control unit 202 as stated, is n according to the determined assembling number of words of expression formula (1); If M can just be divided exactly by n, then M channel data just is assembled into M/n assembling data; If M can not be divided exactly by n; Then M channel data need be assembled into [M/n]+1 an assembling data, and [M/n] wherein is the integer part of M/n, and assemble method is to n the data of preceding [M/n] * in M the data; Assemble successively; Being assembled into [M/n] individual assembling data altogether, also is the data in n passage of M-[M/n] * to remaining part, is assembled into assembling data; To these data of last assembling, its figure place insufficient section can be changed to the data with certain sense with its high-order perhaps low level, and is complete zero such as being changed to, or is changed to other significant data etc.
Step 405: the assembling data through word module units 204 assembles are transferred to other data processing units of system through dsp interface unit 205.Also be other data processing units of system,, call the assembling data through dsp interface unit 205 these data output interfaces.Transfer of data will assembled before other data processing units in dsp interface unit 205, also need receive the data assembling complement mark signal that word module units 204 sends.After receiving this marking signal, transfer of data just will be assembled to other data processing units in dsp interface unit 205.
Data transmission device and method through the present invention's proposition; Not only realized the data synchronization problems in the asynchronous clock process of data communication; And the problem of inefficiency when having solved when quick clockwise and using handshake mechanism during the clock transfer data at a slow speed, also solved the problem that needs infinitely great spatial cache when using fifo interface simultaneously.Apparatus of the present invention are provided with different port numbers through the different fast slow rate of coupling, just can be so that the clock zone data are transferred to clock zone at a slow speed like clockwork fast, and efficiency of transmission is high.
With the compared with techniques that existing employing FIFO realizes, the inventive method is owing to the restriction of the sky that is not similar to FIFO/full scale will control, so the mode of its control is more simple.When hardware is realized, can not resemble yet and limited by certain process the FIFO, thereby further improve the efficient of transfer of data.
In the technical scheme of apparatus of the present invention be with 61.44 megahertzes as the data input clock, explain as this concrete embodiment that uses of data output clock with 50 megahertzes.But obviously, the method and apparatus of this patent description is suitable at any clock zone at a slow speed the next transfer of data of arbitrarily quick clock zone transmission.Such as can the inventive method being applied on the transfer of data of discontinuous business such as voice.It should be noted that apparatus of the present invention according to different data input clock frequencies and data output clock frequency, need to change data channel quantity wherein.
Claims (14)
1. asynchronous clock data transmission device comprises:
Global clock counting unit is used to indicate the sequence number of the input data that derive from the fast source clock zone;
Multichannel distributes and control unit, links to each other with said global clock counting unit, disposes a plurality of data channel, is used for according to said data sequence number, circularly to said sampling input data;
Synchronous control unit links to each other with control unit with said multichannel distribution, is used for the said data sync that samples is arrived target clock territory at a slow speed;
The word module units links to each other with said synchronous control unit, is used for the data set of said synchronous control unit after synchronously dressed up assembling data and output.
2. device as claimed in claim 1 is characterized in that, each data channel in said multichannel distribution and the control unit is carried out said sampling under enable signal effect separately.
3. device as claimed in claim 1 is characterized in that, said multichannel distributes the data channel number with control unit, confirms through emulation according to the frequency of said source clock zone and the frequency in said target clock at a slow speed territory.
4. device as claimed in claim 1 is characterized in that, said synchronous control unit synchronously, adopt two carrying out shake communication mechanism.
5. device as claimed in claim 1 is characterized in that, said word module units is further used for after said each assembling data assembling is accomplished, all generating the marking signal that said assembling data assembling is accomplished, and is used to indicate said assembling data assembling to accomplish.
6. device as claimed in claim 1; It is characterized in that; Said word module units is when carrying out said assembling, and said data set after is synchronously dressed up the number of said assembling data, confirms according to said source clock zone frequency and said target clock at a slow speed territory frequency.
7. device as claimed in claim 1 is characterized in that, further comprises the digital signal processor interface unit, links to each other with said word module units, for said device provides data output interface.
8. asynchronous clock data transmission method comprises step:
(1) indication derives from the sequence number of the input data of fast source clock zone;
(2) according to said data sequence number, through a plurality of data channel circularly to said sampling input data;
(3) the said data sync that samples is arrived target clock territory at a slow speed;
(4) said data set after is synchronously dressed up assembling data and output.
9. method as claimed in claim 8 is characterized in that, in the said step (2), said sampling is carried out under the enable signal control separately of said a plurality of data channel.
10. method as claimed in claim 8 is characterized in that, in the said step (2), said data channel number is confirmed through emulation according to the frequency of said source clock zone and the frequency in said target clock at a slow speed territory.
11. method as claimed in claim 8 is characterized in that, and is said synchronous in the said step (3), adopts two carrying out shake communication mechanism.
12. method as claimed in claim 8 is characterized in that, in the said step (4), said data set after is synchronously dressed up the number of said assembling data, confirms according to said source clock zone frequency and said target clock at a slow speed territory frequency.
13. method as claimed in claim 8 is characterized in that, in the said step (4), after said each assembling data assembling after is synchronously accomplished, further generates the marking signal that the data assembling is accomplished, and indicates said assembling data assembling to accomplish.
14. method as claimed in claim 8 is characterized in that, further comprises step:
(5) said assembling data output to a data output interface and supply the said assembling data of external call.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007100911527A CN101136855B (en) | 2007-04-10 | 2007-04-10 | Asynchronous clock data transmission device and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007100911527A CN101136855B (en) | 2007-04-10 | 2007-04-10 | Asynchronous clock data transmission device and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101136855A CN101136855A (en) | 2008-03-05 |
| CN101136855B true CN101136855B (en) | 2012-04-18 |
Family
ID=39160698
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2007100911527A Expired - Fee Related CN101136855B (en) | 2007-04-10 | 2007-04-10 | Asynchronous clock data transmission device and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101136855B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104639410A (en) * | 2013-11-13 | 2015-05-20 | 沈阳高精数控技术有限公司 | Design method of field bus optical fiber communication interface |
| CN105988959B (en) * | 2015-02-13 | 2021-06-01 | 中兴通讯股份有限公司 | Asynchronous data transmission method and system |
| CN109525350B (en) * | 2018-10-12 | 2020-04-10 | 福建星云电子股份有限公司 | Module synchronization control method based on asynchronous serial port synchronization source |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1560868A (en) * | 2004-02-10 | 2005-01-05 | 中国科学院计算技术研究所 | Implementing asynchronous first-in first-out data transmission by double-port direct access storage device |
| WO2006002374A1 (en) * | 2004-06-24 | 2006-01-05 | Teradyne, Inc. | Synchronization between low frequency and high frequency digital signals |
| CN1841978A (en) * | 2005-04-01 | 2006-10-04 | 大唐电信科技股份有限公司 | Method and apparatus for realizing multipath signal re-timing |
-
2007
- 2007-04-10 CN CN2007100911527A patent/CN101136855B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1560868A (en) * | 2004-02-10 | 2005-01-05 | 中国科学院计算技术研究所 | Implementing asynchronous first-in first-out data transmission by double-port direct access storage device |
| WO2006002374A1 (en) * | 2004-06-24 | 2006-01-05 | Teradyne, Inc. | Synchronization between low frequency and high frequency digital signals |
| CN1841978A (en) * | 2005-04-01 | 2006-10-04 | 大唐电信科技股份有限公司 | Method and apparatus for realizing multipath signal re-timing |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101136855A (en) | 2008-03-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8724665B2 (en) | Pseudo-synchronous time division multiplexing | |
| US10355851B2 (en) | Methods and systems for synchronization between multiple clock domains | |
| US7082504B2 (en) | Method and apparatus for asynchronous read control | |
| US7945803B2 (en) | Clock generation for multiple clock domains | |
| KR950006564A (en) | Two-Point Interconnect Communication Utility | |
| CN104022775A (en) | FIFO protocol based digital interface circuit for SerDes technology | |
| CN101611454A (en) | The ID that is used for the device of serial interlinkage produces equipment and method | |
| EP0826179A1 (en) | Source synchronous clocked data link | |
| CN101103277A (en) | Instrument with interface for synchronization in automatic test equipment | |
| CN101103278A (en) | Automatic test system with synchronized instruments | |
| CN101836193A (en) | A kind of synchronous data bus device and data transmission method | |
| CN102123060A (en) | FPGA (Field Programmable Gate Array) based error code testing method | |
| CN101136855B (en) | Asynchronous clock data transmission device and method | |
| US20080061835A1 (en) | Synchronizing modules in an integrated circuit | |
| CN102651685A (en) | Signal delay device and method | |
| CN103324597B (en) | The scheme of crooked distortion is balanced between the passage of high speed serial digital interface | |
| CN112019194A (en) | High-speed series circuit | |
| Soderquist | Globally updated mesochronous design style | |
| CN104239246B (en) | The storage device and method of multiport function are provided | |
| CN102394808B (en) | Method and apparatus for phase adaption and frame alignment of serial media independent interface of ethernet network | |
| CN111506529B (en) | High-speed SPI instruction response circuit applied to FLASH | |
| CN101741720B (en) | Device and method for multichannel cell time slot multiplexing | |
| CN110808804A (en) | Structure and method for realizing receiving synchronization of multipath RapidIO test board cards and test equipment | |
| CN103814339A (en) | Systems and methods for asynchronous handshake-based interconnects | |
| CN202872805U (en) | A synchronizer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20151119 Address after: 518057 Nanshan District Guangdong high tech Industrial Park, South Road, science and technology, ZTE building, Ministry of Justice Patentee after: ZTE Corp. Patentee after: SANECHIPS TECHNOLOGY Co.,Ltd. Address before: 518057 Nanshan District high tech Industrial Park, Guangdong, South Road, science and technology, ZTE building, legal department Patentee before: ZTE Corp. |
|
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120418 |