CN1560868A - Implementing asynchronous first-in first-out data transmission by double-port direct access storage device - Google Patents
Implementing asynchronous first-in first-out data transmission by double-port direct access storage device Download PDFInfo
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- CN1560868A CN1560868A CNA2004100038861A CN200410003886A CN1560868A CN 1560868 A CN1560868 A CN 1560868A CN A2004100038861 A CNA2004100038861 A CN A2004100038861A CN 200410003886 A CN200410003886 A CN 200410003886A CN 1560868 A CN1560868 A CN 1560868A
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Abstract
The invention relates to a method for realizing asynchronous FIFO data transmission with dual port random access memory. The invention designs a bridge FIFO for asynchronous data transmission, the new FIFO is based on dual port RAM, the dual port RAM is packaged into a universal synchronous FIFO through synchronous control logic, and then uses a small register array to form an asynchronous interface. The steps are: S1: uses dual port RAM to form a universal asynchronous FIFO, S2: determines the data clock region, S3: reads the data, S4: realizes asynchronous data transmission. The FIFO designed with the invention, it can provide the quantity of data in FIFO accurately, thus the two sides of the data transmission can start data reading and writing operations and it upgrades the data transmission efficiency effectively.
Description
Technical field
The present invention relates to special IC (ASIC) design, Design of Digital Circuit technical field, particularly a kind of method that realizes asynchronous first in first out data transmission with dual-port random access memory.
Background technology
In general, synchronization fifo ((First-In First-Out, first in first out)) is simple in structure, is easy to realize; The steering logic relative complex of asynchronous FIFO, special product on the market also has much, but can only provide full (Full) of FIFO, half-full (Half-Full) and empty (Empty) three kinds of states, the internal state that can not reflect FIFO all-sidedly and accurately, make its use be subjected to certain limitation, also be unfavorable for the raising of data transmission performance.
Summary of the invention
Designed FIFO of the present invention, be at two-port RAM (Random-Access Memory, random access memory) on the basis, two-port RAM is packaged into a general synchronization fifo, constitutes asynchronous interface with a less register array again by the synchro control logic.Use designed FIFO of the present invention, data among the FIFO what can accurately and timely provide, make the data transmission both sides can in time initiate data read-write operation, improve the efficient of data transmission effectively.
The invention technical scheme
A kind of implementation method of asynchronous FIFO realizes asynchronous FIFO with two-port RAM and steering logic.
Can realize the two-way burst transfer of high amount of traffic between the different clocks source.
Can accurately and timely provide what of data among the FIFO, make the data transmission both sides can in time initiate data read-write operation, improve the efficient of data transmission effectively.
Description of drawings
Figure one is a universal synchronous FIFO who realizes with two-port RAM.
Figure two is structural drawing of register array unit.
Figure three is the inventive method realization flow figure.
Embodiment
Can be divided into two steps realization asynchronous FIFO with the bridge joint FIFO in the two-port RAM structure asynchronous data transfer.
The first step is that shown in figure one, all signals all are operated in a clock zone among the figure with general synchronization fifo of two-port RAM structure, and this clock zone is identical with outside (data transmission both sides) two clock sources medium velocity the higher person.
Second step was on general synchronization fifo, constituted asynchronous interface with a less register array.The width of register array equates with the data width of FIFO, and adds the status indication register; The degree of depth of register array decides according to the gap ratio of asynchronous clock domain.In fact, the degree of depth is that the register array of n is to be the little FIFO that 1 register array is concatenated into by n the degree of depth, therefore, is the degree of depth that 1 register array is defined as the register array unit.
Among the figure one, two ports of two-port RAM are defined as data-in port and data-out port respectively, write pointer is the address signal of data-in port, and read pointer is the address signal of data-out port.When write signal was effective, the read-write steering logic added 1 to write pointer; When read signal was effective, the read-write steering logic added 1 to read pointer.According to read pointer and write pointer size, the read-write steering logic can provide what and empty/full state of data volume in the two-port RAM in real time.
Among the figure two, the register array unit comprises two flag register R
F1And R
F2And data temporary register R
1, R
2..., and R
nThe input and output of register array unit are operated in two different clock zones, and its work clock is respectively CLK_IN and CLK_OUT.Write fashionablely when the data of input end, data are temporarily stored in register R with input clock CLK_IN
1, R
2..., and R
nIn, while flag register R
F1Put 1.Flag register R
F1Output write flag register R with clock CLK_OUT
F2When data output end detects flag register R
F2When being output as 1 (ready (RDY)), import data and stably be latched in temporary register R already this moment
1, R
2..., and R
nIn, can read it with clock CLK_OUT and read signal, in sense data, flag register R
F1And R
F2Be cleared.When a plurality of register array unit strings are linked to be a little FIFO, just can realize the burst transfer of different clock-domains high amount of traffic.
Realization flow described in the figure three can be divided into S1, S2, S3 and four steps of S4, is respectively described below: step S1: with general synchronization fifo of two-port RAM structure, specifically shown in figure one.Step S2: if the clock frequency in data source territory greater than the clock frequency in datum target territory, synchronization fifo is operated in the data source clock zone, and at asynchronous register array of output termination of synchronization fifo; Otherwise, synchronization fifo is operated in the datum target clock zone, and at asynchronous register array of input termination of synchronization fifo, the width of asynchronous register array equates with the data width of synchronization fifo, the degree of depth of register array decides according to the frequency and the phase differential of asynchronous clock domain, frequency and phase differential are big more, and the degree of depth of register array is big more; When frequency and phase differential approached 0, the degree of depth of register array was equal to or greater than 3 (at this moment could guarantee the uninterrupted flowing water transmission of data); Step S3: when the clock frequency in data source territory during greater than the clock frequency in datum target territory, the register array of synchronization fifo output terminal has the data pre-fetching ability, promptly as long as have data and register array that idle register array unit is arranged in the synchronization fifo, all in time from the synchronization fifo prefetch data to register array, and provide the data ready sign; When the clock frequency in data source territory during less than the clock frequency in datum target territory, as long as in the register array of synchronization fifo input end data are arranged, all read in time in the synchronization fifo, register array provides idle marker simultaneously; Step S4: abovely two-port RAM is packaged into a general synchronization fifo by the synchro control logic, constitute asynchronous interface with an asynchronous register array again, thereby realize the method for asynchronous FIFO function, as long as the asynchronous register array has the enough big degree of depth, just can guarantee that the big flow of asynchronous data transmits continuously.
Claims (5)
1. the implementation method of an asynchronous FIFO is characterized in that, realizes asynchronous FIFO with two-port RAM and steering logic.
2. the implementation method of asynchronous FIFO according to claim 1 is characterized in that, can realize the two-way burst transfer of high amount of traffic between the different clocks source.
3. the implementation method of asynchronous FIFO according to claim 1 is characterized in that, data among the FIFO what can accurately and timely provide, and makes the data transmission both sides can in time initiate data read-write operation, improves the efficient of data transmission effectively.
4. realize the method for bridge joint FIFO in the asynchronous data transfer with two-port RAM, on the basis of two-port RAM, by the synchro control logic two-port RAM is packaged into a general synchronization fifo, constitutes asynchronous interface with a less register array again.
5. according to the method that realizes bridge joint FIFO in the asynchronous data transfer of claim 4 with two-port RAM, its concrete steps are as follows: step S1: with general synchronization fifo of two-port RAM structure; Step S2: if the clock frequency in data source territory greater than the clock frequency in datum target territory, synchronization fifo is operated in the data source clock zone, and at asynchronous register array of output termination of synchronization fifo; Otherwise, synchronization fifo is operated in the datum target clock zone, and at asynchronous register array of input termination of synchronization fifo, the width of asynchronous register array equates with the data width of synchronization fifo, the degree of depth of register array decides according to the frequency and the phase differential of asynchronous clock domain, frequency and phase differential are big more, and the degree of depth of register array is big more; When frequency and phase differential approached 0, the degree of depth of register array was equal to or greater than 3; Step S3: when the clock frequency in data source territory during greater than the clock frequency in datum target territory, the register array of synchronization fifo output terminal has the data pre-fetching ability, promptly as long as have data and register array that idle register array unit is arranged in the synchronization fifo, all in time from the synchronization fifo prefetch data to register array, and provide the data ready sign; When the clock frequency in data source territory during less than the clock frequency in datum target territory, as long as in the register array of synchronization fifo input end data are arranged, all read in time in the synchronization fifo, register array provides idle marker simultaneously; Step S4: abovely two-port RAM is packaged into a general synchronization fifo by the synchro control logic, constitute asynchronous interface with an asynchronous register array again, thereby realize the method for asynchronous FIFO function, as long as the asynchronous register array has the enough big degree of depth, just can guarantee that the big flow of asynchronous data transmits continuously.
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| CNB2004100038861A CN100424663C (en) | 2004-02-10 | 2004-02-10 | Implementing asynchronous first-in first-out data transmission by double-port direct access storage device |
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| CN1560868A true CN1560868A (en) | 2005-01-05 |
| CN100424663C CN100424663C (en) | 2008-10-08 |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100395680C (en) * | 2005-05-26 | 2008-06-18 | 华为技术有限公司 | Configuration method and device for asynchronous clock field parameter |
| CN100463443C (en) * | 2005-07-01 | 2009-02-18 | 中兴通讯股份有限公司 | Asynchronous FIFO realizing system and realizing method |
| CN100465934C (en) * | 2006-05-09 | 2009-03-04 | 华为技术有限公司 | Device and method for transmitting data in asynchronous clock domain |
| CN101232434B (en) * | 2007-01-22 | 2011-08-24 | 中兴通讯股份有限公司 | Apparatus for performing asynchronous data transmission with double port RAM |
| CN101136855B (en) * | 2007-04-10 | 2012-04-18 | 中兴通讯股份有限公司 | Asynchronous clock data transmission device and method |
| CN102609235A (en) * | 2011-01-25 | 2012-07-25 | 中兴通讯股份有限公司 | Method and system for updating data after data reading of double-port RAM (random-access memory) |
| CN102723108A (en) * | 2012-05-23 | 2012-10-10 | 常州芯奇微电子科技有限公司 | Asynchronous FIFO memory for clocks |
| CN105373663A (en) * | 2015-11-17 | 2016-03-02 | 无锡江南计算技术研究所 | Method for realizing asynchronous buffer with entry occupation indication function |
| CN111274171A (en) * | 2018-12-04 | 2020-06-12 | 珠海格力电器股份有限公司 | Data transmission device and method |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5550780A (en) * | 1994-12-19 | 1996-08-27 | Cirrus Logic, Inc. | Two cycle asynchronous FIFO queue |
| JP3013800B2 (en) * | 1997-01-30 | 2000-02-28 | 日本電気株式会社 | Asynchronous FIFO circuit |
| DE19812917A1 (en) * | 1998-03-24 | 1999-09-30 | Siemens Ag | Asynchronous FIFO memory |
| CN1253894C (en) * | 2002-01-23 | 2006-04-26 | 华为技术有限公司 | Method for realizing two first-in first-out queue using one double-port RAM |
| CN1201234C (en) * | 2003-03-28 | 2005-05-11 | 港湾网络有限公司 | Multichannel FILO data buffer storage devices |
-
2004
- 2004-02-10 CN CNB2004100038861A patent/CN100424663C/en not_active Expired - Fee Related
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100395680C (en) * | 2005-05-26 | 2008-06-18 | 华为技术有限公司 | Configuration method and device for asynchronous clock field parameter |
| CN100463443C (en) * | 2005-07-01 | 2009-02-18 | 中兴通讯股份有限公司 | Asynchronous FIFO realizing system and realizing method |
| CN100465934C (en) * | 2006-05-09 | 2009-03-04 | 华为技术有限公司 | Device and method for transmitting data in asynchronous clock domain |
| CN101232434B (en) * | 2007-01-22 | 2011-08-24 | 中兴通讯股份有限公司 | Apparatus for performing asynchronous data transmission with double port RAM |
| CN101136855B (en) * | 2007-04-10 | 2012-04-18 | 中兴通讯股份有限公司 | Asynchronous clock data transmission device and method |
| CN102609235A (en) * | 2011-01-25 | 2012-07-25 | 中兴通讯股份有限公司 | Method and system for updating data after data reading of double-port RAM (random-access memory) |
| CN102609235B (en) * | 2011-01-25 | 2014-08-20 | 中兴通讯股份有限公司 | Method and system for updating data after data reading of double-port RAM (random-access memory) |
| CN102723108A (en) * | 2012-05-23 | 2012-10-10 | 常州芯奇微电子科技有限公司 | Asynchronous FIFO memory for clocks |
| CN105373663A (en) * | 2015-11-17 | 2016-03-02 | 无锡江南计算技术研究所 | Method for realizing asynchronous buffer with entry occupation indication function |
| CN105373663B (en) * | 2015-11-17 | 2018-06-26 | 无锡江南计算技术研究所 | A kind of asynchronous buffer implementation method that instruction is occupied with entry |
| CN111274171A (en) * | 2018-12-04 | 2020-06-12 | 珠海格力电器股份有限公司 | Data transmission device and method |
| CN111274171B (en) * | 2018-12-04 | 2022-02-11 | 珠海格力电器股份有限公司 | Data transmission device and method |
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| CN100424663C (en) | 2008-10-08 |
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