CN101123242A - 制造通孔和电子器件的方法 - Google Patents

制造通孔和电子器件的方法 Download PDF

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CN101123242A
CN101123242A CNA2007101402685A CN200710140268A CN101123242A CN 101123242 A CN101123242 A CN 101123242A CN A2007101402685 A CNA2007101402685 A CN A2007101402685A CN 200710140268 A CN200710140268 A CN 200710140268A CN 101123242 A CN101123242 A CN 101123242A
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T·J·谢纳尔
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Abstract

一种电子器件包括：包括第一热膨胀系数(CTE)的至少一个电子芯片，和通过焊料凸起将芯片的顶侧连接到底侧的载体。所述载体还包括近似匹配所述第一CTE的第二CTE，和从载体的底侧至载体层的顶侧的多个通孔。每个通孔包括在载体的顶表面处暴露的环垫、在载体的底表面处暴露的衬垫、以及在环垫与衬垫之间设置的柱。所述柱延伸通过一定体积的空间。

Description

制造通孔和电子器件的方法
技术领域
本发明的公开宽泛地涉及信息处理***的领域，更具体而言涉及场微电子封装技术。
背景技术
微电子芯片封装使用倒装技术将芯片安装到芯片载体基板上从而提供芯片的高密度互连或空间转换以便能够将IC(集成电路)安装到印刷电路板上。芯片封装的***性能和成本需求驱使着设计者使用低成本有机芯片载体代替更昂贵的陶瓷或玻璃材料。然而，有机芯片载体与硅集成电路芯片之间的热膨胀系数(CTE)失配是一个挑战。在工作期间由环境温度漂移和引起芯片封装结构中温度变化的由芯片产生的热所引起的热膨胀系数失配造成了组件之间的机械应力。
使用有机芯片载体的解决方案包括在芯片和第一级封装之间的环氧树脂底部填充以减少在可控塌陷芯片连接(C4)互连上的表面应变。此外，早先已经提出了解决方案以构建柔性(compliant)互连。因此，需要制造低成本柔性互连。
此外，已经提出发展极高密度硅芯片载体作为IC和下级封装之间的中间***物以提供极高互连密度和对于硅芯片的CTE匹配。这将减少在硅芯片与CTE匹配的硅芯片载体之间的C4焊料互连上的热引起的应力，并能减小C4的尺寸和增加的I/O密度。然而，在下级封装是有机基板的情况下，硅芯片载体的CTE将不会匹配到有机基板，这将导致在载体与下层封装之间的C4焊料互连上的应力。因此，存在提供在硅芯片载体与下层封装之间的柔性的需要。
发明内容
根据本发明的实施例，通过提供柔性的通孔结构实现一种用于向由硅或另一CTE匹配的材料制造的芯片载体并入柔性的方法和***。
在本发明的另一实施例中，通过将柔性结构并入到芯片基板自身中实现在所述芯片与所述下级封装之间的柔性。
附图说明
图1是根据本发明的实施例的硅***物的图；
图2示出了根据本发明的实施例的柔性互连；
图3A-L示出了用柔性材料制造通孔的方法；
图4A-O示出了用空隙制造通孔以形成柔性的方法；
图5A-C示出了在硅芯片中制造的集成柔性；
图6示出了安装在有机基板上的芯片；
图7示出了沿纵和垂直方向都提供柔性的柔性互连；以及
图8示出了其它更复杂的几何形状例如S形柱和L形柱。
具体实施方式
高密度芯片载体的发展包括与芯片CTE匹配的材料例如硅或陶瓷以提供较高互连密度和带宽。如图1所示，硅芯片载体104提供与硅芯片102CTE匹配的基板。这将减少在硅芯片与CTE匹配的硅芯片载体之间的C4微连接焊料互连上的热引起的应力，并能减小C4的尺寸和增加的I/O密度。硅芯片载体使用通孔和C4焊料互连为功率、地和信号提供到达下级封装的通路。在下级封装是有机基板的情况下，硅芯片载体的CTE将不会匹配到有机基板，这将导致C4焊料互连上的应力。因此，存在提供在硅芯片载体与下层封装之间的柔性的需要。
参考图1，示出了根据本发明的实施例的芯片封装100的图。芯片封装包括两个电子芯片102，其顶侧通过焊料凸起连接到芯片的底侧的硅载体104。载体104还包括与芯片102的CTE近似匹配的CTE。根据本发明的实施例，载体104包括从载体的底侧到载体的顶侧的多个柔性通孔107。
参考图2，示出了通孔107的结构。每个通孔结构107包括在载体204的顶表面处暴露的导电(优选铜)通孔环垫(collar)202。在载体204的底表面暴露优选铜衬垫212，和在环垫202与衬垫212之间设置优选铜通孔柱206。
CTE匹配的芯片载体204由其中通孔提供柔性和通路以同时增加I/O密度和对有机基板216的互连柔性的材料例如硅制造。例如，硅的CTE约3ppm(百万分之)和有机基板处于13-15ppm之间。对于50℃的温度变化40mm平方的载体产生的CTE失配将导致载体与有机基板之间的约10微米的横向位移。
导电铜结构延伸通过硅载体基板204中的孔208。用低模量材料填充孔。将铜环垫202接合到硅芯片载体204的顶表面并将其附装到铜柱206，又将所述铜柱206附装到支撑铜衬垫/BLM(球限冶金)212的铜微衬垫。例如，这样产生C4焊料微连接210：在铜衬垫/BLM(球限冶金)212上镀敷铅锡焊料球，然后熔化铅锡焊料球以将212连接到在下级封装结构上的匹配焊料接合衬垫/TSM(顶表面冶金)214，其中所述下级封装结构在该情况下是有机基板216。
因为通过孔的铜柱206自由浮动在硅芯片载体204中或者由柔性材料软支撑，因此相对有机基板216的硅芯片载体204的热膨胀将导致沿纵向的铜柱206的挠曲。该柔性将减小在C4焊料微连接210上的热机械引起的应力，该C4焊料微连接210连接铜衬垫/BLM 212与焊料衬垫/TSM 214以制造硅载体204与下级封装有机基板216之间的电连接。
图7中示出了提供沿垂直和纵向具有柔性的通孔结构的方法。在该实施例中，以相对于垂直安装方向的角度θ718制造铜柱708。例如，角度可以处于30至45度之间。响应垂直力，柱将弯曲以提供沿垂直方向的柔性同时提供沿纵向的柔性。虽然对于倾斜柱的实施例示出了实例，但也可以使用图8中所示出的其它更复杂的几何形状例如S形柱800或L形柱802提供沿所有方向的柔性。
具有软材料的柔性通孔
在图3A-L中示出了根据本发明的另一实施例的一种使用软材料制造柔性通孔的方法。在步骤302中用光致抗蚀剂构图硅。在步骤304中使用公知的深RIE(反应离子蚀刻)方法在硅晶片中蚀刻环孔(annulus)。在蚀刻后，如步骤306中所示使用热生长的氧化物隔离通孔。在步骤308中用柔性材料填充环孔，例如该柔性材料可以为具有比硅的模量低得多的模量的光致抗蚀剂或环氧树脂。在步骤310中再次构图硅，随后是去除氧化物的RIE和去除硅中心柱的DRIE(深反应离子蚀刻)。在步骤314中再次构图硅，和在步骤316中镀敷铜以形成通孔环垫和柱。在步骤318中研磨并抛光晶片的背侧以暴露铜柱。在步骤320中构图晶片的背侧，和在步骤322中镀敷形成铜衬垫和BLM。在步骤324中使用镀敷或者其它转移方法将C4焊料突起制造到BLM上。
具有间隙的柔性通孔
在图4中示出了根据本发明的另一实施例的一种在间隙中制造通孔的方法。在步骤402中使用光致抗蚀剂构图硅基板和在步骤404中用深反应离子蚀刻环状通孔。在步骤406中在每个环状通孔的表面和侧壁上生长热氧化物，和在步骤408中用多晶硅填充每个环状通孔。在步骤410中平面化基板，和在步骤412中生长氧化物。在步骤414中用光致抗蚀剂构图顶表面，和在步骤416中蚀刻氧化物和硅至超过多晶硅环状通孔的深度。在步骤418中构图顶表面并用铜镀敷顶表面以形成通孔环垫和柱。在步骤420中研磨、抛光并蚀刻晶片的背侧以暴露铜通孔柱。在步骤422中构图晶片的背侧，和在步骤424中镀敷铜衬垫和BLM。在步骤426中构图晶片的背侧以暴露围绕铜通孔的硅。在步骤428中选择性地例如用二氟化氙蚀刻围绕铜柱的硅。
在通孔壁上的氧化硅提供蚀刻停止并且二氟化氙去除围绕铜柱的硅以限定间隙。在步骤430中使用镀敷或者其它转移方法将焊料突起制造到BLM结构上，导致在硅基板内自由浮动的通孔柱。这允许通孔柱的柔性。
总之，可以使用结合提供柔性的集成通孔技术的与硅CTE匹配的硅芯片载体，以提供用于***集成的高密度I/O和增加的柔性的技术方案。尽管上述描述针对硅芯片载体，但是可以使用接近匹配硅的CTE并允许加工通孔的任何材料。
如图1和2所示，使用硅***物(或载体)的另一选择为直接将柔性互连并入到硅芯片中。如图5A所示，硅器件包括这样的硅基板500，其包括有源器件层502和几个BEOL(后段制程)金属互连层504，所述金属互连层504包括C4衬垫506，所述C4衬垫506承载将芯片附装到下级封装的焊料凸起508。如图6中所示，将芯片602直接附装到有机载体基板606。在该情况下，通过C4焊料微连接604的柔性确定在芯片602与下级封装606之间的柔性。在BEOL布线结构上产生的热机械应力将依赖相对于载体的芯片的CTE失配、相对于载体的芯片的温度Δ和微连接的柔性。
如图5B中所示，可以将柔性互连结构510集成到在硅基板516上制造的具有有源器件512的硅芯片中，该硅基板516包括通孔518、520以将BEOL布线510连接到C4衬垫522。在该情况下，通过与C4微连接的柔性串联的通孔柔性确定位于芯片与下级封装之间的柔性。通孔铜环垫514附装到硅基板516而不是BEOL布线510。结果，归因于相对于基板的芯片的CTE失配的热机械应力没有被直接施加到BEOL布线层而是施加到C4微连接和通孔。
设计图5B中的通孔柔性以满足封装的需要。在需要通孔柔性的情况下，这可以通过在520所示出的间隙或低模量材料内的铜柱实现。在热机械应力处于C4微连接与硅载体基板的可接受的应力范围的情况下，通孔的柔性需要近乎为零，这可以通过并入518中所示出的用铜完全填充而没有间隙或低柔性材料的通孔实现。
图5B的附加的设计有益效果为消除了硅基板500至图6中示出的热沉608的热阻抗。
图5C中示出的第二制造选择使用例如“绝缘体上硅”技术将有源器件532设置在BEOL布线534的顶上。在该情况下，通孔不通过有源器件区域从而提供用于电路制造的更多的硅区域。通孔环垫536附装到硅基板530以减少热机械应力在BEOL上的效果。如图5B中所示，依赖柔性需要，通孔可以具有间隙或者低模量材料538或者为完全填充540。也可以通过将有源层532设置在芯片结构的最顶表面处消除图5A中示出的硅基板500和图5B中示出的BEOL布线510的热阻抗，由此产生更有效的热通路。
因此，虽然已经描述了目前认为是优选的实施例，但本领域的技术人员将理解在本发明的精神内可以做出其它的修改。

Claims (17)

1.一种电子器件，包括：
至少一个电子芯片，其包括顶侧、底侧、和第一热膨胀系数；以及
载体，其包括底侧和顶侧，所述顶侧连接到所述芯片的所述底侧，所述载体还包括近似匹配所述第一热膨胀系数的第二热膨胀系数，和从所述载体的所述底侧至所述载体层的所述顶侧的多个通孔，每个通孔包括在所述载体的顶表面处暴露的环垫，在所述载体的底表面处暴露的衬垫，和在所述环垫与所述衬垫之间设置的柱，其中所述柱延伸通过一定体积的空的空间。
2.根据权利要求1的器件，其中用低模量材料填充所述体积的空的空间。
3.根据权利要求1的器件，还包括基板，所述基板包括不匹配所述第一热膨胀系数的第三热膨胀系数，和其中通过焊料凸起将所述基板连接到所述载体的底侧。
4.根据权利要求1的器件，其中所述通孔结构包括铜材料。
5.根据权利要求1的器件，其中所述柱以不垂直于所述载体基板的角度制造。
6.根据权利要求1的器件，其中所述柱包括曲线部分。
7.根据权利要求3的器件，其中所述基板由有机材料构成。
8.一种在硅载体中制造柔性通孔的方法，所述方法包括以下步骤：
构图所述硅载体；
使用深反应离子蚀刻方法在所述硅载体中蚀刻环孔；
使用热生长氧化物以隔离所述通孔；
用柔性材料填充所述环孔；
构图所述硅；
进行反应离子蚀刻以去除所述氧化物和深反应离子蚀刻以去除硅中心柱；
再次构图所述硅以在所述硅中形成通孔；
铜镀敷所述硅以形成通孔环垫和柱；
研磨所述载体的背侧以暴露铜柱；
构图所述载体的背侧和镀敷所述载体以形成铜衬垫和球限冶金；以及
使用镀敷或其它转移方法在所述球限冶金上形成焊料凸起。
9.根据权利要求8的方法，其中用低模量材料填充所述环孔。
10.根据权利要求8的方法，其中用光致抗蚀剂填充所述环孔。
11.一种在载体中制造通孔的方法，包括以下步骤：
构图硅基板；
通过深反应离子蚀刻在所述基板中蚀刻环状通孔；
在所述基板上生长热氧化物；
用多晶硅填充所述环状通孔；
平面化和氧化所述基板；
用光致抗蚀剂构图所述基板的顶表面；
蚀刻所述基板的氧化物和硅至超过所述多晶硅环状通孔的深度；
构图所述顶表面并用铜镀敷以形成通孔环垫和柱；
减薄所述晶片的背侧以暴露铜通孔柱；
构图所述晶片的背侧；
镀敷所述铜衬垫和球限冶金；
构图所述晶片的背侧以暴露围绕所述铜通孔的硅；以及
用二氟化氙蚀刻围绕所述铜柱的硅。
12.一种硅芯片，包括：
硅基板，包括有源器件层，和连接到所述有源器件的后段制程布线，多个衬垫，以及将所述后段制程布线连接到衬垫的多个通孔。
13.根据权利要求12的硅芯片，其中用导电材料完全地填充所述通孔。
14.根据权利要求12的硅芯片，其中所述通孔延伸通过一定体积的空的空间或低模量材料。
15.根据权利要求12的硅芯片，其中所述通孔包括以不垂直于所述硅基板的角度制造的柱。
16.一种包括顶部和底部的硅芯片，所述硅芯片包括：
硅基板，包括在所述硅芯片的所述顶部处的有源器件层，和在所述有源器件下连接的后段制程布线，在所述硅芯片的所述底部上的多个衬垫，以及将所述后段制程布线连接到衬垫的多个通孔。
17.根据权利要求16的硅芯片，其中使用绝缘体上硅技术在所述有源器件下连接所述后段制程布线。
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Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102446883A (zh) * 2011-12-12 2012-05-09 清华大学 一种通用封装基板、封装结构和封装方法
CN102470505A (zh) * 2009-07-16 2012-05-23 圣戈班磨料磨具有限公司 用于修整cmp垫的具有平且一致平面形貌的研磨工具及制造方法
CN102593102A (zh) * 2010-12-01 2012-07-18 海力士半导体有限公司 半导体芯片、堆叠型半导体封装体及其制造方法
CN103378017A (zh) * 2012-04-24 2013-10-30 辉达公司 高密度3d封装
CN103855135A (zh) * 2012-11-30 2014-06-11 辉达公司 三维硅穿孔构建
CN105122448A (zh) * 2012-09-13 2015-12-02 伊文萨思公司 可调复合中介层
CN110915306A (zh) * 2017-07-18 2020-03-24 西门子股份公司 电气组件和用于制造电气组件的方法
CN112038321A (zh) * 2020-08-10 2020-12-04 唯捷创芯(天津)电子技术股份有限公司 金属过孔连接封装结构、基板及封装方法
CN113113375A (zh) * 2021-04-09 2021-07-13 中国科学技术大学 一种用于毫米波频段芯片封装的垂直互连结构
CN114487788A (zh) * 2022-04-02 2022-05-13 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） 封装器件的失效定位方法

Families Citing this family (78)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7473577B2 (en) * 2006-08-11 2009-01-06 International Business Machines Corporation Integrated chip carrier with compliant interconnect
US8067814B2 (en) * 2007-06-01 2011-11-29 Panasonic Corporation Semiconductor device and method of manufacturing the same
US8043893B2 (en) 2007-09-14 2011-10-25 International Business Machines Corporation Thermo-compression bonded electrical interconnect structure and method
US7868457B2 (en) * 2007-09-14 2011-01-11 International Business Machines Corporation Thermo-compression bonded electrical interconnect structure and method
US7550853B2 (en) * 2007-10-10 2009-06-23 Itt Manufacturing Enterprises, Inc. Electrical isolation of monolithic circuits using a conductive through-hole in the substrate
US7473618B1 (en) 2008-04-22 2009-01-06 International Business Machines Corporation Temporary structure to reduce stress and warpage in a flip chip organic package
TWI573201B (zh) * 2008-07-18 2017-03-01 聯測總部私人有限公司 封裝結構性元件
KR20100037300A (ko) * 2008-10-01 2010-04-09 삼성전자주식회사 내장형 인터포저를 갖는 반도체장치의 형성방법
JP5308145B2 (ja) * 2008-12-19 2013-10-09 ルネサスエレクトロニクス株式会社 半導体装置
JP2010238821A (ja) * 2009-03-30 2010-10-21 Sony Corp 多層配線基板、スタック構造センサパッケージおよびその製造方法
WO2014011232A1 (en) 2012-07-12 2014-01-16 Hsio Technologies, Llc Semiconductor socket with direct selective metalization
US8955215B2 (en) 2009-05-28 2015-02-17 Hsio Technologies, Llc High performance surface mount electrical interconnect
WO2011153298A1 (en) 2010-06-03 2011-12-08 Hsio Technologies, Llc Electrical connector insulator housing
WO2011139619A1 (en) 2010-04-26 2011-11-10 Hsio Technologies, Llc Semiconductor device package adapter
US9276336B2 (en) 2009-05-28 2016-03-01 Hsio Technologies, Llc Metalized pad to electrical contact interface
US9318862B2 (en) 2009-06-02 2016-04-19 Hsio Technologies, Llc Method of making an electronic interconnect
US9276339B2 (en) 2009-06-02 2016-03-01 Hsio Technologies, Llc Electrical interconnect IC device socket
US8525346B2 (en) * 2009-06-02 2013-09-03 Hsio Technologies, Llc Compliant conductive nano-particle electrical interconnect
US8789272B2 (en) 2009-06-02 2014-07-29 Hsio Technologies, Llc Method of making a compliant printed circuit peripheral lead semiconductor test socket
WO2011002709A1 (en) 2009-06-29 2011-01-06 Hsio Technologies, Llc Compliant printed circuit semiconductor tester interface
US9277654B2 (en) 2009-06-02 2016-03-01 Hsio Technologies, Llc Composite polymer-metal electrical contacts
US8610265B2 (en) 2009-06-02 2013-12-17 Hsio Technologies, Llc Compliant core peripheral lead semiconductor test socket
US8928344B2 (en) 2009-06-02 2015-01-06 Hsio Technologies, Llc Compliant printed circuit socket diagnostic tool
WO2010141296A1 (en) 2009-06-02 2010-12-09 Hsio Technologies, Llc Compliant printed circuit semiconductor package
US8955216B2 (en) 2009-06-02 2015-02-17 Hsio Technologies, Llc Method of making a compliant printed circuit peripheral lead semiconductor package
US9232654B2 (en) 2009-06-02 2016-01-05 Hsio Technologies, Llc High performance electrical circuit structure
US9231328B2 (en) 2009-06-02 2016-01-05 Hsio Technologies, Llc Resilient conductive electrical interconnect
US9699906B2 (en) 2009-06-02 2017-07-04 Hsio Technologies, Llc Hybrid printed circuit assembly with low density main core and embedded high density circuit regions
US8987886B2 (en) 2009-06-02 2015-03-24 Hsio Technologies, Llc Copper pillar full metal via electrical circuit structure
US9613841B2 (en) 2009-06-02 2017-04-04 Hsio Technologies, Llc Area array semiconductor device package interconnect structure with optional package-to-package or flexible circuit to package connection
US9930775B2 (en) 2009-06-02 2018-03-27 Hsio Technologies, Llc Copper pillar full metal via electrical circuit structure
US8988093B2 (en) 2009-06-02 2015-03-24 Hsio Technologies, Llc Bumped semiconductor wafer or die level electrical interconnect
WO2012078493A1 (en) 2010-12-06 2012-06-14 Hsio Technologies, Llc Electrical interconnect ic device socket
US9196980B2 (en) 2009-06-02 2015-11-24 Hsio Technologies, Llc High performance surface mount electrical interconnect with external biased normal force loading
US9603249B2 (en) 2009-06-02 2017-03-21 Hsio Technologies, Llc Direct metalization of electrical circuit structures
WO2010141297A1 (en) 2009-06-02 2010-12-09 Hsio Technologies, Llc Compliant printed circuit wafer level semiconductor package
US9093767B2 (en) 2009-06-02 2015-07-28 Hsio Technologies, Llc High performance surface mount electrical interconnect
WO2010141311A1 (en) 2009-06-02 2010-12-09 Hsio Technologies, Llc Compliant printed circuit area array semiconductor device package
WO2010141295A1 (en) 2009-06-02 2010-12-09 Hsio Technologies, Llc Compliant printed flexible circuit
US8912812B2 (en) 2009-06-02 2014-12-16 Hsio Technologies, Llc Compliant printed circuit wafer probe diagnostic tool
WO2010147934A1 (en) 2009-06-16 2010-12-23 Hsio Technologies, Llc Semiconductor die terminal
US8803539B2 (en) 2009-06-03 2014-08-12 Hsio Technologies, Llc Compliant wafer level probe assembly
WO2010147782A1 (en) 2009-06-16 2010-12-23 Hsio Technologies, Llc Simulated wirebond semiconductor package
US9320144B2 (en) 2009-06-17 2016-04-19 Hsio Technologies, Llc Method of forming a semiconductor socket
US8044512B2 (en) * 2009-06-25 2011-10-25 International Business Machines Corporation Electrical property altering, planar member with solder element in IC chip package
US8984748B2 (en) 2009-06-29 2015-03-24 Hsio Technologies, Llc Singulated semiconductor device separable electrical interconnect
US8048794B2 (en) * 2009-08-18 2011-11-01 International Business Machines Corporation 3D silicon-silicon die stack structure and method for fine pitch interconnection and vertical heat transport
WO2011027186A1 (zh) * 2009-09-02 2011-03-10 先进封装技术私人有限公司 封装结构
TWI436470B (zh) * 2009-09-30 2014-05-01 Advanced Semiconductor Eng 封裝製程及封裝結構
US8148824B2 (en) * 2010-04-16 2012-04-03 Nanya Technology Corp. Semiconductor device with through substrate via
US8298863B2 (en) 2010-04-29 2012-10-30 Texas Instruments Incorporated TCE compensation for package substrates for reduced die warpage assembly
US9689897B2 (en) 2010-06-03 2017-06-27 Hsio Technologies, Llc Performance enhanced semiconductor socket
US9350093B2 (en) 2010-06-03 2016-05-24 Hsio Technologies, Llc Selective metalization of electrical connector or socket housing
US8758067B2 (en) 2010-06-03 2014-06-24 Hsio Technologies, Llc Selective metalization of electrical connector or socket housing
US10159154B2 (en) 2010-06-03 2018-12-18 Hsio Technologies, Llc Fusion bonded liquid crystal polymer circuit structure
CN102157438B (zh) * 2011-01-31 2013-05-01 江阴长电先进封装有限公司 晶圆级转接板的制备方法
TWI475651B (zh) * 2011-08-02 2015-03-01 Global Unichip Corp 半導體裝置與相關方法
US8780576B2 (en) * 2011-09-14 2014-07-15 Invensas Corporation Low CTE interposer
US20130154106A1 (en) 2011-12-14 2013-06-20 Broadcom Corporation Stacked Packaging Using Reconstituted Wafers
US9548251B2 (en) 2012-01-12 2017-01-17 Broadcom Corporation Semiconductor interposer having a cavity for intra-interposer die
US20130187284A1 (en) 2012-01-24 2013-07-25 Broadcom Corporation Low Cost and High Performance Flip Chip Package
US8587132B2 (en) 2012-02-21 2013-11-19 Broadcom Corporation Semiconductor package including an organic substrate and interposer having through-semiconductor vias
US8558395B2 (en) * 2012-02-21 2013-10-15 Broadcom Corporation Organic interface substrate having interposer with through-semiconductor vias
US8749072B2 (en) 2012-02-24 2014-06-10 Broadcom Corporation Semiconductor package with integrated selectively conductive film interposer
US9275976B2 (en) 2012-02-24 2016-03-01 Broadcom Corporation System-in-package with integrated socket
US8872321B2 (en) 2012-02-24 2014-10-28 Broadcom Corporation Semiconductor packages with integrated heat spreaders
US8928128B2 (en) 2012-02-27 2015-01-06 Broadcom Corporation Semiconductor package with integrated electromagnetic shielding
US9761520B2 (en) 2012-07-10 2017-09-12 Hsio Technologies, Llc Method of making an electrical connector having electrodeposited terminals
US9041205B2 (en) * 2013-06-28 2015-05-26 Intel Corporation Reliable microstrip routing for electronics components
US10667410B2 (en) 2013-07-11 2020-05-26 Hsio Technologies, Llc Method of making a fusion bonded circuit structure
US10506722B2 (en) 2013-07-11 2019-12-10 Hsio Technologies, Llc Fusion bonded liquid crystal polymer electrical circuit structure
JP5490949B1 (ja) * 2013-08-08 2014-05-14 有限会社 ナプラ 配線基板及びその製造方法
US9648754B1 (en) 2013-11-12 2017-05-09 Smart Modular Technologies, Inc. Integrated circuit device system with elevated stacked configuration and method of manufacture thereof
US9603252B1 (en) * 2013-11-12 2017-03-21 Smart Modular Technologies, Inc. Integrated circuit device system with elevated configuration and method of manufacture thereof
US9515017B2 (en) 2014-12-18 2016-12-06 Intel Corporation Ground via clustering for crosstalk mitigation
US9755335B2 (en) 2015-03-18 2017-09-05 Hsio Technologies, Llc Low profile electrical interconnect with fusion bonded contact retention and solder wick reduction
TWM555065U (zh) * 2017-09-05 2018-02-01 恆勁科技股份有限公司 電子封裝件及其封裝基板
US11195789B2 (en) 2018-11-30 2021-12-07 International Business Machines Corporation Integrated circuit module with a structurally balanced package using a bottom side interposer

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4791248A (en) * 1987-01-22 1988-12-13 The Boeing Company Printed wire circuit board and its method of manufacture
US5432999A (en) * 1992-08-20 1995-07-18 Capps; David F. Integrated circuit lamination process
US5627106A (en) * 1994-05-06 1997-05-06 United Microelectronics Corporation Trench method for three dimensional chip connecting during IC fabrication
WO1996009645A1 (fr) * 1994-09-20 1996-03-28 Hitachi, Ltd. Composant a semiconducteurs et sa structure de montage
US5973396A (en) * 1996-02-16 1999-10-26 Micron Technology, Inc. Surface mount IC using silicon vias in an area array format or same size as die array
US5777383A (en) * 1996-05-09 1998-07-07 Lsi Logic Corporation Semiconductor chip package with interconnect layers and routing and testing methods
EP0834897B1 (en) * 1996-10-04 2002-05-02 STMicroelectronics S.r.l. Method of fabricating flat field emission display screens and flat screen obtained thereby
US6809421B1 (en) * 1996-12-02 2004-10-26 Kabushiki Kaisha Toshiba Multichip semiconductor device, chip therefor and method of formation thereof
EP0860876A3 (de) * 1997-02-21 1999-09-22 DaimlerChrysler AG Anordnung und Verfahren zur Herstellung von CSP-Gehäusen für elektrische Bauteile
US7030466B1 (en) * 1999-05-03 2006-04-18 United Microelectronics Corporation Intermediate structure for making integrated circuit device and wafer
US6617681B1 (en) * 1999-06-28 2003-09-09 Intel Corporation Interposer and method of making same
JP3356122B2 (ja) * 1999-07-08 2002-12-09 日本電気株式会社 システム半導体装置及びシステム半導体装置の製造方法
JP4023076B2 (ja) * 2000-07-27 2007-12-19 富士通株式会社 表裏導通基板及びその製造方法
TW465039B (en) * 2000-11-06 2001-11-21 United Microelectronics Corp Void-type metal interconnect and method for making the same
US7074885B2 (en) * 2001-05-03 2006-07-11 E.I. Du Pont De Nemours And Company Electroactive fluorene copolymers and devices made with such polymers
JP3495727B2 (ja) * 2001-11-07 2004-02-09 新光電気工業株式会社 半導体パッケージおよびその製造方法
US6855631B2 (en) * 2003-07-03 2005-02-15 Micron Technology, Inc. Methods of forming via plugs using an aerosol stream of particles to deposit conductive materials
US7276787B2 (en) * 2003-12-05 2007-10-02 International Business Machines Corporation Silicon chip carrier with conductive through-vias and method for fabricating same
US7049170B2 (en) * 2003-12-17 2006-05-23 Tru-Si Technologies, Inc. Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities
US6943106B1 (en) * 2004-02-20 2005-09-13 Micron Technology, Inc. Methods of fabricating interconnects for semiconductor components including plating solder-wetting material and solder filling
TWI272683B (en) * 2004-05-24 2007-02-01 Sanyo Electric Co Semiconductor device and manufacturing method thereof
JP4365750B2 (ja) * 2004-08-20 2009-11-18 ローム株式会社 半導体チップの製造方法、および半導体装置の製造方法
JP4345705B2 (ja) * 2005-04-19 2009-10-14 エルピーダメモリ株式会社 メモリモジュール
US7898095B2 (en) * 2006-03-20 2011-03-01 Tezzaron Semiconductor, Inc. Fiducial scheme adapted for stacked integrated circuits
US7605019B2 (en) * 2006-07-07 2009-10-20 Qimonda Ag Semiconductor device with stacked chips and method for manufacturing thereof
US7344959B1 (en) * 2006-07-25 2008-03-18 International Business Machines Corporation Metal filled through via structure for providing vertical wafer-to-wafer interconnection
US7473577B2 (en) * 2006-08-11 2009-01-06 International Business Machines Corporation Integrated chip carrier with compliant interconnect
US7589394B2 (en) * 2007-04-10 2009-09-15 Ibiden Co., Ltd. Interposer
US7791174B2 (en) * 2008-03-07 2010-09-07 Advanced Inquiry Systems, Inc. Wafer translator having a silicon core isolated from signal paths by a ground plane
US7754601B2 (en) * 2008-06-03 2010-07-13 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor interconnect air gap formation process

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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US8721395B2 (en) 2009-07-16 2014-05-13 Saint-Gobain Abrasives, Inc. Abrasive tool with flat and consistent surface topography for conditioning a CMP pad and method for making
CN102593102A (zh) * 2010-12-01 2012-07-18 海力士半导体有限公司 半导体芯片、堆叠型半导体封装体及其制造方法
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