TWM555065U - 電子封裝件及其封裝基板 - Google Patents
電子封裝件及其封裝基板 Download PDFInfo
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- 239000000758 substrate Substances 0.000 title claims abstract description 63
- 239000002184 metal Substances 0.000 claims abstract description 50
- 229910052751 metal Inorganic materials 0.000 claims abstract description 50
- 239000010410 layer Substances 0.000 claims description 76
- 238000004806 packaging method and process Methods 0.000 claims description 19
- 238000009413 insulation Methods 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 13
- 238000000465 moulding Methods 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 229910000831 Steel Inorganic materials 0.000 claims description 6
- 150000001875 compounds Chemical class 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 239000010959 steel Substances 0.000 claims description 6
- 230000005855 radiation Effects 0.000 claims description 4
- 239000011241 protective layer Substances 0.000 claims description 3
- 230000017525 heat dissipation Effects 0.000 abstract description 23
- 238000000034 method Methods 0.000 description 13
- 239000003292 glue Substances 0.000 description 9
- 230000000694 effects Effects 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 8
- 239000000853 adhesive Substances 0.000 description 7
- 230000001070 adhesive effect Effects 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 7
- 239000000945 filler Substances 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 239000003989 dielectric material Substances 0.000 description 5
- 239000003822 epoxy resin Substances 0.000 description 5
- 229920000647 polyepoxide Polymers 0.000 description 5
- 238000000059 patterning Methods 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 238000005266 casting Methods 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000006835 compression Effects 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 239000000084 colloidal system Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000013021 overheating Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
- H05K1/0203—Cooling of mounted components
- H05K1/0209—External configuration of printed circuit board adapted for heat dissipation, e.g. lay-out of conductors, coatings
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
- H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H01L24/42—Wire connectors; Manufacturing methods related thereto
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Abstract
一種電子封裝件,係包括封裝基板及設於該封裝基板上之電子元件,且該封裝基板係包含絕緣部、結合於該絕緣部中之線路部、以及設於該絕緣部上並接觸結合該線路部之金屬板,其中,該金屬板係定義有相分離之複數電性接點與散熱部,使該金屬板不僅能藉由該散熱部維持預定之散熱面積,且能利用該些電性接點外接電路板。
Description
本創作係有關一種電子封裝件及其封裝基板,尤指一種電子封裝件及其封裝基板。
諸多電子產品皆已裝載感測系統,例如,應用於高散熱、高平整性以及高剛性需求之光學模組產品與感應器模組產品。
現行光學模組產品因解析度不斷提高,導致細線路與散熱要求隨之增加,再加上雙攝/三攝像頭產品因鏡頭間聯動需求,需要高平整性與高剛性基板作為支撐。例如,隨著自動駕駛技術發展,車用感應器不但精準度需求提高,且需要長時間、高溫下連續作動,對模組基板的散熱、剛性與可靠度需求也隨之提高,需要開發新的基板才能符合技術發展需求。
如第1圖所示,習知感測(sensor)型半導體封裝件1係於一封裝基板10上設置至少一感測晶片11,並使該感測晶片11之感測區11a朝上,再以封裝膠體12包覆該感測晶片11,之後由於該感測區11a上方需感應光線而不能設
置會影響感應品質之物件(如散熱片13),故於該封裝基板10下側藉由導電膠130結合一散熱片13,以將來自該感測晶片11之熱能經由該封裝基板10而從該導電膠130與該散熱片13散出。
惟,習知半導體封裝件1中,該散熱片13係整片貼合於該封裝基板10下側,故單一該散熱片13僅能作為單一接點(用以接地),致使該封裝基板10需增加其佈設面積(如增加寬度)以佈設用以接置電路板9之電性接點100,導致該封裝基板10之整體寬度增加,因而使該半導體封裝件1難以符合微小化之需求。
再者,若不增加該封裝基板10’之佈設面積,如第1’圖所示,則可縮小該散熱片13’之寬度,以於該封裝基板10’下表面露出用以接置電路板9之電性接點100,但此方式將因縮小該散熱片13’之尺寸而減少該散熱片13’之散熱量,致使該感測晶片11或該封裝基板10’容易因過熱而損壞。
又,使用該導電膠130將該散熱片13貼合至該封裝基板10,10’上,容易因該導電膠130之導熱性較該散熱片13,13’差,致使該散熱片13,13’無法達到預期之導熱效果。
另外,使用該導電膠130將該散熱片13,13’貼合至該封裝基板10,10’上,該散熱片13,13’會因該導電膠130之影響而產生貼合對位精度不佳之問題,甚至該導電膠130會衍生出缺膠、溢膠等可靠度不佳之問題。
因此,如何克服習知技術中之種種問題,實已成目前亟欲解決的課題。
鑑於上述習知技術之缺失,本創作提供一種封裝基板,係包括:絕緣部,係具有相對之第一側與第二側;線路部,係結合於該絕緣部中;以及金屬板,係設於該絕緣部之第一側上並接觸結合該線路部,其中,該金屬板係定義有相分離之複數電性接點與散熱部。
本創作復提供一種電子封裝件,係包括:一前述之封裝基板;以及電子元件,係設於該絕緣部之第二側上並電性連接該線路部。
前述之電子封裝件中,該電子元件係為感測式晶片。
前述之電子封裝件,復包括用以包覆該電子元件之封裝層。
前述之電子封裝件及其封裝基板中,形成該絕緣部之材質係為介電材,例如鑄模化合物(Molding compound)或底層塗料(Primer)。
前述之電子封裝件及其封裝基板中,該金屬板係包含鋼材或銅材。
前述之電子封裝件及其封裝基板中,復包括絕緣保護層,係設於該絕緣部之第二側上並外露該線路部。
由上可知,本創作之電子封裝件及其封裝基板中,主要藉由將該金屬板定義出複數電性接點與該散熱部,使單一該金屬板不僅能藉由該散熱部維持預定之散熱面積,且
能利用複數電性接點外接電路板,故相較於習知技術,本創作之封裝基板不需增加其佈設面積即可外接電路板,且不需縮小該散熱面積即可具有預定之散熱效果。
再者,本創作之電子封裝件藉由將該金屬板直接接觸該絕緣部與線路部,使該電子元件之熱能能直接由該金屬板傳遞至外部,而無需經過導電膠,故相較於習知技術,本創作之電子封裝件因無導電膠之影響,而使該散熱部能達到預期之導熱效果,且該金屬板能準確對位設置,並能避免可靠度不佳之問題。
1‧‧‧半導體封裝件
10,10’,2’,3’‧‧‧封裝基板
100,200‧‧‧電性接點
11‧‧‧感測晶片
11a,27a‧‧‧感測區
12‧‧‧封裝膠體
13,13’‧‧‧散熱片
130‧‧‧導電膠
2‧‧‧電子封裝件
2a‧‧‧第一線路部
2b‧‧‧第二線路部
2c,3c‧‧‧絕緣部
20‧‧‧金屬基材
20’‧‧‧金屬板
20a‧‧‧金屬層
201‧‧‧散熱部
202‧‧‧開孔
21,31‧‧‧第一線路層
22‧‧‧第一導電柱
23‧‧‧第一絕緣層
23a,33a‧‧‧第一側
24,34‧‧‧第二線路層
25‧‧‧第二導電柱
26‧‧‧第二絕緣層
26a,33c‧‧‧第二側
27‧‧‧電子元件
270‧‧‧導線
28‧‧‧封裝層
29,39‧‧‧絕緣保護層
3a‧‧‧線路部
32‧‧‧導電柱
33‧‧‧絕緣層
330‧‧‧盲孔
35‧‧‧導電層
36‧‧‧阻層
9‧‧‧電路板
90‧‧‧焊錫材料
第1圖係為習知半導體封裝件之剖視示意圖;第1’圖係為習知另一種半導體封裝件之剖視示意圖;第2A至2E圖係為本創作之電子封裝件之製法之剖視示意圖;其中,第2D’圖係為第2D圖之下視平面圖;以及第3A至3C圖係為第2A至2C圖之製程之另一實施例。
以下藉由特定的具體實施例說明本創作之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本創作之其他優點及功效。
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本創作可實施之限定
條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本創作所能產生之功效及所能達成之目的下,均應仍落在本創作所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如“上”、“下”、“第一”、“第二”及“一”等之用語,亦僅為便於敘述之明瞭,而非用以限定本創作可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本創作可實施之範疇。
第2A至2E圖係為本創作之電子封裝件2之製法之剖視示意圖。
如第2A圖所示,藉由圖案化製程,以形成一第一線路部2a於一金屬基材20上,其中係先以第一次圖案化製程,以形成第一線路層21,接續以第二次圖案化製程,以形成複數第一導電柱22於第一線路層21上,使該第一線路部2a係包含相堆疊結合之第一線路層21及第一導電柱22。
於本實施例中,該金屬基材20係為鋼基材,其兩側可依需求具有如銅層之金屬層20a,但有關該金屬基材20之構造並不限於上述。
再者,該些第一導電柱22係接觸且電性連接該第一線路層21。
如第2B圖所示,形成一第一絕緣層23於該金屬基材20上,且該些第一導電柱22外露於該第一絕緣層23,其中,該第一導電柱22表面係齊平於該第一絕緣層23表面。
於本實施例中,該第一絕緣層23係以鑄模方式、塗佈方式或壓合方式形成於該金屬基材20上,且形成該第一絕緣層23之材質係為介電材料,該介電材料可為環氧樹脂(Epoxy),且該環氧樹脂更包含鑄模化合物(Molding Compound)或底層塗料(Primer),如環氧模壓樹脂(Epoxy Molding Compound,簡稱EMC),其中,該環氧模壓樹脂係含有充填物(filler),且該充填物之含量為70至90wt%。
如第2C圖所示,依需求形成一增層結構於該第一絕緣層23與該些第一導電柱22上。
於本實施例中,該增層結構係包含第二線路部2b與第二絕緣層26,其中,該第二線路部2b係包含相堆疊結合之第二線路層24及複數第二導電柱25,且該第二線路層24係接觸且電性連接該些第二導電柱25與該第一導電柱22。
再者,該第二絕緣層26係形成於該第一絕緣層23上以包覆該第二線路部2b,並使該第一絕緣層23與該第二絕緣層26作為一絕緣部2c。具體地,該第一絕緣層23之表面係作為該絕緣部2c之第一側23a,且該第二絕緣層26之表面係作為該絕緣部2c之第二側26a,使該絕緣部2c具有相對之第一側23a與第二側26a。
又,該第二絕緣層26係以鑄模方式、塗佈方式或壓合方式形成者,且形成該第二絕緣層26之材質係為介電材料,該介電材料可為環氧樹脂,且該環氧樹脂更包括鑄模化合物(Molding Compound)或底層塗料(Primer),如環氧模
壓樹脂(EMC),其中,該環氧模壓樹脂係含有充填物(filler),其中,該充填物之含量為70~90wt%。
另外,該第二絕緣層26之材質可與該第一絕緣層23之材質相同或不相同。
如第2D圖所示,藉由圖案化製程移除部分該金屬基材20而形成具有複數電性接點200與散熱部201之金屬板20’,以形成一封裝基板2’,且該些電性接點200與該散熱部201係相分離,其中,該些電性接點200係電性連接該第一線路層21,且該散熱部201係熱連接該第一線路層21。
於本實施例中,係如第2D’圖所示,於該金屬基材20上形成環狀開孔202,以將位於該開孔202中之金屬柱定義為電性接點200,而其它金屬材則作為散熱部201。
再者,該封裝基板2’之金屬板20’藉由具有該銅材之金屬層20a(相較於鋼材)之設計,以提供該些電性接點200較佳之導電性、及該散熱部201較佳之導熱性。
如第2E圖所示,設置至少一電子元件27於該封裝基板2’上,並使該電子元件27電性連接該第二導電柱25,再形成一封裝層28於該封裝基板2’上以包覆該電子元件27。
於本實施例中,可先於該第二絕緣層26與該些第二導電柱25上形成一絕緣保護層29,且令該些第二導電柱25外露於該絕緣保護層29,再設置該電子元件27。
再者,該電子元件27係為主動元件、被動元件或其二
者組合,且該主動元件係例如半導體晶片,而該被動元件係例如電阻、電容及電感。例如,該電子元件27係為感測式晶片,其具有感測區27a,以偵測光線、電荷變化、溫度差或壓力等,使該電子元件27能藉由該感測區27a所接收的訊號進行辨識。具體地,該電子元件27可藉由複數如銲錫材料之導電凸塊(圖略)以覆晶方式設於該封裝基板2’上並電性連接該封裝基板2’;或者,該電子元件27可藉由複數導線270以打線方式電性連接該封裝基板2’。然而,有關該電子元件電性連接該封裝基板之方式不限於上述。
又,於後續製程中,該電子封裝件2可以其金屬板20’之電性接點200藉由焊錫材料90結合至一如電路板9之電子裝置上。
因此,本創作之電子封裝件2係藉由將該封裝基板2’之金屬板20’定義出複數電性接點200與該散熱部201,使單一該金屬板20’不僅能藉由該散熱部201維持預定之散熱面積,且能利用複數電性接點200外接如電路板9之電子裝置,故相較於習知技術,本創作之封裝基板2’不需增加其佈設面積(如增加寬度)即可外接如電路板9之電子裝置,且不需縮小該散熱面積即可具有預定之散熱效果,因而能同時符合微小化及散熱之需求。
再者,本創作之電子封裝件2藉由將該金屬板20’直接接觸該絕緣部2c與第一線路部2a,使該電子元件27之熱能能直接由該金屬板20’傳遞至外部,而無需經過導電
膠,故相較於習知技術,本創作之電子封裝件2因無導電膠之影響,而使該散熱部201能達到預期之導熱效果,且該金屬板20’能準確對位設置而不會產生貼合對位精度不佳之問題,並能避免如導電膠所衍生之缺膠、溢膠等可靠度不佳之問題。
另外,有關本創作之封裝基板之製程並不限於上述,亦可如第3A至3C圖所示之曝光顯影電鍍方式,具體如下說明。
如第3A圖所示,於該金屬基材20上形成一第一線路層31與絕緣層33,且於該絕緣層33上形成複數盲孔330,使該第一線路層31之部分表面外露於該盲孔330。
如第3B圖所示,於該絕緣層33上與該盲孔330中形成一導電層35,再於該導電層35上形成一阻層36,且該阻層36利用曝光顯影方式形成有複數開口區,以令該絕緣層33上之部分導電層35及該盲孔330外露於該些開口區。
接著,於該開口區中電鍍形成一第二線路層34與導電柱32(兩者以圖中虛線作界定)。其中,該導電柱32係形成於該盲孔330中以電性連接該第一線路層31與該第二線路層34。
如第3C圖所示,移除該阻層36及其下之導電層35,且加工該金屬基材20,以定義出該些電性接點200與該散熱部201。
於本實施例中,該第一線路層31、第二線路層34與導電柱32係作為該封裝基板3’之線路部3a,且該絕緣層
33作為該封裝基板3’之絕緣部3c,使該絕緣部3c具有相對之第一側33a與第二側33b,以令該些電性接點200與該散熱部201設於該絕緣部3c之第一側33a上。
再者,該線路部3a之層數可依需求設計,並不限於上述之層數。
又,可於該絕緣部3c之第二側33b上形成一作為防焊層之絕緣保護層39,且令該線路部3a(如該第二線路層34)外露於該絕緣保護層39,以於後續封裝製程中,電性連接該電子元件27。
本創作提供一種電子封裝件2,係包括:一封裝基板2’,3’以及至少一電子元件27,其中,該封裝基板2’,3’係包括:一絕緣部2c,3c、一線路部3a(或第一與第二線路部2a,2b)以及一金屬板20’。
所述之絕緣部2c,3c係具有相對之第一側23a,33a與第二側26a,33b。
所述之線路部3a(或第一與第二線路部2a,2b)係結合於該絕緣部2c,3c中。
所述之金屬板20’係設於該絕緣部2c,3c之第一側23a,33a上並接觸結合該線路部3a(或第一線路部2a),其中,該金屬板20’係定義有相分離之複數電性接點200與散熱部201。
所述之電子元件27係設於該絕緣部2c,3c之第二側26a,33b上並電性連接該線路部3a(或第二線路部2b)。
於一實施例中,形成該絕緣部2c,3c之材質係為介電
材料,例如鑄模化合物(Molding Compound)或底層塗料(Primer),其包含充填物(filler),其中,該充填物之含量為70至90wt%。
於一實施例中,該金屬板20’係包含鋼材或銅材(如上述之金屬層20a)。
於一實施例中,所述之封裝基板2’,3’復包括一絕緣保護層29,39,係設於該絕緣部2c,3c之第二側26a,33b上並外露該線路部3a(或第二線路部2b)。
於一實施例中,該電子元件27係為感測式晶片。
於一實施例中,所述之電子封裝件2復包括一用以包覆該電子元件27之封裝層28。
綜上所述,本創作之電子封裝件及其封裝基板,係藉由將該金屬板定義出複數電性接點與該散熱部,使單一該金屬板不僅能藉由該散熱部維持預定之散熱面積,且能利用複數電性接點外接電子裝置,故本創作之封裝基板不需增加其佈設面積即可外接電子裝置,且不需縮小該散熱面積即可具有預定之散熱效果,因而能同時符合微小化及散熱之需求。
再者,本創作之電子封裝件藉由將該金屬板直接接觸該絕緣部與該線路部,使該電子元件之熱能能直接由該金屬板傳遞至外部,而無需經過導電膠,故本創作之電子封裝件能達到預期之導熱效果,且該金屬板能準確對位貼合,並能避免可靠度不佳之問題。
上述實施例係用以例示性說明本創作之原理及其功
效,而非用於限制本創作。任何熟習此項技藝之人士均可在不違背本創作之精神及範疇下,對上述實施例進行修改。因此本創作之權利保護範圍,應如後述之申請專利範圍所列。
2’‧‧‧封裝基板
2a‧‧‧第一線路部
2b‧‧‧第二線路部
2c‧‧‧絕緣部
20’‧‧‧金屬板
200‧‧‧電性接點
201‧‧‧散熱部
202‧‧‧開孔
21‧‧‧第一線路層
22‧‧‧第一導電柱
23‧‧‧第一絕緣層
23a‧‧‧第一側
24‧‧‧第二線路層
25‧‧‧第二導電柱
26‧‧‧第二絕緣層
26a‧‧‧第二側
Claims (10)
- 一種封裝基板,係包括:絕緣部,係具有相對之第一側與第二側;線路部,係結合於該絕緣部中;以及金屬板,係設於該絕緣部之第一側上並接觸結合該線路部,其中,該金屬板係定義有相分離之複數電性接點與散熱部。
- 如申請專利範圍第1項所述之封裝基板,其中,形成該絕緣部之材質係為鑄模化合物(Molding Compound)或底層塗料(Primer)。
- 如申請專利範圍第1項所述之封裝基板,其中,該金屬板係包含鋼材或銅材。
- 如申請專利範圍第1項所述之封裝基板,復包括絕緣保護層,係設於該絕緣部之第二側上並外露該線路部。
- 一種電子封裝件,係包括:一如申請專利範圍第1項所述之封裝基板;以及電子元件,係設於該絕緣部之第二側上並電性連接該線路部。
- 如申請專利範圍第5項所述之電子封裝件,其中,形成該絕緣層之材質係為鑄模化合物(Molding Compound)或底層塗料(Primer)。
- 如申請專利範圍第5項所述之電子封裝件,其中,該金屬板係包含鋼材或銅材。
- 如申請專利範圍第5項所述之電子封裝件,復包括絕緣 保護層,係設於該絕緣部之第二側上並外露該線路部以電性連接該電子元件。
- 如申請專利範圍第5項所述之電子封裝件,其中,該電子元件係為感測式晶片。
- 如申請專利範圍第5項所述之電子封裝件,復包括用以包覆該電子元件之封裝層。
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- 2017-09-05 TW TW106213140U patent/TWM555065U/zh unknown
- 2017-11-28 US US15/823,831 patent/US10366906B2/en active Active
Also Published As
Publication number | Publication date |
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US10366906B2 (en) | 2019-07-30 |
US20190074196A1 (en) | 2019-03-07 |
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