CN101103459A - 选择性金属敷镀形成的布线图案 - Google Patents

选择性金属敷镀形成的布线图案 Download PDF

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CN101103459A
CN101103459A CN200680001918.1A CN200680001918A CN101103459A CN 101103459 A CN101103459 A CN 101103459A CN 200680001918 A CN200680001918 A CN 200680001918A CN 101103459 A CN101103459 A CN 101103459A
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sidewall
seed material
axle
wire structures
plating
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古川俊治
马克·C.·哈克
史蒂文·J.·福尔摩斯
大卫·V.·霍拉克
查尔斯·W.·考伯格三世
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Abstract

使用形成结构(心轴)的图案并且激活该结构的侧壁的方法形成导电侧壁间隔物结构。金属离子被附着于该结构的侧壁上并且该金属离子被还原以形成种子材料。该结构接着被修整并且种子材料被敷镀以在该结构的侧壁上形成布线。

Description

选择性金属敷镀形成的布线图案
技术领域
本发明总地来说涉及导电侧壁布线,其以下述方法形成,在该方法中金属离子被附着于侧壁,然后被还原以形成种子材料。然后对该结构进行修整并且种子材料被敷镀(plate)以在侧壁上形成布线。
背景技术
因为集成电路尺寸减小,连接有源和无源器件的布线也必须减小尺寸。这使得现有的布线更为昂贵并且电阻更大。形成较小尺寸的布线的一种方法涉及沿绝缘心轴(insulating mandrel)的侧壁形成导电材料。该结构有时被称为导电侧壁间隔物(conductive sidewallspacer)。如果该心轴被形成为可达到的最小光刻尺寸,则沿着该结构形成的侧壁布线实际上比以光刻方式形成的侧壁布线小。侧壁间隔物的详细讨论可以参见美国专利5331116、5593920和6127257,这些专利在此处被引用参考。
发明内容
此处的一个实施例包括一种形成导电侧壁布线的方法。该方法形成结构(心轴)的图案并且激活这些结构的侧壁。接着,金属离子被附着于该结构的侧壁上并且该金属离子被还原以形成种子材料。接着对该结构进行修整并且种子材料被敷镀以在该结构的侧壁上形成布线。
激活这些结构的侧壁的过程包括将NH3等离子体、O2等离子体等,或者TEOS或者胺蒸气/溶液施加到该结构的侧壁上。附着金属离子的过程包括将金属化合物的水溶液施加于该结构的侧壁上,该金属化合物例如金属硝酸盐等。还原金属离子的过程包括将H2蒸气或者肼溶液施加到金属离子上。在形成种子材料之前,也可以在结构上形成盖(cap)。另外,修整过程修整在心轴的侧壁周围形成的种子材料环。
这样生成布线结构,该布线结构在结构的侧壁上具有种子材料,并且在结构的种子材料和侧壁上具有敷镀金属的布线。因此,该敷镀金属的布线包括多个金属层,这些金属层沿垂直侧表面非对称。该侧壁在被NH3等离子体、O2等离子体,或者TEOS或者胺蒸气/溶液激活之后,具有氨基和羧酸的官能度之一。心轴结构可以包括有机聚合物,例如光致抗蚀剂等。
当与具体实施方式和附图结合考虑的时候,本发明的这些和其他方面和目的可以更好地加以理解。然而可以理解,尽管下述具体实施方式表明本发明的实施例以及其中许多具体的细节,但是其是以示例的方式给出,而不是以限制的方式给出。在不脱离本发明的精神的前提下,在本发明的范围内可以做出许多改变和变化,并且本发明包括所有该变化。
附图说明
参考附图,本发明可以在下述具体实施方式部分得到更好的理解,其中:
附图1是部分完成的布线结构的示例性截面图;
附图2是部分完成的布线结构的示例性截面图;
附图3是部分完成的布线结构的示例性截面图;
附图4是部分完成的布线结构的示例性顶视图;
附图5是部分完成的布线结构的示例性顶视图;
附图6A和6B是部分完成的布线结构的示例性顶视图;
附图7是部分完成的布线结构的示例性顶视图;
附图8是部分完成的布线结构的示例性截面图;
附图9是根据一个实施例的部分完成的布线结构的示例性截面图;
附图10是根据一个实施例的部分完成的布线结构的示例性截面图;
附图11是根据另一个实施例的部分完成的布线结构的示例性截面图;
附图12是根据另一个实施例的部分完成的布线结构的示例性截面图;
附图13是根据另一个实施例的部分完成的布线结构的示例性截面图;
附图14是根据另一个实施例的部分完成的布线结构的示例性截面图;
附图15是根据另外一个实施例的部分完成的布线结构的示例性截面图;
附图16是根据另外一个实施例的部分完成的布线结构的示例性截面图;
附图17是根据另外一个实施例的部分完成的布线结构的示例性截面图;
附图18是根据另外一个实施例的部分完成的布线结构的示例性截面图;
附图19是根据另外一个实施例的部分完成的布线结构的示例性截面图;
附图20是根据另外一个实施例的部分完成的布线结构的示例性截面图;
附图21是根据另外一个实施例的部分完成的布线结构的示例性截面图;
附图22是根据另外一个具体实施例的部分完成的布线结构的示例性截面图。
具体实施方式
如上所述,导电侧壁间隔物可以被应用为极其密集的布线和电容结构的导电板。然而,制造导电侧壁间隔物的现有方法具有形成具有高宽高比的结构的困难。另外,有时难以控制侧壁间隔物实际形成的位置,其会导致断路或者短路。因此,开发出下述方法,以产生具有非常高的宽高比并且易于界定导电侧壁形成的位置的结构。
更为具体地,如附图1的截面图所示,该方法开始于在任何形式的衬底10上形成心轴材料12,该心轴材料例如包括氧化物、玻璃、聚合物、有机物等的任何常见的绝缘体,该衬底10例如硅晶片或者非硅晶片等等。接着,如附图2的截面图所示,本发明在心轴材料12上形成可选的盖22的图案,例如氮化硅或者类似材料。更为具体地,盖材料22可以沉积在整个心轴材料12上,并且接着可以在盖材料22上形成单独的光致抗蚀剂掩模24的图案。从公知技术中可以得知,光致抗蚀剂掩模可以接着被暴光,显影等等。接着,使用光致抗蚀剂掩模24,通过反应性离子刻蚀(RIE)形成盖材料22的图案。接着,可利用定向RIE将心轴材料12图案化为绝缘心轴20。
接着,如附图2的箭头26所示,本发明通过将NH3等离子体、O2等离子体或者TEOS(原硅酸四乙酯,Si(OC2H5)4)或者胺蒸气/溶液施加到该结构的侧壁上,来激活该结构的侧壁。激活侧壁的过程调节心轴材料20,以向其提供有机氨基、羧酸、羟基等等的官能度。因此,除了激活上述等离子体、蒸气或者溶液,向侧壁提供有机氨基、羧酸等官能度的任何处理都可以用于本发明。
举例而言,通过等离子CVD方法对顺丁烯二酸酐聚合物(maleicanhydride polymer)进行沉积之后,用枝状胺(dendritic amine)进行激活。如果期望,胺激活可以在修整步骤之后执行,以避免修整掩模和胺材料之间的相互作用。等离子聚合顺丁烯二酸酐是非选择性的,并且将沉积在衬底的所有表面上。其可以由氧RIE刻蚀,以将材料从水平表面移除,在心轴的侧壁上留有聚合物材料的薄间隔物。胺枝状物可以被用作甲醇溶液(聚酰胺胺,10%w/v甲醇溶液)然后进行甲醇清洗。可替换地,可溶顺丁烯二酸酐聚合物或者共聚物可以被旋涂并且被轻烘焙(soft-bake),并且被直接用作心轴材料,在蚀刻和显影之后由胺溶液激活。可替换地,包含反应成分的抗蚀剂可以按图形被暴光并且显影,其后由胺激活,该反应成分例如是顺丁烯二酸酐聚合物或者共聚物。可以采用氧气或者氩气RIE将胺材料从抗蚀剂图形的水平表面移除,使得抗蚀剂的侧壁胺官能化。
在另一种方法中,氨等离子体可以被用于胺化心轴表面。氧气或者氩气RIE可以被用于在金属沉积之前清洗水平表面。如果期望的话,氢倍半硅氧烷材料可以被用于形成心轴,并且可以在半导体装置中留下作为电介质材料的一部分。有机心轴也可以用于该方法。
在另一种方法中,等离子体聚合化乙醛、乙酸或者二胺基乙烷,或者类似材料可以沉积于心轴表面上。氩气或者氧气RIE可以用于从水平表面移除该材料,在心轴的侧壁上留下薄的聚合物间隔物。保留在心轴侧壁上的醛、羧酸或者胺官能度可以被用于将金属离子种子层材料固定在心轴的侧面。
在另一种方法中,心轴自身包括一种材料,该材料包含活性胺或者羧酸脂类作为该材料的一部分,或者作为聚合物基体的添加物或者作为聚合物本身的组分。
在形成盖材料22的图案之后,光致抗蚀剂24在所有点被移除,如附图3的截面图所示。接着,如附图3所示,将金属离子附着于结构20的侧壁上,并且所述金属离子被还原以形成金属种子材料40,所述金属离子例如钯、铂、Ni、Rh、Ru、Co、Ag、Cu、Pt离子(可以被用于将铜的二价离子还原为铜金属等等)。附着金属离子的过程包括将金属化合物的水溶液施加于该结构的侧壁上,所述金属化合物例如是金属硝酸盐、氯化物、溴化物、氟化物、硫酸盐、磺酸盐、磷酸盐、四氟硼酸盐、六氟硫酸盐(hexafluorosulfate)、乙酰丙酮酸盐或者类似材料等等。有机金属试剂也可以以气态或者在溶液中使用,例如(甲基环戊二烯基)三甲基铂或者羰基化合物,该羰基化合物例如是羰基镍(Ni(CO)4),羰基镍在周围环境中处于气态。
还原金属离子的过程包括根据所要还原的金属,在环境温度到400C的温度下,施加氢气或者混有氩气或者其他惰性气体的氢气,所述其他惰性气体例如He、Ne、N2。肼或者烷基肼也可以用作溶液中对金属离子的还原剂。附图4从顶视方向示出了与附图3相同的结构。
如附图5-6B的顶视图所示,接着对心轴20接着进行修整。更为具体地,形成掩模50(例如光致抗蚀剂或者硬掩模),如附图5所示。接着,如附图6A所示,使用掩模50,使用任何公知的材料移除过程,对心轴20的端部(以及种子材料40)进行修整,该材料移除过程例如是湿刻蚀或者干刻蚀、化学清洗等。可替换地,如附图6B所示,可以通过选择性的刻蚀或化学清洗过程使得心轴20留下而通过而移除种子材料40的非受保护区域。该过程选择性地将在心轴20的侧壁周围形成的种子材料40的环修整为单独长度的种子材料,其将在下面的敷镀过程中加以使用以形成单独的直的导电侧壁敷镀结构。
更为具体地,如附图7的顶视图和附图8的截面图所示,种子材料被敷镀导电材料70(例如铜、钯、铂等)以在该结构的侧壁上形成布线。该敷镀过程可以包括任何公知的基于电或者与非基于电的敷镀过程,并且能够与易于敷镀到种子材料40上的任何类型的金属一起使用。本领域技术人员在公开内容的基础上可以得知,种子材料40被选择为与被敷镀到种子材料40上的材料70相容,并且易于敷镀到一起的任何类型的导电材料可以用于本发明。因此,本发明并不限于上而所讨论的材料,上述材料仅仅用于示例。布线包括种子材料40和敷镀材料70的剩余物,二者都是导电性的(镀层导体)。
接着,如附图9所示,选择性材料移除过程例如刻蚀或者化学清洗等被用于移除盖22和心轴20,使得敷镀的布线70和种子材料40保持独立。接着,如附图10所示,整个结构由绝缘体100覆盖,该绝缘体例如二氧化硅、氟化二氧化硅或者其他公知的低K电介质薄膜,以及TaN、TiN、Ta、WN,其可以如附图10所示被平面化。其生成最终的布线结构,该布线结构具有由绝缘体100分开的种子材料40和种子材料40上的敷镀的布线70。该敷镀的布线因此包括多个金属层(40,70),该金属层在垂直方向上不对称。
另一个实施例在附图11-14中示出,开始于附图8所示的结构但是在此之后使用不同的处理步骤。更为具体地,如附图11所示,例如任何上述绝缘体的绝缘体110被沉积在该结构之上。该结构如附图12所示被平面化,其中移除了盖22。接着,如附图13所示,使用任何公知的选择性移除过程,移除种子材料40和敷镀的布线70,以留下绝缘材料20、110之间的开口130。接着,如附图14所示,开口130由电介质衬垫140衬垫并且接着被填充任何形式的导体142并进行镶嵌处理。
另一个实施例在附图15-21中示出。该附图也始于附图8所示的结构,并且给该结构涂上额外的盖材料150,举例而言,该盖材料可以是使用等离子处理而沉积的二氧化硅。接着,如附图16所示,例如黑金刚石电介质的电介质160被沉积在结构上并且该结构被平面化以移除盖22。接着,如附图17所示,另一种电介质170(与上述电介质类似)被沉积在该结构上并且另一层盖材料172的图案以与上述方式类似的方式形成在结构上。接着,利用材料移除处理来形成通过绝缘体170和一部分心轴20的开口174。
接着,如附图18所示,开口174被注入任何形式的导体180并且该结构被平面化。接着,如附图19所示,使用与上述类似的处理,在盖层172中形成开口190的图案。如附图20所示,材料移除处理通过开口190执行以移除绝缘体170和心轴20。这将留下空气作为由种子材料40和敷镀材料70形成的导体之间的绝缘体。
如附图21所示,通过重复上述处理,另一个实施例可以堆叠如附图20所示的结构。请注意在该实施例中,盖材料150和绝缘体160将每个导体180与覆盖层的导电的种子材料和敷镀材料40、70绝缘。通过对于各层不同排列可以实现上述内容。如附图22所示,另一个实施例可以类似地排列各层,以使得导体180和每个层由导电的种子材料和敷镀材料40、70电连接。
上面,参考非限制性的实施例对本发明和各种特征和具有有益效果的细节进行了更为全面的解释,该实施例在附图中示出并且在上述具体实施方式中详细描述。应当注意,附图中所示的特征并不一定是按照比例绘制的。公知的组件和处理技术的描述被省略以避免不必要地模糊本发明。此处使用的示例仅仅旨在促进对于本发明实现方式的理解,并且旨在使得本领域技术人员能够实现本发明。因此,示例不能被理解为对于发明范围的限制。
本发明所形成的布线图案非常狭窄并且具有非常高的宽高比,并且在芯片、晶片或者批量晶片上具有小的图形宽度公差值。通过选择性沉积形成图案,其中使用表面受限并且因此高度共形的处理。该图案的宽度由沉积时间和沉积条件决定,而不是由下述内容决定:晶片上或者芯片上掩模的一致性、光学一致性、步进器的聚焦控制、曝光剂量一致性、或者刻蚀的一致性。布线特征的高的宽高比有助于降低电容,因为较厚的电介质层可以被用于分离临近的布线掩模层。降低电容提高了芯片速度或者性能。尽管本发明以实施例的方式进行了描述,但是本领域技术人员能够意识到,在不脱离所附权利要求的精神和范围的前提下,在实施本发明时可以进行修改。

Claims (33)

1.一种布线结构,包括:
具有侧壁的结构;
位于所述结构的所述侧壁上的种子材料;和
位于所述结构的所述种子材料和侧壁上的敷镀的布线。
2.如权利要求1所述的布线结构,其中所述侧壁具有氨基、羧酸、羟基官能度之一。
3.如权利要求1所述的布线结构,其中所述种子材料和所述敷镀的布线在所述结构的所述侧壁上形成非对称的垂直结构。
4.如权利要求1所述的布线结构,其中所述种子材料包括金属。
5.如权利要求1所述的布线结构,其中所述敷镀的布线包括修整的导线。
6.如权利要求1所述的布线结构,其中所述结构包括有机聚合物。
7.如权利要求1所述的布线结构,其中所述具有侧壁的结构包括SiO2、FSiO2、TaN、TiN、Ta、WN之一。
8.一种布线结构,包括:
具有侧壁的结构;
位于所述结构的所述侧壁上的种子材料;和
位于所述种子材料和所述结构的侧壁上的敷镀的布线,其中所述敷镀的布线包括多个金属层。
9.如权利要求8所述的布线结构,其中所述侧壁具有氨基、羧酸、羟基官能度之一。
10.如权利要求8所述的布线结构,其中所述种子材料和所述敷镀的布线在所述结构的所述侧壁上形成非对称的垂直结构。
11.如权利要求8所述的布线结构,其中所述种子材料包括金属。
12.如权利要求8所述的布线结构,其中所述敷镀的布线包括修整的导线。
13.如权利要求8所述的布线结构,其中所述结构包括有机聚合物。
14.如权利要求8所述的布线结构,其中所述具有侧壁的结构包括SiO2、FSiO2、TaN、TiN、Ta、WN之一。
15.一种形成布线的方法,所述方法包括:
形成结构的图案;
在所述结构的侧壁上形成种子材料;
修整所述结构;和
将金属敷镀在所述种子材料上以在所述结构的所述侧壁上形成所述布线。
16.如权利要求15所述的方法,其中形成所述种子材料的所述过程包括:
激活所述结构的所述侧壁;
将金属离子附着于所述结构的所述侧壁上;和
还原所述金属离子以形成所述种子材料。
17.如权利要求16所述的方法,其中附着所述金属离子的所述过程包括将金属硝酸盐的水溶液施加于所述结构的所述侧壁。
18.如权利要求16所述的方法,进一步包括在形成所述种子材料之前在所述结构上形成盖。
19.如权利要求16所述的方法,其中所述结构包括心轴,并且所述修整过程修整在所述心轴的侧壁周围形成的所述种子材料的环。
20.一种形成布线的方法,所述方法包括:
形成结构的图案;
激活所述结构的所述侧壁;
将金属离子附着在所述结构的所述侧壁上;
还原所述金属离子以形成种子材料;
修整所述结构;和
敷镀所述种子材料以在所述结构的所述侧壁上形成所述布线。
21.如权利要求22所述的方法,其中附着所述金属离子的所述过程包括将金属硝酸盐的水溶液施加于所述结构的所述侧壁。
22.如权利要求22所述的方法,进一步包括在形成所述种子材料之前在所述结构上形成盖。
23.如权利要求22所述的方法,其中所述结构包括心轴,并且所述修整过程修整形成于所述心轴的侧壁周围的所述种子材料的环。
24.一种形成布线的方法,所述方法包括:
在衬底上形成心轴;
用敷镀导体敷镀所述心轴的侧壁;
用绝缘体覆盖所述心轴和所述敷镀导体;
移除所述导体,以留下所述心轴和所述绝缘体之间的开口;和
用镶嵌导体填充所述开口。
25.如权利要求24所述的方法,其中所述敷镀过程包括:
在所述心轴的侧壁上形成种子材料;
修整所述心轴;和
敷镀所述种子材料以在所述结构的所述侧壁上形成所述敷镀导体。
26.如权利要求25所述的方法,其中形成所述种子材料的所述过程包括:
激活所述结构的所述侧壁;
将金属离子附着于所述结构的所述侧壁;和
还原所述金属离子以形成所述种子材料。
27.如权利要求26所述的方法,其中附着所述金属离子的所述过程包括将金属硝酸盐的水溶液施加于所述结构的所述侧壁上。
28.如权利要求25所述的方法,其中所述修整过程修整形成于所述心轴的侧壁周围的所述种子材料的环。
29.一种形成布线的方法,所述方法包括:
在衬底上形成心轴;
用敷镀导体敷镀所述心轴的侧壁;
用第一盖材料涂覆所述心轴和所述敷镀导体;
用绝缘体填充所述心轴之间的空间;
对所述结构进行平面化以露出所述心轴;
在所述心轴和所述绝缘体上形成牺牲材料;
在所述牺牲材料上形成第二盖材料的图案;
通过所述第二盖材料中的开口形成所述牺牲材料的图案;
在所述牺牲材料中的开口中沉积导体;
在所述第二盖材料中形成额外的开口;和
通过所述额外的开口移除所述牺牲材料和所述心轴。
30.如权利要求29所述的方法,其中所述敷镀处理包括:
在所述心轴的侧壁上形成种子材料;
修整所述心轴;和
在所述种子材料上敷镀金属以在所述结构的所述侧壁上形成所述敷镀导体。
31.如权利要求30所述的方法,其中形成所述种子材料的所述过程包括:
激活所述结构的所述侧壁;
将金属离子附着于所述结构的所述侧壁上;和
还原所述金属离子以形成所述种子材料。
32.如权利要求31所述的方法,其中附着所述金属离子的所述过程包括将金属硝酸盐的水溶液施加于所述结构的所述侧壁上。
33.如权利要求30所述的方法,其中所述修整过程修整形成于所述心轴的侧壁周围的所述种子材料的环。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104425214A (zh) * 2013-08-20 2015-03-18 台湾积体电路制造股份有限公司 集成电路布局以及具有双重图案的方法
CN105051883A (zh) * 2013-03-15 2015-11-11 密克罗奇普技术公司 在集成电路中形成栅栏导体
CN105304555A (zh) * 2014-06-13 2016-02-03 台湾积体电路制造股份有限公司 导体纳米线的选择性形成

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7510939B2 (en) * 2006-01-31 2009-03-31 International Business Machines Corporation Microelectronic structure by selective deposition
US7968008B2 (en) 2006-08-03 2011-06-28 Fry's Metals, Inc. Particles and inks and films using them
US8043931B1 (en) * 2006-09-18 2011-10-25 Gang Zhang Methods for forming multi-layer silicon structures
US9615463B2 (en) * 2006-09-22 2017-04-04 Oscar Khaselev Method for producing a high-aspect ratio conductive pattern on a substrate
KR101913184B1 (ko) * 2007-08-03 2018-10-30 알파 어셈블리 솔루션스 인크. 도전 패턴 및 그 사용방법
GB2466255B (en) 2008-12-17 2013-05-22 Antenova Ltd Antennas conducive to semiconductor packaging technology and a process for their manufacture
US8809128B2 (en) * 2009-10-26 2014-08-19 Sandisk 3D Llc Methods and apparatus for layout of three dimensional matrix array memory for reduced cost patterning
US8815747B2 (en) * 2010-06-03 2014-08-26 Micron Technology, Inc. Methods of forming patterns on substrates
JP2013105891A (ja) * 2011-11-14 2013-05-30 Toshiba Corp 半導体装置およびその製造方法
US9034758B2 (en) 2013-03-15 2015-05-19 Microchip Technology Incorporated Forming fence conductors using spacer etched trenches
US9583435B2 (en) 2013-03-15 2017-02-28 Microchip Technology Incorporated Forming fence conductors using spacer etched trenches
US9406331B1 (en) 2013-06-17 2016-08-02 Western Digital (Fremont), Llc Method for making ultra-narrow read sensor and read transducer device resulting therefrom
US9330914B2 (en) 2013-10-08 2016-05-03 Micron Technology, Inc. Methods of forming line patterns in substrates
US9312064B1 (en) 2015-03-02 2016-04-12 Western Digital (Fremont), Llc Method to fabricate a magnetic head including ion milling of read gap using dual layer hard mask
US10037957B2 (en) * 2016-11-14 2018-07-31 Amkor Technology, Inc. Semiconductor device and method of manufacturing thereof
US9966338B1 (en) 2017-04-18 2018-05-08 Globalfoundries Inc. Pre-spacer self-aligned cut formation
US20230290682A1 (en) * 2022-03-09 2023-09-14 International Business Machines Corporation Additive interconnect formation

Family Cites Families (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5687326A (en) 1979-12-17 1981-07-15 Sony Corp Method of forming wiring
IL84255A (en) 1987-10-23 1993-02-21 Galram Technology Ind Ltd Process for removal of post- baked photoresist layer
US4919768A (en) 1989-09-22 1990-04-24 Shipley Company Inc. Electroplating process
US5342501A (en) 1989-11-21 1994-08-30 Eric F. Harnden Method for electroplating metal onto a non-conductive substrate treated with basic accelerating solutions for metal plating
US5331116A (en) 1992-04-30 1994-07-19 Sgs-Thomson Microelectronics, Inc. Structure and method for forming contact structures in integrated circuits
US6127257A (en) 1993-11-18 2000-10-03 Motorola Inc. Method of making a contact structure
US6576976B2 (en) 1997-01-03 2003-06-10 Integrated Device Technology, Inc. Semiconductor integrated circuit with an insulation structure having reduced permittivity
JPH10261710A (ja) 1997-03-18 1998-09-29 Sony Corp 配線形成方法及び半導体装置の製造方法
US6117784A (en) 1997-11-12 2000-09-12 International Business Machines Corporation Process for integrated circuit wiring
US6040214A (en) 1998-02-19 2000-03-21 International Business Machines Corporation Method for making field effect transistors having sub-lithographic gates with vertical side walls
KR100635685B1 (ko) * 1998-05-25 2006-10-17 가부시키가이샤 히타치세이사쿠쇼 반도체장치 및 그 제조방법
AT405842B (de) * 1998-06-19 1999-11-25 Miba Gleitlager Ag Verfahren zum aufbringen einer metallischen schicht auf eine polymeroberfläche eines werkstückes
US6190986B1 (en) 1999-01-04 2001-02-20 International Business Machines Corporation Method of producing sulithographic fuses using a phase shift mask
US7007378B2 (en) * 1999-06-24 2006-03-07 International Business Machines Corporation Process for manufacturing a printed wiring board
US6440839B1 (en) 1999-08-18 2002-08-27 Advanced Micro Devices, Inc. Selective air gap insulation
US6815329B2 (en) * 2000-02-08 2004-11-09 International Business Machines Corporation Multilayer interconnect structure containing air gaps and method for making
KR100803770B1 (ko) * 2000-03-07 2008-02-15 에이에스엠 인터내셔널 엔.브이. 구배(graded)박막
US6632741B1 (en) * 2000-07-19 2003-10-14 International Business Machines Corporation Self-trimming method on looped patterns
JP2002075995A (ja) 2000-08-24 2002-03-15 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
TWI226103B (en) 2000-08-31 2005-01-01 Georgia Tech Res Inst Fabrication of semiconductor devices with air gaps for ultra low capacitance interconnections and methods of making same
US6660154B2 (en) 2000-10-25 2003-12-09 Shipley Company, L.L.C. Seed layer
JP2002170885A (ja) * 2000-12-04 2002-06-14 Fujitsu Ltd 半導体装置の製造方法
US20020092673A1 (en) * 2001-01-17 2002-07-18 International Business Machines Corporation Tungsten encapsulated copper interconnections using electroplating
US6653231B2 (en) 2001-03-28 2003-11-25 Advanced Micro Devices, Inc. Process for reducing the critical dimensions of integrated circuit device features
JP3795459B2 (ja) * 2001-05-16 2006-07-12 積水化学工業株式会社 硬化性樹脂組成物、表示素子用シール剤及び表示素子用封口剤
JP3561240B2 (ja) * 2001-05-25 2004-09-02 京セラ株式会社 配線基板の製造方法
US20030008243A1 (en) * 2001-07-09 2003-01-09 Micron Technology, Inc. Copper electroless deposition technology for ULSI metalization
TWI312166B (en) * 2001-09-28 2009-07-11 Toppan Printing Co Ltd Multi-layer circuit board, integrated circuit package, and manufacturing method for multi-layer circuit board
JP3967108B2 (ja) 2001-10-26 2007-08-29 富士通株式会社 半導体装置およびその製造方法
US20030116439A1 (en) * 2001-12-21 2003-06-26 International Business Machines Corporation Method for forming encapsulated metal interconnect structures in semiconductor integrated circuit devices
JP4063619B2 (ja) * 2002-03-13 2008-03-19 Necエレクトロニクス株式会社 半導体装置の製造方法
JP2003298232A (ja) * 2002-04-02 2003-10-17 Sony Corp 多層配線基板の製造方法および多層配線基板
US6713396B2 (en) 2002-04-29 2004-03-30 Hewlett-Packard Development Company, L.P. Method of fabricating high density sub-lithographic features on a substrate
US6716753B1 (en) * 2002-07-29 2004-04-06 Taiwan Semiconductor Manufacturing Company Method for forming a self-passivated copper interconnect structure
US6911229B2 (en) * 2002-08-09 2005-06-28 International Business Machines Corporation Structure comprising an interlayer of palladium and/or platinum and method for fabrication thereof
JP2004103911A (ja) 2002-09-11 2004-04-02 Shinko Electric Ind Co Ltd 配線形成方法
US7001833B2 (en) * 2002-09-27 2006-02-21 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming openings in low-k dielectric layers
US7148265B2 (en) * 2002-09-30 2006-12-12 Rohm And Haas Electronic Materials Llc Functional polymer
US6936536B2 (en) * 2002-10-09 2005-08-30 Micron Technology, Inc. Methods of forming conductive through-wafer vias
US6900126B2 (en) * 2002-11-20 2005-05-31 International Business Machines Corporation Method of forming metallized pattern
US20040108136A1 (en) * 2002-12-04 2004-06-10 International Business Machines Corporation Structure comprising a barrier layer of a tungsten alloy comprising cobalt and/or nickel
JP2004273969A (ja) * 2003-03-12 2004-09-30 Sony Corp 磁気記憶装置の製造方法
US7485162B2 (en) * 2003-09-30 2009-02-03 Fujimi Incorporated Polishing composition
US7068138B2 (en) * 2004-01-29 2006-06-27 International Business Machines Corporation High Q factor integrated circuit inductor
US7052932B2 (en) * 2004-02-24 2006-05-30 Chartered Semiconductor Manufacturing Ltd. Oxygen doped SiC for Cu barrier and etch stop layer in dual damascene fabrication
US20060145350A1 (en) * 2004-12-30 2006-07-06 Harald Gross High frequency conductors for packages of integrated circuits
JP2007163268A (ja) * 2005-12-13 2007-06-28 Canon Inc 酵素電極

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105051883A (zh) * 2013-03-15 2015-11-11 密克罗奇普技术公司 在集成电路中形成栅栏导体
CN104425214A (zh) * 2013-08-20 2015-03-18 台湾积体电路制造股份有限公司 集成电路布局以及具有双重图案的方法
CN105304555A (zh) * 2014-06-13 2016-02-03 台湾积体电路制造股份有限公司 导体纳米线的选择性形成
US10490497B2 (en) 2014-06-13 2019-11-26 Taiwan Semiconductor Manufacturing Company, Ltd. Selective formation of conductor nanowires
CN113192880A (zh) * 2014-06-13 2021-07-30 台湾积体电路制造股份有限公司 导体纳米线的选择性形成
US11908789B2 (en) 2014-06-13 2024-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Selective formation of conductor nanowires
CN113192880B (zh) * 2014-06-13 2024-02-23 台湾积体电路制造股份有限公司 导体纳米线的选择性形成

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