CN101010781A - 使用晶片键合技术制造无缺陷高Ge含量(25%)绝缘体上SIGE(SGOI)衬底的方法 - Google Patents
使用晶片键合技术制造无缺陷高Ge含量(25%)绝缘体上SIGE(SGOI)衬底的方法 Download PDFInfo
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- CN101010781A CN101010781A CNA2005800293853A CN200580029385A CN101010781A CN 101010781 A CN101010781 A CN 101010781A CN A2005800293853 A CNA2005800293853 A CN A2005800293853A CN 200580029385 A CN200580029385 A CN 200580029385A CN 101010781 A CN101010781 A CN 101010781A
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Classifications
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02441—Group 14 semiconducting materials
- H01L21/0245—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
Claims (40)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/939,736 | 2004-09-13 | ||
US10/939,736 US7235812B2 (en) | 2004-09-13 | 2004-09-13 | Method of creating defect free high Ge content (>25%) SiGe-on-insulator (SGOI) substrates using wafer bonding techniques |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101010781A true CN101010781A (zh) | 2007-08-01 |
CN100456424C CN100456424C (zh) | 2009-01-28 |
Family
ID=36032957
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2005800293853A Expired - Fee Related CN100456424C (zh) | 2004-09-13 | 2005-03-15 | 绝缘体上sige衬底及其形成方法 |
Country Status (7)
Country | Link |
---|---|
US (3) | US7235812B2 (zh) |
EP (1) | EP1800345B1 (zh) |
JP (1) | JP4906727B2 (zh) |
KR (1) | KR100968320B1 (zh) |
CN (1) | CN100456424C (zh) |
TW (1) | TWI353670B (zh) |
WO (1) | WO2006031247A2 (zh) |
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CN101866874A (zh) * | 2010-06-01 | 2010-10-20 | 中国科学院上海微***与信息技术研究所 | 一种利用层转移技术制备绝缘体上锗硅材料的方法 |
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KR100968320B1 (ko) | 2010-07-08 |
EP1800345A2 (en) | 2007-06-27 |
US20060054891A1 (en) | 2006-03-16 |
US20090004831A1 (en) | 2009-01-01 |
WO2006031247A2 (en) | 2006-03-23 |
WO2006031247A3 (en) | 2006-10-12 |
US7445977B2 (en) | 2008-11-04 |
CN100456424C (zh) | 2009-01-28 |
JP4906727B2 (ja) | 2012-03-28 |
EP1800345A4 (en) | 2008-11-05 |
US7704815B2 (en) | 2010-04-27 |
US7235812B2 (en) | 2007-06-26 |
EP1800345B1 (en) | 2013-08-14 |
JP2008512868A (ja) | 2008-04-24 |
TWI353670B (en) | 2011-12-01 |
US20070218647A1 (en) | 2007-09-20 |
KR20070055513A (ko) | 2007-05-30 |
TW200623408A (en) | 2006-07-01 |
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