CN100483683C - Cmos图像传感器及其制造方法 - Google Patents
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Abstract
公开了一种CMOS图像传感器及其制造方法。该方法包括下列步骤:在半导体基片上形成隔离层以限定包括光电二极管区和晶体管区的有源区;在所述晶体管区上形成栅,包括栅绝缘层和其上的栅电极;在所述栅电极的侧面上形成绝缘侧壁;按相继顺序在所述半导体基片的整个表面上形成下绝缘层和上绝缘层;移除除了所述光电二极管区以外的区中的上和下绝缘层;在所述半导体基片的整个表面上形成金属层;并且将所述半导体基片退火以选择性地在所述半导体基片的表面上形成自对准硅化物层。
Description
相关申请的交叉引用
本申请要求了提交于2005年6月17日的韩国专利申请No.10-2005-0052377的权利,其整体通过引用结合于此。
技术领域
本发明涉及一种图像传感器,更具体地,涉及一种互补金属氧化物半导体(CMOS)图像传感器及其制造方法。
背景技术
常规地,作为一种半导体器件的图像传感器将光图像转换为电信号,通常可分类为电荷耦合器件(CCD)和CMOS图像传感器。
CCD包括:布置为矩阵形式的多个光电二极管,以将光信号转换为电信号;形成在所述光电二极管之间的多个竖直电荷耦合器件(VCCD),以在竖直方向上传输产生在每个光电二极管中的电荷;多个水平电荷耦合器件(HCCD),用于在水平方向上传输从每个VCCD传输的电荷;以及感测放大器,用于感测在水平方向传输的电荷以输出电信号。
众所周知,CCD具有复杂的工作机构以及高功率消耗。另外,其制造方法也很复杂,因为在其制作中需要多个步骤的光刻法工艺。特别地,难以将CCD与如控制电路、信号处理电路、模拟/数字转换器等的其它器件集成在单个芯片中。CCD的这些缺点可能阻碍包含CCD的产品的微型化。
为了克服CCD的上述缺点,CMOS图像传感器最近发展为下一代图像传感器。CMOS图像传感器通常包括通过CMOS制作技术形成在半导体基片中的MOS晶体管。在CMOS图像传感器中,MOS晶体管相关于单位像素的数目、连同如控制电路、信号处理电路等的***电路一起形成。CMOS图像传感器采用MOS晶体管依次检测每个像素的输出的切换模式。
更具体地,CMOS图像传感器在每个像素中包括光电二极管和MOS晶体管,因此以切换模式依次检测每个像素的电信号以表示给定的图像。
CMOS图像传感器具有如低功率消耗和相对简单的制作工艺的优点。另外,CMOS图像传感器可与控制电路、信号处理电路、模拟/数字转换器等集成,因为这些电路可使用CMOS制造技术来制造,其使产品能够微型化。
CMOS图像传感器广泛使用在如数字静态照相机、数字摄像机等的各种应用中。
同时,根据单位像素中晶体管的数目,CMOS图像传感器还可分类为3T、4T、5T类型等。所述3T类型的CMOS图像传感器包括1个光电二极管和3个晶体管,且4T类型包括1个光电二极管和4个晶体管。此处,3T类型CMOS图像传感器的电路图和单位像素布局配置如下。
图1为常规CMOS图像传感器的电路图,且图2所示为常规3T类型CMOS图像传感器中的单位像素的布局。
如图1所示,常规3T类型CMOS图像传感器的单位像素包括1个光电二极管PD和3个NMOS晶体管T1、T2和T3。光电二极管PD的阴极连接到第一NMOS晶体管T1的漏和第二NMOS晶体管T2的栅。
特别地,第一和第二NMOS晶体管T1和T2的源连接到用于供应标准电压的供应端子(VR),且第一NMOS晶体管T1的栅连接到用于供应复位信号的复位端子。
另外,第三NMOS晶体管T3的源连接到第二NMOS晶体管T2的漏,且第三NMOS晶体管T3的漏通过单个线连接到检测电路(未示出)。此外,第三NMOS晶体管T3的栅连接到选择信号线SLCT。
一般而言,第一NMOS晶体管T1称为复位晶体管Rx,第二NMOS晶体管T2称为驱动晶体管Dx,且第三NMOS晶体管T3称为选择晶体管Sx。
如图2所示,在常规3T类型CMOS图像传感器中,一个光电二极管20形成在被限定的有源区10的一大部分中,且第一到第三晶体管的3个栅电极30、40和50分别形成为重叠在有源区10的其它部分中。
第一栅电极30构成复位晶体管Rx。第二栅电极40构成驱动晶体管Dx。第三栅电极50构成选择晶体管Sx。
此处,掺杂剂离子被注入其中形成有每个晶体管的有源区10,除了每个栅电极30、40和50下面的有源区部分,以形成每个晶体管的源和漏区。
此处,供应电压Vdd施加于复位晶体管Rx与驱动晶体管Dx之间的源/漏区,且形成在选择晶体管Sx的一侧的源/漏区连接到检测电路(未示出)。
在上述CMOS图像传感器的结构中,反向偏置施加于光电二极管PD,从而导致其中电子由光产生的耗尽层。当复位晶体管Rx关断时,所产生的电子降低驱动晶体管Dx的电势。驱动晶体管电势的降低从复位晶体管Rx的关断开始持续进行,从而导致电势差。图像传感器可通过将所述电势差作为一个信号检测来操作。
图3a到3g是考虑了图2中的A-A'线依次图示了用于制造CMOS图像传感器的常规方法的横截面视图。
如图3a所示,使用外延工艺,低浓度P型外延层62形成在高浓度P++型半导体基片61上。此处,外延层62作用为在光电二极管区中形成深的和宽的耗尽区。因此,可以改善低电压光电二极管的聚集光电子的能力,且还可以改善光灵敏度。
随后,在半导体基片61上限定有源区和隔离区之后,使用浅沟槽隔离(STI)工艺或硅的局部氧化(LOCOS)工艺,隔离层63形成在隔离区中。
接下来,栅绝缘层64和导电层(例如,重掺杂的多晶硅层)以相继顺序沉积在外延层62的整个表面上。使用光刻法和蚀刻工艺,传导层和栅绝缘层64被选择性地图案化,从而形成栅电极65。栅绝缘层64可使用热氧化工艺或化学汽相沉积(CVD)工艺形成。
参考图3b,第一光致抗蚀剂层66施加于包括栅电极65的半导体基片61的整个表面之上,且然后它使用曝光和显影工艺来图案化,从而覆盖光电二极管区并暴露其中将形成源/漏区的晶体管区。
使用第一光致抗蚀剂图案66作为掩模,低浓度N型掺杂剂离子被注入所暴露的晶体管区以形成低浓度N型扩散区67。
如图3c所示,在移除第一光致抗蚀剂图案66之后,第二光致抗蚀剂层68施加于半导体基片61之上,且然后它使用曝光和显影工艺来图案化,从而暴露光电二极管区。
然后,使用第二光致抗蚀剂图案68作为掩模,低浓度N型掺杂剂离子被注入光电二极管区,从而形成低浓度N型扩散区69。此处,使用较高的注入能量,低浓度N型扩散区69优选地以大于低浓度N型扩散区67的扩散深度的扩散深度来形成。
如图3d所示,在移除第二光致抗蚀剂图案68之后,绝缘层形成在基片61的整个表面之上。然后,在绝缘层上执行回蚀刻工艺以在栅电极65的两侧面上形成绝缘侧壁70。
连续地,第三光致抗蚀剂层71形成在基片61的整个表面之上,且然后它使用曝光和显影工艺来图案化,以覆盖光电二极管区并暴露晶体管源/漏区。
使用第三光致抗蚀剂图案71作为掩模,高浓度N型掺杂剂离子被注入源/漏区以形成高浓度N型扩散区72,即N+型扩散区。
然后,第四光致抗蚀剂层82施加于基片61的整个表面之上,且然后它使用曝光和显影工艺来图案化,以覆盖光电二极管区并暴露每个晶体管的源/漏区。
使用湿蚀刻或干蚀刻工艺,通过第四光致抗蚀剂图案82暴露的TEOS层80的一部分被移除,然后所述基片被清洁或漂洗。
如图3f所示,清洁基片61之后,使用物理汽相沉积(PVD)或化学汽相沉积(CVD)工艺,包括如镍等的金属材料的金属层84沉积在基片61的整个表面上。
然后,如图3g所示,半导体基片61经历自对准硅化物工艺,从而在栅电极65上以及其中形成有N+型扩散区72的所述基片的部分上选择性地形成自对准硅化物层73。
在上述常规CMOS图像传感器中,要求不在光电二极管区上形成自对准硅化物层,因为自对准硅化物层反射光。光电二极管区用于吸收光并将其转换为电荷。因此,必须在光电二极管区中进行NSAL处理以防止在其上形成自对准硅化物层,从而减小暗电流。由于相同的原因,光电二极管区中的单个像素接触优选地以非自对准硅化物接触来形成。
但是,上述用于制造CMOS图像传感器的常规方法具有如下问题。
即,如图3e所示,在TEOS氧化物层80通过湿蚀刻工艺来部分地移除的情况下,下切(undercut)可发生在光电二极管区内部,即使其依赖于像素设计裕度。下切引入光电二极管区的自对准硅化(salicidation),从而导致光电二极管结的侵入(invasion)。因此,下切起到电流泄漏的源的作用,导致CMOS图像传感器的暗图像特性和产量的降级。
发明内容
因此,本发明的一个目的是提供一种CMOS图像传感器及其制造方法,其可防止图像传感器的暗图像特性的降级,并改善构成所述图像传感器的晶体管的阈值电压的一致性。最终,本发明可增加CMOS图像传感器的产量
为了实现以上目的,根据本发明的用于制造CMOS图像传感器的方法的一个实施例包括下列步骤:
在半导体基片上形成隔离层以限定包括光电二极管区和晶体管区的有源区;在所述晶体管区上形成栅,包括栅绝缘层和其上的栅电极;在所述栅电极的侧面上形成绝缘侧壁;在源/漏区中形成高浓度部分扩散区;按相继顺序在所述半导体基片的整个表面上形成下绝缘层和上绝缘层;移除除了所述光电二极管区以外的所述基片的区上的上和下绝缘层;在所述半导体基片的整个表面上形成金属层;将所述半导体基片退火以选择性地在所述半导体基片的暴露表面上形成自对准硅化物层;并且去除所述金属层、上和下绝缘层;其中,所述上绝缘层和所述下绝缘层具有不同的厚度,且其中所述下绝缘层具有从到的厚度;其中,通过干蚀刻工艺移除所述上绝缘层;并且,通过湿蚀刻工艺移除所述下绝缘层。
通过参考以下本发明的说明,通常参考附图,本发明的这些和其它方面将变得明显。
附图说明
图1为常规CMOS图像传感器中的单位像素的电路图。
图2为常规CMOS图像传感器中的单位像素的布局。
图3a到3g是考虑了图2中的A-A'线依次图示了用于制造CMOS图像传感器的常规方法的横截面视图。
图4a到4g是考虑了图2中的A-A'线依次图示了用于根据本发明制造CMOS图像传感器的方法的横截面视图。
具体实施方式
在下文中,参考图4a到4g,将以相继顺序说明根据本发明制造CMOS图像传感器的方法的一个实施例。
如图4a所示,使用外延工艺,低浓度P型外延层102形成在高浓度P++型半导体基片101上。此处,外延层102作用为在光电二极管区中形成深的和宽的耗尽区。因此,可以改善低电压光电二极管的聚集光电子的能力,且还可以改善光灵敏度。
随后,在半导体基片101上限定有源区和隔离区之后,使用STI或LOCOS工艺,隔离层103形成在隔离区中。
接下来,栅绝缘层104和导电层(例如,重掺杂的多晶硅层)以相继顺序沉积在外延层102的整个表面上。所述导电层和栅绝缘层被选择性地图案化,从而形成栅电极105。栅绝缘层104可使用热氧化工艺或CVD工艺形成。
参考图4b,第一光致抗蚀剂层106施加于包括栅电极105的基片101的整个表面之上,且然后它使用曝光和显影工艺来图案化,从而覆盖光电二极管区并暴露其中将形成源/漏区的晶体管区。
使用第一光致抗蚀剂图案106作为掩模,低浓度N型掺杂剂离子被注入所暴露的晶体管区以形成低浓度N型扩散区107。
如图4c所示,在移除第一光致抗蚀剂图案106之后,第二光致抗蚀剂层108施加于半导体基片101之上,且然后它使用曝光和显影工艺来图案化,从而暴露光电二极管区。
然后,使用第二光致抗蚀剂图案108作为掩模,低浓度N型掺杂剂离子被注入光电二极管区,从而形成低浓度N型扩散区109。此处,使用较高的注入能量,低浓度N型扩散区109优选地以大于低浓度N型扩散区107的扩散深度的扩散深度来形成。
如图4d所示,在移除第二光致抗蚀剂图案108之后,绝缘层形成在基片101的整个表面之上。然后,在绝缘层上执行回蚀刻工艺以在栅电极105的两侧面上形成绝缘侧壁110。
连续地,第三光致抗蚀剂层111形成在基片101的整个表面之上,且然后它通过曝光和显影工艺来图案化以覆盖光电二极管区并暴露晶体管区源/漏区。
使用第三光致抗蚀剂图案111作为掩模,高浓度N型掺杂剂离子被注入源/漏区以形成高浓度N型扩散区112,即N+型扩散区。
如图4e所示,使用低压CVD工艺(LPCVD),下绝缘层119和上绝缘层120以相继顺序沉积在半导体基片101的整个表面上。下和上绝缘层119和120被用作自对准硅化物阻挡层,且它们具有彼此不同的蚀刻选择性。使用诸如氮化硅(SiN)的材料,下绝缘层119优选地以从约到约的厚度来形成。另外,使用诸如TEOS的材料,上绝缘层120优选地以从约到约的厚度来形成。特别地,使用LPCVD工艺的原因是为了防止硅基片被等离子体损坏。在等离子体损坏的情况下,暗和白状态下的图像传感器的泄漏特性变得恶化,从而导致减少器件的产量和性能。
然后,第四光致抗蚀剂层122施加于基片101的整个表面之上,且然后它通过曝光和显影工艺来图案化以覆盖光电二极管区并暴露每个晶体管的源/漏区。
随后,在通过第四光致抗蚀剂图案122暴露的区上的上绝缘层120通过使用50%过蚀刻率的干蚀刻工艺来部分地移除。然后,半导体基片101经历清洁工艺。在上绝缘层120的这种干蚀刻工艺中,与一常规的实例相比,待被干蚀刻的上绝缘层相对薄。另外,因为具有优良蚀刻选择性的下绝缘层119形成在上绝缘层120之下,所以硅基片的等离子体损坏可在干蚀刻工艺期间被最小化。特别地,在常规方法中,绝缘层需要保留小于约的厚度。但是,在本发明中,不必要保留上绝缘层,因为具有大于约的厚度的下绝缘层119存在于上绝缘层120之下。
然后,在通过第四光致抗蚀剂图案122暴露的区中的下绝缘层119通过湿蚀刻工艺移除。然后,半导体基片101被清洁或漂洗。磷酸(H3PO4)可在湿蚀刻工艺中用作蚀刻剂以在除光电二极管区之外的区中完全移除下绝缘层119。在下绝缘层119的这种湿蚀刻工艺中,由各向同性的蚀刻工艺引起的下切很少发生在第四光致抗蚀剂图案122内部,因为下绝缘层119的沉积厚度(即)相对薄。
如图4f所示,在完成基片101的清洁工艺之后,使用PVD或CVD工艺,包括金属材料(例如镍)的金属层124沉积在基片101的整个表面上。而且,金属层124可包括钴、钛、钨、钽、钼以及其它具有高熔点的金属材料。
然后,如图4g所示,半导体基片101经历包括退火处理的自对准硅化物工艺,且保留的金属层124被移除。从而,自对准硅化物层113选择性地形成在栅电极105上和其中形成有N+型扩散区112的基片的部分上。
上述根据本发明制造CMOS图像传感器的方法具有以下优点。
首先,形成在光电二极管区中具有不同材料和厚度的上和下绝缘层,防止光电二极管区的自对准硅化。因此,确认可以防止由光电二极管的泄漏特性的降级引起的暗电流的增大。最终,可防止图像传感器的暗图像特性的恶化。
其次,当上绝缘层被干蚀刻且下绝缘层被湿蚀刻时,由干蚀刻工艺引起的等离子体损坏和由湿蚀刻工艺引起的下切可被最小化。从而,可相当地减小CMOS图像传感器的暗电流,并且可以改善暗图像特性。结果,可以增加CMOS图像传感器的产量。特别地,PMOS晶体管的阀值电压的变化可被最小化,从而导致器件可靠性的改善。
尽管已参考某些优选实施例示出并说明了本发明,本领域技术人员应理解,可以不背离如所附权利要求所限定的本发明的精神和范围而对形式和细节做出各种改变。
Claims (7)
1.一种用于制造CMOS图像传感器的方法,包括下列步骤:
在半导体基片上形成隔离层以限定包括光电二极管区和晶体管区的有源区;
在所述晶体管区上形成栅,包括栅绝缘层和其上的栅电极;
在所述栅电极的侧面上形成绝缘侧壁;
在源/漏区中形成高浓度部分扩散区;
按相继顺序在所述半导体基片的整个表面上形成下绝缘层和上绝缘层;
移除除了所述光电二极管区以外的所述基片的区上的上和下绝缘层;
在所述半导体基片的整个表面上形成金属层;
将所述半导体基片退火以选择性地在所述半导体基片的暴露表面上形成自对准硅化物层;并且
去除所述金属层、上和下绝缘层;
其中,通过干蚀刻工艺移除所述上绝缘层,并且通过湿蚀刻工艺移除所述下绝缘层。
3.权利要求1的方法,其中所述下绝缘层包括氮化硅。
4.权利要求1的方法,其中所述上绝缘层使用原硅酸四乙酯形成。
5.权利要求1的方法,其中所述上和下绝缘层具有彼此不同的蚀刻选择性。
6.权利要求1的方法,其中所述下绝缘层使用包括磷酸的蚀刻剂来湿蚀刻。
7.权利要求1的方法,其中所述上和下绝缘层使用低压化学汽相沉积工艺来形成。
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Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100672729B1 (ko) * | 2005-07-14 | 2007-01-24 | 동부일렉트로닉스 주식회사 | 씨모스 이미지 센서의 제조방법 |
US20080160731A1 (en) * | 2006-12-27 | 2008-07-03 | Dongbu Hitek Co., Ltd. | Method for fabricating cmos image sensor |
KR100881016B1 (ko) * | 2007-06-25 | 2009-01-30 | 주식회사 동부하이텍 | 이미지 센서 및 그 제조방법 |
US9093379B2 (en) * | 2013-05-29 | 2015-07-28 | International Business Machines Corporation | Silicidation blocking process using optically sensitive HSQ resist and organic planarizing layer |
CN103456615B (zh) * | 2013-09-02 | 2016-04-27 | 上海华力微电子有限公司 | 改善金属硅化物掩模层缺陷的方法 |
Family Cites Families (71)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR950000141B1 (ko) * | 1990-04-03 | 1995-01-10 | 미쓰비시 뎅끼 가부시끼가이샤 | 반도체 장치 및 그 제조방법 |
JP3036565B2 (ja) * | 1992-08-28 | 2000-04-24 | 日本電気株式会社 | 不揮発性半導体記憶装置の製造方法 |
JP3221766B2 (ja) * | 1993-04-23 | 2001-10-22 | 三菱電機株式会社 | 電界効果トランジスタの製造方法 |
US5510279A (en) * | 1995-01-06 | 1996-04-23 | United Microelectronics Corp. | Method of fabricating an asymmetric lightly doped drain transistor device |
US5550073A (en) * | 1995-07-07 | 1996-08-27 | United Microelectronics Corporation | Method for manufacturing an EEPROM cell |
US5672531A (en) * | 1996-07-17 | 1997-09-30 | Advanced Micro Devices, Inc. | Method for fabrication of a non-symmetrical transistor |
US5874340A (en) * | 1996-07-17 | 1999-02-23 | Advanced Micro Devices, Inc. | Method for fabrication of a non-symmetrical transistor with sequentially formed gate electrode sidewalls |
US5930631A (en) * | 1996-07-19 | 1999-07-27 | Mosel Vitelic Inc. | Method of making double-poly MONOS flash EEPROM cell |
US5793079A (en) * | 1996-07-22 | 1998-08-11 | Catalyst Semiconductor, Inc. | Single transistor non-volatile electrically alterable semiconductor memory device |
US5677224A (en) * | 1996-09-03 | 1997-10-14 | Advanced Micro Devices, Inc. | Method of making asymmetrical N-channel and P-channel devices |
US5759897A (en) * | 1996-09-03 | 1998-06-02 | Advanced Micro Devices, Inc. | Method of making an asymmetrical transistor with lightly and heavily doped drain regions and ultra-heavily doped source region |
US6051471A (en) * | 1996-09-03 | 2000-04-18 | Advanced Micro Devices, Inc. | Method for making asymmetrical N-channel and symmetrical P-channel devices |
US5656518A (en) * | 1996-09-13 | 1997-08-12 | Advanced Micro Devices, Inc. | Method for fabrication of a non-symmetrical transistor |
JPH10163311A (ja) * | 1996-11-27 | 1998-06-19 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
US5904528A (en) * | 1997-01-17 | 1999-05-18 | Advanced Micro Devices, Inc. | Method of forming asymmetrically doped source/drain regions |
US5923982A (en) * | 1997-04-21 | 1999-07-13 | Advanced Micro Devices, Inc. | Method of making asymmetrical transistor with lightly and heavily doped drain regions and ultra-heavily doped source region using two source/drain implant steps |
DE69841732D1 (de) * | 1997-05-13 | 2010-08-05 | St Microelectronics Srl | Verfahren zur selektiven Herstellung von Salizid über aktiven Oberflächen von MOS-Vorrichtungen |
SE512813C2 (sv) * | 1997-05-23 | 2000-05-15 | Ericsson Telefon Ab L M | Förfarande för framställning av en integrerad krets innefattande en dislokationsfri kollektorplugg förbunden med en begravd kollektor i en halvledarkomponent, som är omgiven av en dislokationsfri trench samt integrerad krets framställd enligt förfarandet |
US5920103A (en) * | 1997-06-20 | 1999-07-06 | Advanced Micro Devices, Inc. | Asymmetrical transistor having a gate dielectric which is substantially resistant to hot carrier injection |
US6100170A (en) * | 1997-07-07 | 2000-08-08 | Matsushita Electronics Corporation | Method of manufacturing semiconductor device |
US5851893A (en) * | 1997-07-18 | 1998-12-22 | Advanced Micro Devices, Inc. | Method of making transistor having a gate dielectric which is substantially resistant to drain-side hot carrier injection |
US6004849A (en) * | 1997-08-15 | 1999-12-21 | Advanced Micro Devices, Inc. | Method of making an asymmetrical IGFET with a silicide contact on the drain without a silicide contact on the source |
US5986310A (en) * | 1997-09-08 | 1999-11-16 | Winbond Electronics Corp. | Prolonging a polysilicon layer in smaller memory cells to prevent polysilicon load punch through |
US6023081A (en) * | 1997-11-14 | 2000-02-08 | Motorola, Inc. | Semiconductor image sensor |
US6096605A (en) * | 1997-12-24 | 2000-08-01 | United Semiconductor Corp. | Fabricating method of non-volatile flash memory device |
US6069042A (en) * | 1998-02-13 | 2000-05-30 | Taiwan Semiconductor Manufacturing Company | Multi-layer spacer technology for flash EEPROM |
US6153477A (en) * | 1998-04-14 | 2000-11-28 | Advanced Micro Devices, Inc. | Ultra short transistor channel length formed using a gate dielectric having a relatively high dielectric constant |
JP3103064B2 (ja) * | 1998-04-23 | 2000-10-23 | 松下電子工業株式会社 | 固体撮像装置およびその製造方法 |
US6096615A (en) * | 1998-04-29 | 2000-08-01 | Advanced Micro Devices, Inc. | Method of forming a semiconductor device having narrow gate electrode |
US6239011B1 (en) * | 1998-06-03 | 2001-05-29 | Vanguard International Semiconductor Corporation | Method of self-aligned contact hole etching by fluorine-containing discharges |
US6252271B1 (en) * | 1998-06-15 | 2001-06-26 | International Business Machines Corporation | Flash memory structure using sidewall floating gate and method for forming the same |
US6124610A (en) * | 1998-06-26 | 2000-09-26 | Advanced Micro Devices, Inc. | Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant |
US5972751A (en) * | 1998-08-28 | 1999-10-26 | Advanced Micro Devices, Inc. | Methods and arrangements for introducing nitrogen into a tunnel oxide in a non-volatile semiconductor memory device |
JP2000091574A (ja) * | 1998-09-07 | 2000-03-31 | Denso Corp | 半導体装置および半導体装置の製造方法 |
US6376868B1 (en) * | 1999-06-15 | 2002-04-23 | Micron Technology, Inc. | Multi-layered gate for a CMOS imager |
JP3307372B2 (ja) * | 1999-07-28 | 2002-07-24 | 日本電気株式会社 | 半導体装置およびその製造方法 |
TW429615B (en) * | 1999-11-06 | 2001-04-11 | United Microelectronics Corp | Fabricating method for the capacitor of dynamic random access memory |
US6339248B1 (en) * | 1999-11-15 | 2002-01-15 | Omnivision Technologies, Inc. | Optimized floating P+ region photodiode for a CMOS image sensor |
US6530380B1 (en) * | 1999-11-19 | 2003-03-11 | Chartered Semiconductor Manufacturing Ltd. | Method for selective oxide etching in pre-metal deposition |
JP3782297B2 (ja) * | 2000-03-28 | 2006-06-07 | 株式会社東芝 | 固体撮像装置及びその製造方法 |
US6518137B2 (en) * | 2001-01-19 | 2003-02-11 | United Microelectronics Corp. | Method for forming steep spacer in a MOS device |
JP4897146B2 (ja) * | 2001-03-02 | 2012-03-14 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法、および半導体装置 |
US6872612B2 (en) * | 2001-06-27 | 2005-03-29 | Lsi Logic Corporation | Local interconnect for integrated circuit |
TW535293B (en) * | 2001-10-03 | 2003-06-01 | Hannstar Display Corp | Structure of and method for producing double vertical channel thin film transistor (DVC TFT) CMOS |
KR100399952B1 (ko) * | 2001-11-16 | 2003-09-29 | 주식회사 하이닉스반도체 | 암전류를 감소시키기 위한 이미지센서의 제조 방법 |
IL156497A (en) * | 2002-06-20 | 2007-08-19 | Samsung Electronics Co Ltd | Image sensor and method of fabricating the same |
JP3795843B2 (ja) * | 2002-08-01 | 2006-07-12 | 富士通株式会社 | 半導体受光装置 |
US6767770B1 (en) * | 2002-10-01 | 2004-07-27 | T-Ram, Inc. | Method of forming self-aligned thin capacitively-coupled thyristor structure |
KR100479208B1 (ko) * | 2002-10-23 | 2005-03-28 | 매그나칩 반도체 유한회사 | 살리사이드 공정을 이용한 이미지센서의 제조 방법 |
JP2004200321A (ja) * | 2002-12-17 | 2004-07-15 | Fuji Film Microdevices Co Ltd | 固体撮像素子およびその製造方法 |
US6974715B2 (en) * | 2002-12-27 | 2005-12-13 | Hynix Semiconductor Inc. | Method for manufacturing CMOS image sensor using spacer etching barrier film |
US7037763B1 (en) * | 2002-12-31 | 2006-05-02 | T-Ram Semiconductor, Inc. | Gated-thyristor approach having angle-implanted base region |
US6734070B1 (en) * | 2003-03-17 | 2004-05-11 | Oki Electric Industry Co., Ltd. | Method of fabricating a semiconductor device with field-effect transistors having shallow source and drain junctions |
JP2004335588A (ja) * | 2003-05-01 | 2004-11-25 | Renesas Technology Corp | 固体撮像装置及びその製造方法 |
US6908839B2 (en) * | 2003-09-17 | 2005-06-21 | Micron Technology, Inc. | Method of producing an imaging device |
KR100544957B1 (ko) * | 2003-09-23 | 2006-01-24 | 동부아남반도체 주식회사 | 시모스 이미지 센서의 제조방법 |
JP3724648B2 (ja) * | 2003-10-01 | 2005-12-07 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
KR100508867B1 (ko) * | 2003-12-27 | 2005-08-17 | 동부아남반도체 주식회사 | p채널형 모스 트랜지스터 및 상보형 모스 트랜지스터의제조 방법 |
KR20050066872A (ko) * | 2003-12-27 | 2005-06-30 | 동부아남반도체 주식회사 | 높은 브레이크다운 전압을 갖는 고전압 반도체 소자 및 그제조 방법 |
KR100595899B1 (ko) * | 2003-12-31 | 2006-06-30 | 동부일렉트로닉스 주식회사 | 이미지 센서 및 그 제조방법 |
KR100719338B1 (ko) * | 2004-06-15 | 2007-05-17 | 삼성전자주식회사 | 이미지 센서 및 그 형성 방법 |
US7368775B2 (en) * | 2004-07-31 | 2008-05-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Single transistor DRAM cell with reduced current leakage and method of manufacture |
US7122435B2 (en) * | 2004-08-02 | 2006-10-17 | Texas Instruments Incorporated | Methods, systems and structures for forming improved transistors |
JP2006114657A (ja) * | 2004-10-14 | 2006-04-27 | Matsushita Electric Ind Co Ltd | 固体撮像装置およびその製造方法 |
JP2006140447A (ja) * | 2004-10-14 | 2006-06-01 | Renesas Technology Corp | 半導体装置およびその製造方法 |
US7345330B2 (en) * | 2004-12-09 | 2008-03-18 | Omnivision Technologies, Inc. | Local interconnect structure and method for a CMOS image sensor |
US7858458B2 (en) * | 2005-06-14 | 2010-12-28 | Micron Technology, Inc. | CMOS fabrication |
US20070161144A1 (en) * | 2005-12-28 | 2007-07-12 | Im Ki S | Method for Manufacturing CMOS Image Sensor |
KR100721245B1 (ko) * | 2005-12-29 | 2007-05-22 | 동부일렉트로닉스 주식회사 | 트랜지스터 소자 및 형성 방법 |
CN1992215A (zh) * | 2005-12-29 | 2007-07-04 | 东部电子股份有限公司 | 制造cmos图像传感器的方法 |
JP2008021957A (ja) * | 2006-06-15 | 2008-01-31 | Matsushita Electric Ind Co Ltd | 固体撮像装置 |
-
2005
- 2005-06-17 KR KR1020050052377A patent/KR100720474B1/ko not_active IP Right Cessation
-
2006
- 2006-06-16 CN CNB2006100870823A patent/CN100483683C/zh not_active Expired - Fee Related
- 2006-06-19 US US11/471,244 patent/US20060284223A1/en not_active Abandoned
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US20060284223A1 (en) | 2006-12-21 |
KR20060132180A (ko) | 2006-12-21 |
KR100720474B1 (ko) | 2007-05-22 |
CN1881565A (zh) | 2006-12-20 |
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