CN100466712C - 再现设备、数据处理***以及再现方法 - Google Patents

再现设备、数据处理***以及再现方法 Download PDF

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Publication number
CN100466712C
CN100466712C CNB2005101141652A CN200510114165A CN100466712C CN 100466712 C CN100466712 C CN 100466712C CN B2005101141652 A CNB2005101141652 A CN B2005101141652A CN 200510114165 A CN200510114165 A CN 200510114165A CN 100466712 C CN100466712 C CN 100466712C
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picture data
reproduction
data
picture
decoding
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CN1767622A (zh
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纲岛修二
柴田正二郎
高村元嗣
小薮恭平
柿田新次郎
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Sony Corp
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Sony Corp
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Abstract

一种用于按次序解码和再现形成再现数据的多个画面数据的再现设备，包含：再现存储器；解码器，用于对画面数据进行解码，在再现存储器中写入解码结果，并且再现和输出从再现存储器中读取的解码结果；以及处理电路，用于执行解码调度，以便确定按多个画面数据的预定单位、在该解码器处解码画面数据的次序，以由解码调度所确定的次序选择要被处理的画面数据，依据所指定的再现速度、确定是否解码所选择的画面数据或者再现和输出解码结果，以及基于该判定控制解码器的解码以及再现和输出。

Description

再现设备、数据处理***以及再现方法
相关申请的交叉引用
本发明包含与2004年10月26在日本专利局提交的日本专利申请2004-311596以及在2005年8月24日在日本专利局提交的日本专利申请2005-243292相关的主题，它们的整个内容通过引用包含在此。
技术领域
本发明涉及用于对已再现的数据进行再现的再现设备、数据处理***、再现方法、程序、以及存储介质。
背景技术
例如，存在有对由MPEG(运动图像专家组)方案编码的再现数据进行解码和再现的再现设备。这样的再现设备，例如，执行解码调度，以便以形成再现数据(GOP)的I、P、和B画面数据组为单位、确定对依据画面数据的参考关系和再现速度所选择的画面数据进行解码的计时和次序，并且依据解码调度的结果解码该画面数据并且再现和输出解码结果。在这个再现设备中，例如，当接收到改变再现速度的命令时，在正被再现的GOP之后的下一个GOP的解码调度中，生成对应于改变的再现速度的解码调度的结果。作为参考，参见日本专利公开(A)2003-101967。
然而，在上述相关领域的再现设备中，当接收到改变再现速度的命令时，因为在正被再现的GOP之后的下一个GOP的解码调度中生成对应于所改变的再现速度的解码调度结果，所以仅仅在当接收到该改变命令时正被解码并且被再现和输出的GOP之后的下一个GOP中，获得对应于所改变的再现速度的再现和输出。因此，从接收改变再现速度的命令的时刻到获得对应于所改变的再现速度的再现和输出的时刻需要较长时间，也就是说，其具有响应差的缺点。
发明内容
本发明的一个目的是提供一种再现设备、数据处理***、再现方法、程序、和存储介质，它们在连续地解码并且再现和输出多个画面数据的时候，和相关技术相比，能够缩短从接收改变再现速度的命令的时刻到获得对应于所改变的再现速度的再现和输出的时刻的时间。
依据本发明的第一方面，提供了一种用于按次序解码和再现形成再现数据的多个画面数据的再现设备，该设备包含：再现存储器；解码器，用于对画面数据进行解码，在再现存储器中写入解码结果，并且再现和输出从再现存储器中读取的解码结果；以及处理电路，用于执行解码调度，以便确定使解码器按多个画面数据的预定单位解码画面数据的次序，以由解码调度所确定的次序选择要被处理的画面数据，依据所指定的再现速度、确定是否解码所选择的画面数据或者再现和输出解码结果，以及基于该判定控制解码器的解码以及再现和输出。
处理电路执行解码调度，以便确定使解码器按多个画面数据的预定单位解码画面数据的次序。此外，处理电路以由解码调度所确定的次序，选择要被处理的画面数据。处理电路然后依据所指定的再现速度、确定是否解码所选择的画面数据或者再现和输出该解码结果，并且基于该判定控制解码器的解码以及再现和输出。
依据本发明的第二方面，提供了一种数据处理***，该***包含：数据处理设备，用于输出形成再现数据的多个画面数据到再现设备；以及再现设备，用于连续地解码和再现从数据处理设备输入的多个画面数据，该再现设备包含：输入存储器，用于存储从数据处理设备输入的画面数据；再现存储器；解码器，对从输入存储器读取的画面数据进行解码，在再现存储器中写入解码结果，并且再现和输出从再现存储器中读取的解码结果；以及处理电路，用于执行解码调度，以便确定使解码器以预定多个画面数据为单位解码画面数据的次序，以由解码调度所确定的次序选择要被处理的画面数据，依据所指定的再现速度、确定是否解码所选择的画面数据或者再现或输出解码结果，以及基于那个确定控制解码器的解码以及再现和输出。
依据本发明的第三方面，提供了一种用于连续地解码和再现形成再现数据的多个画面数据的再现方法，该方法包含：第一步骤，执行解码调度，以便确定以预定多个画面数据为单位解码画面数据的次序；第二步骤，基于由在第一步骤中的解码调度所确定的次序选择要被处理的画面数据；第三步骤，依据所指定的再现速度、确定是否解码在第二步骤选择的画面数据或者再现和输出解码结果；以及第四步骤，基于第三步骤的确定、控制解码以及解码结果的再现和输出。
依据本发明的第四方面，提供了一种再现方法，该方法包含：第一步骤，用于从数据处理设备输出形成再现数据的多个画面数据到再现设备；第二步骤，使再现设备执行解码调度，以便确定以预定多个画面数据为单位解码在第一步骤中从数据处理设备输入的画面数据的次序；第三步骤，基于由在第二步骤中执行的解码调度所确定的次序选择要被处理的画面数据；第四步骤，依据所指定的再现速度、确定是否解码在第三步骤选择的画面数据或者再现和输出解码结果；以及第五步骤，基于第四步骤的确定、控制解码以及解码结果的再现和输出。
依据本发明的第五方面，提供了一种由连续地解码和再现形成再现数据的多个画面数据的再现设备执行的程序，该程序包含：第一例程，执行解码调度，以便确定以预定多个画面数据为单位解码画面数据的次序；第二例程，以由在第一例程中的解码调度所确定的次序选择要被处理的画面数据；第三例程，依据所指定的再现速度、确定是否解码在第二例程中选择的画面数据或者再现和输出这些解码结果；以及第四例程，基于第三例程的确定、控制解码以及解码结果的再现和输出。
依据本发明的第六方面，提供了一种存储程序的存储介质，该程序由连续地解码和再现形成再现数据的多个画面数据的再现设备执行，该程序包含：第一例程，执行解码调度，以便确定以预定多个画面数据为单位解码画面数据的次序；第二例程，以由在第一例程中的解码调度所确定的次序选择要被处理的画面数据；第三例程，依据所指定的再现速度、确定是否解码在第二例程中选择的画面数据或者再现和输出这些解码结果；以及第四例程，基于第三例程的确定、控制解码以及解码结果的再现和输出。
依据本发明的第七方面，提供了一种数据处理设备，该设备包含：存储介质，存储形成再现数据的多个画面数据；读取装置，用于从存储介质中读取画面数据；输入存储器，用于存储由读取装置读取的画面数据；再现存储器；解码器，用于对从输入存储器读取的画面数据进行解码，在再现存储器中写入解码结果，并且再现和输出从再现存储器中读取的解码结果；以及处理电路，用于执行解码调度，以便确定使解码器以预定多个画面数据为单位解码画面数据的次序，以由解码调度所确定的次序选择要被处理的画面数据，依据所指定的再现速度、确定是否解码所选择的画面数据或者再现或输出这些解码结果，以及基于那个确定控制解码器的解码以及解码器的再现和输出。
依据本发明，有可能提供这样的再现设备、数据处理***、再现方法、程序、和存储介质，它们在连续地解码和再现多个画面数据的情况下，和相关技术相比，能够缩短从接收改变再现速度的命令的时刻到获得对应于所改变的再现速度的再现和输出的时刻的时间。
附图说明
根据以下参考附图给出的优选实施例的描述，本发明的这些及其他目的和特征将变得更清楚，其中：
图1是依据本发明第一实施例的数据处理***的整体配置的视图；
图2是用于说明要由图1所示的数据处理***解码的再现数据ENC的视图；
图3是在沿前向方向再现图2所示的再现数据ENC的情况下，由解码器34_1、34_2、和34_3进行的解码、再现存储器36_1到36_3的存储状态、以及再现和输出的视图；
图4是在沿前向方向再现图2所示的再现数据ENC的情况下，由解码器34_1、34_2、和34_3进行的解码、再现存储器36_1到36_3的存储状态、以及再现和输出的接着图3的视图；
图5是用于说明图1所示的数据处理***的整体操作的示例的流程图；
图6是用于说明图1所示的数据处理***的整体操作的示例的接着图5的流程图；
图7是用于说明图1所示的数据处理***的整体操作的示例的接着图6的流程图；
图8为一个视图，用于说明在当如图3和图4所示执行前向(FWD)1X速度再现时、在以1.5X速度再现、3X速度再现、和1X速度再现的次序改变再现速度的情况下再现设备的操作示例；
图9为接着图8的视图，用于说明在当如图3和图4所示执行前向(FWD)1X速度再现时、在以1.5X速度再现、3X速度再现、和1X速度再现的次序改变再现速度的情况下再现设备的操作示例；
图10是依据本发明第二实施例的数据处理***的整体配置的视图；
图11为一个视图，用于说明其中图10所示的数据处理***以反向(REV)方向对再现数据ENC进行再现的操作；
图12为接着图11的视图，用于说明其中图10所示的数据处理***以反向(REV)方向对再现数据ENC进行再现的操作；
图13为一个视图，用于说明在图10所示的数据处理***中，从图11所示的1X速度反向再现以变到1.5X速度反向再现、3X速度反向再现、和1X速度反向再现的次序改变再现速度的情况；
图14为接着图13的视图，用于说明在图10所示的数据处理***中，从图11所示的1X速度反向再现以变到1.5X速度反向再现、3X速度反向再现、和1X速度反向再现的次序改变再现速度的情况；
图15是依据本发明第三实施例的数据处理***的整体配置的视图；
图16是用于说明图15所示的调度缓冲器的视图；
图17是用于说明画面属性数据PP的格式的视图；
图18是一个视图，用于说明在图15所示的再现设备中、连续地输出从1X速度再现到2X速度改变命令和3X速度改变命令的情况下，调度缓冲器45_1中的状态改变；
图19是一个视图，用于说明在图15所示的再现设备中、连续地输出从3X速度再现到2X速度改变命令和1X速度改变命令的情况下，调度缓冲器45_1中的状态改变；
图20是用于说明图15所示的数据处理***的操作示例的流程图；
图21是用于说明图15所示的数据处理***的操作示例的接着图20的流程图；
图22是用于说明图15所示的数据处理***的操作示例的接着图21的流程图；以及
图23是用于说明图15所示的数据处理***的操作示例的接着图22的流程图。
具体实施方式
下面，将描述依据本发明实施例的数据处理***。
<第一实施例>
在这个实施例中，示出了其中再现设备具有多个解码器的情况。
图1是依据本发明一个实施例的数据处理***1的整体配置的视图。如图1所示，数据处理***1例如具有计算机2和再现设备4。
[计算机2]
如图1所示，计算机2具有HDD 12、桥接器14、存储器16、桥接器18、操作设备19、以及CPU 20。例如，HDD 12存储依据MPEG方案编码的再现数据ENC。如图2所示，再现数据ENC由在再现设备4处连续解码的多个GOP(画面组)组成。在图2所示的示例中，以GOP(N-1)、(N)、(N+1)、(N+2)、和(N+3)的次序进行解码。每个GOP由I、P、和B画面数据(帧数据)组成。此外，每个GOP包括单个I画面数据。在当前实施例中，例如，使用在GOP中具有相对大量画面数据的所谓的“长GOP”。要注意到：在这个申请的附图中，在左上部分没有向属于GOP(N-1)的画面数据给出任何符号，在左上部分向属于GOP(N)的画面数据给出星号，在左上部分向属于GOP(N+1)的画面数据给出“+”，在左上部分向属于GOP(N+2)的画面数据给出“-”，以及在左上部分向属于GOP(N+3)的画面数据给出“/”。此外，在附图中，附在“I”、“P”、和“B”的底部右侧的数字示出其中画面数据的解码结果被再现和输出的次序。
I画面数据是内(帧内)编码图像的画面数据，并且独立于其它画面数据进行编码。此外，P画面数据是沿前向方向预测性地编码的帧的画面数据，并且参考在时间方面位于过去(先前的显示次序)的I或者P画面数据进行解码。要注意到，“I和P画面数据”还被称为“锚(anchor)画面数据”。此外，B画面数据是在两个方向预测性编码的帧的画面数据，并且在参考在时间方面位于之前或者之后(在前或者在后的显示次序)的I或者P画面数据的同时进行解码。要注意到：HDD12的读出速度比再现设备4的最大再现速度要慢。
桥接器14提供了桥接器18的扩展功能并且具有PCI扩展槽或者IDE(集成驱动器电子电路)槽等。桥接器14基本上具有与桥接器18相同的功能，但是具有比桥接器18更窄的带宽，并且与连接到桥接器18的设备相比，连接到桥接器14的设备的具有较低的存取速度。
存储器16例如是半导体存储器，并且存储用于CPU 20进行处理的程序和数据。操作设备19是键盘、鼠标、或者其它操作装置，并且输出对应于用户操作的操作信号到CPU 20。操作设备19接收用于指定再现数据ENC的再现点的操作、用于发出所指定的再现点的再现开始命令的操作、以及依据基于未显示的操作屏幕的用户操作的瞬变命令操作，并且向CPU 20输出表明该操作的操作信号。桥接器18与桥接器14、存储器16、PCI总线6、和CPU 20相连，而且转换数据并且通过CPU 20地址总线和数据总线传输该数据。
例如，CPU 20执行从存储器16读取的程序，以便控制计算机2的操作。当CPU 20从操作设备19接收到指示用于指定再现点的操作的操作信号时，它从HDD 12中读取包括所指定的再现点的画面数据的GOP，并且通过桥接器18和PCI总线6将GOP输出到再现设备4。此外，当CPU 20从操作设备19接收到指示再现开始命令的操作信号时，它通过桥接器18和PCI总线6输出包括所指定的再现点的再现开始命令到再现设备4。此外，当CPU 20从操作设备19接收到指示速度改变命令的操作信号时，它通过桥接器18和PCI总线6输出速度改变命令到再现设备4。此外，当CPU 20从操作设备19接收到指示瞬变命令操作的操作信号时，它通过桥接器18和PCI总线6输出该瞬变命令到再现设备4。此外，CPU 20将GOP输出到再现设备，以便将在再现数据ENC中的GOP当中、按显示次序在这样的GOP之前一个位置的GOP、以及按显示次序在这样的GOP之后一个位置的GOP存储到再现设备的输入存储器32中，其中所述这样的GOP包括在再现设备4中的再现点的画面数据。
[再现设备4]
如图1所示，例如，再现设备4具有PCI桥接器30、输入存储器32、解码器34_1到34_3、再现存储器36_1到36_3、选择器38、控制存储器40、CPU42、以及控制总线46。要注意到，控制存储器40存储预定程序(本发明的程序)，而且CPU 42读取并且执行该程序以执行以下的处理。预定程序可以存储在半导体存储器或者其它控制存储器40中，或者可以存储在HDD、光盘、或者其它存储介质上。
PCI桥接器30具有存储器，用于缓存经由PCI总线6从计算机2输入的GOP和命令。此外，桥接器18具有动态存储器存取(DMA)传输功能。
“输入存储器32”：
输入存储器32是SDRAM或者其它半导体存储器，并且暂时存储经由PCI桥接器30输入的GOP。
“解码器34_1、34_2、34_3”：
解码器34_1依据从CPU 42输入的解码命令(CPU 42的控制)，通过PCI桥接器30接收从输入存储器32读取的再现数据ENC作为输入，依据MPEG***解码该数据，并且把结果写入到再现存储器36_1中。具体地说，解码器34_1在CPU 42的控制下，解码从输入存储器32读取的I画面数据而不用参考其它画面数据的解码结果。此外，解码器34_1在CPU 42的控制下，通过参考在时间方面处于过去的、并且已经将解码结果存储在相应的再现存储器36_1中的I或者P画面数据的解码结果，解码从输入存储器32读取的P画面数据。
图3和图4是示出由解码器34_1、34_2、和34_3沿前向方向以1X速度对再现数据ENC进行再现时进行的解码、再现存储器36_1到36_3的存储器状态、以及产物和输出。在图3、图4、以及后面说明的相应附图中，被示为与解码器34_1相联系的存储体区域“0”到“7”是在再现存储器36_1中定义的存储体区域，被示为与解码器34_2相联系的存储体区域“0”到“7”是在再现存储器36_2中定义的存储体区域，以及被示为与解码器34_3相联系的存储体区域“0”到“7”是在再现存储器36_3中定义的存储体区域。此外，“out0”、“out1”、和“out2”表示从解码器34_1、34_2、和34_3输出到选择器38的解码结果。此外，最底部的“再现和输出”示出来自选择器38的再现和输出。此外，在图3、图4、以及后面说明的相应附图中，被示为由粗线包围的部分表示由解码器34_1、34_2、和34_3所进行的解码。
如图3和图4所示，在依据来自CPU 42的解码命令、沿CPU 42指定的再现方向连续再现的情况下，解码器34_1在再现存储器36_1中保持不再用于再现和输出的I和P画面数据的解码结果的存储。例如，解码器34_1即使在完成GOP(N-1)的再现和输出之后还保持I2、P5、P8、P11、P14、＊I2的解码结果。为此，如下所述，当出现速度改变命令时，通过使用保持存储在再现存储器36_1中的解码结果，能够就在速度改变之后、在用于一个画面的处理时间内执行再现和输出。也就是说，当出现速度改变命令时，解码器34_1能够使用在该速度改变命令之前、早已经存储在再现存储器36_1中的I和P画面数据的解码结果用于再现和输出。具体地说，对于I和P画面数据，解码器34_1依据来自CPU 42的解码命令、在速度改变命令之后读取并且再现和输出早已经存储在再现存储器36_1中的I和P画面数据的解码结果。此外，对于B画面数据，解码器34_1依据来自CPU 42的解码命令、在速度改变命令之后参考早已经存储在再现存储器36_1中的、形成该B画面数据的锚画面数据的I和P画面数据的解码结果来执行解码，并且依据来自CPU 42的显示命令再现和输出该解码结果。
此外，如图3所示，解码器34_1依据来自CPU 42的解码命令、在B画面数据之前解码在正被解码的GOP中的I和P画面数据，并且把解码结果写入到再现存储器36_1中。
解码器34_2和34_3具有与解码器34_1相同的配置。它们依据MPEG方案解码经由PCI桥接器30输入的图像数据，并且把结果写入到它们相应的再现存储器36_2和36_3中。
在下面，将说明由解码器34_1、34_2、和34_3将解码结果写入到再现存储器36_1、36_2、和36_3中的方法。如图3和图4所示，再现存储器36_1、36_2、和36_3每个都具有八个存储体区域“0”到“7”。在这个实施例中，如图3和图4所示，在每个再现存储器36_1、36_2、和36_3处提供的八个存储体区域当中，六个存储体区域“0”到“6”固定地用作用于排他地存储I和P画面数据的解码结果的存储区域，而且两个存储体区域“6”和“7”固定地用作用于存储B画面数据的解码结果的存储区域。也就是说，再现存储器36_1到36_3同时存储在相应的解码器34_1、34_2、和34_3处解码的所有I和P画面数据的解码结果。保持这个存储直到用下一个要被解码的GOP的I和P画面数据的解码结果写入解码器为止。
当解码图2所示的再现数据ENC时，例如如图3所示，解码器34_1在再现存储器36_1的存储体区域“0”到“5”中写入在GOP(N-1)中的I2、P5、P8、P11、和P14画面数据，以及在GOP(N)中的I2画面数据。此外，例如如图3和图4所示，解码器34_2在再现存储器36_2的存储体区域“0”到“5”中写入GOP(N)中的I2、P5、P8、P11、和P14画面数据，以及GOP(N+1)中的I2画面数据。此外，例如如图4所示，解码器34_3在再现存储器36_3的存储体区域“0”到“5”中写入GOP(N+1)中的I2、P5、P8、P11、和P14画面数据，以及在GOP(N+2)中的I2画面数据。
此外，当解码器34_1解码在GOP(N-1)中的B画面数据时，其参考存储在再现存储器36_1的存储体区域“0”到“5”中的I和P画面数据的解码结果。此外，当解码器34_2解码在GOP(N)中的B画面数据时，其参考存储在再现存储器36_2的存储体区域“0”到“5”中的I和P画面数据的解码结果。此外，当解码器34_3解码在GOP(N+1)中的B画面数据时，其参考存储在再现存储器36_3的存储体区域“0”到“5”中的I和P画面数据的解码结果。要注意到，解码器34_1、34_2、和34_3用在那个B画面数据之后三个画面的B画面数据的解码结果，连续地覆写再现存储器36_1到36_3的存储体“6”和“7”所存储的、那个B画面数据的解码结果。为此，不需要提供对应于在GOP中的所有B画面数据的存储体区域，而且能够使再现存储器36_1到36_3的尺寸变小。
“选择器38”：
选择器38在CPU 42的控制下，切换并且有选择地再现和输出从再现存储器36_1、36_2、和36_3读取的、在解码之后的画面数据作为画面数据S38。
“CPU 42”：
CPU 42为存储在输入存储器32中的每个GOP执行解码调度，以便依据指定的再现速度解码包括在那个GOP中的画面数据。具体地说，CPU 42选择在包括在GOP中的画面数据中、要以指定再现速度进行解码的画面数据，确定用于解码在所选择的画面数据中的头画面数据(例如，I画面数据)的定时、以及用于解码所选择的画面数据的次序，并且生成显示该结果的解码调度结果。CPU 42基于上述解码调度结果和指定的再现速度，以画面数据为单位确定是否解码每个画面数据。当确定要对画面数据进行解码时，它发出用于那个画面数据的解码命令并且使解码器34_1、34_2、和34_3执行以下的解码处理。此外，CPU 42基于上述解码调度结果和指定的再现速度，以画面数据为单位确定是否再现和输出每个画面数据。当确定再现和输出该画面数据时，它发出那个画面数据的显示命令。要注意到，在这个实施例中，即使当指定了某个再现速度时，CPU 42也优先于B画面数据而解码在每个GOP中的I和P画面数据。因此，在接收到速度改变命令之后，速度改变之后的再现和输出能够在用于解码一个画面数据的时间内获得I、P、和B画面数据中任何一个的解码结果，也就是说，能够在短时间内开始在改变速度之后的再现和输出。
例如，CPU 42从输入存储器32中读取画面数据，以便由相同的解码器34_1、34_2、和34_3解码属于相同GOP的I和P画面数据以及参考该I和P画面数据的解码结果的B画面数据。例如，CPU 42通过PCI桥接器30从输入存储器32中读出在GOP(N-1)中的I和P画面数据，以及通过参考该I和P画面数据的解码结果而解码的、在GOP(N)中的B画面数据，并且把它们输出到解码器34_1。这里，在当前实施例中，参考了一个打开的(open)GOP，其参考具有不同B画面数据的GOP中的I和P画面数据的解码结果进行解码。具体地说，例如，在图2所示的GOP(N)中的B0和B1画面数据是参考在GOP(N-1)中的I和P画面数据的解码结果而进行解码的。因此，CPU 42将在GOP(N)中的B0和B1画面数据输出到解码器34_1。
此外，例如，CPU 42通过PCI桥接器30从输入存储器32中读取在GOP(N)中的I和P画面数据，以及通过参考该I和P画面数据的解码结果而解码的、在GOP(N+1)中的B画面数据，并且把它们输出到解码器34_2。此外，例如，CPU 42通过PCI桥接器30从输入存储器32中读取在GOP(N+1)中的I和P画面数据，以及通过参考该I和P画面数据的解码结果而解码的、在GOP(N+2)中的B画面数据，并且把它们输出到解码器34_3。
当例如CPU 42从计算机2的CPU 20接收到再现开始命令时，CPU 42使解码器34_1、34_2、和34_3对包括该再现点的多个GOP进行解码。在这时候，CPU 42控制由解码器34_1、34_2、和34_3进行的B画面数据的解码、从再现存储器36_1、36_2、和36_3到选择器38的读取、以及选择器38的选择，以便从再现点开始沿指定方向、以指定速度执行数据的再现和输出。
下面，将描述图1所示的数据处理***1的操作示例。
[第一操作示例]
下面，将说明从计算机2指定用于再现的画面数据的时刻到再现设备4再现并且输出该画面数据的时刻的操作的示例。图5和图6是用于说明该操作示例的流程图。
步骤ST1：
计算机2的CPU 20判断是否已经从操作设备19输入了指示用于指定在再现数据ENC中的再现点的操作的操作信号。当判断出已经指定了时就继续到步骤ST2，而当判断出没有指定时就重复步骤ST1的处理。
步骤ST2：
计算机2的CPU 20从HDD 12中读取包括在步骤ST1指定的再现点的画面数据的GOP，以及周围的GOP或者总共三个(多个)GOP。
步骤ST3：
计算机2的CPU 20通过桥接器18和PCI总线6将在步骤ST2读取的多个GOP输出到再现设备4。再现设备4的CPU 42通过PCI桥接器30将从计算机2输入的GOP写入到输入存储器32中。
步骤ST4：
计算机2的CPU 20将传输完成通知输出到再现设备4的CPU42。这个传输完成通知示出在步骤ST3从计算机2输出(传输)到再现设备4的GOP的标识数据，在输入存储器32中的写入了GOP的地址，以及GOP中的数据的大小。此外，传输完成通知示出在输出的GOP中的每个画面数据的标识数据、在输入存储器32中的其中已经写入了画面数据的地址、以及画面数据的大小。CPU 42在控制存储器40中写入传输完成通知。
步骤ST5：
再现设备4的CPU 42在完成步骤ST4的处理之后，将准备完成通知输出到计算机2的CPU 20。
步骤ST6：
计算机2的CPU 20判断是否已经从操作设备19输入了指示指定再现点的再现开始命令操作的操作信号。当判断出已经输入了该命令时就继续到步骤ST7，而当判断出还没有输入时就重复步骤ST6的处理。
步骤ST7：
当判断出输入了该命令时，计算机2的CPU 20向再现设备4的CPU 42输出指定再现点的再现开始命令。
步骤ST8：
再现设备4的CPU 42执行调度，以便依据在画面数据之间的相互参考关系和再现方向，确定对存储在输入存储器32中、包括由在步骤ST7输入的再现开始命令所指示的再现点的画面数据的GOP中的画面数据进行解码的次序。
步骤ST9：
再现设备4的CPU 42基于步骤ST8的解码调度结果、连续地指定用于处理的画面数据。
步骤ST10：
再现设备4的CPU 42判断所指定的再现速度是否是1X速度或更多。如果判断为1X速度或更多，则继续到步骤ST11，而如果相反，则继续到步骤ST12。
步骤ST11：
再现设备4的CPU 42基于所指定的再现速度确定是否解码在步骤ST10指定的画面数据。
步骤ST12：
再现设备4的CPU 42基于所指定的再现速度确定定时是否是用于再现和输出的更新的定时。
步骤ST13：
当再现设备4的CPU 42在步骤ST12处断定该定时是更新定时时，它继续到步骤ST14。
步骤ST14：
当在步骤ST11中确定解码或者当在步骤ST13中判断更新定时时，再现设备4的CPU 42输出在步骤ST9中指定的画面数据的解码命令到任意一个解码器34_1、34_2、和34_3。要注意到，当在步骤ST9中指定的的画面数据的解码结果已经存储在再现存储器36_1、36_2、和36_3中时，CPU 42不输出解码命令。
步骤ST15：
再现设备4的解码器34_1、34_2、和34_3读取由在步骤ST14输入的解码命令所指示的画面数据，并且把解码结果写入到再现存储器36_1到36_3中。
步骤ST16：
再现设备4的CPU 42基于所指定的再现速度确定是否再现和输出在步骤ST9指定的画面数据的解码结果。
步骤ST17：
当在步骤ST16确定再现和输出时，再现设备4的CPU 42将指定画面数据的显示命令输出到相应的解码器34_1、34_2、和34_3。
步骤ST18：
再现设备4的解码器34_1、34_2、和34_3基于在步骤ST17输入的显示命令、从再现存储器36_1、36_2、和36_3中读取由显示命令指定的画面数据的解码结果，并且把它们输出到选择器38。由此，再现并且输出所指定的画面数据的解码结果。
步骤ST19：
计算机2的CPU 20判断是否已经从操作设备19输入了指示瞬变命令操作的操作信号。当判断输入了时，继续到步骤ST20，而如果没有，则继续到步骤ST21。
步骤ST20：
计算机2的CPU将瞬变命令(再现方向切换命令)输出到再现设备4的CPU 42。在出现瞬变命令之后，CPU 20和CPU 42基于切换的再现方向执行处理。再现设备4以画面数据为单位、执行步骤ST10到ST19的处理。
步骤ST21：
CPU 20和CPU 42判断在步骤ST10到ST19中处理的画面数据是否是在GOP中的最后画面数据。如果判断它是最后画面数据的话，则它们继续到步骤ST22，而如果不是，则它们返回到步骤ST9并且执行用于下一个画面数据的处理。
步骤ST22：
CPU 20和CPU 42判断所处理的画面数据是否是在它所属的再现数据ENC中的最后的GOP。如果判断它是最后的GOP，则结束该处理，而如果不是，则它们继续到步骤ST23。
步骤ST23：
计算机2的CP U20依据再现方向从HDD 12中读取下一个GOP。
步骤ST24：
计算机2的CPU 20通过桥接器18和PCI总线6将在步骤ST23读取的多个GOP输出到再现设备4。再现设备4的CPU 42通过PCI桥接器30将从计算机2输入的GOP写入到输入存储器32中。
步骤ST25：
计算机2的CPU 20将在步骤ST24输出的GOP的传输完成通知输出到再现设备4的CPU 42。CPU 42在控制存储器40中写入传输完成通知。
步骤ST26：
再现设备4的CPU 42在完成步骤ST25的处理之后，将准备完成通知输出到计算机2的CPU 20。
步骤ST27：
例如，再现设备4的CPU 42判断包括依据再现方向的下一个再现点的画面数据的GOP的调度是否已经完成了(也就是说，是否需要调度)。当判断调度没有完成时，它继续到步骤ST8，而当判断它已经完成时，它继续到步骤ST9。
[第二操作示例]
在这个操作示例中，将详细说明图6所示的步骤ST15的解码。例如，如使用图3和图4所述，再现设备4的CPU 42基于上述调度结果、读取存储在输入存储器32中的GOP所包括的画面数据，并且把上述数据输出到解码器34_1、34_2、和34_3。此外，如上所述，解码器34_1、34_2、和34_3对其进行解码，并且在再现存储器36_1、36_2、和36_3中写入解码结果。
如图3和图4所示，再现设备4在B画面数据之前首先在解码器34_1、34_2、和34_3中解码在GOP中的I和P画面数据，并且把结果写入到再现存储器36_1、36_2、和36_3中的固定存储体区域中。由此，如果在该写入之后有用于解码一个画面数据(一帧)的时间，则有可能再现和输出在正被处理的GOP中的任何画面数据。也就是说，如稍后所说明的那样，当正在解码并且再现和输出在GOP中的画面数据的过程当中出现用于改变再现速度的命令时，有可能在该速度改变命令之后用于解码1个画面数据的时间内，使用图6和图7所示的步骤ST9到ST18的处理，依据所改变的再现速度再现和输出画面数据。例如，当解码并且再现和输出图3所示的GOP(N-1)中的B9画面数据时，在GOP(N-1)中的P8和P11画面数据的解码结果是必需的。此外，P8画面数据的解码需要P5画面数据的解码结果，而P5画面数据的解码需要I2画面数据的解码结果。因此，解码B9画面数据需要I2、P5、P8、和P11画面数据的解码结果。如图3所示，依据再现设备4，通过在再现存储器36_1中存储I和P画面数据，如果解码器34_1接收GOP(N-1)的B9画面数据，则解码器34_1能够利用早已经存储在再现存储器36_1的存储体区域“2”和“3”中的P8和P11画面数据，以立即解码并且再现和输出GOP(N-1)的B9画面数据。由此，改变再现速度而没有时间滞后是可能的。
[第三操作示例]
下面，将说明当如图3和图4所示、执行前向(FWD)1X速度再现时并且以1.5X速度再现、3X速度再现、和1X速度再现的次序改变再现速度时再现设备4的操作示例。图8和图9是用于说明这个操作示例的视图。如图8所示，在解码器34_2正在再现和输出GOP(N)的B1画面数据的解码结果的同时，如果由再现设备4的CPU 42接收了用于改变到1.5X速度的命令的话，则CPU 42继续进行图6和图7所示的步骤ST9到ST18，以在完成GOP(N)的解码以及再现和输出之前，执行对应于1.5X速度的解码以及再现和输出。由此，有可能从再现和输出GOP(N)的B4画面数据起变换到1.5X速度。也就是说，如果再现设备4没有再现和输出在以1X速度再现进行解码的解码调度结果中的B0、B3、B6、和B9画面数据，则再现设备4能够实现1.5X速度，所以通过从用于改变到1.5X速度的命令变得有效的定时开始、使在时间方面不会被再现和输出的画面数据无效或者对其进行压缩，能够简单地实现1.5X速度。在这时候，再现设备4以与1X速度再现相同的方式、解码由I和P画面数据构成的锚画面数据，把它写入到再现存储器36_1、36_2、和36_3中，并且由解码器34_1、342、和34_3解码在时间方面变得无效和进行了压缩的B画面数据。
此后，如图9所示，在解码器34_3正在再现和输出GOP(N+1)的P8画面数据的解码结果的同时，如果由再现设备4的CPU 42接收了改变到3X速度的命令的话，则CPU 42继续进行图6和图7所示的步骤ST9到ST18，以在完成GOP(N+1)的解码以及再现和输出之前执行对应于3X速度的解码以及再现和输出。由此，有可能从GOP(N+1)的P11画面数据的再现和输出起变换到3X速度再现和输出。
此后，如图9所示，在解码器34_2正在再现和输出GOP(N+2)的P14画面数据的解码结果的同时，如果由再现设备4的CPU 42接收了改变到1X速度的命令的话，则CPU 42继续进行图6和图7所示的步骤ST9到ST18，以从GOP(N+3)的P5画面数据开始执行对应于1X速度的解码以及再现和输出。在这时候，因为GOP(N+3)的I和P画面数据的解码结果存储在再现存储器36_3中，所以有可能在短时间内从3X速度再现变换到1X速度再现。以这种方法，例如再现设备4通过解码调度事先确定1X速度再现时的解码次序，当指定(改变)再现速度时、判断具有解码调度中所显示的解码次序的画面数据的有效性，并且仅仅解码被判断为有效的画面数据，所以能够用快速响应执行可变速度再现。
如上所述，如使用图6和图7所说明的那样，数据处理***1以GOP为单位执行解码调度。在实际上解码并且再现和输出形成GOP的画面数据的时候，基于解码调度的结果以及再现速度、以画面数据为单位确定是否解码以及是否再现和输出被调度用于解码的画面数据。因此，依据数据处理***1，如果在一个GOP的再现期间出现用于改变再现速度的命令，则有可能在该GOP的再现完成之前、以画面数据为单位执行对应于所改变的再现速度的解码以及再现和输出。因此，和过去相比较，有可能缩短从再现设备4接收用于改变再现速度的命令的时刻到实际上执行对应于所改变的再现速度的再现和输出的时刻的时间。
此外，在数据处理***1中，再现设备4在B画面数据之前，将I和P画面数据的解码结果写入到再现存储器36_1到36_3的固定存储体区域中，并且持续地保持它。因此，再现设备4能够在解码B画面数据的期间，再现和输出在正被处理的GOP中的所有画面数据。此外，再现设备4在再现存储器36_1、36_2、和36_3的固定存储体中连续地覆写B画面数据的解码结果。由此，有可能在短时间内执行对应于改变的再现速度的再现和输出，而不会极大地增加再现存储器36_1到36_3的存储容量。
当画面数据是高清晰度(HD)图像或者其它具有大量数据的图像时，或者当采用与普通GOP相比、在每个GOP中有更多数量的画面数据的长GOP时，上述效果是非常显著的。
<第二实施例>
在这个实施例中，举例说明了其中再现设备具有单个解码器的情况。图10是依据本发明一个实施例的数据处理***1a的整体配置的视图。如图10所示，数据处理***1a具有例如计算机2和再现设备4a。图10所示的计算机2与第一实施例的计算机2相同。如图10所示，再现设备4a具有例如PCI桥接器30、输入存储器32、解码器34、再现存储器36、控制存储器40、CPU 42a、以及控制总线46。在图10所示的再现设备4a的配置中，分配了与图1相同的参考数字的部件类似于第一实施例的那些部件。再现设备4a具有单个解码器34以及再现存储器36。依据此，CPU 42a控制画面数据的解码以及再现和输出。要注意到，除了单个解码器34的解码并且再现和输出这一点之外，再现设备4a的处理与图5到图7中的第一个实施例的再现设备4的处理相同。
下面，将说明其中数据处理***1a执行1X速度反向(REV)再现的情况。图11和图12是视图，用于说明其中图10所示的数据处理***1a以反向(REV)方向对再现数据ENC进行再现的操作。如图11和图12所示，在反向再现的情况下，解码器34首先解码GOP(N+3)的I和P画面数据以及GOP(N+2)的I2画面数据，并且把解码结果写入到解码器34的存储体区域“0”到“5”中。此后，解码器34连续地解码GOP(N+3)的B13和B12画面数据、GOP(N+2)的P5画面数据、GOP(N+3)的B10和B9画面数据、以及GOP(N+2)的P8画面数据。进一步，解码器34连续地再现和输出GOP(N+3)的P14、B13、B12、P11、P10、B9、...的解码结果。
下面，将说明连续地将再现速度从图11所示的1X速度反向再现改变到1.5X速度反向再现、3X速度反向再现、和1X速度反向再现的情况。图13和图14是用于说明这个操作示例的视图。如图13所示，在解码器34正在以1X速度反向再现来再现和输出GOP(N+3)中的P5画面数据的解码结果的同时，如果由再现设备4的CPU 42接收了改变到1.5X速度反向再现的命令的话，则CPU 42继续进行图6和图7所示的步骤ST9到ST18，以在完成GOP(N+3)的解码以及再现和输出之前执行对应于1.5X速度的解码以及再现和输出。由此，有可能从GOP(N+3)中的B4画面数据的再现和输出起变换到1.5X速度反向再现的再现和输出。
此后，如图14所示，在解码器34正在再现和输出GOP(N+1)的P11画面数据的解码结果的同时，如果由再现设备4的CPU 42接收了改变到3X速度反向再现的命令的话，则CPU 42继续进行图6和图7所示的步骤ST9到ST18，以在完成GOP(N+1)的解码以及再现和输出之前执行对应于3X速度反向再现的解码以及再现和输出。由此，有可能从GOP(N+1)中的P8画面数据的再现和输出起变换到3X速度反向再现的再现和输出。
此后，如图14所示，在解码器34正在再现和输出GOP(N)的I2画面数据的解码结果的同时，如果由再现设备4的CPU 42接收了改变到1X速度反向再现的命令的话，则CPU 42继续进行图6和图7所示的步骤ST9到ST18，以从GOP(N-1)的B13画面数据开始执行对应于1X速度反向再现的解码以及再现和输出。在这时候，因为GOP(N+3)的I和P画面数据的解码结果存储在再现存储器36中，所以有可能在短时间内从3X速度反向再现变换到1X速度反向再现。以这种方式，例如，在再现设备4a中，事先通过解码调度确定1X速度反向再现的解码次序。当指定(改变)反向再现速度时，判断具有解码调度中所示的解码次序的画面数据的有效性。仅仅解码被判断为有效的画面数据。由此，即使在反向再现时用良好的响应进行可变速度再现也是可能的。同样，利用这个数据处理***1a，可获得类似于第一实施例中的数据处理***1的效果。
<第三实施例>
在这个实施例中，将说明在第一实施例中说明的***的下述情形，其中在调度缓冲器中调度和存储指示是否对画面数据进行解码的画面属性数据PP，并且基于该数据执行解码。图15是依据本发明一个实施例的数据处理***1b的整体配置的视图。如图15所示，数据处理***1b具有例如计算机2和再现设备4b。图15所示的计算机2与第一实施例的计算机2相同。如图15所示，再现设备4b具有例如PCI桥接器30、输入存储器32、解码器34、再现存储器36、控制存储器40、CPU 42b、调度缓冲器45、以及控制总线46。在图15所示的再现设备4b的配置中，分配了与图1相同的参考数字的部件类似于在第一实施例中的那些部件。
图16是用于说明图15所示的调度缓冲器45的视图。如图16所示，调度缓冲器45具有调度缓冲器45_1到45_3。调度缓冲器45_1用于管理要在图15所示的解码器34_1处进行解码的画面数据，并且在1X速度再现时允许以解码次序读出在解码器34_1处调度的画面数据的画面属性数据PP。调度缓冲器45_2用于管理要在图15所示的解码器34_2处进行解码的画面数据，并且在1X速度再现时允许以解码次序读出在解码器34_2处调度的画面数据的画面属性数据PP。调度缓冲器45_3用于管理要在图15所示的解码器34_3处进行解码的画面数据，并且在1X速度再现时允许以解码次序读出在解码器34_3处调度的画面数据的画面属性数据PP。
图17是用于说明画面属性数据PP的格式的视图。如图17所示，画面属性数据PP包括指向写入相应画面数据的解码结果的再现存储器36_1到36_3中的存储体的指针数据(cur_p)，指向存储用于对其进行解码的前向预测画面(画面数据)的再现存储器36_1到36_3中的存储体的指针数据(fore_p)，指向存储用于对其进行解码的后向预测画面(画面数据)的再现存储器36_1到36_3的存储体的指针数据(back_p)，正被解码的GOP的数目，用于开始解码(再现)的时间(“time”)，以及示出解码的有效性的有效性标志数据(“valid”)。
图18是视图，用于说明在连续地输出用于从1X速度再现改变到2X速度的命令以及改变到3X速度的命令的情况下调度缓冲器45_1的状态改变。如图18A所示，再现设备4b的CPU 42b在它的最初设置中，将存储在调度缓冲器45_1中的所有画面属性数据的有效性标志数据“valid”设置为有效。此后，当CPU 42b依据用户操作接收了改变到2X速度的命令时，如图18B所示，它每隔一个，将在正被再现的画面数据的画面属性数据PP之后调度的画面属性数据PP的有效性标志数据“valid”设置为有效。此后，当CPU 42b依据用户操作接收了改变到3X速度的命令时，如图18C所示，它在每两个数据之后，将在正被再现的画面数据的画面属性数据PP之后调度的画面属性数据PP的有效性标志数据“valid”设置为无效。
图19是视图，用于说明在连续地输出用于从3X速度再现改变到2X速度的命令以及改变到1X速度的命令的情况下调度缓冲器45_1的状态改变。如图19A所示，以3X速度再现时，每隔两个数据，把存储在调度缓冲器45_1中的画面属性数据PP的有效性标志数据“valid”设置为有效。此后，当CPU 42b依据用户操作接收了改变到2X速度的命令时，如图19B所示，它每隔一个数据，将在正被再现的画面数据的画面属性数据PP之后调度的画面属性数据PP的有效性标志数据“valid”设置为有效。此后，当CPU 42b依据用户操作接收了IX速度改变命令时，如图19C所示，它将在正被再现的画面数据的画面属性数据PP之后调度的画面属性数据PP的所有有效性标志数据“valid”设置为有效。
下面，将描述图15所示的数据处理***1b的操作示例。图20到图23是用于说明图15所示的数据处理***1b的操作示例的流程图。
步骤ST51：
计算机2的CPU 20判断是否已经从操作设备19输入了指示用于指定在再现数据ENC中的再现点的操作的操作信号。当判断已经指定了时就继续到步骤ST52，而当判断没有指定时就重复步骤ST51的处理。
步骤ST52：
计算机2的CPU 20从HDD 12中读取包括在步骤ST51指定的再现点的画面数据的GOP以及周围的GOP，或者总共三个(多个)GOP。
步骤ST53：
计算机2的CPU 20通过桥接器18和PCI总线6将在步骤ST52读取的多个GOP输出到再现设备4b。再现设备4b的CPU 42通过PCI桥接器30将从计算机2输入的GOP写入到输入存储器32中。
步骤ST54：
计算机2的CPU 20将传输完成通知输出到再现设备4b的CPU42b。这个传输完成通知示出在步骤ST53中从计算机2输出(传输)到再现设备4b的GOP的标识数据，在输入存储器32中的其中写入了GOP的地址，以及GOP中的数据的大小。此外，传输完成通知示出在输出的GOP中的每个画面数据的标识数据、在输入存储器32中的其中已经写入了画面数据的地址、以及画面数据的大小。CPU 42b在控制存储器40中写入传输完成通知。
步骤ST55：
再现设备4b的CPU 42a在完成步骤ST54的处理之后，将准备完成通知输出到计算机2的CPU 20。
步骤ST56：
计算机2的CPU 20判断是否已经从操作设备19输入了指示指定再现点的再现开始命令操作的操作信号。当判断已经输入了该命令时就继续到步骤ST57，而当判断没有输入时就重复步骤ST66的处理。
步骤ST57：
当判断输入了该命令时，计算机2的CPU 20向再现设备4b的CPU 42b输出指定再现点的再现开始命令。
步骤ST58：
再现设备4b的CPU 42b调度一个新GOP的画面数据的解码次序，并且以那个调度次序16在图16所示的调度缓冲器45_1到45_3中写入画面数据的画面属性数据PP。此外，如图18A所示，CPU 42b将存储在调度缓冲器45_1到45_3中的所有画面属性数据PP的有效性标志数据“valid”设置为有效。
步骤ST59：
再现设备4b的CPU 42b确定在存储在调度缓冲器45_1到45_3中的画面属性数据PP中的、具有有效的有效性标志数据“valid”的画面属性数据的再现(解码)开始时间，并且将这个时间确定为画面属性数据PP的再现开始时间“time”。
步骤ST60：
再现设备4b的CPU 42b判断所指定的再现速度是否是1X速度或更多。如果是1X速度或更多，则继续到步骤ST61，而如果不是，则继续到步骤ST63。
步骤ST61：
再现设备4b的CPU 42b，依据需要(当有速度改变命令等时)，基于所指定的再现速度，使在存储在调度缓冲器45_1到45_3中的画面属性数据PP中的、就在之前再现的画面数据之后的所有画面数据的画面属性数据的有效性标志数据“valid”为有效。
步骤ST62：
再现设备4b的CPU 42b在小于1X速度再现(慢动作再现)的时候，计算正被显示的画面数据的下一个更新定时。
步骤ST63：
再现设备4b的CPU 42b判断由在再现设备4b中提供的未示出的计时器所指示的定时是否已经变为在步骤ST62中计算的更新定时。如果是，则继续到步骤ST66，而如果不是，则继续到步骤ST73。
步骤ST64：
再现设备4b的CPU 42b判断是否已经输入了用于改变再现速度的命令。如果是，则继续到步骤ST65，而如果不是，则继续到步骤ST67。
步骤ST65：
再现设备4b的CPU 42b依据对应于用于改变再现速度的命令而改变的再现速度，将存储在调度缓冲器45_1到45_3中的画面属性数据PP的有效性标志数据“valid”设置为有效或者无效。也就是说，CPU42b重置存储在调度缓冲器45_1到45_3中的画面属性数据PP的有效性标志数据“valid”。例如，CPU 42b执行如使用图18和图19所说明的处理。
步骤ST66：
再现设备4b的CPU 42b再次确定在存储在调度缓冲器45_1到45_3中的画面属性数据PP中的、具有有效的有效性标志数据“valid”的画面属性数据的再现(解码)开始时间，并且将这个时间设置为画面属性数据PP的再现开始时间“time”。也就是说，CPU 42b基于步骤ST65的结果重置画面属性数据PP的再现开始时间“time”。要注意到，例如通过将“1”加到就在先前的再现开始时间，来计算重置的再现开始时间“time”。当以画面数据为单位进行解码时输出了用于改变再现速度的命令时，再现设备4b立即执行步骤ST65和ST66，并且重置存储在调度缓冲器45_1到45_3中的画面属性数据PP的有效性标志数据“valid”。由此，依据再现设备4b，有可能在作为整体完成GOP的再现之前，依据所改变的再现速度、以画面为单位解码并且再现和输出数据。因此，和过去相比较，有可能缩短从再现设备4接收用于改变再现速度的命令的时刻到实际上执行对应于所改变的再现速度的再现和输出的时刻的时间。
步骤ST67：
再现设备4b的CPU 42b连续地读取在调度缓冲器45_1到45_3当中被选择用于处理的调度缓冲器中存储的画面属性数据PP的有效性标志数据“valid”。此外，CPU 42b在所读取的画面属性数据PP的有效性标志数据“valid”指示有效的条件下，输出用于相应的画面数据的解码命令到解码器34_1到34_3。
步骤ST68：
解码器34_1、34_2、和34_3从输入存储器32中读取由在步骤ST67中输入的解码命令所指示的画面数据，并且把解码结果写入到再现存储器36_1到36_3中。
步骤ST69：
再现设备4b的CPU 42b基于所指定的再现方向和调度结果、标识接下来要被再现和输出的解码结果，生成指示该解码结果的显示命令以及用于期望的再现和输出的选择器38的切换命令，并且将其写入到控制存储器40中。
步骤ST70：
再现设备4b的CPU 42b将在步骤ST68中生成的显示命令输出到解码器34_1、34_2、和34_3，并且将切换命令输出到选择器38。
步骤ST71：
解码器34_1、34_2、和34_3从再现存储器36_1到36_3中读出由输入的显示命令所指示的解码结果，并且把它们输出到选择器38。此外，选择器38基于在步骤ST12中输入的切换命令，切换从解码器34_1、34_2、和34_3输入的解码结果，以便对它们进行选择以及再现和输出。
步骤ST72：
再现设备4b的CPU 42b将在存储在调度缓冲器45_1到45_3中的正被处理的画面属性数据PP中的、对应于在步骤ST71中解码的画面数据的画面属性数据PP的有效性标志数据“valid”设置为无效。
步骤ST73：
CPU 20和CPU 42b判断所处理的画面数据是否是在GOP中的最后画面数据。如果判断出它是最后的画面数据，则继续到步骤ST74，而如果不是，则继续到步骤ST60并且处理下一个画面数据。
步骤ST74：
CPU 20和CPU 42b判断所处理的画面数据所属的GOP是否是在再现数据ENC中最后的GOP。如果判断它是最后的GOP，则它们结束该处理，而如果不是，则它们继续到步骤ST75。
步骤ST75：
计算机2的CPU 20依据再现方向从HDD 12中读取下一个GOP。
步骤ST76：
计算机2的CPU 20通过桥接器18和PCI总线6将在步骤ST75读取的GOP输出到再现设备4b。再现设备4b的CPU 4b2b通过PCI桥接器30将从计算机2输到的GOP写到输入存储器32中。
步骤ST77：
计算机2的CPU 20将GOP传输完成通知输出到再现设备4b的CPU 42b。CPU 42b在控制存储器40中写入传输完成通知。
步骤ST78：
再现设备4b的CPU 42b输出准备完成通知到计算机2的CPU20。
步骤ST79：
例如，再现设备4b的CPU 42b判断包括依据再现方向的下一个再现点的画面数据的GOP的调度是否已经完成了(也就是说，是否需要调度)。如果判断出调度还没有完成，则继续到步骤ST58，而如果相反，则继续到步骤ST60。
如上所述，以与第一实施例的数据处理***1相同的方式，数据处理***1b以GOP为单位执行解码调度，并且基于解码调度的结果和再现速度，在用于实际上解码并且再现和输出形成GOP的画面数据的时候，以画面数据为单位确定是否要解码以及是否再现和输出被调度用于解码的画面数据。因此，依据数据处理***1b，当在GOP的再现期间发出了用于改变再现速度的命令时，有可能在完成GOP的再现之前、依据所改变的再现速度以画面数据为单位解码并且再现和输出数据。因此，和过去相比较，有可能缩短从再现设备4b接收用于改变再现速度的命令的时刻到实际上执行对应于那个改变的再现速度的再现和输出的时刻的时间。此外，在数据处理***1b中，仅仅通过设置(重写)存储在调度缓冲器45_1到45_3中的画面属性数据PP的有效性标志数据“valid”，能够处理再现速度的改变。也就是说，不需要诸如重新安排画面属性数据PP之类的、涉及大处理负荷的处理。因此，依据数据处理***1b，能够通过小的处理负荷并且在短时间内处理速度的改变。在采用长GOP的情况下，以及在其中由调度涵盖的画面数据的数量大的情况下，这些效果是尤其显著的。
本发明不局限于上述实施例。在上述实施例上，说明了MPEG画面数据作为多个画面数据，但是本发明还可以应用于音频数据，只要该音频数据按次序进行解码即可。
此外，在上述实施例中，作为编码方案举例说明了MPEG，但是本发明可以类似地应用于H.264/AVC(高级视频编码)等，还可应用于其中解码数据由第一类型画面数据和第二类型画面数据组成的情况，其中第一类型画面数据的解码结果被其它画面数据的解码所参考，而且第二类型画面数据的解码结果不会被其它数据的解码所参考。
此外，在上述实施例中，还有可能生成在解码调度中调度GOP中的所有画面数据的结果，以及生成依据再现速度定义是将在所有画面数据中的每个画面数据设置为有效还是无效的属性数据(标志数据)，并且在画面数据的解码以及再现和输出过程中、依据所指定的再现速度更新该属性数据。此外，在画面数据的解码以及再现和输出过程中，基于所更新的属性数据、解码以及再现和输出画面数据。
在上述实施例中，说明了其中压缩的画面数据存储在HDD 12中的情况，但是本发明不局限于此，例如，本发明还可以应用于通过输入/输出接口等在光盘、磁光盘、半导体存储器、磁盘、或者其它各种存储介质上进行的存储。此外，连接方式不局限于通过电缆等的连接。例如，通过诸如来自外面的有线或者无线连接之类的其它类型连接方式的连接也是可能的。
此外，在上述实施例中，说明了由具有那些功能的硬件执行一系列处理的情况，但是本发明不局限于此。为此使用软件也是可能的。在这时候，当通过软件执行一系列处理时，可以通过把各种程序安装到计算机中来实现各种类型的功能，其中在该计算机中，形成该软件的程序被构建到专用硬件中。例如，程序从例如存储介质中安装到通用个人计算机等中。此外，例如，存储介质包括光盘、磁光盘、半导体存储器、磁盘或者其它各种存储介质，这是不言而喻的。此外，例如，也有可能例如通过Internet或者其它网络下载各种类型的程序，来把它们安装到通用个人计算机等中。
此外，在上述实施例中，描述存储在存储介质中的程序的步骤当然可以以沿着所描述的次序的时间顺序执行，但是本发明不局限于该时间顺序。还包括并行或者独立的执行。
此外，在上述实施例中，没有特别地限制再现速度。本发明可以广泛地应用于以任何可变速度进行再现操作的再现设备的特定处理。
此外，实施例中的块配置是块配置的示例。本发明不局限于所说明的示例。
此外，通过适当地提供一组用于存储在HDD 12中的压缩和编码数据的、指示从HDD 12读取的数据是否有效的读取标志，一组指示在解码调度的时候的有效性的解码标志，一组用于解码数据的显示的、指示调度时的有效性的显示标志等作为元数据，并且依据再现速度和方向自动地更新这一系列的标志组，能够管理调度。在这时候，可以作为单独的调度元数据(历史记录信息)，管理过去的一系列使用可变速度再现处理的调度和标志组的更新信息。这可以依据需要描述为压缩和编码数据中的语法或者可以分开地存储在诸如HDD 12之类的存储介质中。
此外，也可以作为元数据(部件历史记录信息)管理解码器的数目、存储体的数目、解码器ID等。此外，还可以作为元数据(再现历史记录信息)管理再现速度、再现方向等。在这时候，如果必要，元数据可以描述为压缩和编码数据中的语法或者可以分开地存储在诸如HDD 12之类的存储介质中。通过参考这样的元数据(历史记录信息)，有可能重新使用过去执行的调度并且更快和更准确地执行调度。要注意到，还可以包含这些元数据，以便在例如数据库的外面设备处管理这些元数据。
要注意到，在上述实施例中，本发明还能够应用于当解码器34_1到343不完全解码存储在HDD 12上的压缩和编码数据(将该数据解码到中间阶段)时的情况。具体地说，例如，本发明还可以应用于其中解码器34_1到34_3仅仅执行用于可变长度编码的解码和逆量化、而不执行逆DCT的情况，其中解码器执行逆量化、但不执行用于可变长度编码的解码的情况等。在这种情况下，例如，解码器34_1到34_3可以生成例如指示它们所执行的处理直至编码和解码的什么阶段(例如，逆量化阶段)的历史记录信息，并且与不完全解码的数据相联系地输出该信息。
此外，在上述实施例中，HDD 12存储不完全编码的数据(例如，执行了DCT和量化但是没有执行可变长度编码的数据)，而且依据需要存储编码和解码的历史记录信息，但是本发明还可以应用于其中解码器34_1到34_3能够在CPU 20的控制下解码所提供的不完全编码的数据、并且把该数据转换为基带信号的情况。具体地说，本发明还能够应用于其中例如解码器34_1到34_3对已经应用了DCT和量化但是没有应用可变长度编码的数据执行逆DCT和逆量化但是不执行用于可变长度编码的解码的情况。此外，在这种情况下，例如，CPU20可以获得与不完全编码的数据相联系的、存储在HDD 12中的编码和解码历史记录信息，并且基于该信息调度由解码器34_1到34_3进行的解码。
此外，在上述实施例中，HDD 12存储不完全编码的数据，并且依据需要存储编码和解码的历史记录信息，但是本发明还可以应用于其中解码器34_1到34_3在CPU 20的控制下不完全解码所提供的、不完全编码的数据(仅仅将数据解码到中间阶段)的情况。此外，在这种情况下，同样，例如，CPU 20可以获得与不完全编码的数据相联系的、存储在HDD 12中的编码和解码历史数据，并且基于该信息调度由解码器34_1到34_3进行的解码。换句话说，本发明甚至能够应用于其中解码器34_1到34_3在CPU 20的控制下执行部分解码(执行解码处理的一部分)的情况。CPU 20获得与不完全编码的数据相联系的、存储在HDD 12中的编码和解码的历史记录信息。基于这个信息，有可能调度由解码器34_1到34_3进行的解码。解码器34_1到34_3还能够根据需要生成解码和解码的历史记录信息，并且与不完全解码的数据相联系地输出该信息。
此外，HDD 12可以进一步存储与压缩和编码的流数据相联系的、有关编码和解码处理的历史记录的信息，而且CPU 20可以基于有关编码处理和解码处理的历史记录的信息、调度该压缩和编码的流数据的解码。此外，即使当解码器34_1到34_3能够在CPU 20的控制下解码压缩和编码的流数据并且把它转换为基带信号时，也有可能根据需要生成有关编码和解码的历史记录的信息，并且允许与该基带信号相联系地输出该信息。
要注意到，在上述实施例中，再现设备4被说明为具有多个解码器，但是本发明也能够应用于单个解码器的情况。在这时候，单个解码器不仅可以接收、解码、和显示或者输出压缩和编码的数据，而且还可以以与上述相同的方式，接收压缩和编码的数据、将该数据部分解码至中间阶段、并且将该数据与编码和解码的历史记录信息一起输出到外面，接收部分编码的数据、解码该数据、并且把该数据转换为基带信号以便输出到外面，或者接收部分编码的数据、将该数据部分解码到中间阶段、并且将该数据与编码和解码历史记录信息一起输出到外面。
此外，在上述实施例中，分开地配置CPU 20与CPU 42，但是本发明不局限于此。例如，还可以想得到由作为整体控制再现设备4的单个CPU来配置CPU 20和CPU 42。此外，即使当独立地配置CPU20和CPU 42时，CPU 20和CPU 42也可以在单个芯片上形成。
此外，当独立地配置CPU 20和CPU 42时，有可能使在上述实施例中由CPU 20执行的处理的至少一部分由CPU 42例如通过时间划分执行，或者使由CPU 42执行的处理的至少一部分由CPU 20例如通过时间划分执行。也就是说，CPU 20和CPU 42还可以利用能够执行分散处理的处理器实现。
此外，例如，再现设备4可以被配置为能够连接到网络，而且在上述实施例中，由CPU 20或者CPU 42执行的处理的至少一部分可以在通过网络连接的另一个设备的CPU处执行。类似地，在上述实施例中，分开地配置存储器32、40等，但是本发明不局限于此。也可以想得到由再现设备4中的单个存储器配置这些存储器。
此外，在上述实施例中，说明了HDD 12、解码器34_1到34_3、和选择器38经由桥接器和总线连接并且集成为再现设备的情况，但是本发明不局限于此。例如，本发明还可以应用于其中这些部件中的一部分通过有线或者无线从外面连接的情况，以及其中这些部件以其它各种连接方式相互连接的情况。
此外，在上述实施例中，说明了压缩的流数据存储在HDD中的情况，但是本发明不局限于此。例如，本发明还可以应用于再现和处理存储在光盘、磁光盘、半导体存储器、磁盘、或者其它各种存储介质上的流数据的情况。
此外，在上述实施例中，CPU 42、存储器32、存储器40、解码器34_1到34_3、以及选择器38安装在同一扩展卡(例如，PCI卡或者PCI快速(PCI-Express)卡)上，但是发明不局限于此。例如，当在卡之间的传输速度高时，PCI-快速(PCI-Express)或者其它技术可以用来把这些部件安装在单独的扩展卡上。
此外，在这个说明书中，“***”意指多个设备的逻辑集合。它与不同配置的设备是否处于同一外壳中无关。
本发明可以应用于用于再现已再现的数据的***。
本领域的技术人员应当理解：在权利要求和它们的等效含义的范围之内，取决于设计要求及其他因素，可以进行各种修改、组合、子组合以及改变。

Claims (16)

1、一种用于按次序解码和再现形成再现数据的多个画面数据的再现设备，该设备包含:
多个再现存储器；
多个解码器，对所述画面数据进行解码，在所述再现存储器中写入解码结果，并且再现和输出从所述再现存储器中读取的所述解码结果，
其中，所述解码器以所述画面数据为单位，再现由第一类型画面数据和第二类型画面数据组成的再现数据，其中关于第一类型画面数据，其解码结果在其它画面数据的解码中被参考，而且关于第二类型画面数据，其解码结果不在其它画面数据的解码中被参考；
在所述再现存储器中保持所述第一类型画面数据的所述解码结果的存储；以及
在参考已经存储在所述再现存储器中的所述第一类型画面数据的解码结果时，解码并且再现和输出所述第二类型画面数据；以及
处理电路，用于执行解码调度，以便以预定多个所述画面数据为单位确定在所述解码器处解码所述画面数据的次序，以由所述解码调度所确定的所述次序选择要被处理的所述画面数据，依据所指定的再现速度判定是否解码所述选择的画面数据或者再现和输出解码结果，以及基于所述判定、控制所述解码器的所述解码以及所述再现和输出，
其中，
所述多个解码器进一步用于并行地处理所述再现数据；
所述多个再现存储器，对应于所述多个解码器而设置；以及
所述再现设备进一步包括又一个处理电路，用于使所述解码器解码所述画面数据，以便由同一个解码器解码参考相同的第一类型画面数据的解码结果的所述第二类型画面数据，以及由同一个解码器解码包括在所述画面数据组中的所述第一类型画面数据。
2、如权利要求1所述的再现设备，其特征在于:所述处理电路在所述指定的再现速度至少为1X速度的条件下，执行所述判定。
3、如权利要求1所述的再现设备，其特征在于:所述处理电路以所述画面数据为单位基于所述判定控制所述画面数据的所述解码以及所述再现和输出。
4、如权利要求1所述的再现设备，其特征在于:所述解码器优先于所述第二类型画面数据解码所述第一类型的画面数据，所述第二类型画面数据是参考所述第一类型画面数据的解码结果而进行解码的，所述第一类型的画面数据在形成所述再现数据的所述多个画面数据中。
5、如权利要求1所述的再现设备，其特征在于:
在所述设备中，将不用参考其它画面数据的解码结果进行解码的I画面数据、和参考其它画面数据的解码结果进行解码的P画面数据，作为所述第一类型画面数据，
所述第二类型画面数据是参考其它画面数据的解码结果进行解码的B画面数据，
所述解码器在所述再现存储器的第一存储区域中同时存储和保持所述P画面数据的解码结果以及所述第一I画面数据的解码结果，其中所述P画面数据位于解码结果存储在所述存储器中的第一I画面数据和第二I画面数据之间，而且该第二I画面数据是在多个所述I画面数据中沿所述再现方向位于所述第一I画面数据后的下一个I画面数据。
6、如权利要求5所述的再现设备，其特征在于:
所述再现存储器具有与所述第一存储区域分离的第二存储区域，用于存储所述B画面数据，以及
所述解码器按次序在其它B画面数据的解码结果上写入所述再现和输出的B画面数据的解码结果，直到完成位于所述第一I画面数据和所述第二I画面数据之间的所有B画面数据的解码为止。
7、如权利要求1所述的再现设备，其特征在于:所述处理电路使所述多个解码器解码多个画面数据组，这些画面数据组每个都包含由不同的解码电路连续地再现和输出的多个画面数据。
8、如权利要求7所述的再现设备，其特征在于:在紧临存储在所述再现存储器中的第一组画面数据之前由所述解码器解码的第二组画面数据的所述第一类型画面数据的解码结果上，所述解码器写入第一组画面数据中的所述第一类型画面数据的解码结果。
9、如权利要求1所述的再现设备，
所述设备为每个所述画面数据定义用于指示是否解码所述画面数据的画面属性数据，并且
包含控制存储装置，用于存储所述多个画面数据的所述画面属性数据；以及
所述解码器基于从所述控制存储装置读取的所述画面属性数据、确定是否解码对应于所述画面属性数据的所述画面数据。
10、如权利要求9所述的再现设备，其特征在于:所述解码器依据所指定的再现速度更新存储在所述控制存储装置中的所述画面属性数据。
11、如权利要求10所述的再现设备，其特征在于:每当更新所述画面属性数据时，所述解码器更新对应于指示进行解码的所述画面属性数据的所述画面数据的再现定时。
12、一种数据处理***，包含:
数据处理设备，用于将形成再现数据的多个画面数据输出到再现设备；以及
再现设备，用于连续地解码和再现从所述数据处理设备输入的多个画面数据；
所述再现设备包含:
输入存储器，用于存储从所述数据处理设备输入的所述画面数据；
多个再现存储器；
多个解码器，对从所述输入存储器读取的所述画面数据进行解码，在所述再现存储器中写入解码结果，并且再现和输出从所述再现存储器中读取的所述解码结果，
其中，所述解码器以所述画面数据为单位，再现由第一类型画面数据和第二类型画面数据组成的再现数据，其中关于第一类型画面数据，其解码结果在其它画面数据的解码中被参考，而且关于第二类型画面数据，其解码结果不在其它画面数据的解码中被参考；
在所述再现存储器中保持所述第一类型画面数据的所述解码结果的存储；以及
在参考已经存储在所述再现存储器中的所述第一类型画面数据的解码结果时，解码并且再现和输出所述第二类型画面数据；以及
处理电路，用于执行解码调度，以便以预定多个所述画面数据为单位确定使所述解码器解码所述画面数据的次序，以由所述解码调度所确定的所述次序选择要被处理的所述画面数据，依据所指定的再现速度、判定是否解码所述选择的画面数据或者再现或者输出解码结果，以及基于该判定结果、控制所述解码器的解码以及再现和输出，
其中，
所述多个解码器进一步用于并行地处理所述再现数据；
所述多个再现存储器，对应于所述多个解码器而设置；以及
所述再现设备进一步包括又一个处理电路，用于使所述解码器解码所述画面数据，以便由同一个解码器解码参考相同的第一类型画面数据的解码结果的所述第二类型画面数据，以及由同一个解码器解码包括在所述画面数据组中的所述第一类型画面数据。
13、一种连续地解码和再现形成再现数据的多个画面数据的再现方法，该方法包含:
第一步骤，执行解码调度，以便以预定多个所述画面数据为单位确定解码所述画面数据的次序；
第二步骤，基于由在所述第一步骤中的所述解码调度确定的次序选择要被处理的所述画面数据；
第三步骤，依据所指定的再现速度、确定是否解码在所述第二步骤中选择的所述画面数据或者再现和输出解码结果；以及
第四步骤，基于所述第三步骤的确定、控制所述解码以及所述解码结果的再现和输出。
14、如权利要求13所述的再现方法，其特征在于:所述第三步骤基于为每个所述画面数据定义的、指示是否解码所述画面数据的画面属性数据，确定是否解码对应于所述画面属性数据的所述画面数据。
15、一种再现方法，包含:
第一步骤，用于将形成再现数据的多个画面数据从数据处理设备输出到再现设备；
第二步骤，使所述再现设备执行解码调度，以便以预定多个所述画面数据为单位确定解码在所述第一步骤中从所述数据处理设备输入的画面数据的次序；
第三步骤，由在所述第二步骤中执行的所述解码调度确定的次序，选择被处理的所述画面数据；
第四步骤，依据所指定的再现速度、确定是否解码在所述第三步骤中选择的所述画面数据或者再现和输出解码结果；以及
第五步骤，基于所述第四步骤的确定、控制所述解码以及所述解码结果的所述再现和输出。
16、一种数据处理设备，包含:
存储介质，存储形成再现数据的多个画面数据；
读取装置，用于从所述存储介质中读取所述画面数据；
输入存储器，用于存储由所述读取装置读取的所述画面数据；
多个再现存储器；
多个解码器，用于对从所述输入存储器读取的所述画面数据进行解码，在所述再现存储器中写入解码结果，并且再现和输出从所述再现存储器中读取的所述解码结果，
其中，所述解码器以所述画面数据为单位，再现由第一类型画面数据和第二类型画面数据组成的再现数据，其中关于第一类型画面数据，其解码结果在其它画面数据的解码中被参考，而且关于第二类型画面数据，其解码结果不在其它画面数据的解码中被参考；
在所述再现存储器中保持所述第一类型画面数据的所述解码结果的存储；以及
在参考已经存储在所述再现存储器中的所述第一类型画面数据的解码结果时，解码并且再现和输出所述第二类型画面数据；以及
处理电路，用于执行解码调度，以便以预定多个所述画面数据为单位确定使所述解码器解码所述画面数据的次序，以由所述解码调度所确定的所述次序选择要被处理的所述画面数据，依据所指定的再现速度、判定是否解码所选择的画面数据或者再现或者输出解码结果，以及基于该判定结果控制所述解码器的解码以及再现和输出，
其中，
所述多个解码器进一步用于并行地处理所述再现数据；
所述多个再现存储器，对应于所述多个解码器而设置；以及
所述数据处理设备进一步包括又一个处理电路，用于使所述解码器解码所述画面数据，以便由同一个解码器解码参考相同的第一类型画面数据的解码结果的所述第二类型画面数据，以及由同一个解码器解码包括在所述画面数据组中的所述第一类型画面数据。
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