CN100466443C - Rectifier circuit and radio communication device - Google Patents
Rectifier circuit and radio communication device Download PDFInfo
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- CN100466443C CN100466443C CNB2005100781628A CN200510078162A CN100466443C CN 100466443 C CN100466443 C CN 100466443C CN B2005100781628 A CNB2005100781628 A CN B2005100781628A CN 200510078162 A CN200510078162 A CN 200510078162A CN 100466443 C CN100466443 C CN 100466443C
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Abstract
A rectifier circuit includes: a bias circuit which is used for outputting direct current voltage; a first MOS transistor which is equipped with a gate and a source cathode; a second MOS transistor which is equipped with a gate, a source cathode and a drain that is connected with the source cathode of the first MOS transistor. Only the direct current voltage is applied between the gate and the source cathode of the first MOS transistor, and only the direct current voltage is applied between the gate and the source cathode of the second MOS transistor. The rectifier circuit also includes a coupling capacitor which is equipped with a first end part that is connected with the source cathode of the first MOS transistor and a second end part for inputting AC current signals to the coupling capacitor.
Description
The cross reference of related application
The Japanese patent application 2005-152990 that the application submits to based on the No.2004-180164 of Japanese patent application formerly that submitted on June 17th, 2004 with on May 25th, 2005 and required its benefit of priority, the whole contents of these two pieces of documents here is cited as a reference.
Technical field
The present invention relates to a kind of rectifier circuit and the radio communications set that comprises this rectifier circuit.
Background technology
Rectifier circuit is transformed into direct current (DC) by the rectification of diode with alternating current (AC).This rectifier circuit has adopted its source electrode and the interconnective diode connection of grid (diode-connected) MOS transistor as diode when being provided as semiconductor integrated circuit.For example, when adopting the nmos pass transistor of isolating by Mitsui (triple well) and substrate as diode, its drain electrode is connected with the n well with source electrode, and source electrode also is positioned on the aboveground back of the body grid (backgate) of the p that locates transistorized bottom with being connected.
The rule class is communicator and discerns (RFID) labeling requirement rectifier circuit owing to it is widely used the radio frequency that receives publicity recently.The RFID label produces the DC power supply voltage of the integrated circuit that is used for driving the RFID label and with demodulated data signal from the alternating current that induces loop aerial.Voltage produces and demodulation needs rectifier circuit.
People such as No.2002-152080 and M.Usami " Powder LSI:An ultra small RF identification chip for individualrecognition applications " for example disclosed in Japanese patent application, ISSCC Dig.Tech.Papers, in March, 2003, this rectifier circuit in a kind of RFID of being used in label has been proposed in the 398-398 page or leaf.
But, in order to carry out the rectification of diode, must be at the voltage that promptly in source electrode and drain electrode, applies the threshold value (being approximately 0.7V) that is not less than MOS transistor on the PN junction.Therefore, the conventional rectifier circuit can not be adjusted the AC signal with the root mean square numerical value that is not less than this threshold value.This means that the RFID label can not receive the weak signal that is sent by reader/writer.In fact, but the distance limit that the RFID label can be communicated by letter with reader/writer to this restriction of received signal power at about 30cm.The close reader/writer of people that this carries the RFID label apart from needs or posts this RFID lebal article, thus convenience reduced.This distance also makes a reader/writer be difficult to detect simultaneously a plurality of RFID labels, and has limited the range of application of RFID label.
Summary of the invention
According to one aspect of the invention, a kind of rectifier circuit is provided, it comprises: be used for the biasing circuit of output dc voltage; One first MOS transistor, it has a grid and one source pole, only applies described direct voltage between the grid of this first MOS transistor and source electrode; One second MOS transistor, it has the drain electrode that a grid, one source pole are connected with source electrode with first MOS transistor, only applies described direct voltage between the grid of this second MOS transistor and source electrode; And a coupling capacitor, it has the first end that is connected with the source electrode of described first MOS transistor and to the second end of its input exchange signal.
According to second aspect present invention, a kind of rectifier circuit is provided, it comprises first rectifier circuit and second rectifier circuit, each rectifier circuit structure is identical, include: be used for the biasing circuit of output dc voltage, one first MOS transistor, it has a grid and one source pole, between the grid of this first MOS transistor and source electrode, only apply described direct voltage, one second MOS transistor, it has a grid, the drain electrode that one source pole is connected with source electrode with first MOS transistor, between the grid of this second MOS transistor and source electrode, only apply described direct voltage, and a coupling capacitor, it has the first end that is connected with the source electrode of described first MOS transistor and to the second end of its input exchange signal; And wherein the source electrode of second MOS transistor in the drain electrode of first MOS transistor in first rectifier circuit and second rectifier circuit is connected.
According to third aspect present invention, a kind of rectifier circuit is provided, it comprises: one first floating boom transistor, it has first floating boom of an interconnective control gate and one source pole, a drain electrode and maintenance predetermined potential; One second floating boom transistor, it has second floating boom of an interconnective control gate and one source pole, the drain electrode that is connected with the transistorized source electrode of first floating boom and maintenance predetermined potential; And a coupling capacitor, it has the first end that is connected with the transistorized source electrode of first floating boom and to the second end of its input exchange signal.
Another aspect according to the present invention provides a kind of radio communications set, and it comprises: a loop aerial; One rectifier circuit, it comprises: be used for the biasing circuit of output dc voltage, one first MOS transistor, it has a grid and one source pole, between the grid of this first MOS transistor and source electrode, only apply described direct voltage, one second MOS transistor, it has a grid, the drain electrode that one source pole is connected with source electrode with first MOS transistor, between the grid of this second MOS transistor and source electrode, only apply described direct voltage, and a coupling capacitor, it has the first end that is connected with the source electrode of described first MOS transistor and the second end of the AC signal responded to its input in loop aerial; One memory, its storage tags identifying information; And a signal processing circuit, its receives and sends described tag recognition information according to the direct current that is gone out by the rectifier circuit rectification by loop aerial.
Description of drawings
Fig. 1 is the circuit diagram according to the part of the rectification circuit of first embodiment;
Fig. 2 is the circuit diagram of the embodiment of biasing circuit;
Fig. 3 is the block diagram according to the rectifier circuit of first embodiment;
Fig. 4 is the circuit diagram that is used in according to the clock generator circuit in the rectifier circuit of first embodiment;
Fig. 5 is the time diagram according to the clock generator circuit of the rectifier circuit of first embodiment;
Fig. 6 is the circuit diagram of the embodiment of DC generator circuit;
Fig. 7 is the circuit diagram of another embodiment of DC generator circuit;
Fig. 8 is the circuit diagram according to the part of the rectifier circuit of second embodiment;
Fig. 9 is the circuit diagram according to the rectifier circuit of the 3rd embodiment; Figure 10 is the block diagram according to the dc voltage source of the rectifier circuit of the 3rd embodiment; Figure 11 is the circuit diagram of the booster circuit in dc voltage source;
Figure 12 is the flow chart of the control of floating boom;
Figure 13 is the flow chart of electric weight testing process;
Figure 14 is the flow chart of the operation of the current detecting pattern in the dc voltage source;
Figure 15 is the flow chart of charging assignment procedure;
Figure 16 is the flow chart that the voltage in the dc voltage source is set the operation of pattern;
Figure 17 is the circuit diagram according to the rectifier circuit of the 4th embodiment;
Figure 18 is the circuit diagram according to the rectifier circuit of the 5th embodiment;
Figure 19 is the circuit diagram according to the rectifier circuit of the 6th embodiment;
Figure 20 is a curve chart, wherein demonstrates according to the rectification characteristic of the RFID label of the 6th embodiment (solid line) and the rectification characteristic of traditional RFID label (dotted line); And
Figure 21 is the block diagram according to the another kind of RFID label of the 6th embodiment.
Embodiment
Be elaborated to comprising with reference to these accompanying drawings below according to the rectifier circuit of RFID label of the present invention and the exemplary of radio communications set.Specifically, the example of RFID label as radio communications set is illustrated.
Rectifier circuit according to first embodiment of the invention comprises a diode-connected transistor, has wherein applied constant voltage between its source electrode and grid.Specifically, this constant voltage is less than carrying out the threshold value that rectifier needs, preferably less than the magnitude of voltage near this threshold value in MOS transistor.
Fig. 1 is the circuit diagram according to the part of the rectifier circuit (being referred to below as " diode circuit ") of first embodiment.Comprise nmos pass transistor M1 at the diode circuit shown in Fig. 1, its back of the body grid and source electrode interconnect, and its drain electrode is connected with positive terminal T1.This diode circuit also comprises the source electrode that is connected nmos pass transistor M1 and the biasing circuit 10a between the grid.This biasing circuit 10a produces predetermined voltage.This connection makes nmos pass transistor M1 as the diode that has PN junction on drain side.This biasing circuit 10a applies predetermined voltage between the grid of nmos pass transistor M1 and source electrode.Specifically, biasing circuit 10a produces less than the voltage (being referred to below as " diode biasing ") that carries out the threshold value that rectifier needs in nmos pass transistor M1 as this predetermined voltage.This diode biasing for example is 0 to 1.0V, is preferably the numerical value near threshold value, for example is 0.6V.In other words, utilize the diode biasing between grid and source electrode to apply bias voltage to use the root mean square numerical value rectification AC signal that is not more than threshold voltage for nmos pass transistor M1.This diode circuit diode biasing can enough about 100mV during for example for 0.6V root mean square numerical value rectification AC signal.
This diode circuit also comprises its back of the body grid and interconnective nmos pass transistor M2 of source electrode.The source electrode of this nmos pass transistor M2 is connected with negative terminal T2.Biasing circuit 10b is connected between the grid and source electrode of nmos pass transistor M2.Nmos pass transistor M2 also has the identical functions with nmos pass transistor M1, and is subjected to diode biasing between its grid and source electrode by biasing circuit 10b.
The drain electrode of the source electrode of nmos pass transistor M1 and nmos pass transistor M2 interconnects, and the lead that connects them is connected on the end of capacitor C1.Another end of this capacitor C1 is connected on the signal input terminal TA.This capacitor C1 is as coupling capacitor.This capacitor C1 is connected with loop aerial in the time will being used in the RFID label according to the rectifier circuit of this embodiment, and as series resonance capacitor.
Capacitor C2 is connected between the source electrode of the drain electrode of nmos pass transistor M1 and nmos pass transistor M2.Make by the signal half-wave of nmos pass transistor M1 and M2 rectification level and smooth by capacitor C2.This smoothly makes it possible to from two ends of capacitor C2 i.e. output dc voltage between positive terminal T1 and negative terminal T2.
Nmos pass transistor M1 and M2 form has three well constructions, and insulate with substrate.Therefore, each source electrode is connected with the p well at the place, bottom that is positioned at nmos pass transistor, and each drain electrode is connected with the n well.Diode forms PN junction in each MOS transistor.
Fig. 2 is the circuit diagram of the embodiment of biasing circuit 10a or 10b.At the biasing circuit shown in Fig. 2 100 corresponding to biasing circuit 10a or 10b.This biasing circuit 100 comprises two the nmos pass transistor M11 and the M12 that are connected in series.Each of these nmos pass transistors M11 and M12 is used as TG transfer gate (transfer gate), and is arranged on the main track L1.Biasing circuit 100 also comprises two nmos pass transistor M21 and M22, and they are connected in series on negative wire L2 and are used separately as TG transfer gate.The grid of nmos pass transistor M11 and M21 interconnects, and the grid of nmos pass transistor M12 and M22 interconnects.Capacitor C11 is connected the drain electrode that is used for nmos pass transistor M11 and is connected the lead on the source electrode of nmos pass transistor M12 and is used for drain electrode with nmos pass transistor 21 and be connected between the lead on the source electrode of nmos pass transistor M22.Capacitor C12 is connected between the drain electrode of the drain electrode of nmos pass transistor M12 and nmos pass transistor M22.
Biasing circuit 100 is connected with DC generator circuit 110 with phase inverter INV1, phase inverter INV2 as peripheral circuit.DC generator circuit 110 produces the dc voltage corresponding with diode biasing from offer the main power voltage according to the rectifier circuit of this embodiment.To be elaborated to this DC generator below.The dc voltage that is produced by DC generator circuit 110 is applied between the main track L1 and negative wire L2 of biasing circuit 100.Since representative at the nmos pass transistor M10 of nmos pass transistor M1 shown in Fig. 1 and M2 with for example several GHz level operations of higher frequency, so should be reduced in parasitic capacitance among the nmos pass transistor M10 as far as possible.DC generator circuit 110 has high capacitance to produce stable dc voltage.Therefore, be provided with biasing circuit 100 as shown in Figure 2, thereby be not applied directly between the grid and source electrode of nmos pass transistor M10 from the diode biasing of DC generator circuit 110 outputs.
The input terminal of phase inverter INV1 is connected on the clock input terminal TC, and receives the clock pulse with preset frequency.These clock pulse are for example produced by described clock generator circuit in the back.The lead-out terminal of phase inverter INV1 is connected with each grid of nmos pass transistor M11 and M21 and the input terminal of phase inverter INV2.The lead-out terminal of phase inverter INV2 is connected with each grid of nmos pass transistor M12 and M22.
When the clock pulse from clock input terminal TC input is logic " low ", phase inverter INV1 output logic " height ", and phase inverter INV2 output logic " low ".Therefore, nmos pass transistor M11 and M21 open, and the dc voltage that provides from DC generator circuit 110 are provided with for capacitor C11.And nmos pass transistor M12 and M22 close, and do not apply any dc voltage to capacitor C12.
When the clock pulse from clock input terminal TC input is logic " height ", phase inverter INV1 output logic " low ", and phase inverter INV2 output logic " height ".Therefore, nmos pass transistor M11 and M21 close, and nmos pass transistor M12 and M22 open, thereby the electric charge that charges at capacitor C11 offers capacitor C12.Because the two ends of capacitor C12 are connected with the lead-out terminal of biasing circuit 100, so the voltage of locating in these ends of capacitor C12 is applied to as diode biasing between the grid and source electrode of diode connection nmos pass transistor M10.
At last, the voltage that only need locate at the two ends of capacitor C12 is the diode biasing of nmos pass transistor M10.The dc voltage that provides from DC generator circuit 110 can be identical with diode biasing.For example, can the voltage of capacitor C12 be fixed on any number place by adopting pulse-width modulation (PWM) control to switch nmos pass transistor M11, M12, M21 and M22.In this case, main power source can be connected between main track L1 and the negative wire L2, and need not DC generator circuit 110.
Fig. 3 is the block diagram according to the rectifier circuit of first embodiment.At the rectifier circuit shown in Fig. 3 120 is such circuit, wherein will be applied on the diode circuit shown in Figure 1 at biasing circuit shown in Fig. 2 100 and peripheral circuit (DC generator circuit 110 and phase inverter INV1 and INV2).In each of biasing circuit 100a shown in Fig. 3 and 100b with corresponding at the biasing circuit shown in Fig. 2 100.As shown in Figure 3, each all is that the nmos pass transistor M1 and the M2 of diode connection need be at the biasing circuit shown in Fig. 2 100.Share by biasing circuit 100a and 100b as the DC generator circuit 110 of peripheral circuit and phase inverter INV1 and INV2.
Though two diode connections of aforesaid diode electrically route nmos pass transistor forms, what replace is to use two diode connection PMOS transistors.In addition, constitute the TG transfer gate of biasing circuit 100, promptly aforesaid nmos pass transistor can be nmos pass transistor.Can under the situation that does not have phase inverter INV2, replace at nmos pass transistor M12 and the M22 shown in Fig. 2 with the PMOS transistor.
Fig. 4 is the circuit diagram of clock generator circuit 130 that is used for producing the clock pulse of the clock input terminal TC that inputs to rectifier circuit 120.This clock generator circuit 130 comprises one virtual (dummy) rectification module, a virtual handover module and a differential amplifier 310.Virtual rectification module is the part repeat circuit of the rectification module of rectifier circuit 120, comprises having and nmos pass transistor M1 or the identical shaped nmos pass transistor Md5 of M2.Back of the body grid and the source electrode of nmos pass transistor Md5 interconnect.The source electrode of nmos pass transistor Md5 is connected with negative terminal with drain electrode, and has electromotive force V3.Capacitor Cd2 is connected electrically between the grid and source electrode of nmos pass transistor Md5.Specifically, virtual rectification module has imitated one of them rectifying device that constitutes the rectification module of rectifier circuit 120.
Virtual handover module comprises nmos pass transistor Md1 to Md4, capacitor Cd1 and Cd2 and phase inverter INV1 and INV2.Being connected of nmos pass transistor Md1 to Md4 and capacitor Cd1 and Cd2 is identical with the handover module of the biasing circuit 100a of rectifier circuit 200 or 100b.
Specifically, each of nmos pass transistor Md1 and Md2 is used as TG transfer gate, and is arranged on the main track.Nmos pass transistor M11 that is connected in series and each of M12 are used as TG transfer gate, and are arranged on the negative wire.The grid both of the grid of nmos pass transistor Md1 and nmos pass transistor Md3 is connected on the lead-out terminal of phase inverter INV12.The input terminal of phase inverter INV12 is connected on the lead-out terminal of phase inverter INV11.The grid both of the grid of nmos pass transistor Md2 and nmos pass transistor Md4 is connected on the lead-out terminal of phase inverter INV11.Capacitor Cd1 is connected the drain electrode that is used for nmos pass transistor Md1 and is connected the lead on the source electrode of nmos pass transistor Md2 and is used for drain electrode with nmos pass transistor Md3 and be connected between the lead on the source electrode of nmos pass transistor Md4.Capacitor Cd2 is connected between the drain electrode of the drain electrode of nmos pass transistor Md2 and nmos pass transistor Md4.
On the source electrode of the source electrode of nmos pass transistor Md1 and nmos pass transistor Md3 and the same positive terminal and negative terminal that is connected to DC generator circuit 110 in biasing circuit shown in Figure 2 100.Suitable gain will be amplified to export a fundamental clock voltage V at voltage on two ends of capacitor Cd2 and the differential pressure between the reference voltage in the differential amplifier position
EReference voltage is expressed as voltage V
T-V
X, V wherein
TThe dc voltage that provides from DC generator circuit 110 is provided, and V
XBe for example 50mV.In other words, the voltage of differential amplifier 310 monitoring capacitor Cd2 is to produce fundamental clock voltage V
E
The lead-out terminal of differential amplifier 310 is connected with the input terminal of phase inverter INV11.The lead-out terminal of phase inverter INV11 is connected with the lead-out terminal BC of clock generator circuit 130.This lead-out terminal BC is connected with the clock input terminal TC of rectifier circuit 120.Therefore, as fundamental clock voltage V from differential amplifier 310 outputs
EWhen reaching the numerical value that is not less than predetermined level, and as fundamental clock voltage V
EWhen dropping to less than predetermined level, phase inverter INV1 output logic " height ".
Fig. 5 is the electromotive force V at the place, an end of capacitor Cd2
0, from the differential pressure V of differential amplifier 310 output
E, phase inverter INV11 output potential V
1Output potential V with phase inverter INV12
2Time diagram.
Because the leakage current by nmos pass transistor Md5 discharges capacitor Cd2, so electromotive force V
0Reduce gradually and finally become less than reference voltage V
T-V
X(second stage).Specifically, the differential pressure V that exports from differential amplifier 310
EBegin to reduce gradually from positive saturation level, and finally become for phase inverter INV11 input signal for logic " low " (t1 constantly: the phase III).Therefore, the output potential V of phase inverter INV11
1Become logic " height ", and the output potential V of phase inverter INV12
2Become logic " low ".And nmos pass transistor Md2 and Md4 open, and are applied on the capacitor Cd2 at the electric charge on the capacitor Cd1.Specifically, the electromotive force V of capacitor Cd2
0No better than greater than reference voltage V
T-V
XElectromotive force V
T, and enter the phase I.Afterwards, repeat first to the phase III.
Output potential V
1For repeating the pulse that period produces in the stage.Rectifier circuit 120 is accepted this output potential V
1As clock pulse.Specifically, because clock generator circuit 130 has imitated a part of rectifier circuit 120, so this clock pulse is in the output of the time of the best so that effectively to biasing circuit 100a or the capacitor among the 100b (corresponding with capacitor C11 and C12 in Fig. 1) charging at rectifier circuit 120.Therefore, the nmos pass transistor M1 of formation rectification module and M2 always are subjected to the bias voltage greater than the voltage of predetermined level, and the gain of rectifier circuit 120 always keeps greater than predetermined value.
Can adopt the PMOS transistor as the MOS transistor that is used for clock generator circuit 130.
The constant dc voltage that provides from DC generator circuit 110 has been provided for rectifier circuit 120 and clock generator circuit 130 boths.Because constitute the manufacturing variation of the electronic installation of DC generator circuit 110, this dc voltage may not can be represented desired numerical value.But, may produce the dc voltage that does not depend on this manufacturing variation according to the DC generator circuit 110 of this embodiment.
Fig. 6 is the circuit diagram of the embodiment of DC generator circuit 110.Comprise that at the DC generator circuit 110a shown in Fig. 6 its grid is with the interconnective nmos pass transistor M101 of drain electrode and from supply voltage V
DDIn produce the constant-current source 111 of constant current.The drain electrode of the lead-out terminal of constant-current source 111 and nmos pass transistor M101 interconnects by switch SW.The source ground of nmos pass transistor M101.Grid and voltage between the source electrode and the dc voltage V that exports from DC generator circuit 110a at nmos pass transistor M101
TCorresponding.
When switch SW is connected, provide constant current to nmos pass transistor M101 from constant-current source 111.This nmos pass transistor 101 produces voltage according to this constant current between grid and source electrode.When the electric current that provides from constant-current source 111 is very low when for example being not more than 1 μ A, nmos pass transistor M101 is in the boundary condition that switches on and off.Specifically, at the grid of nmos pass transistor M101 and the voltage between source electrode threshold voltage no better than.This is based on such theory, and promptly the characteristic of MOS transistor is generally by I
D=β (V
GS-V
Th)
2Expression, and low current I
DMake the voltage V between grid and source electrode
GSThreshold value V no better than
ThTherefore, this voltage can be as the diode biasing of rectifier circuit 120.
Switch SW needn't always be connected during the clock pulse of logic " height ".This switch SW can be just connected in the specific period of the clock pulse of logic " height ".
Fig. 7 is the circuit diagram of another embodiment of DC generator circuit 110.Comprise two nmos pass transistor M111 and M112 at the clock generator circuit 110b shown in Fig. 7, each has interconnective grid and drain electrode, and is used for producing the constant-current source 111 as the constant current among Fig. 6.Nmos pass transistor M111 and M112 are connected in series.The drain electrode of the lead-out terminal of constant-current source 111 and nmos pass transistor M111 interconnects by switch SW.The grid of nmos pass transistor M112 and the voltage between the source electrode and in the summation of the grid of nmos pass transistor M111 and the voltage between the source electrode corresponding to dc voltage V from DC generator circuit 110b output
T
In DC generator circuit 110b, each threshold value of nmos pass transistor M111 and M112 is less than the threshold voltage of the nmos pass transistor Md5 of each threshold voltage of the nmos pass transistor M1 of rectifier circuit 120 and M2 and clock generator circuit 130, and have such level, thereby the summation of grid-source voltage becomes and equals dc voltage V
TTherefore, even comprise that in employing its threshold value is lower than under the situation of supply voltage of MOS transistor of threshold value of nmos pass transistor M1, M2 and M5, also can utilize this DC transmitter circuit 110a with not made differentia influence.
And this DC generator circuit 110 is preferred to adopt the transistor of its shapes and the MOS transistor identical (especially, the MOS transistor M1 of diode circuit or M2) of rectifier circuit 120.Even in having difform transistorized situation, the ratio aspect that this transistor is preferably in grid width and grid length has scalable shape.
According to the rectifier circuit of aforesaid first embodiment, this biasing circuit applies constant voltage between diode connection MOS transistor, and wherein this constant voltage is less than being used for the threshold level that the MOS transistor rectifier needs, preferably near this threshold level.Therefore, can use root mean square numerical value to come rectification AC signal less than the threshold level of MOS transistor.
Fig. 8 is the circuit diagram according to the part of the rectifier circuit of second embodiment (diode circuit).Comprise two stacked diode circuits at the diode circuit shown in Fig. 8, each circuit is with corresponding at the diode circuit shown in Fig. 1.Each is corresponding with nmos pass transistor M1 for nmos pass transistor M41 and M51, and nmos pass transistor M42 and M52 each is all corresponding with nmos pass transistor M2.Each is all corresponding with capacitor C1 for capacitor C41 and C51, and capacitor C42 and C52 each is all corresponding with capacitor C2.And each of biasing circuit 50a, 50b, 50c and 50d is with identical at biasing circuit 10a or the 10b shown in Fig. 1.
Difference AC signal is inputed to positive signal input terminal TA1 that is connected with the end of capacitor C41 and the negative signal input terminal TA2 that is connected with the end of capacitor C51.These positive signal input terminals are connected with two ends of loop aerial respectively in the time will being used in the RFID label according to the rectifier circuit of this embodiment with negative signal input terminal TA2.
Each of biasing circuit 50a, 50b, 50c and the 50d shown in Fig. 8 as in the first embodiment with corresponding at the biasing circuit as shown in Fig. 2.Adopt the rectifier circuit of these biasing circuits can have with in the identical structure of the structure shown in Fig. 3.Should be noted that to have the structure that wherein is laminated with at least two diode circuits according to the rectifier circuit of second embodiment.
Therefore, identical according to its advantage of rectifier circuit of this embodiment with advantage according to the rectifier circuit of first embodiment.
Rectifier circuit according to the 3rd embodiment has adopted the floating gate fet of diode connection as rectifying device.Specifically, floating boom by the threshold level that needs less than this floating gate fet rectifier preferably near the constant-potential charge of this threshold level.
Fig. 9 is the circuit diagram according to the rectifier circuit of the 3rd embodiment.Comprise a floating gate fet M71 at the rectifier circuit shown in Fig. 9 200, its control gate and drain electrode interconnect, and its drain electrode is connected with positive terminal T71.And, voltage (the being referred to below as diode biasing) charging that the floating boom of floating gate fet M71 is needed by this floating gate fet M71 rectifier.Here, suppose that diode biasing equals the threshold level of floating gate fet M71.Therefore, the threshold level vanishing basically of this floating gate fet M71, and can comprise all AC signals of this AC signal with the root mean square numerical value rectification that is not more than threshold level.
The drain electrode of the source electrode of floating gate fet M71 and floating gate fet M72 interconnects, and the lead that connects them is connected on the end of capacitor C71.Another end of this capacitor C71 is connected on the signal input terminal TA.This capacitor C71 is as coupling capacitor.In the time will being used in the RFID label according to the rectifier circuit 200 of this embodiment, this capacitor C71 be connected with loop aerial, and as the series coupled capacitor.
Capacitor C72 is connected between the source electrode of the drain electrode of floating gate fet M71 and floating gate fet M72.Make by the signal half-wave of these floating gate fets M71 and M72 rectification level and smooth by capacitor C72.This smoothing makes promptly can output dc voltage between positive terminal T71 and negative terminal T72 from the two ends of capacitor C72.
Specifically, comprise the weak AC signal that the diode circuit of floating gate fet M71 and M72 and capacitor C71 and C72 can be difficult to rectification with the amplitude rectification conventional rectifier circuit of about 100mV.Therefore, the RFID label of use rectifier circuit 200 can rectification light current ripple.In other words, even RFID also can carry out rectification and long haul communication away from the base station time.
Figure 10 is the circuit diagram as the dc voltage source 220 of the embodiment of dc voltage source 220a, 220b and 220c.Comprise the switch SW 200 that is used for changing two operator schemes, voltage setting pattern and current detecting pattern in the dc voltage source 220 shown in Figure 10.Dc voltage source 220 also comprises a voltmeter 221, a booster circuit 222, an ammeter 233 and a variable voltage source 224 and a control circuit 225.Voltmeter 221 and booster circuit 222 are connected and are used to select voltage to set an end of the switch SW 200 of pattern.This variable voltage source 224 is electrically connected by ammeter 223 another end with the switch SW 200 that is used to select the current detecting pattern.Control circuit 225 is being controlled switch SW 200 and is being set the voltage of giving booster circuit 222 and variable voltage source 224 according to the control signal from control circuit 210 outputs of rectifier circuit 200, and will represent the magnitude of voltage measured by voltmeter 221 and the signal of the current value measured by ammeter 223 sends to control circuit 210.
Figure 11 is the circuit diagram of embodiment of the booster circuit 222 in dc voltage source 220.At the booster circuit shown in Figure 11 222 is general charge pump circuit.This charge pump circuit is by being connected the capacitor Cc1 receive clock pulse CK between transistor Mc1 and the Mc2, and receives the clock pulse/CK of the inverse of this clock pulse CK by being connected capacitor Cc2 between transistor Mc2 and the Mc3.Dotted line in Figure 11 is represented the repetition of these parts.Supply voltage V
DDBy towards lead-out terminal V
OUTReceive clock pulse when boosting and conversion.If charge pump circuit comprises n transistor, then from the voltage of lead-out terminal VOUT output by (N+1)/(V
DD-V
Th) expression, wherein V
ThBe transistorized threshold level.Can provide the voltage of about 10V so that set the electromotive force of floating boom by booster circuit 222.
To the control of the floating boom of floating gate fet M71 and M72 be described below.Figure 12 is the flow chart of the control of floating boom.At first detect the electric weight (amount of charge) (step S101) on each floating boom of floating gate fet M71 and M72.Figure 13 is the flow chart of electric weight testing process.The control circuit 210 of this rectifier circuit 200 sent to control signal each control circuit 225 of dc voltage source 220a to 220c before detecting electric weight.This control signal represents to be used to switch to current detecting pattern and the request (step S201 to S203) of setting the voltage value of giving each variable voltage source 224.In addition, the control circuit 210 of rectifier circuit 200 is opened switch SW 1 to SW3 (step S204).
Figure 14 is the operational flowchart in the current detecting pattern in dc voltage source 220.The control signal that the control circuit 225 in dc voltage source 220 receives from the control circuit 210 of rectifier circuit 200 switches to the current detecting pattern with switch SW 200, and this voltage is set to variable voltage source 224 (step S402).For example, in order to detect the electric weight on the floating boom of floating gate fet M71, the variable voltage source 224 of this dc voltage source 220a is set at 1 volt, and the variable voltage source 224 of this dc voltage source 220b is set at zero volt.Then, measure current values (step S403) with the ammeter 223 in each dc voltage source 220.In fact this current values is measured after step S204.
The control circuit 210 of rectifier circuit 200 is received in each current value of measuring among dc voltage source 220a, 220b and the 220c, calculates the voltage V corresponding with electric weight from each current value
c(step S205), and off switch SW1 to SW3 (step S206).
Afterwards, control circuit 210 definite voltage V that calculated
cBe not less than threshold level V
Th(step S102).For this is determined, voltage on the same source electrode that must will be applied to floating gate fet with the embodiment of above-mentioned setting voltage is set at and is higher than the level that is applied to the voltage in the drain electrode: the variable voltage source 224 of dc voltage source 220a is set at 1 volt, the variable voltage source 224 of dc voltage source 220b is set at zero volt.For example, when electric current between the source electrode of floating gate fet M71 and drain electrode by the time, promptly when when higher, determining the voltage V of floating gate fet M71 from the current values of dc voltage source 220a acquisition
cBe not less than the threshold level V of floating gate fet M71
ThAs Vc during less than threshold level Vth, promptly when the current values that obtains from power supply 220a be zero or enough little (step S102: in the time of not), the floating boom of floating gate fet M71 is recharged (step S103).Before this charging is set, calculate in the voltage of floating boom and the differential pressure between the threshold level.By equally detecting electric weight repeatedly calculates this differential pressure as mentioned above.For example, when calculating, the variable voltage source 224 of dc voltage source 220a is set at zero volt, and the variable voltage source 224 of dc voltage source 220b is set at 0.5 volt in the voltage of the floating boom of floating gate fet M71 and the differential pressure between its threshold level.Then, open switch SW 1 and SW2, and detect the current values that obtains from dc voltage source 220b.
In this case, be applied to grid voltage V on the passage of floating gate fet M71
gBy V
g=V
f+ 0.5 expression, wherein V
fMagnitude of voltage for floating boom.Under this state, the current values of the dc voltage source 220b that flows through and (V
g-V
Th)
2=(V
f+ 0.5-V
Th)
2Proportional.When current value at this moment is higher, the variable voltage source of dc voltage source 220b is set at is lower than 0.5 volt level.When current value is zero or when enough low, the voltage source of this dc voltage source 220b is set at is higher than 0.5 volt level.Therefore, by reading out in the magnitude of voltage at current boundary place, thereby calculate in the voltage value of floating boom and the differential pressure between the threshold value.According to this differential pressure, determine to set voltage to the booster circuit 222 in dc voltage source 200.
Figure 15 is the flow chart of electric weight assignment procedure.The control circuit 210 of rectifier circuit 200 transmits control signal to each control circuit 225 of dc voltage source 220a to 220c.This control signal represents that being used to switch to voltage sets pattern and the request (step S301 to S303) that will set to the voltage value of each booster circuit 222.In addition, the control circuit 210 of rectifier circuit 200 is opened switch SW 1 to SW3 (step S304).
Figure 16 is the flow chart that the voltage in dc voltage source 220 is set the operation of pattern.The control signal that the control circuit 225 in this dc voltage source 220 receives from the control circuit 210 of rectifier circuit 200 switches to voltage with switch SW 200 and sets pattern (step S501), and this voltage is set to booster circuit 222 (step S502).For example, in order to give the floating boom charging of floating gate fet M71, the booster circuit 222 of dc voltage source 220a is set at high pressure, and the booster circuit 222 of dc voltage source 220b is set at zero volt.Measure the magnitude of voltage (step S503) of the floating boom of this floating gate fet M71 with the voltmeter 221 in each dc voltage source 220.This magnitude of voltage is actually to be measured after step S304.
The control circuit 210 of rectifier circuit 200 is by adopting cut-off switch SW1 to SW3 (step 306) after the booster circuit 222, applies the high pressure duration Δ t (step S305) on high pressure is applied to floating gate fet M71 with cut-out the floating boom.This time Δ t is defined as making that floating boom can be by the time of unsaturated charging.
At voltage V
cWhen step 102 place is not less than threshold level Vth, promptly when the current values that obtains from dc voltage source 220a is higher (step 102: be), determine this voltage V
cWhether greater than threshold level V
Th(step S104).As voltage V
cGreater than threshold level V
ThThe time (step S104: be), rectification efficiency reduces owing to floating gate fet M71 always connects.For fear of this state occurring, give floating gate discharging (step S105).
Can realize the setting of discharging by setting identical process with as shown in Figure 15 electric weight.For example, for floating gate discharging, the booster circuit 222 of dc voltage source 220a is set at zero volt, and the booster circuit 222 of dc voltage source 220b is set at high pressure, connect these switch SW 1 and SW2 afterwards floating gate fet M71.Therefore, the electronics that remains in the source electrode of floating gate fet M71 is transmitted to floating boom to be reduced in the electric charge on the floating boom.
As voltage V
cBe not more than threshold level V
ThThe time (step S104: not), promptly as voltage V
cEqual threshold level V
ThThe time, to the control end of floating boom.
Though adopt floating gate fet M71 as floating gate fet, also can adopt floating gate fet M72.The threshold level of each floating gate fet can be set at high potential.In this case, can not the weak radio signal of rectification.Specifically, when being applied in this rectifier circuit 200 on the RFID label, have only the RFID label of close base station can be subjected to the rectification operation.Can also control communication distance according to the electric weight that is applied on the floating boom, therefore can change the performance of RFID label according to fail safe, privacy and long haul communication.
According to the rectifier circuit of aforesaid the 3rd embodiment, in the floating boom of floating gate fet, kept constant voltage, this voltage is less than carrying out the threshold level (preferably near this threshold level) that the floating gate fet rectifier needs.Therefore, can use root mean square to come rectification AC signal less than the threshold level of floating gate fet.
According to the rectifier circuit of the 4th embodiment is modification according to the rectifier circuit 200 of the 3rd embodiment.Specifically, switch SW 1 to SW3, control circuit 210 and dc voltage source 220a to 220c are provided as the peripheral hardware different with rectifier circuit.Figure 17 is the circuit diagram according to the rectifier circuit of the 4th embodiment.In rectifier circuit shown in Figure 17 300, represent by identical reference symbol with those the identical parts in Fig. 9, and the explanation of these parts here will be omitted.
Except the parts of the rectifier circuit shown in Fig. 9 200, rectifier circuit 300 also comprises floating gate fet M71 and M72, capacitor C71 and C72.This rectifier circuit 300 also is arranged to an IC chip, and comprises the electrode pad P1 that is connected with the drain electrode of floating gate fet M71, the electrode pad P2 that is connected with the drain electrode of floating gate fet M71 and the electrode pad P3 that is connected with the source electrode of floating gate fet M72.These electrode pads P1, P2 can be connected with the respective end of switch SW 1, SW2 and SW3 with P3.
Rectifier circuit 300 is just once controlled (referring to Figure 12) by the electrode pad P1 to P3 on the floating boom of floating gate fet M71 and M72 to floating boom when agent's shipment for example.Because floating boom scribbles insulating material,, keep identical state thus so electric charge in case preserve, can not discharge in long-time.For example, the data that guarantee to be stored in the memory cell of EEPROM kept 10 years at least.Therefore, the rectifier circuit according to this embodiment can need not recharge with several years after to the floating boom charging.
Specifically, the user can use the RFID label that includes rectifier circuit 300 in the conventional mode, and this RFID can when agent's shipment, should charge set to give floating boom once after, carry out long haul communication.
According to the rectifier circuit of the 5th embodiment is another modification according to the rectifier circuit 200 of the 3rd embodiment.Specifically, rectifier circuit comprises the control gate that is connected each floating gate fet M71 and M72 and the capacitor between the source electrode, and the voltage that remains in the capacitor is controlled.
Figure 18 is the circuit diagram according to the rectifier circuit of the 5th embodiment.In rectifier circuit shown in Figure 180 400, represent by identical reference symbol with those the identical parts in Fig. 9, so the explanation of these parts here will be omitted.Except the parts of the rectifier circuit shown in Fig. 9 200, this rectifier circuit 400 comprises the control gate and the capacitor C81 between the source electrode that are connected floating gate fet M71, is connected the control gate of floating gate fet M72 and the capacitor C82 between the source electrode and dc voltage source 220d and 220e.And switch SW 4 is connected between the lead-out terminal of the control gate of floating gate fet M71 and dc voltage source 220d, and switch SW 5 is connected between the lead-out terminal of the control gate of floating gate fet M72 and dc voltage source 220e. Dc voltage source 220d and 220e and switch SW 4 and SW5 also have switch SW 4 and SW5 control by control circuit 210 and other dc voltage source 220a to 200c.Each of dc voltage source 220d and 220e is with the same in the dc voltage source 220 shown in Figure 10.
According to this structure, can be respectively apply various input voltages separately to each control gate of floating gate fet M71 and M72.Can be that the applied signal voltage that floating gate fet M71 and M72 rectifier need is adjusted to any level with being used to connect floating gate fet M71 and the necessary applied signal voltage of M72.
The 6th embodiment is the example of communicator of rectifier circuit that has adopted according to any of first to the 5th embodiment.Specifically, now the example of RFID label as communicator described.Figure 19 is the block diagram according to the RFID label of the 6th embodiment.Comprise a loop aerial 510 at the RFID label 500 shown in Figure 19, and according to the identical rectifier circuit 520 of any rectifier circuit of first to the 5th embodiment, a backflow preventer circuit 530, a signal processing circuit 540, a memory 550 with as the battery 560 of storage battery.Specifically, this RFID label 500 is by the supply voltage operation that provides from battery 560, and it needn't always produce the supply voltage that is used for its work from rectifier circuit 200.Specifically.Rectifier circuit 520, backflow preventer circuit 530, signal processing circuit 540 and memory 550 be connected with earth connection GL from battery 560 extended power line PL.
This loop aerial 510 induces alternating current according to the flux change that is produced by reader/writer (not shown in this Figure) in its antenna traces.This alternating current inputs to the signal input terminal of rectifier circuit 520.Rectifier circuit 520 is operated under the supply voltage that provides from battery 560.Therefore, the DC generator circuit of rectifier circuit 520 desired voltage is provided from the supply voltage that is provided by battery 560 and operates under this supply voltage.Specifically, always between the grid of the MOS transistor that constitutes diode circuit and source electrode, apply diode biasing, and no matter whether applied alternating current from loop aerial 510 to rectifier circuit 520.Can apply this diode biasing according to external trigger.Therefore, as described in first to the 5th embodiment, this rectifier circuit 520 can be with the weak alternating current that induce in loop aerial 510 less than the about root mean square numerical value rectification of 0.7V.In other words, can be with the weak demodulated data signal that receives by loop aerial 510.Send the demodulated data signal to signal processing circuit 540.The dc voltage that is obtained by rectifier circuit 520 offers battery 560 as the power supply that is used to charge by backflow preventer circuit 530.
Figure 20 is a curve chart, wherein demonstrates the rectification characteristic according to RFID label (solid line) and traditional RFID label (dotted line) of the 6th embodiment.Even the RFID label according to this embodiment receiving-also can produce the DC output voltage of 1.5V during the weak AC signal (AC input power) of 10dBm.This-signal of 10dBm is with approximately the distance of 10m is corresponding between RFID label and reader/writer.This DC output voltage by at the voltage limiter in this circuit as shown in this curve chart, under high AC input power, becoming stable.As can be seen from Figure 20, traditional RFID label only produces the dc voltage of 0.05V and this rectifier no longer as rectifier circuit.
According to the RFID label of the 6th embodiment as mentioned above, can identify the weak signal that traditional RFID label can not rectification by any rectifier circuit according to first to the 5th embodiment.This means that the required distance between RFID label and reader/writer of identification RFID label significantly enlarges.Therefore, this rfid system can have purposes widely.For example, reader/writer can almost identify simultaneously and be distributed in tens meters a large amount of RFID labels to the hundreds of rice scope.Therefore, attaching rfid tag makes it possible to manage the pasture animal and finds the child who loses and the elderly who wanders away.
And, owing to comprise battery according to the RFID label of this embodiment, so for example temperature sensor, loud speaker, microphone and light-emitting device are installed in the RFID label with various input/output devices easily.This RFID label has purposes widely.RFID label with transducer for example has in the structure shown in Figure 21.In the RFID label 600 shown in Figure 21, the parts that as shown in Figure 19 those are identical are represented by identical reference symbol.The power-supply system that is included in the input/output device 570 in the RFID label 600 be connected with earth connection GL from battery 560 extended power line PL.Signal processing circuit 540 sends and received signal with respect to input/output device 570.Example as being installed in the input/output device 570 in the RFID label will describe temperature sensor now.Temperature sensor is in the sleep and is not using energy during reader/writer (not shown in this Figure) sends out signal.Signal processing circuit 540 according to the signal that transmits by reader/writer when the RFID label with temperature sensor sends request, the actuation temperatures transducer sends temperature data to signal processing circuit 540 then with detected temperatures.This temperature data and the peculiar data of this RFID label send reader/writer to from the RFID label.As another operation of this temperature sensor, signal processing circuit 540 can send to temperature sensor so that this temperature data is stored in memory 550 with the request that the given time interval will be used for the output temperature data.And, signal processing circuit 540 when the request that receives from reader/writer with the temperature data stored with detection time data send reader/writer to.Can start this temperature sensor so that temperature data is stored in the memory 550 by for example vibration of trigger, sound and light.
Those of ordinary skills will readily understand other advantage and modification.Therefore, the present invention is not limited to detail shown here and described and representative embodiment on its broad aspect.Therefore, under situation about not breaking away from, make various modification by the spirit or scope of claims and the present general inventive concept that equivalent limited thereof.
Claims (22)
1. rectifier circuit, it comprises:
Be used for the biasing circuit of output dc voltage;
One first MOS transistor, it has a grid and one source pole, only applies described direct voltage between the grid of this first MOS transistor and source electrode;
One second MOS transistor, it has the drain electrode that a grid, one source pole are connected with source electrode with first MOS transistor, only applies described direct voltage between the grid of this second MOS transistor and source electrode; And
One coupling capacitor, it has the first end that is connected with the source electrode of described first MOS transistor and to the second end of its input exchange signal.
2. rectifier circuit as claimed in claim 1, wherein said first and second MOS transistor form has three well constructions on the semiconductor-based end.
3. rectifier circuit as claimed in claim 1, wherein said first MOS transistor has the back of the body grid that are connected with the source electrode of described first MOS transistor, and
Described second MOS transistor has the back of the body grid that are connected with the source electrode of described second MOS transistor.
4. rectifier circuit as claimed in claim 1 also comprises the smmothing capacitor between the source electrode of the drain electrode that is connected described first MOS transistor and described second MOS transistor.
5. rectifier circuit as claimed in claim 1, wherein said biasing circuit comprises:
First biasing circuit is used for applying direct voltage between the grid of described first MOS transistor and source electrode; And
Second biasing circuit is used for applying direct voltage between the grid of described second MOS transistor and source electrode.
6. rectifier circuit as claimed in claim 5 also comprises the DC voltage generator circuit that is used for producing with reference to direct voltage, wherein
Each of described first and second biasing circuits is according to reference direct voltage output dc voltage.
7. rectifier circuit as claimed in claim 6, wherein:
Described first and second MOS transistor and described DC voltage generator circuit are combined in the integrated circuit (IC) chip; And
The threshold level of described at least one with reference to direct voltage and described first and second MOS transistor equates.
8. rectifier circuit as claimed in claim 7, wherein said DC voltage generator circuit comprises:
The 3rd MOS transistor, it has interconnective drain electrode and source electrode; And
One constant-current source, it is connected with the drain electrode of described the 3rd MOS transistor.
9. rectifier circuit as claimed in claim 8, wherein said DC voltage generator circuit adopts at the drain electrode of described the 3rd MOS transistor and the voltage between the source electrode as the reference direct voltage, produces by the constant current that flows between the drain electrode of described the 3rd MOS transistor and source electrode at the voltage between drain electrode and the source electrode.
10. rectifier circuit as claimed in claim 8, wherein said the 3rd MOS transistor form the grid width with described first MOS transistor and the ratio of grid length.
11. rectifier circuit as claimed in claim 8, wherein
Described constant-current source provides constant current, and
Described DC voltage generator circuit comprises that one switches the unit, and it is connected between described constant-current source and described the 3rd MOS transistor, and exports with reference to direct voltage off and on by described switch unit.
12. rectifier circuit as claimed in claim 1, wherein said direct voltage is variable.
13. rectifier circuit as claimed in claim 1, wherein said biasing circuit comprises the capacitor that keeps described direct voltage.
14. rectifier circuit as claimed in claim 1, wherein said biasing circuit comprises:
First switch unit, it is connected with predetermined voltage source;
First capacitor, the voltage that provides by described first switch unit is being provided for it;
Second switch unit, it is connected with described first capacitor, the operation complementation of the operation of described second switch unit and described first switch unit; And
Second capacitor, it will remain direct voltage by the voltage that second switch unit provides.
15. a rectifier circuit, it comprises first rectifier circuit and second rectifier circuit, and each all has the structure identical with rectifier circuit as claimed in claim 1, wherein
The source electrode of second MOS transistor in the drain electrode of first MOS transistor in first rectifier circuit and second rectifier circuit is connected.
16. a rectifier circuit, it comprises:
One first floating boom transistor, it has first floating boom of an interconnective control gate and one source pole, a drain electrode and maintenance predetermined potential;
One second floating boom transistor, it has second floating boom of an interconnective control gate and one source pole, the drain electrode that is connected with the transistorized source electrode of first floating boom and maintenance predetermined potential; And
One coupling capacitor, it has the first end that is connected with the transistorized source electrode of first floating boom and to the second end of its input exchange signal.
17. rectifier circuit as claimed in claim 16, wherein:
Electromotive force at the described first floating boom place equates with the transistorized threshold level of described first floating boom; And
Electromotive force at the described second floating boom place equates with the transistorized threshold level of described second floating boom.
18. rectifier circuit as claimed in claim 16 also comprises:
One first direct voltage source, it is connected with the described first floating boom transistor drain;
One second direct voltage source, it is connected with the described second floating boom transistor drain;
One the 3rd direct voltage source, it is connected with the transistorized source electrode of described second floating boom; And
One control unit, it comes to carry out charge or discharge on each of first and second floating booms by each output voltage of controlling described first, second and the 3rd direct voltage source.
19. a radio communications set, it comprises:
One loop aerial;
One rectifier circuit, it comprises:
Be used for the biasing circuit of output dc voltage;
One first MOS transistor, it has a grid and one source pole, only applies described direct voltage between the grid of this first MOS transistor and source electrode;
One second MOS transistor, it has the drain electrode that a grid, one source pole are connected with source electrode with first MOS transistor, only applies described direct voltage between the grid of this second MOS transistor and source electrode; And
One coupling capacitor, it has the first end that is connected with the source electrode of described first MOS transistor and the second end of the AC signal responded to its input in loop aerial;
One memory, its storage tags identifying information; And
One signal processing circuit, it sends and receives described tag recognition information according to the direct current by described rectifier circuit rectification by described loop aerial.
20. radio communications set as claimed in claim 19 also comprises the battery that is charged by the direct current through described rectifier circuit rectification, wherein
Described rectifier circuit, memory and signal processing circuit are connected with described battery.
21. radio communications set as claimed in claim 20 also comprises a transducer, wherein:
Described signal processing circuit is by the signal of described loop aerial transmission by described sensor.
22. radio communications set as claimed in claim 20 also comprises an input/output device, wherein:
Described signal processing circuit is according to the described input/output device of signal enabling that receives by described loop aerial.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004180164 | 2004-06-17 | ||
| JP2004180164 | 2004-06-17 | ||
| JP2005152990 | 2005-05-25 |
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| CN1722595A CN1722595A (en) | 2006-01-18 |
| CN100466443C true CN100466443C (en) | 2009-03-04 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005100781628A Expired - Fee Related CN100466443C (en) | 2004-06-17 | 2005-06-17 | Rectifier circuit and radio communication device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4257377B2 (en) | 2006-10-27 | 2009-04-22 | 株式会社東芝 | Trigger signal generator |
| US7889528B2 (en) * | 2006-11-29 | 2011-02-15 | Semiconductor Energy Laroratory Co., Ltd. | Rectifier circuit, power supply circuit, and semiconductor device |
| JP4377946B1 (en) * | 2008-06-10 | 2009-12-02 | 株式会社東芝 | Demodulator |
| CN102165579B (en) * | 2008-09-29 | 2014-03-12 | 株式会社半导体能源研究所 | Semiconductor device |
| EP2555422A1 (en) | 2010-03-31 | 2013-02-06 | Kabushiki Kaisha Toshiba | Receiver device and remote control system |
| WO2016123755A1 (en) * | 2015-02-04 | 2016-08-11 | 中国科学院微电子研究所 | Cmos rectification diode circuit unit |
| CN105991002B (en) * | 2015-02-04 | 2018-10-09 | 中国科学院微电子研究所 | CMOS rectifier diode circuit units |
| CN113659856B (en) * | 2021-10-19 | 2022-05-10 | 成都凯路威电子有限公司 | UHF-RFID differential rectification circuit module and differential rectification circuit |
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|---|---|---|---|---|
| US4455628A (en) * | 1981-12-17 | 1984-06-19 | Mitsubishi Denki Kabushiki Kaisha | Substrate bias generating circuit |
| US5173849A (en) * | 1987-09-19 | 1992-12-22 | Magellan Corporation (Australia) Pty. Ltd. | Integratable synchronous rectifier |
| US20020118557A1 (en) * | 2001-02-16 | 2002-08-29 | Zarlink Semiconductor Ab | MOS circuit for lowering forward voltage of diodes |
| CN2524424Y (en) * | 2001-09-14 | 2002-12-04 | 清华大学 | Half wave rectifying circuit |
| US20030021158A1 (en) * | 2000-04-05 | 2003-01-30 | Bertrand Gomez | Load modulation device in a remotely powered integration circut |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4455628A (en) * | 1981-12-17 | 1984-06-19 | Mitsubishi Denki Kabushiki Kaisha | Substrate bias generating circuit |
| US5173849A (en) * | 1987-09-19 | 1992-12-22 | Magellan Corporation (Australia) Pty. Ltd. | Integratable synchronous rectifier |
| US20030021158A1 (en) * | 2000-04-05 | 2003-01-30 | Bertrand Gomez | Load modulation device in a remotely powered integration circut |
| US20020118557A1 (en) * | 2001-02-16 | 2002-08-29 | Zarlink Semiconductor Ab | MOS circuit for lowering forward voltage of diodes |
| CN2524424Y (en) * | 2001-09-14 | 2002-12-04 | 清华大学 | Half wave rectifying circuit |
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