CN100464394C - Manufacture of semiconductor device with cmp - Google Patents
Manufacture of semiconductor device with cmp Download PDFInfo
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- CN100464394C CN100464394C CNB2005101250664A CN200510125066A CN100464394C CN 100464394 C CN100464394 C CN 100464394C CN B2005101250664 A CNB2005101250664 A CN B2005101250664A CN 200510125066 A CN200510125066 A CN 200510125066A CN 100464394 C CN100464394 C CN 100464394C
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Abstract
A manufacture method for a semiconductor device, includes the steps: in CMP for forming STI, polishing the surface of a film formed on a semiconductor substrate until the surface of the film is planarized, by using first abrasive containing cerium dioxide abrasive grains and additive of interfacial active agent; polishing the surface of the film is polished by using second abrasive having a physical polishing function; polishing the surface of the film by using third abrasive containing cerium dioxide abrasive grains, additive of interfacial active agent, and diluent. The manufacture method further includes the steps: forming wirings above the semiconductor substrate; depositing a first insulating film by HDP CVD, the first insulating film burying the wirings; depositing a second insulating film above the first insulating film by a deposition method different from HDP-CVD; and planarizing the second insulating film by chemical mechanical polishing using abrasive containing cerium dioxide abrasive grains. It is possible to solve an issue of a left film after polishing newly found from a large size substrate and to suppress a distribution of thicknesses of an interlayer insulating film at a wafer level.
Description
The cross reference of related application
The application based on and require the Japanese patent application No.2005-202060 of on July 11st, 2005 application and 202061 priority, at this by with reference to quoting its full content.
Technical field
The present invention relates to a kind of manufacture method of semiconductor device and the semiconductor device of making by this method, particularly a kind of comprising can be with the manufacture method of the semiconductor device of chemico-mechanical polishing (CMP) technology of deposited film planarization and the semiconductor device of making by this method.
Background technology
Local oxidation of silicon (LOCOS) technology is widely used as forming the technology of the isolated area that is limited with the source region, wherein by utilize the silicon nitride mask that forms, selective oxidation silicon substrate on the buffer oxide film on the silicon substrate.When forming the isolated area of silica by LOCOS, silicon substrate is also oxidized below the peripheral edge of silicon nitride mask, therefore forms " beak " shape zone, and the area of active area is reduced.The silica isolated area is swelled from surface of silicon, and forms big step.Thereby LOCOS is difficult to make the further microminiaturization of semiconductor device and reaches higher integrated level.
Shallow-trench isolation (STI) technology is used as the substitute technology of LOCOS technology.
In forming STI, the thermal oxidation silicon substrate surface is to form the buffer oxide silicon fiml, and silicon nitride film on the buffer oxide silicon fiml is passed the opening of silicon nitride film formation corresponding to STI by photoetching and etching, and form groove in silicon substrate.Silicon nitride film is as the layer that stops of etching mask and CMP.
Exposed silicon surface to be forming silicon oxide film lining (liner) in the thermal oxidation groove, and silicon nitride film is to form the silicon nitride film lining.Then, in groove, imbed dielectric film, for example unadulterated silicate glass (USG) film.For usg film being imbedded in the small groove, use high-density plasma (HDP) chemical vapor deposition (CVD).By the usg film of CMP removal in the groove outside deposition.After CMP, by the silicon nitride film of etch exposed such as hot phosphoric acid, and by etch buffer silicon oxide films such as dilute hydrofluoric acid.
In CMP, use the additive comprise the abrasive particle (abrasive grain) for example made, to make by KOH and the grinding agent of water by silica.Require grinding agent polishing speed to be provided faster and to provide slow as far as possible polishing speed (silicon nitride stops thing as polishing), and require grinding agent can make the polished surface planarization largely with respect to silicon nitride with respect to silica.The grinding agent of the additive that comprises the abrasive particle made by silica and made by KOH provides not too fast polishing velocity with respect to silica, even and exposing the polishing speed that silicon nitride still shows about 300 nm/minute after stopping layer.Although make the polished surface planarization to a certain extent, but still can stay some steps.Therefore, be to have faster polishing speed, high selectivity and after polishing, have good planarized surface to the requirement of required grinding agent with respect to silicon dioxide.
The grinding agent that meets these requirements is suggested, and it comprises by ceria (CeO
2)) abrasive particle made and the additive made by the polyacrylic acid ester ammonium salt etc.The grinding agent that mixes ceria and water has too fast polishing speed and lower step mitigation (relaxing) function.Owing to added the polyacrylic acid ester ammonium salt, therefore polishing speed can be controlled to be and have appropriate value and suppress the polishing in the recessed district and improve the planarization function, thereby when making the polished surface planarization, realize automatic hold function.The grinding agent that comprises ceria and additive has the premium properties that can make the irregular surface planarization.
For the chemico-mechanical polishing of using ceria, for example, please refer to JP-A-2001-009702, the JP-A-2001-085373 and the JP-A-2000-248263 that quote by reference herein.Be called main polishing until the polishing of removing irregular surface.In addition, also propose to detect the temperature of polished surface and the technology of torque among the JP-A-HEI-11-104955, detect the technology of polishing end point during as the irregular surface of removing polished surface.
The CMP polishing system is equipped with the rotatable polishing block with polished surface, rotatable rubbing head and a plurality of nozzle that is used to provide additive and water that is used to keep substrate.At rotary finishing head and polishing block and when grinding agent is provided, exert pressure so that rubbing head is pressed to polishing block, polish thereby carry out.For the common practise of CMP polishing system, for example, please refer to the JP-A-2001-338902 and the JP-A-2002-083787 that quote by reference herein.
People also propose CMP to be divided into two stages and to carry out the method for two stages of CMP with the acquisition high flat degree under different conditions.For example, when additive is provided, use first polishing pad to carry out main polishing, then, stop to provide additive, and when water is provided, use second polishing pad harder to carry out finishing polish (finish polishing), thereby prevent pit (dishing) than first polishing pad.For example, please refer to JP-A-2004-296591.
CMP is used to form STI and other structure.Except that STI, in dielectric film, form the recessed portion that arrives lower floor's conductor, for example hole and groove form the conducting film of imbedding recessed portion, and the unnecessary conducting film on the removal substrate surface is to form connector and to embed wiring.Use CMP to remove unnecessary conducting film.Form the wiring comprise gate electrode etc. on dielectric film, deposition covers another dielectric film of wiring, and with the flattening surface of another dielectric film.Use CMP with this flattening surface.By with flattening surface, can improve the precision of photoetching process of (depth of focus) that only has shallow depth of focus and the uniformity of etch process.
In the gate electrode of MOS transistor forms, on the surfaces of active regions of silicon substrate, form silicon oxide film, form gate insulating film by nitrating as required.On gate insulating film, the deposit spathic silicon film also is patterned into the gate electrode shape.After the ion that execution is used to form the extension area of source/drain regions injects, form sidewall spacers (spacer), the ion of carrying out the high impurity concentration district that is used to form source/drain regions then injects.If necessary, after carrying out silicification technics, sedimentary phosphor silicate glass (PSG) film, it is phosphorous silicon oxide film, to form the interlayer dielectric of covering grid electrode.
The interlayer dielectric of covering grid electrode has irregular surface.In order to remove irregular surface, by CMP with the interlayer dielectric planarization.The interlayer dielectric of deposition has the critical thickness (marginal thickness) by the CMP polishing.After planarization, form the contact hole of source/drain regions etc. by etching, and the conductive plug of polysilicon, tungsten etc. is imbedded in the contact hole.By the unnecessary conducting film on the CMP removal interlayer dielectric.
The integrated level development that the semiconductor device forward is further microminiaturized and higher.The grid length of MOS transistor foreshortens to 65 nanometers from 90 nanometers.The bottom wiring layer of integrated circuit (IC)-components is the grid wiring layer.Along with the development of microminiaturization, the distance between the grid wiring becomes narrower, and wiring becomes close.After forming grid wiring, the deposition psg film is to form the interlayer dielectric of buried gate wiring.Usually, by on electrode of opposite, applying RF power, utilize plasma to strengthen (PE) CVD deposition psg film.But,, bury performance and become not enough along with the distance between the grid shortens.When psg film being imbedded in the gap narrow between the grid, in psg film, can form space (void) in some cases.In order to utilize psg film to fill narrow gap, use high-density plasma (HDP) CVD to substitute PE-CVD, this high-density plasma CVD is applied to inductive coupler coils with RF power.
Summary of the invention
The objective of the invention is to solve big substrate and newfound problem afterwards occurs.
Another object of the present invention provides a kind of manufacture method that comprises the semiconductor device of glossing, and it has excellent characteristic aspect planarization of polished surface.
Another object of the present invention provides a kind of method, semi-conductor device manufacturing method, and it has excellent characteristic aspect wafer scale thickness evenness of interlayer dielectric.
Another object of the present invention provides a kind of manufacture method that comprises the semiconductor device of efficient CMP technology.
Another object of the present invention provides a kind of semiconductor device with new structure.
According to a kind of scheme of the present invention, a kind of manufacture method of semiconductor device is provided, comprise the steps: that (a) providing first grinding agent in the polishing block that is provided with polishing pad, utilize this polishing pad, and by the rubbing head support semiconductor substrates, the surface of the film that polishing forms on this Semiconductor substrate, until the flattening surface with this film, this first grinding agent comprises the additive of ceria abrasive particles and interfacial agent; (b) afterwards, use second grinding agent comprise silica or zirconia and to have physics polishing function, the surface of polishing this film in this step (a); And (c) afterwards, use to comprise the additive of ceria abrasive particles, interfacial agent and the 3rd grinding agent of diluent, the surface of polishing this film in this step (b).
According to another program of the present invention, a kind of manufacture method of semiconductor device is provided, comprise the steps: that (a) forms wiring on Semiconductor substrate; (b) afterwards, deposit first dielectric film by high-density plasma (HDP) chemical vapor deposition (CVD), this first dielectric film is buried described wiring in this step (a); (c) afterwards, by being different from the deposition process of HDP-CVD, deposition second dielectric film on this first dielectric film in this step (b); And (d) in this step (c) afterwards, the grinding agent that comprises ceria abrasive particles by use carries out chemico-mechanical polishing with this second dielectric film planarization.
According to another program of the present invention, a kind of semiconductor device is provided, comprising: silicon substrate; Shallow groove isolation structure (STI), the unadulterated silicate glass film that it is formed in this silicon substrate and comprises the groove that is limited with the source region and imbed this groove; Gate insulating film, it is formed on this active area; Gate electrode, it is formed on this gate insulating film; Following dielectric film, it is made by phosphosilicate glass (PSG) or boron phosphorus silicate glass (BPSG), has uneven surface, is formed on this silicon substrate and covers this gate electrode; And upper nonconductive Film, it is made by tetraethoxysilane (TEOS) silica, is formed on this time dielectric film and has the surface of planarization.
After the CMP that uses first grinding agent, by the surface of the film on the physics glossing polished silicon substrate, to remove the residue of first grinding agent.Then, carry out another chemico-mechanical polishing to obtain the surface of high planarization in whole semiconductor surface zone.
When by HDP-CVD deposition interlayer dielectric, the thickness of interlayer dielectric there are differences.But the combination of HDP-CVD and another deposition process can form the uniform interlayer dielectric of thickness.
Description of drawings
Figure 1A is the vertical view of polishing system, and Figure 1B is the partial cross section end view of a polishing block, and Fig. 1 C is the vertical view of a polishing block, and Fig. 1 D is the partial cross section end view of lapping device (grinder unit).
Fig. 2 A to 2D is the schematic cross section that is illustrated in the state that is used for the film that glossing that Primary Study carries out polishes, and Fig. 2 E is the vertical view of the wafer that has residual oxide-film behind glossing.
Fig. 3 A to 3E is the cross-sectional view that illustrates according to the semiconductor wafer of the glossing of an embodiment.
Fig. 4 illustrates the chart that torque changes in the glossing process.
Fig. 5 A and 5B are the vertical view and the cross-sectional view of semiconductor device.
Fig. 6 A is the cross-sectional view that the structures of samples of preliminary experiment employing is shown, and Fig. 6 B is illustrated in the chart that substrate S UB goes up the thickness distribution of three kinds of silicon oxide film OX that deposit.
Fig. 7 A is the chart that the polishing speed of the three kinds of silicon oxide films of ceria sizing agent (slurry) polishing that use identical type is shown, and Fig. 7 B is the chart that the polishing speed of the ceria sizing agent polishing HDP-PSG film that uses the polyacrylic acid ester ammonium salt that comprises variable concentrations is shown.
Fig. 8 A to 8C is the cross-sectional view that illustrates according to the semiconductor wafer of the manufacture method of the semiconductor device of another embodiment.
Fig. 9 A is the chart that the thickness distribution of interlayer dielectric is shown, and Fig. 9 B illustrates with respect to the chart of following interlayer insulator film thickness with the variation of the ratio thickness deviation of wiring height.
Figure 10 A is the cross-sectional view of semiconductor wafer that two steps of glossing are shown, and Figure 10 B is the vertical view that the polishing system of polishing designs of nozzles is shown.
Figure 10 C is the chart that first and second steps cut number afterwards is shown, and Figure 10 D is the chart that polishing film thickness distribution afterwards is shown.
Figure 11 A and 11B are the cross-sectional view of semiconductor wafer of two kinds of modifications of embodiment.
Figure 12 A and 12B are the cross-sectional view that illustrates according to the semiconductor wafer of the DRAM manufacture method of another embodiment.
Embodiment
The grinding agent of the additive that comprises ceria abrasive particles and made by interfacial agent provides high polishing speed with respect to silica, and provides stop the automatic hold function to polish automatically when polished surface becomes flat surfaces.If add water to grinding agent to increase water constituent with respect to abrasive particle and additive, then automatic hold function is suppressed, and with respect to the polishing speed recovery of the silica with flat surfaces, and maintenance is with respect to the polishing selectivity of silicon nitride film.
Therefore, can think, by at first using grinding agent with first composition, the additive that wherein comprises ceria abrasive particles and make by interfacial agent, with polished film planarization, use this film of the abrasive polishing with second composition that adds water to grinding agent acquisition by adding then, can expose the surface of lower membrane with good state with first composition.
With reference to Figure 1A to 1D, the example of the structure of the polishing system that illustrative experiment is adopted.Figure 1A is the vertical view of polishing system, and Figure 1B is the partial cross section end view of a polishing block, and Fig. 1 C is the vertical view of a polishing block, and the partial cross section end view of Fig. 1 D lapping device of being.
Shown in Figure 1A, three polishing block 102a, 102b and 102c are installed on the pedestal 100 of polishing system.In order to distinguish a plurality of similar parts, use suffix a, b, c, d etc.If refer to that similar parts are all, then omit suffix a, b etc.Rotary conveyer (carrousel) 110 with four arm 108a to 108d is installed on the pedestal 100.The end of each arm 108 is connected to the rubbing head 112 that is used to support polished object.Three rubbing heads are set with the while polishing object on polishing block.Utilize remaining rubbing head to change polished object.Polishing block 102, rotary conveyer 110 and rubbing head 112 are all rotatable.Each polishing block 102 is provided with lapping device 114.
Shown in Figure 1B and 1C, polishing pad 104 is installed on each polishing block 102.For example, use the polishing pad of the model of Nitta Haas company production as IC1400.Can under the situation of not using polishing pad, polish.Rubbing head 112 can support polished object, and for example semiconductor wafer 10, and is pressed to polishing block 102.Nozzle 124a, 124b and 124c provide abrasive particle, diluent etc. to polishing block.For example, three nozzle 124a, 124b and 124c the ceria that comprises as abrasive particle is provided, as the grinding agent of the pure water of diluent or cleaning agent and comprise grinding agent as the silica of abrasive particle.Conventional method is not used nozzle 124c.
When rotary finishing platform 102 and rubbing head 112, rubbing head 112 is pressed to polishing block 102, and ceria based grinding agent is provided to polishing block, thereby the polished object that is supported by rubbing head is carried out main polishing from nozzle 124a.After main polishing, provide ceria based grinding agent and water to carry out at inhomogeneity finishing polish.When carrying out a plurality of glossing, can on same polishing block or different polishing block, carry out each technology.
Shown in Fig. 1 D, lapping device 114 can grind the polishing pad 104 of each polishing block 102.Lapping device 114 has the diamond disk 116 of the rotating shaft that is connected to this device.For example utilize nickel coating 122 that diamond particles 120 is fixed to stainless steel disc 118 and formation diamond disk 116, wherein the particle diameter of diamond particles is about several particles on 150 microns and every square centimeter.When polishing block 102 rotations, diamond disk 116 rotations are also pressed to polishing pad to grind this polishing pad.Can carry out before polishing or in the polishing process and grind.
By using the polishing system shown in Figure 1A to 1D, utilize the abrasive polishing that comprises ceria to be used to bury the silicon oxide film of shallow-trench isolation (STI) structure.
Fig. 2 A illustrates the polishing schematic cross section of the state of film before.Polished silicon oxide film 220 has irregular surface.The additive of being made by interfacial agent 224 adheres to (attach) to the film surface.Polishing pad 104 is pressed to film 220 and it is rotated with respect to film.Apply the convex region of high pressure from polishing pad 104, to remove additive 224 to film 220.
Shown in Fig. 2 B, use polishing abrasive particle 226 polishing convex regions.Because additive 224 is attached to surface, recessed district, polishes in recessed district thereby stop.The convex region of selectivity polished film 220 by this way.
Shown in Fig. 2 C, along with the flattening surface of film 220, the additive of being made by interfacial agent 224 is attached to the whole surface of film 220, thereby polishing speed is significantly reduced.At this moment, stop to provide grinding agent, and pure water is provided.
Shown in Fig. 2 D, can expect, because additive 226 has water-soluble thereby can be at short notice with its removal, and because polishing abrasive particle 224 is water insoluble thereby be difficult to its removal.Therefore, use the polishing abrasive particle that between polishing pad 104 and film 220, stays, further polished film 220.But through considering to think in the above described manner uniform polish and remove film.
But shown in Fig. 2 E, the silicon oxide film 220 on the wafer 10 is not removed fully in some cases, and remains in the center of wafer.Diameter at wafer is extended to from 200 nanometers under the situation of 300 nanometers, and the residual silicon oxide film in center wafer district can become obvious especially.
The inventor considers owing to the additive that is attached to wafer surface can not be removed fully and causes silicon oxide film to be easy to remain in the center wafer district.Think through consideration,, should guarantee physics polished wafer surface in order evenly to remove the grinding agent that is attached to wafer surface.Use contains as the silica of polishing abrasive particle or zirconic grinding agent can carry out the physics polishing.Below embodiments of the invention will be described.
As shown in Figure 3A, the surface of thermal oxidation silicon wafer semiconductor substrate 10 is to form the silicon oxide film 12 that thickness is about 10 nanometers.By chemical vapor deposition (CVD), deposit thickness is about the silicon nitride film 13 of 100 nanometers on silicon oxide film 12.Pass this silicon nitride film 13 and silicon oxide film 12 formation openings 14 by photoetching and etching, this opening exposes the surface of Semiconductor substrate 10.Can remove the corrosion-resisting pattern that forms by photoetching in this stage.At least utilize silicon nitride film 13 as mask, by active-ion-etch (RIE) anisotropic etching Semiconductor substrate 10, to form the groove 15 that the degree of depth of measuring from silicon nitride film 13 surfaces for example is about 300 nanometers with opening.Preferred etch substrate under the condition of the sidewall slope that makes groove.
Shown in Fig. 3 B, thermal oxidation is exposed silicon surface on flute surfaces, for example is the silicon oxide film (lining) 17 of about 1 to 5 nanometer to form thickness.By low pressure (LP) CVD deposit thickness for example is the silicon nitride film (lining) 18 of about 2 to 8 nanometers, the surface of these silicon nitride film 18 capping oxidation silicon fimls 17 and silicon nitride film 13.Thickness is that the silicon oxide film of about 1 to 5 nanometer makes that dilute hydrofluoric acid is difficult to invade, and thickness to be the silicon nitride film of about 2 to 8 nanometers make that hot phosphoric acid is difficult to invade.For example be the silicon oxide film 20 of about 450 nanometers by high-density plasma (HDP) CVD deposit thickness on Semiconductor substrate with silicon nitride film 18.Use silicon oxide film 20 filling grooves 15.Silicon oxide film 20 at the level height place higher than silicon nitride film 13 (and silicon nitride film 18) surface is polished film.
Shown in Fig. 3 C, carry out main polishing until removing the irregular of surface, so that the flattening surface of film 20.For example, carry out this master's polishing under the following conditions:
Rubbing head is pressed to the pressure of polishing pad: 100-500 grammes per square metre/square centimeter, 210 grammes per square metre/square centimeters for example,
The rotating speed of rubbing head: 70-150rpm, 142rpm for example,
The rotating speed of polishing block: 70-150rpm, 140rpm for example,
Grinding agent: comprise as the ceria abrasive particles of polishing abrasive particle and (for example as the grinding agent of the polyacrylic acid ester ammonium salt of the additive in the pure water, the model that dupont air products nanomaterials company (Dupont AirProducts NanoMaterials L.L.C.) produces is the grinding agent of MICROPLANAR STI2100)
The amount of providing of grinding agent: the 0.1-0.3 liter/minute, for example 0.15 liter/minute, and
Grinding agent the position is provided: the center of polishing block (polishing pad).
Fig. 4 is the chart that the variation of the torque that puts on polishing block or rubbing head in the polishing process is shown.Usually begin to apply about 80 seconds constant torque from polishing, torque reduces once then, sharply increases also saturated.Continue (last) that detect torque increases, and the time when being reduced to the increment rate of torque greater than certain definite value is defined as polishing end point.When rubbing head and polishing block rotate with constant rotational speed, can be by measuring driving voltage or drive current monitoring torque.Can detect main polishing end point by other method.For example, can monitor torque self.If necessary, can be before main polishing or in the main polishing process grinding and polishing pad.
Grinding and polishing pad under the following conditions:
Be applied to the load of polishing pad 104 from diamond disk 116: 1300 to 4600 grammes per square metres, and
The rotating speed of diamond disk 116: 70-120rpm.
After finishing main polishing and flattening surface, provide pure water to rinse out grinding agent from nozzle 124b with silicon oxide film 20.Only the additive that is attached to semiconductor substrate surface might can not be removed by pure water.
Then, carry out the pre-polish(ing) of finishing polish.By providing the center of the grinding agent of silica-based, carry out the pre-polish(ing) of finishing polish to polishing pad from for example nozzle 124c.The grinding agent of silica-based can be the grinding agent of Semi-Sperse25 for the model of being produced by Cabot Microelectronics Corporpation (Cabot Microelectronic Corporation).When rubbing head 112 rotations, Semiconductor substrate is pressed towards the polishing pad 104 of rotary finishing platform 102.For example, carry out the pre-polish(ing) of finishing polish under the following conditions:
Polishing pressure: 100 to 500 grammes per square metre/square centimeters, 210 grammes per square metre/square centimeters for example,
The rotating speed of rubbing head: 70-150rpm, 122rpm for example,
The rotating speed of polishing block: 70-150rpm, 120rpm for example,
The amount of providing of grinding agent: the 0.05-0.3 liter/minute, for example 0.1 liter/minute, and
Polished amount (time): 10 nanometers or thinner thickness, for example 5 seconds.
By remove film more shallowly, the additive that may be attached to this film is removed in the pre-polish(ing) of finishing polish.Preferably, do not expose silicon nitride film 18 and 13.
After the pre-polish(ing) of finishing finishing polish, for example provide about 10 seconds pure water to rinse out the grinding agent of silica-based from nozzle 124b.If stay the grinding agent of silica-based, then the selectivity of finishing polish will reduce.
Then, shown in Fig. 3 D, by providing ceria based grinding agent, and provide pure water, carry out the main polishing of finishing polish from nozzle 124b from nozzle 124a.For example, provide center with ceria based grinding agent, and pure water is provided to the zone of outside, center to polishing pad.Provide the position to be not limited to these zones.Rubbing head and polishing pad all rotate.
For example, carry out the main polishing of finishing polish under the following conditions:
Polishing pressure: 100 to 500 grammes per square metre/square centimeters, 210 grammes per square metre/square centimeters for example,
The rotating speed of rubbing head: 70-150rpm, 122rpm for example,
The rotating speed of polishing block: 70-150rpm, 120rpm for example,
The amount of providing of grinding agent: the 0.05-0.3 liter/minute, for example 0.05 liter/minute,
The amount of providing of pure water: the 0.05-0.3 liter/minute, for example 0.15 liter/minute, and
Polished amount (time): until exposing silicon nitride film, for example about 60 seconds.
The condition of the main polishing of finishing polish is not limited to above-mentioned condition.If can remove the silicon oxide film on the silicon nitride film 13 (silicon nitride film 18) and expose silicon nitride film, can use other condition.Can remove or keep thin silicon nitride film 18.
Shown in Fig. 3 E, use for example hot phosphoric acid etch silicon nitride film 13 (18), and use for example dilute hydrofluoric acid etching oxidation silicon fiml 12.Preferably, silicon oxide film 20 and silicon oxide film 17 between the Semiconductor substrate 10 and the silicon nitride film 18 imbedded of not etching.Because etchant is difficult to invade, and therefore can suppress etching by above-mentioned thickness.
As mentioned above, before the main polishing of finishing polish, carry out the pre-polish(ing) of finishing polish by the physics polishing.Therefore, even additive is attached to wafer surface, also can guarantee to remove additive.Even have larger-diameter wafer, also can remove its whole lip-deep silicon oxide film.
Then, in the active area that limits by STI, form semiconductor device, for example the CMOS transistor.
Fig. 5 A and Fig. 5 B illustrate the transistorized topology example of CMOS.
Fig. 5 A is the vertical view that the shape of active area AR that is limited by element isolation zone 20 and the gate electrode 32 that forms on silicon substrate is shown.STI forms element isolation zone 20 and is limited with the source region.Among Fig. 5 A, in two active area AR, form the CMOS inverter.Fig. 5 A illustrates and forms sidewall spacers state before.
The cross-sectional view of Fig. 5 B for being got along the line VB-VB shown in Fig. 5 A.The inner surface of silicon oxide film lining 17 and silicon nitride film lining 18 covering grooves, and silicon oxide film 20 is embedded in the groove.Carry out polishing for the unnecessary zone of removing silicon oxide film 20, comprising the pre-polish(ing) of above-mentioned main polishing, finishing polish and the main polishing of finishing polish.The gate insulating film 31 of silicon oxynitride of (traversing) p type active area and the gate electrode 32 of polysilicon are crossed in formation, and with n type foreign ion with in the substrate of low concentration injection grid electrode both sides to form the LDD district.On the sidewall of gate electrode, form sidewall spacers SW, and n type foreign ion is injected substrate to form the source/drain regions S/D of high impurity concentration with high concentration.Another active area AR is the n type, and is injected into p type foreign ion.For example, after ion injected, deposition Co film was also carried out silicification technics to form silicide film 33 on silicon face.Form the CMOS transistor by this way.Then, form interlayer dielectric and wiring, finish semiconductor device.
Owing to from entire wafer surface removal dielectric film, rather than partly stay dielectric film, therefore can on the entire wafer surface, form semiconductor chip with good productive rate.
Find that after deliberation a new problem arose in following technology.After in silicon substrate, forming groove, by HDP-CVD deposition usg film, utilization contains the grinding agent of ceria abrasive particles and removes the unnecessary zone of usg film by CMP to form sti structure, after forming gate electrode, deposit psg film, and utilization contains the grinding agent of ceria abrasive particles with the psg film planarization by HDP-CVD.
Below the experiment that the present invention is done for this problem of research will be described.
As shown in Figure 6A, by on silicon substrate SUB, forming silicon oxide film OX, form wafer W AF.Form the sample of three kinds of silicon oxide film OX, comprise sample by HDP-CVD deposition usg film HDP-USG, the sample by HDP-CVD deposition psg film HDP-PSG and utilize tetraethoxysilane (TEOS) as the silicon source by the sample of PE-CVD deposition as the TEOS oxide-film PE-TEOS of interlayer dielectric etc.
Fig. 6 B is the chart that the measurement result of three kinds of silicon oxide film sample thickness distributions is shown.Film thickness distribution with sample P E-TEOS of the TEOS oxide-film that forms by PE-CVD has the numerical value of about 580 nanometers usually in the entire wafer zone, and has high uniformity.Having the wafer scale that the film thickness distribution of two sample HDP-USG of the silicon oxide film that forms by HDP-CVD and HDP-PSG has much at one changes.Thickness is about 570 nanometers in the center wafer district, and thickness increases gradually in the zone of outside, center, reaches the maximum of about 592 nanometers, is becoming 585 nanometers or thinner near wafer edge region then, shows alphabetical M shape usually and distributes.
This alphabetical M shape is distributed in wafer scale and on a large scale and gently changes, and localized variation not.Can expect, although local thickness can be changed planarization by CMP, can not be by CMP with the mild varied in thickness planarization in the big zone.
The chip that forms in the center wafer district has dielectric film between thin layer, and the chip that forms in wafer edge region has dielectric film between thick-layer.When passing interlayer dielectric by etching and form contact hole, dielectric film forms contact hole between thick-layer in the marginal zone owing to also pass, and therefore crossing etching in thin center increases.The chip that forms in the center has short conductive plug and the lower contact resistance of imbedding contact hole, and the chip in the marginal zone has long conductive plug and higher contact resistance.For improving technology and reliability of products, need suppress the varied in thickness of wafer scale as much as possible.Next, by having the CMP system of structure shown in Figure 1A to 1D, and use the slurry that comprises ceria abrasive particles and interfacial agent, polish three kinds of samples.
Fig. 7 A illustrates and uses identical slurry three kinds of samples to be carried out the polishing speed of 1 minute CMP.Ordinate is represented polishing speed, and unit is a nm/minute.By measure before the polishing and thickness after the polishing and with the thickness reduction divided by polishing time, calculate polishing speed.Polishing condition is as follows:
The pressure of rubbing head: 200 grammes per square metre/square centimeters,
The rotating speed of rubbing head: 100rpm,
The rotating speed of polishing block: 100rpm, and
The amount of providing of ceria sizing agent: 0.2 liter/minute.
The groove-shaped model of the K that uses Nitta Haas company to produce is the polishing pad of IC1400, and uses the ceria sizing agent of the model of dupont air products nanomaterials company production as MICROPLANAR STI2100 RA9.The film thickness measuring device A SET-F5x that utilizes KLA-Tencor company to produce measures thickness.
The polishing speed of HDP-USG film and PE-TEOS film is all lower, is respectively 12 nm/minute and 14 nm/minute, and polishing all is difficult to carry out.This is to use the feature of the ceria sizing agent polishing planar film that contains the polyacrylic acid ester ammonium salt.Be appreciated that and realize automatic hold function.The average polished speed of HDP-PSG film is 210 nm/minute, compares quite high with 12 nm/minute and 14 nm/minute.Be appreciated that and realize automatic hold function.
Fig. 7 B illustrates the chart of the polishing speed of HDP-PSG film when the amount of the polyacrylic acid ester ammonium salt that comprises in the change ceria sizing agent.The low concentration in left side is identical with Fig. 7 A, and increases about 10 times of high concentrations of setting the right side by the amount with the polyacrylic acid ester ammonium salt.Because the amount of polyacrylic acid ester ammonium salt increases about 10 times, therefore also can realize automatic hold function for the HDP-PSG film.
Can understand from the result of Fig. 7 A and 7B,, then need greatly to change the amount of polyacrylic acid ester ammonium salt if use the ceria sizing agent that contains the polyacrylic acid ester ammonium salt that HDP-USG film and HDP-PSG film are carried out CMP.If the STI of buried oxidation film is made by the HDP-USG film, and the interlayer dielectric of burying gate electrode made by the HDP-PSG film, then needs to carry out different CMP.If a polishing system is used for a kind of CMP, then need to use two kinds of polishing systems to carry out two kinds of CMP.
The polishing speed of PE-TEOS film and HDP-USG film are identical.If will carry out CMP, then can use the ceria sizing agent of same type to carry out CMP under the same conditions to HDP-USG film and PE-TEOS film.But, the PE-TEOS film to bury performance lower, and can not be as the interlayer dielectric of burying gate electrode.
The inventor considers the interlayer dielectric of burying gate electrode is made by the lamination of HDP-PSG film and PE-TEOS film.Use HDP-PSG to bury gate electrode, and be stacked in the PE-TEOS film on this DP-PSG film and polish.
Fig. 8 A to 8C is the partial cross sectional view that illustrates according to the semiconductor wafer of the method, semi-conductor device manufacturing method of another embodiment of the present invention.
Fig. 8 A illustrates the state of Fig. 3 E.Form STI20 by being similar to the technology shown in Fig. 3 A to 3E in silicon substrate 10, STI is limited with the source region.
Shown in Fig. 8 B, be formed with on the silicon substrate of STI, form Etching mask, and foreign ion is injected substrate with the n type trap NW of formation p channel transistor and the p type trap PW of n channel transistor.Then, the surface of the active area that thermal oxidation is limited by STI to be forming silicon oxide film, and carries out nitrogen and handle to introduce nitrogen and to form silicon oxynitride film.On this silicon oxynitride film, be the 100-200 nanometer by the hot CVD deposit thickness, the polysilicon film of 180 nanometers for example, and utilize the resist pattern with its patterning.Form the gate electrode of insulation thus.
By p type foreign ion being injected p channel transistor district and n type foreign ion is injected n channel transistor district, form shallow extension area with low acceleration energy and low concentration.After forming the sidewall spacers SW of silica etc.,, form low-resistance source/drain regions S/D by with high concentration p type foreign ion being injected p channel transistor district and n type foreign ion being injected n channel transistor district
pAnd S/D
nTherefore form the CMOS structure.
By HDP-CVD deposition psg film 41, its thickness is 200 nanometers for example greater than gate electrode, and buries space and covering grid electrode between the gate electrode.Owing to not using PE-CVD to use HDP-CVD, therefore bury functionally, and can bury space between the gate electrode fully.Psg film 41 has the irregular surface consistent with gate electrode.
Shown in Fig. 8 C, on psg film 41, for example depositing by PE-CVD, thickness is the TEOS oxide-film 42 of 250 nanometers.Because the radius of curvature and the depth-to-width ratio of laminar surface are down relaxed in the surface of HDP-PSG film 41, can not produce the problem relevant with burying performance even therefore have the low PE-CVD that buries performance yet.Interlayer dielectric 40 is made of HDP-PSG film 41 and PE-TEOS film 42.As a comparative example, form the sample of interlayer dielectric 40 with individual layer HDP-PSG film.Measure the film thickness distribution of interlayer dielectric film on the wafer.
Fig. 9 A is the chart that the measurement result of film thickness distribution is shown.The film thickness distribution performance of sample with interlayer dielectric 40 of individual layer HDP-PSG film is similar to the alphabetical M shape shown in Fig. 6 B and distributes.Thickness is about 440 nanometers in the center wafer district, and thickness increases gradually in the zone of outside, center, reaches the maximum of about 462 nanometers, is becoming about 453 nanometers near wafer edge region then.
The film thickness distribution of sample of interlayer dielectric 40 with lamination of HDP-PSG film 41 and PE-TEOS film 42 shows as the almost smooth and stable value of about 450 nanometers usually in the entire wafer zone.Although reason the unknown can obtain smooth surface by stacked HDP-CVD film and PE-CVD film.By changing the film thickness distribution of the thickness research interlayer dielectric 40 of interlayer dielectric film 41 down.
Fig. 9 B is the chart that the measurement result of film thickness distribution is shown.The thickness of utilization wiring (gate electrode) is equal to or higher than wiring psg film 41 highly by the HDP-CVD deposit thickness as a reference, and deposits the TEOS oxide-film by PE-CVD on this psg film 41.Abscissa is represented HDP-PSG film thickness and wiring ratio highly.Ordinate is represented the thickness deviation of arbitrary unit.The multiple with wiring height be 2.5 or bigger zone in, thickness deviation is tending towards and the proportional increase of multiple usually.In multiple was lower than 2 zone, along with multiple reduces, thickness deviation diminished.In order to suppress the thickness deviation, think that preferably forming thickness is wiring height twice or thinner HDP-PSG film, more preferably 1.5 times of the wiring height or thinner.
Shown in Figure 10 A, polish the interlayer dielectric of making by the lamination of HDP-PSG film 41 and PE-TEOS film 42 40 by two steps.At first, carry out the first step polishing until the irregular surface of removing interlayer dielectric 40.Current polish stop is at the surperficial P1 place shown in Figure 10 A.Carry out current polishing by the CMP that can realize automatic hold function.Concrete polishing condition is provided with as follows:
The pressure of rubbing head: 200 grammes per square metre/square centimeters,
The rotating speed of rubbing head: 100rpm,
The rotating speed of polishing block: 100rpm, and
The amount of providing of ceria sizing agent: 0.2 liter/minute.
The groove-shaped model of the K that uses Nitta Haas company to produce is the polishing pad of IC1400, and uses the ceria sizing agent of the model of dupont air products nanomaterials company production as MICROPLANAR STI2100 RA9.Polishing time is 100 seconds.
The polishing consumable film also forms cut on polished surface.Along with automatic hold function works, the consumption of polished surface descends fast.But the cut number on the polished surface is difficult to change.If the consumption polished surface, the cut that forms before also consuming.But if do not consume polished surface, then cut accumulates continuously.
By relaxing automatic hold function, under the condition of certain polishing speed, carry out second polishing and reduce cut.Automatically stop performance for relaxing, the amount of providing by reducing ceria sizing agent is also supplied pure water, carries out polishing until surperficial P2.Concrete polishing condition is provided with as follows:
The pressure of rubbing head: 200 grammes per square metre/square centimeters,
The rotating speed of rubbing head: 100rpm,
The rotating speed of polishing block: 100rpm
The amount of providing of ceria sizing agent: 0.1 liter/minute, and
The amount of providing of pure water: 0.35 liter/minute.
The groove-shaped model of the K that uses Nitta Haas company to produce is the polishing pad of IC1400, and uses the ceria sizing agent of the model of dupont air products nanomaterials company production as MICROPLANAR STI2100 RA9.The used kind of this ceria sizing agent and first step is identical.This ceria sizing agent of dilution on polishing block.In this case, cost is lower than the slurry that use has been diluted.The polishing speed of second step is 100 nm/minute.
Shown in Figure 10 B, provide the nozzle 124b of pure water to be arranged on the position further from the polishing block center than the nozzle 124a that ceria sizing agent is provided.
Figure 10 C is the chart that first and second steps cut number afterwards is shown.Left side bar chart is represented the cut number after the first step polishing.Form the cut of greater number, i.e. 300 cuts.Right bar chart is represented the cut number after the polishing of second step.Although the cut number after the first step is about 300, the cut number significantly is reduced to about 10 cuts after second step.
Figure 10 D is the chart that polishing film thickness distribution afterwards is shown.Figure 10 D also illustrates the film thickness distribution of comparative sample (interlayer dielectric of the individual layer PSG layer that forms by HDP-CVD).The film thickness distribution of comparative sample is: thickness is about 316 nanometers in the center wafer district, and thickness increases gradually in the zone of outside, center, reaches the maximum of about 332 nanometers, is becoming about 323 nanometers near wafer edge region then.Keep alphabetical M shape to distribute.The interlayer dielectric of present embodiment has the stable thickness of about 320 nanometers usually in the entire wafer zone.As seen the lamination interlayer dielectric of present embodiment can prevent the thickness deviation in the entire wafer zone.By using the ceria sizing agent with the CMP identical type of STI, can suitably carry out the CMP of the interlayer dielectric that is used to bury gate electrode.
Can between the first step CMP and the second step CMP, insert the pure water rinsing step.Can insert the physics polishing step in case of necessity.If insert the physics polishing step, the preferred pure water rinsing of carrying out afterwards.More than in the explanation, the deposition degree of depth is equal to or greater than the following interlayer dielectric film of wiring (gate electrode) height.The cubic structure (step, radius of curvature etc.) that the thickness of following interlayer dielectric film can relax the lower floor that is difficult for burying gets final product.The surface that does not require down the interlayer dielectric film must be higher than the wiring surface.
Figure 11 A illustrates the modification of present embodiment.Thickness by interlayer dielectric film 41 under the PSG of HDP-CVD deposition is set to the height less than gate electrode G.The following interlayer dielectric film that is deposited has uneven surface, and its recessed district is lower than the surface (upper surface) of gate electrode.Although the HDP-PSG film has the good performance of burying, can not guarantee the uniformity of thickness.If expect that the thickness by interlayer dielectric film 41 under the restriction HDP-PSG relaxes the cubic structure of below, then can stably guarantee the uniformity of the film thickness distribution of whole lamination interlayer dielectric 40.
Figure 11 B illustrates another kind of the modification.If by using the layer identical to form the W that connects up with grid wiring G, local interlinkage for example, the height of the following interlayer dielectric film 41 on the W that then connects up may be higher than other zone.In this upper zone, can expose part interlayer dielectric film 41 down by first step CMP.Even expose interlayer dielectric film down by first step CMP, this exposure also allows, unless practical problem takes place.
Though the interlayer dielectric film is made by the HDP-PSG film under in the foregoing description, it also can be made by the HDP-USG film.Have the good dielectric film of burying performance by HDP-CVD formation, and on this dielectric film, form polished oxide-film, for example TEOS oxide-film by PE-CVD.If the thickness of restriction HDP-CVD dielectric film also forms the PE-CVD film with good flatness on the HDP-CVD dielectric film, then expection can form the lamination interlayer dielectric with good flatness.If target only is the film thickness uniformity in the entire wafer zone, the material of then going up the interlayer dielectric film is not limited to the TEOS oxide, and film build method also is not limited to PE-CVD, as long as this method can form the film with good film thickness uniformity.Wiring is not limited to by layer wiring that constitutes identical with gate electrode.
Figure 12 A and Figure 12 B illustrate the example of the wiring that is different from grid wiring.
Figure 12 A and 12B illustrate the manufacture method of dynamic random access memory (DRAM).Shown in Figure 12 A, in the memory cell areas of Semiconductor substrate, form the n channel MOS transistor by being similar to the technology shown in Fig. 8 A to 8C.In Figure 12 A and 12B, two n channel MOS transistors are shared a center source/drain regions, and holding capacitor is connected to relative source/drain regions.After forming MOS transistor, form the interlayer dielectric 40 of burying gate electrode.
After by the flattening surface of CMP with interlayer dielectric 40, form the contact hole that arrives source/drain regions by photoetching and etching, and in contact hole deposit spathic silicon etc. to form conductive plug PLG1.After removing conducting film unnecessary on the surface by CMP, the cvd silicon oxide film is to form interlayer dielectric 50.
Form the HDP-PSG film 61 and the PE-TEOS film 62 that cover bit line BL.By be similar to two above-mentioned step CMP with flattening surface to form interlayer dielectric 60.
Shown in Figure 12 B, pass interlayer dielectric 60 and 50 and form the contact hole of the conductive plug PLG1 that arrives opposite side, and in contact hole, imbed conductive plug PLG2.Formation is connected to the storage electrode SE of polysilicon of conductive plug PLG2 etc.The counterelectrode OE of the capacitor dielectric film CDF that formation is made by silicon oxide film of thermal oxidation etc. and polysilicon etc.Can use the manufacture method of any known method as the DRAM capacitor.Deposition is buried the HDP-PSG film 71 and the PE-TEOS film 72 of capacitor, to form interlayer dielectric 70.Influenced by following capacitor arrangement, the surface of interlayer dielectric 70 is irregular surface.By being similar to the flattening surface of two above-mentioned step CMP with interlayer dielectric 70.
As mentioned above, if wire structures has irregular surface, then at first by providing the good HDP-CVD that buries performance to relax step, radius of curvature etc., then by good film thickness uniformity can being provided and can stablizing the PE-CVD cvd silicon oxide film of CMP, thereby form interlayer dielectric with good quality.With the interlayer dielectric planarization, has the interlayer dielectric of uniform thickness and flat surfaces by two step CMP with formation.
The present invention has been described in conjunction with the preferred embodiments.The present invention is not limited only to the foregoing description.For example, except the polyacrylic acid ester ammonium salt, can use the additive as ceria based grinding agent such as polyvinylpyrrolidone.Except the silica-based grinding agent, zirconia base grinding agent etc. also can be used for the physics polishing.Polished film is not limited to silicon oxide film, also can use other film, for example silicon oxynitride film.In a word, form down dielectric film, and on this time dielectric film, form upper nonconductive Film with excellent homogeneity (thickness evenness) by the good HDP-CVD that buries performance can be provided.Those skilled in the art can know that understanding can make other multiple modification, improvement, combination etc.
Claims (9)
1. the manufacture method of a semiconductor device comprises the steps:
(a) first grinding agent is being provided in the polishing block that is provided with polishing pad, utilize described polishing pad, and by the rubbing head support semiconductor substrates, the surface of the film that polishing forms on described Semiconductor substrate, until the flattening surface with described film, wherein said first grinding agent comprises the additive of ceria abrasive particles and interfacial agent;
(b) afterwards, use second grinding agent comprise silica or zirconia and to have physics polishing function, the surface of polishing described film in described step (a); And
(c) afterwards, use comprises the additive of ceria abrasive particles, interfacial agent and the 3rd grinding agent of diluent, the surface of polishing described film in described step (b).
2. according to the manufacture method of the described semiconductor device of claim 1, wherein said diluent is a water, and forms described the 3rd grinding agent by described first grinding agent of mixing and water on described polishing block.
3. according to the manufacture method of the described semiconductor device of claim 1, wherein after described step (a) and one of them step of described step (b), with water provide to described polishing block to rinse out grinding agent.
4. according to the manufacture method of each described semiconductor device in the claim 1 to 3, wherein on same polishing block, carry out described step (a) and (b) and reach (c).
5. according to the manufacture method of each described semiconductor device in the claim 1 to 3, wherein on two or three polishing blocks, carry out described step (a) and (b) and reach (c).
6. according to the manufacture method of each described semiconductor device in the claim 1 to 3, wherein in described step (a) and one of them step of described step (c), according to the torque change-detection polishing end point of described polishing block or described rubbing head.
7. according to the manufacture method of each described semiconductor device in the claim 1 to 3, wherein:
Described Semiconductor substrate is a silicon substrate;
In described step (a) before, this manufacture method also comprises the steps:
(x) stacked buffer oxide silicon fiml and silicon nitride film on described surface of silicon substrate, and by forming etching mask to the described silicon nitride film patterning of major general;
(y) utilize described etching mask in described silicon substrate, to form groove, described trench isolations active area; And
(z) on described silicon substrate, deposit dielectric film, and use described dielectric film to bury described groove; And
In described step (c), when utilizing described etching mask, carry out polishing as polishing stop layer.
8. according to the manufacture method of the described semiconductor device of claim 7, wherein in described step (z), the surface of the described groove of thermal oxidation before the described dielectric film of deposition, to form silicon oxide film, silicon nitride film is come the cvd silicon oxide film by high density plasma CVD afterwards then.
9. according to the manufacture method of the described semiconductor device of claim 7, wherein in described step (c) afterwards, described silicon nitride film of etching and described buffer oxide silicon fiml form MOS transistor then in described active area.
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|---|---|---|---|---|
| CN102610509A (en) * | 2010-12-22 | 2012-07-25 | 拉碧斯半导体株式会社 | Method of forming element isolation layer |
| CN102610509B (en) * | 2010-12-22 | 2016-12-14 | 拉碧斯半导体株式会社 | The forming method of element isolation layer |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP5168935B2 (en) * | 2007-02-21 | 2013-03-27 | 富士通セミコンダクター株式会社 | Manufacturing method of semiconductor device |
| CN101797709B (en) * | 2010-04-12 | 2011-05-11 | 天津大学 | Composite grinding method for large-caliber quartz glass substrate |
| JP6821291B2 (en) * | 2015-05-29 | 2021-01-27 | キヤノン株式会社 | Manufacturing method of photoelectric conversion device, imaging system and photoelectric conversion device |
| CN111599677B (en) * | 2019-02-21 | 2023-08-01 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor structure and forming method thereof |
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Also Published As
| Publication number | Publication date |
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| CN101471288B (en) | 2011-07-27 |
| JP2007019427A (en) | 2007-01-25 |
| CN1897227A (en) | 2007-01-17 |
| CN101471288A (en) | 2009-07-01 |
| JP4679277B2 (en) | 2011-04-27 |
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