JPH07263537A - Formation of trench element separation - Google Patents
Formation of trench element separationInfo
- Publication number
- JPH07263537A JPH07263537A JP7256794A JP7256794A JPH07263537A JP H07263537 A JPH07263537 A JP H07263537A JP 7256794 A JP7256794 A JP 7256794A JP 7256794 A JP7256794 A JP 7256794A JP H07263537 A JPH07263537 A JP H07263537A
- Authority
- JP
- Japan
- Prior art keywords
- polishing
- semiconductor substrate
- insulating film
- forming
- chemical mechanical
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Element Separation (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置の素子分離
技術に関し、特にはトレンチ素子分離の形成方法に関す
るものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an element isolation technique for a semiconductor device, and more particularly to a method for forming trench element isolation.
【０００２】[0002]
【従来の技術】化学的機械研磨を用いた素子分離領域の
形成方法は、特願昭５９−１３６９４３号に開示されて
いるように、化学的機械研磨を１回のみ行う方法、１回
の化学的機械研磨とフッ酸を用いたウェットエッチング
処理とを組み合わせた方法が提案されている。上記いず
れの場合も、研磨剤にはシリカ系のものまたは酸化セリ
ウム系のものが用いられている。2. Description of the Related Art As a method of forming an element isolation region by using chemical mechanical polishing, as disclosed in Japanese Patent Application No. 59-136943, a method of performing chemical mechanical polishing only once, one chemical A method that combines a mechanical polishing and a wet etching process using hydrofluoric acid has been proposed. In any of the above cases, a silica-based or cerium oxide-based abrasive is used.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、シリカ
系の研磨剤を用いて研磨を行った場合には、酸化シリコ
ンの研磨に非常に時間がかかる。通常、シリカ系の研磨
剤は主としてシリコン基体を研磨するものであって、絶
縁膜である酸化シリコンに対する研磨速度が非常に遅い
ためである。一方、酸化セリウム系の研磨剤を用いて酸
化シリコンを研磨する条件で研磨を行った場合には、酸
化シリコンは短時間に研磨される。しかしながら、酸化
シリコンの研磨が進行してシリコン基体が露出したと
き、シリコン基体の研磨面側には深さが０．２μｍまた
はそれ以下の深さに転移，結晶欠陥等の加工変質層が発
生する。そのため、例えばリーク電流が多くなるので、
シリコン基体を半導体装置の基体として用いることがで
きない。また、１回の化学的機械研磨のみでは、シリコ
ン基体と酸化シリコンとのエッチング速度が異なるため
に、シリコン基体の表面と酸化シリコンとの表面とを互
いに同様な高さに形成することは困難である。上記説明
したように、シリコン基体表面が平坦な素子分離構造を
形成することが困難になっている。However, when polishing is performed using a silica-based abrasive, polishing of silicon oxide takes a very long time. This is because the silica-based polishing agent is mainly used to polish a silicon substrate, and the polishing rate for silicon oxide, which is an insulating film, is very slow. On the other hand, when the polishing is performed under the condition that the silicon oxide is polished using the cerium oxide-based polishing agent, the silicon oxide is polished in a short time. However, when the polishing of silicon oxide progresses and the silicon substrate is exposed, a work-affected layer such as a transition or a crystal defect occurs at a depth of 0.2 μm or less on the polished surface side of the silicon substrate. . Therefore, for example, since the leak current increases,
A silicon substrate cannot be used as a substrate for semiconductor devices. Further, it is difficult to form the surface of the silicon substrate and the surface of the silicon oxide at the same height by only one chemical mechanical polishing because the etching rates of the silicon substrate and the silicon oxide are different. is there. As described above, it is difficult to form an element isolation structure having a flat silicon substrate surface.
【０００４】本発明は、半導体装置の素子分離におい
て、その表面を平坦化したトレンチ素子分離の形成方法
を提供することを目的とする。An object of the present invention is to provide a method for forming a trench element isolation having a flat surface in the element isolation of a semiconductor device.
【０００５】[0005]
【課題を解決するための手段】本発明は、上記目的を達
成するためになされたトレンチ素子分離の形成方法であ
る。すなわち、第１工程で、半導体基体の表面側に溝を
形成した後、その溝の内部を埋め込む状態にして半導体
基体の表面に絶縁膜を形成する。次いで第２工程で、酸
化セリウム系の研磨剤を含む研磨液を用いた化学的機械
研磨によって、絶縁膜の表面側を除去して半導体基体を
露出させる。そして第３工程で、シリカ系の研磨剤を含
む研磨液を用いた化学的機械研磨によって、主として半
導体基体の表面側を除去する。上記第２工程での化学的
機械研磨では、半導体基体に対する研磨選択比を２以上
に設定するのがよい。また第３工程の化学的機械研磨で
は、絶縁膜に対する研磨選択比を２以上に設定するのが
よい。SUMMARY OF THE INVENTION The present invention is a method of forming a trench isolation for achieving the above object. That is, in the first step, after forming a groove on the surface side of the semiconductor substrate, an insulating film is formed on the surface of the semiconductor substrate with the inside of the groove being filled. Next, in the second step, the surface side of the insulating film is removed by chemical mechanical polishing using a polishing liquid containing a cerium oxide-based polishing agent to expose the semiconductor substrate. Then, in the third step, the surface side of the semiconductor substrate is mainly removed by chemical mechanical polishing using a polishing liquid containing a silica-based polishing agent. In the chemical mechanical polishing in the second step, the polishing selection ratio with respect to the semiconductor substrate is preferably set to 2 or more. Further, in the chemical mechanical polishing in the third step, it is preferable to set the polishing selection ratio to the insulating film to 2 or more.
【０００６】[0006]
【作用】上記トレンチ素子分離の形成方法では、酸化セ
リウム系の研磨剤を含む研磨液を用いて、絶縁膜を研磨
して半導体基体を露出させてから、シリカ系の研磨剤を
含む研磨液を用いて主として半導体基体の表面側を研磨
する。そのため、初めの研磨では絶縁膜が優先的に研磨
されるので、研磨によって露出した半導体基体表面より
も絶縁膜表面のほうが低くなる。そして次の研磨では半
導体基体が優先的に研磨されるので、研磨時間を調節す
ることによって、半導体基体表面と絶縁膜表面とがほぼ
同一平面上になるようになる。また第２工程の研磨で、
半導体基体に対する研磨選択比を２以上に設定すること
から、半導体基体に対して絶縁膜が優先的に研磨され
る。また第３工程の研磨で、絶縁膜に対する研磨選択比
を２以上に設定することから、絶縁膜に対して半導体基
体が優先的に研磨される。In the trench element isolation forming method described above, a polishing liquid containing a cerium oxide-based polishing agent is used to polish the insulating film to expose the semiconductor substrate, and then a polishing liquid containing a silica-based polishing agent is used. It is mainly used to polish the surface side of the semiconductor substrate. Therefore, since the insulating film is preferentially polished in the first polishing, the surface of the insulating film is lower than the surface of the semiconductor substrate exposed by polishing. Then, in the next polishing, the semiconductor substrate is preferentially polished, so that the surface of the semiconductor substrate and the surface of the insulating film are substantially flush with each other by adjusting the polishing time. Also, in the second step of polishing,
Since the polishing selection ratio for the semiconductor substrate is set to 2 or more, the insulating film is preferentially polished for the semiconductor substrate. Further, in the polishing of the third step, since the polishing selection ratio for the insulating film is set to 2 or more, the semiconductor substrate is preferentially polished for the insulating film.
【０００７】[0007]
【実施例】本発明の実施例を図１の形成工程図により説
明する。図１の（１）に示すように、第１工程を行う。
この工程では、通常のリソグラフィー技術とドライエッ
チング（例えば、反応性イオンエッチング，ＥＣＲプラ
ズマエッチング等）とによって、半導体基体（例えばシ
リコン基体）１１の表面側における素子分離領域の形成
部分に溝１２を形成する。以下、半導体基体１１はシリ
コン基体１１と記す。また図ではシリコン基体１１と記
す。なお、図では、エッチングマスクに用いたレジスト
膜の図示は省略した。そして溝１２を形成した後、アッ
シング処理またはウェットエッチングによって、上記レ
ジストからなるエッチングマスクを除去する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described with reference to the process chart of FIG. As shown in (1) of FIG. 1, the first step is performed.
In this step, the groove 12 is formed in the portion where the element isolation region is formed on the surface side of the semiconductor substrate (for example, silicon substrate) 11 by the ordinary lithography technique and dry etching (for example, reactive ion etching, ECR plasma etching, etc.). To do. Hereinafter, the semiconductor substrate 11 will be referred to as the silicon substrate 11. Also, in the figure, it is referred to as a silicon substrate 11. In the figure, the resist film used as the etching mask is not shown. Then, after forming the groove 12, the etching mask made of the resist is removed by ashing treatment or wet etching.
【０００８】その後、化学的気相成長（以下ＣＶＤと記
す）法，蒸着法，スパッタ法等に代表される成膜技術に
よって、上記溝１２の内部を埋め込む状態にしてシリコ
ン基体１１の表面に絶縁膜１３を形成する。この絶縁膜
１３は、例えば酸化シリコンからなる。After that, the inside of the groove 12 is filled with the film by a film forming technique typified by a chemical vapor deposition (hereinafter referred to as CVD) method, a vapor deposition method, a sputtering method and the like, and the surface of the silicon substrate 11 is insulated. The film 13 is formed. The insulating film 13 is made of, for example, silicon oxide.
【０００９】なお、図示はしないが、素子分離機能を確
実にするため、絶縁膜１３を形成する前に犠牲酸化を行
ってもよい。また、絶縁膜１３を成膜する前に溝１２の
内壁に熱酸化膜（図示せず）を形成してもよい。Although not shown, sacrificial oxidation may be performed before forming the insulating film 13 in order to ensure the element isolation function. Further, before forming the insulating film 13, a thermal oxide film (not shown) may be formed on the inner wall of the groove 12.
【００１０】次いで図１の（２）に示す第２工程を行
う。この工程では、酸化セリウム系の研磨剤を含む研磨
液を用いた化学的機械研磨（例えばメカノケミカルポリ
シング）を行って、絶縁膜１３の２点鎖線で示す部分を
研磨する。そして、シリコン基体１１の表面１１ａを露
出させる。このとき、絶縁膜１３は表面１１ａよりも少
しだけ低く研磨される。上記化学的機械研磨では、例え
ば、研磨砥粒には粒径が３００ｎｍ〜６００ｎｍ程度の
酸化セリウム（ＣｅＯ2 ）を用い、研磨液にはアルカリ
性溶液（ｐＨ＝１０〜１１程度）を用いる。またポリシ
ングクロスには、硬度としてＡｓｋｅｒ−Ｃが６０〜９
０程度のものを用いる。Next, the second step shown in FIG. 1B is performed. In this step, chemical mechanical polishing (for example, mechanochemical polishing) using a polishing liquid containing a cerium oxide-based polishing agent is performed to polish the portion of the insulating film 13 indicated by the chain double-dashed line. Then, the surface 11a of the silicon substrate 11 is exposed. At this time, the insulating film 13 is polished slightly lower than the surface 11a. In the chemical mechanical polishing, for example, cerium oxide (CeO 2 ) having a particle size of about 300 nm to 600 nm is used as the polishing abrasive grains, and an alkaline solution (pH = about 10 to 11) is used as the polishing liquid. Asker-C has a hardness of 60 to 9 on the polishing cloth.
The one of about 0 is used.
【００１１】その後図１の（３）に示す第３工程を行
う。この工程では、シリカ系の研磨剤を含む研磨液を用
いた化学的機械研磨（例えばメカノケミカルポリシン
グ）を行って、主としてシリコン基体１１の表面側（２
点鎖線で示す部分）を研磨する。そして、シリコン基体
１１の表面１１ｂと溝１２内の絶縁膜１３の表面１３ｂ
とをほぼ同一高さに形成する。上記化学的機械研磨で
は、例えば、研磨砥粒には粒径が１０ｎｍ〜２０ｎｍ程
度のコロイダルシリカを用い、研磨液にはシリコン基体
１１に対してエッチング性を有するアルカリ性溶液（例
えばｐＨ＝１０〜１１程度）を用いる。このアルカリ性
溶液としては、例えばアンモニア水を用いる。Thereafter, the third step shown in FIG. 1C is performed. In this step, chemical mechanical polishing (for example, mechanochemical polishing) using a polishing liquid containing a silica-based polishing agent is performed, and the surface side of the silicon substrate 11 (2
The part indicated by the dotted line) is polished. The surface 11b of the silicon substrate 11 and the surface 13b of the insulating film 13 in the groove 12
And are formed almost at the same height. In the chemical mechanical polishing, for example, colloidal silica having a particle size of about 10 nm to 20 nm is used as the polishing abrasive grains, and an alkaline solution having an etching property with respect to the silicon substrate 11 (for example, pH = 10 to 11) is used as the polishing liquid. Degree) is used. Ammonia water, for example, is used as the alkaline solution.
【００１２】上記トレンチ素子分離の形成方法では、酸
化セリウム系の研磨剤を含む研磨液を用いて、絶縁膜１
３を研磨してシリコン基体１１の表面を露出させてか
ら、シリカ系の研磨剤を含む研磨液を用いて主としてシ
リコン基体１１の表面側を研磨する。そのため、初めの
研磨では絶縁膜１３が優先的に研磨されるので、研磨に
よって露出したシリコン基体１１の表面よりも絶縁膜１
２の表面のほうが低くなる。そして次の研磨ではシリコ
ン基体１１が優先的に研磨されるので、研磨時間を調節
することによって、シリコン基体１１の表面１１ｂと絶
縁膜１３の表面１１ｂとがほぼ同一平面になる。In the method for forming the trench element isolation, the insulating film 1 is formed by using a polishing liquid containing a cerium oxide-based polishing agent.
After polishing 3 to expose the surface of the silicon substrate 11, the surface side of the silicon substrate 11 is mainly polished using a polishing liquid containing a silica-based polishing agent. Therefore, since the insulating film 13 is preferentially polished in the first polishing, the insulating film 1 is more than the surface of the silicon substrate 11 exposed by polishing.
The surface of 2 becomes lower. Since the silicon substrate 11 is preferentially polished in the next polishing, the surface 11b of the silicon substrate 11 and the surface 11b of the insulating film 13 are substantially flush with each other by adjusting the polishing time.
【００１３】また上記第２工程の研磨では、シリコン基
体１１に対する研磨選択比を２以上に設定して行うこと
が好ましい。研磨の選択比を高める方法としては、例え
ば、フッ酸とフッ化アンモニウムと酢酸との混合液のよ
うなシリコンに対して酸化シリコンを選択的にエッチン
グするような液を研磨液に用いる。このように、シリコ
ン基体１１に対する研磨選択比を２以上に設定すること
から、シリコン基体１１に対して絶縁膜１３が優先的に
研磨される。The polishing in the second step is preferably performed by setting the polishing selection ratio with respect to the silicon substrate 11 to 2 or more. As a method of increasing the polishing selection ratio, for example, a liquid such as a mixed liquid of hydrofluoric acid, ammonium fluoride and acetic acid that selectively etches silicon oxide with respect to silicon is used as the polishing liquid. In this way, since the polishing selection ratio for the silicon substrate 11 is set to 2 or more, the insulating film 13 is preferentially polished for the silicon substrate 11.
【００１４】さらに上記第３工程の研磨では、絶縁膜１
３に対する研磨選択比を２以上に設定して行うことが好
ましい。研磨の選択比を高める方法としては、例えば、
フッ硝酸のような酸化シリコンに対してシリコンを選択
的にエッチングするような液を研磨液に用いる。このよ
うに、絶縁膜１３に対する研磨選択比を２以上に設定す
ることから、絶縁膜１３に対してシリコン基体１１が優
先的に研磨される。Further, in the polishing in the third step, the insulating film 1
It is preferable to set the polishing selection ratio to 3 to 2 or more. As a method of increasing the selection ratio of polishing, for example,
A liquid such as hydrofluoric nitric acid that selectively etches silicon with respect to silicon oxide is used as the polishing liquid. In this way, since the polishing selection ratio with respect to the insulating film 13 is set to 2 or more, the silicon substrate 11 is preferentially polished with respect to the insulating film 13.
【００１５】[0015]
【発明の効果】以上、説明したように本発明によれば、
第２工程の絶縁膜の研磨は、研磨速度が速い酸化セリウ
ム系の研磨剤を用いた化学的機械研磨で行うので、絶縁
膜を優先的に研磨することができる。また第３工程の半
導体基体の研磨は、シリカ系の研磨剤を用いた化学的機
械研磨で行うので、半導体基体を優先的に研磨すること
ができる。そのため、研磨時間を調節することによっ
て、半導体基体表面と絶縁膜表面とをほぼ同一平面に形
成することができる。さらに第２工程で研磨された半導
体基体表面を研磨するため、先の研磨で形成された加工
変質層を除去することができる。そのため、半導体基体
は高品質になるので、そこに形成された素子の性能の向
上が図れる。As described above, according to the present invention,
Since the polishing of the insulating film in the second step is performed by chemical mechanical polishing using a cerium oxide-based polishing agent having a high polishing rate, the insulating film can be preferentially polished. Further, since the polishing of the semiconductor substrate in the third step is performed by chemical mechanical polishing using a silica-based polishing agent, the semiconductor substrate can be preferentially polished. Therefore, the surface of the semiconductor substrate and the surface of the insulating film can be formed on substantially the same plane by adjusting the polishing time. Further, since the surface of the semiconductor substrate polished in the second step is polished, the work-affected layer formed by the previous polishing can be removed. Therefore, since the semiconductor substrate has high quality, the performance of the element formed therein can be improved.
【図１】実施例の形成工程図である。FIG. 1 is a process drawing of an example.
１１ 半導体基体 １２ 溝 １３ 絶縁膜 11 semiconductor substrate 12 groove 13 insulating film
Claims (3)
該溝の内部を埋め込む状態にして該半導体基体の表面に
絶縁膜を形成する第１工程と、 酸化セリウム系の研磨剤を含む研磨液を用いた化学的機
械研磨によって、前記絶縁膜の表面側を除去して前記半
導体基体を露出させる第２工程と、 シリカ系の研磨剤を含む研磨液を用いた化学的機械研磨
によって、主として前記半導体基体の表面側を除去する
第３工程とからなることを特徴とするトレンチ素子分離
の形成方法。1. After forming a groove on the surface side of a semiconductor substrate,
The first step of forming an insulating film on the surface of the semiconductor substrate while filling the inside of the groove, and the surface side of the insulating film by chemical mechanical polishing using a polishing liquid containing a cerium oxide-based polishing agent. And exposing the semiconductor substrate, and a third step of mainly removing the surface side of the semiconductor substrate by chemical mechanical polishing using a polishing liquid containing a silica-based polishing agent. A method for forming a trench element isolation, characterized by.
方法において、 前記第２工程の化学的機械研磨は、半導体基体に対する
研磨選択比を２以上に設定して行うことを特徴とするト
レンチ素子分離の形成方法。2. The method for forming a trench device according to claim 1, wherein the chemical mechanical polishing in the second step is performed by setting a polishing selection ratio with respect to a semiconductor substrate to 2 or more. Method of forming isolation.
素子分離の形成方法において、 前記第３工程の化学的機械研磨は、絶縁膜に対する研磨
選択比を２以上に設定して行うことを特徴とするトレン
チ素子分離の形成方法。3. The method for forming a trench element isolation according to claim 1, wherein the chemical mechanical polishing in the third step is performed by setting a polishing selection ratio with respect to the insulating film to 2 or more. And method for forming trench isolation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7256794A JPH07263537A (en) | 1994-03-16 | 1994-03-16 | Formation of trench element separation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7256794A JPH07263537A (en) | 1994-03-16 | 1994-03-16 | Formation of trench element separation |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07263537A true JPH07263537A (en) | 1995-10-13 |
Family
ID=13493084
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7256794A Pending JPH07263537A (en) | 1994-03-16 | 1994-03-16 | Formation of trench element separation |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07263537A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6204184B1 (en) | 1998-03-30 | 2001-03-20 | Hitachi, Ltd. | Method of manufacturing semiconductor devices |
| JP2003517720A (en) * | 1999-03-29 | 2003-05-27 | スピードファム−アイピーイーシー コーポレイション | Two-step CMP for damascene structures on semiconductor wafers |
| JP2004266276A (en) * | 2003-02-28 | 2004-09-24 | Samsung Electronics Co Ltd | Method for forming trench, and method for manufacturing semiconductor using the same |
| CN100464394C (en) * | 2005-07-11 | 2009-02-25 | 富士通微电子株式会社 | Manufacture of semiconductor device with cmp |
-
1994
- 1994-03-16 JP JP7256794A patent/JPH07263537A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6204184B1 (en) | 1998-03-30 | 2001-03-20 | Hitachi, Ltd. | Method of manufacturing semiconductor devices |
| US6380085B2 (en) | 1998-03-30 | 2002-04-30 | Hitachi, Ltd. | Method of manufacturing semiconductor devices |
| US6498100B2 (en) | 1998-03-30 | 2002-12-24 | Hitachi, Ltd. | Method of manufacturing semiconductor devices |
| JP2003517720A (en) * | 1999-03-29 | 2003-05-27 | スピードファム−アイピーイーシー コーポレイション | Two-step CMP for damascene structures on semiconductor wafers |
| JP4750948B2 (en) * | 1999-03-29 | 2011-08-17 | スピードファム−アイピーイーシー コーポレイション | Two-step CMP for damascene structures on semiconductor wafers |
| JP2004266276A (en) * | 2003-02-28 | 2004-09-24 | Samsung Electronics Co Ltd | Method for forming trench, and method for manufacturing semiconductor using the same |
| CN100464394C (en) * | 2005-07-11 | 2009-02-25 | 富士通微电子株式会社 | Manufacture of semiconductor device with cmp |
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