JP2007019427A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP2007019427A
JP2007019427A JP2005202060A JP2005202060A JP2007019427A JP 2007019427 A JP2007019427 A JP 2007019427A JP 2005202060 A JP2005202060 A JP 2005202060A JP 2005202060 A JP2005202060 A JP 2005202060A JP 2007019427 A JP2007019427 A JP 2007019427A
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film
insulating film
polishing
semiconductor device
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JP4679277B2 (en
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Naoki Itani
直毅 井谷
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Fujitsu Ltd
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Priority to US11/264,240 priority patent/US20070007246A1/en
Priority to KR1020050108065A priority patent/KR100692472B1/en
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device having superior uniformity in the thickness of an interlayer insulating film at a wafer level. <P>SOLUTION: The method of manufacturing the semiconductor device includes a process for forming wiring at the upper portion on a silicon substrate (a); a process for burying the wiring to deposit a first insulating film by HDP-CVD (b); a process for depositing a second insulating film at the upper portion of the first insulating film by a deposition method except HDP-CVD (c); and a process for flatting the second insulating film by chemical mechanical polishing using abrasive containing a cerium dioxide abrasive grain (d). <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、半導体装置の製造方法と得られる半導体装置に関し、特に被研磨膜を研磨して平坦化する化学機械研磨（chemicalmechanical polishing, ＣＭＰ）工程を含む半導体装置の製造方法と得られる半導体装置に関する。   The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device to be obtained, and more particularly to a method for manufacturing a semiconductor device including a chemical mechanical polishing (CMP) process for polishing and planarizing a film to be polished and a semiconductor device to be obtained. .

半導体装置の製造方法において、化学機械研磨(chemical mechanical polishing、ＣＭＰ)が用いられている。化学機械研磨は、下地に溝などの凹部を形成し、凹部を埋め込む成膜を行い、表面上の不要膜を除去する、ダマシン配線形成やシャロートレンチアイソレーション（ＳＴＩ）形成等、およびゲート電極を含む配線等を形成した、表面に凹凸を有する下地上に絶縁膜を堆積し、表面を平坦化する絶縁膜の表面平坦化等に用いられている。表面を平坦化することにより、浅い焦点深度しか有さないホトリソ工程の精度や、エッチング工程の均一性を向上することが可能になる。   In a method for manufacturing a semiconductor device, chemical mechanical polishing (CMP) is used. Chemical mechanical polishing forms recesses such as grooves in the base, forms films that fill the recesses, removes unnecessary films on the surface, forms damascene wiring, shallow trench isolation (STI), etc. An insulating film is deposited on a base having irregularities on the surface on which wiring and the like are formed, and is used for surface flattening of the insulating film for flattening the surface. By flattening the surface, it is possible to improve the accuracy of the photolithography process having only a shallow depth of focus and the uniformity of the etching process.

例えば、ＳＴＩ形成においては、シリコン基板表面を熱酸化してバッファ酸化シリコン膜を形成し,その上に窒化シリコン膜を堆積し,ホトリソグラフィとエッチングで窒化シリコンにＳＴＩに対応する開口を形成し、シリコン基板にトレンチをエッチングする。窒化シリコン膜はエッチングマスクとして機能する他、後のＣＭＰにおいてストッパとして機能する。   For example, in STI formation, the silicon substrate surface is thermally oxidized to form a buffer silicon oxide film, a silicon nitride film is deposited thereon, an opening corresponding to the STI is formed in silicon nitride by photolithography and etching, Etch the trench in the silicon substrate. The silicon nitride film functions as an etching mask and also functions as a stopper in later CMP.

トレンチ内に露出したシリコン表面を熱酸化して酸化シリコン膜ライナを形成し、窒化シリコン膜を堆積して窒化シリコン膜ライナを形成した後、トレンチ内を絶縁膜、例えばアンドープトシリケートガラス（ＵＳＧ）膜で埋め込む。微細化されたトレンチをＵＳＧ膜で埋め込むために、高密度プラズマ（ＨＤＰ）化学気相堆積（ＣＶＤ）が用いられるようになった。トレンチ外に堆積したＵＳＧ膜は、ＣＭＰで除去する。ＣＭＰの後、露出する窒化シリコン膜は熱燐酸等でエッチングし、バッファ酸化シリコン膜は希フッ酸等でエッチングする。   The silicon surface exposed in the trench is thermally oxidized to form a silicon oxide film liner, a silicon nitride film is deposited to form a silicon nitride film liner, and then an insulating film such as undoped silicate glass (USG) is formed in the trench. Embed with film. High density plasma (HDP) chemical vapor deposition (CVD) has been used to fill the miniaturized trenches with USG films. The USG film deposited outside the trench is removed by CMP. After the CMP, the exposed silicon nitride film is etched with hot phosphoric acid or the like, and the buffer silicon oxide film is etched with dilute hydrofluoric acid or the like.

ＭＯＳトランジスタのゲート電極形成においては、シリコン基板の活性領域表面に熱酸化で酸化シリコン膜を形成し、必要に応じて窒素を導入してゲート絶縁膜とする。ゲート絶縁膜上に、多結晶シリコン膜を堆積し、ゲート電極形状にパターニングする。ソース／ドレインのエクステンション領域形成用のイオン注入を行った後、サイドウォールスペーサを形成し、ソース／ドレインの高濃度領域形成用イオン注入を行う。必要に応じてシリサイド化工程を行った後、燐を含む酸化シリコン膜であるホスホシリケートガラス（ＰＳＧ）膜を堆積し、ゲート電極を覆う層間絶縁膜を形成する。   In forming the gate electrode of the MOS transistor, a silicon oxide film is formed on the surface of the active region of the silicon substrate by thermal oxidation, and nitrogen is introduced as necessary to form a gate insulating film. A polycrystalline silicon film is deposited on the gate insulating film and patterned into a gate electrode shape. After ion implantation for forming source / drain extension regions, sidewall spacers are formed, and ion implantation for forming high-concentration source / drain regions is performed. After performing a silicidation step as necessary, a phosphosilicate glass (PSG) film, which is a silicon oxide film containing phosphorus, is deposited to form an interlayer insulating film covering the gate electrode.

ゲート電極を覆う層間絶縁膜は、表面に凹凸を有する。凹凸を除去するため、ＣＭＰにより層間絶縁膜表面を平坦化する。堆積する層間絶縁膜の厚さは、ＣＭＰの研磨代分厚くしておく。平坦化後、ソース／ドレイン等に対するコンタクトホールをエッチングし、多結晶シリコン、タングステン等の導電性プラグをコンタクトホール内に埋め込む。層間絶縁膜上の不要導電層をＣＭＰで除去する。   The interlayer insulating film covering the gate electrode has irregularities on the surface. In order to remove the unevenness, the surface of the interlayer insulating film is planarized by CMP. The interlayer insulating film to be deposited is made thick enough for CMP polishing. After planarization, the contact hole for the source / drain or the like is etched, and a conductive plug such as polycrystalline silicon or tungsten is buried in the contact hole. An unnecessary conductive layer on the interlayer insulating film is removed by CMP.

ＣＭＰにおいては、例えばシリカよりなる研磨砥粒とＫＯＨよりなる添加剤を含む研磨剤が用いられた。より高平坦化を達成する研磨剤として、研磨砥粒として酸化セリウム（セリア、二酸化セリウムＣｅＯ２）、添加剤としてポリアクリル酸アンモニウム塩やポリビニルピロリドン等を含む研磨剤が提案されている。酸化セリウムを水と混合した研磨剤は、研磨レートが非常に高く、段差緩和機能は低い。例えば、ポリアクリル酸アンモニウム塩を適量添加すると、研磨速度を適当な値に制御でき、凹部での研磨を抑制して平坦化機能が高くなり、研磨面が平坦化された時には自動停止（オートストップ）機能を生じる。 In CMP, for example, an abrasive containing abrasive grains made of silica and an additive made of KOH was used. As an abrasive that achieves higher planarization, an abrasive containing cerium oxide (ceria, cerium dioxide CeO 2 ) as abrasive grains and polyacrylic acid ammonium salt, polyvinylpyrrolidone, or the like as an additive has been proposed. An abrasive in which cerium oxide is mixed with water has a very high polishing rate and a low step relief function. For example, when an appropriate amount of poly (ammonium acrylate) salt is added, the polishing rate can be controlled to an appropriate value, polishing at the recesses is suppressed and the leveling function is enhanced, and when the polishing surface is flattened, automatic stop (auto stop) Create function.

特開２００１−００９７０２号公報JP 2001-009702 A 特開２００１−０８５３７３号公報JP 2001-085373 A 特開２０００−２４８２６３号公報 研磨面の凹凸が消滅した研磨終点を検出する技術として、研磨面の温度や回転トルクを検出する技術も提案されている。JP, 2000-248263, A As a technique of detecting the polish end point in which the unevenness of the polish surface disappeared, the technique of detecting the temperature and the rotation torque of the polish surface is also proposed. 特開平１１−１０４９５５号公報 高平坦化を達成するため、ＣＭＰを２段階に分け、２段階のＣＭＰを異なる条件で行う方法も提案されている。例えば、研磨剤を供給しながら、第１の研磨パッドでメイン研磨を行い、その後研磨剤の供給を止め、水を供給しながら第１の研磨パッドより硬い第２の研磨パッドを用いて仕上げ研磨を行い、ディッシングを防止する。JP, 11-104955, A In order to achieve high planarization, a method of dividing CMP into two stages and performing two stages of CMP under different conditions has been proposed. For example, the main polishing is performed with the first polishing pad while supplying the abrasive, and then the polishing is stopped and the final polishing is performed using the second polishing pad harder than the first polishing pad while supplying water. To prevent dishing. 特開２００４−２９６５９１号公報 ＣＭＰを行う研磨装置は、研磨面を有する回転可能な研磨テーブルと、基板を保持する回転可能な研磨ヘッドと、研磨剤や純水を供給する複数のノズルを備え、研磨テーブルに対して研磨ヘッドを押し付ける押圧力を加えながら、研磨ヘッド、研磨テーブルを回転させ、研磨剤を供給しながら研磨を行う。A polishing apparatus that performs CMP includes a rotatable polishing table having a polishing surface, a rotatable polishing head that holds a substrate, and a plurality of nozzles that supply abrasive and pure water. While applying a pressing force to press the polishing head against the polishing table, the polishing head and the polishing table are rotated, and polishing is performed while supplying an abrasive. 特開２００２−０８３７８７号公報 半導体集積回路装置は、ますます微細化、高集積化が進んでいる。ＭＯＳトランジスタのゲート長は９０ｎｍ、６５ｎｍと短くなる。集積回路装置に置ける最下層配線はゲート配線である。微細化と共にゲート配線の間隔が狭くなり、配線が緻密化する。ゲート配線形成後、ＰＳＧ膜を堆積して、ゲート配線を埋め込む層間絶縁膜を形成する。従来、対向電極間に高周波電力を印加するプラズマ（ＰＥ）ＣＶＤによってＰＳＧ膜を堆積していたが、ゲート間隔の減少と共に、埋め込み性能が不足するようになり、狭い間隙を埋め込もうとすると、すが入ってしまうことがある。狭い間隙もＰＳＧ膜で充填するために、ＰＥ−ＣＶＤに代わって、誘導結合コイルに高周波電力を印加する高密度プラズマ（high density plasma, ＨＤＰ）ＣＶＤを用いるようになってきた。The semiconductor integrated circuit device is increasingly miniaturized and highly integrated. The gate length of the MOS transistor is as short as 90 nm and 65 nm. The lowermost layer wiring that can be placed in the integrated circuit device is a gate wiring. Along with miniaturization, the interval between the gate wirings becomes narrower and the wirings become denser. After the gate wiring is formed, a PSG film is deposited to form an interlayer insulating film that embeds the gate wiring. Conventionally, a PSG film has been deposited by plasma (PE) CVD that applies high-frequency power between the counter electrodes. However, as the gate interval decreases, the embedding performance becomes insufficient, and an attempt is made to embed a narrow gap. There are times when it enters. In order to fill a narrow gap with a PSG film, high density plasma (HDP) CVD that applies high frequency power to the inductive coupling coil has been used instead of PE-CVD.

本発明の目的は、ウエハレベルで層間絶縁膜の厚さの均一性に優れた半導体装置の製造方法を提供することである。   An object of the present invention is to provide a method of manufacturing a semiconductor device having excellent uniformity of thickness of an interlayer insulating film at a wafer level.

本発明の他の目的は、効率的なＣＭＰ工程を含む半導体装置の製造方法を提供することである。   Another object of the present invention is to provide a semiconductor device manufacturing method including an efficient CMP process.

本発明の他の目的は、新規な構成を有する半導体装置を提供することである。   Another object of the present invention is to provide a semiconductor device having a novel configuration.

本発明の１観点によれば、
（ａ）半導体基板上方に配線を形成する工程と、
（ｂ）工程（ａ）の後、前記配線を埋め込んで、高密度プラズマ（ＨＤＰ）化学的気相成長（ＣＶＤ）により第１の絶縁膜を堆積する工程と、
（ｃ）工程（ｂ）の後、ＨＤＰ−ＣＶＤ以外の堆積方法により、第１の絶縁膜上方に第２の絶縁膜を堆積する工程と、
（ｄ）工程(ｃ)の後、２酸化セリウム砥粒を含む研磨剤を用いた化学的機械的研磨により前記第２の絶縁膜を平坦化する工程と、
を含む半導体装置の製造方法
が提供される。 According to one aspect of the present invention,
(A) forming a wiring above the semiconductor substrate;
(B) After the step (a), a step of burying the wiring and depositing a first insulating film by high density plasma (HDP) chemical vapor deposition (CVD);
(C) After step (b), depositing a second insulating film above the first insulating film by a deposition method other than HDP-CVD;
(D) after the step (c), planarizing the second insulating film by chemical mechanical polishing using a polishing agent containing cerium dioxide abrasive grains;
A method for manufacturing a semiconductor device is provided.

本発明の他の観点によれば、
シリコン基板と、
前記シリコン基板に形成され、活性領域を画定するトレンチと、トレンチを埋め込むアンドープトシリケートガラス膜と、を含むシャロートレンチアイソレーション（ＳＴＩ）と、
前記活性領域上に形成されたゲート絶縁膜と、
前記ゲート絶縁膜上方に形成されたゲート電極と、
前記ゲート電極を覆って前記シリコン基板上方に形成され、凹凸のある表面を有する、ホスホシリケートガラス（ＰＳＧ）、又はボロホスホシリケートガラス（ＢＰＳＧ）の下層絶縁膜と、
前記下層絶縁膜上方に、ＴＥＯＳ酸化シリコン膜で形成され、平坦化された表面を有する上層絶縁膜と、
を有する半導体装置
が提供される。 According to another aspect of the invention,
A silicon substrate;
A shallow trench isolation (STI) formed in the silicon substrate and including a trench defining an active region and an undoped silicate glass film filling the trench;
A gate insulating film formed on the active region;
A gate electrode formed above the gate insulating film;
A lower insulating film of phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG), which is formed above the silicon substrate so as to cover the gate electrode and has an uneven surface;
An upper insulating film formed of a TEOS silicon oxide film and having a planarized surface above the lower insulating film;
A semiconductor device is provided.

ＨＤＰ−ＣＶＤで層間絶縁膜を堆積するとウエハレベルで厚さ変動が生じるが、ＨＤＰ−ＣＶＤと他の堆積方法を組み合わせることにより均一な厚さを有する層間絶縁膜を形成できる。   When an interlayer insulating film is deposited by HDP-CVD, the thickness varies at the wafer level. By combining HDP-CVD and another deposition method, an interlayer insulating film having a uniform thickness can be formed.

シリコン基板にトレンチを形成後、ＵＳＧ膜をＨＤＰ−ＣＶＤで堆積し、２酸化セリウム砥粒を含む研磨剤を用いたＣＭＰにより不要部を除去してＳＴＩを形成し、ゲート電極形成後にＰＳＧ膜をＨＤＰ−ＣＶＤにより堆積し、２酸化セリウム砥粒を含む研磨剤を用いて平坦化すると新たな問題が生じることが判った。   After forming a trench in a silicon substrate, a USG film is deposited by HDP-CVD, an unnecessary portion is removed by CMP using a polishing agent containing cerium dioxide oxide grains, an STI is formed, and a PSG film is formed after forming a gate electrode It has been found that new problems arise when deposited by HDP-CVD and planarized with an abrasive containing cerium dioxide abrasive grains.

以下、この問題を究明するために、本発明者が行った実験を説明する。   Hereinafter, an experiment conducted by the present inventor in order to investigate this problem will be described.

図１Ａに示すように、シリコン基板ＳＵＢ上に、酸化シリコン膜ＯＸを形成したウエハＷＡＦを作成した。酸化シリコン膜ＯＸとして３種類のサンプル、ＨＤＰ−ＣＶＤでＵＳＧ膜ＨＤＰ−ＵＳＧを堆積したサンプル、ＨＤＰ−ＣＶＤでＰＳＧ膜ＨＤＰ−ＰＳＧを堆積したサンプル、さらに層間絶縁膜等に用いられる、テトラエトキシシラン（ＴＥＯＳ）をシリコンソースとしてＰＥ−ＣＶＤでＴＥＯＳ酸化膜ＰＥ−ＴＥＯＳを堆積したサンプル、を作成した。   As shown in FIG. 1A, a wafer WAF having a silicon oxide film OX formed on a silicon substrate SUB was created. Three types of samples as silicon oxide film OX, a sample in which USG film HDP-USG is deposited by HDP-CVD, a sample in which PSG film HDP-PSG is deposited by HDP-CVD, and tetraethoxysilane used for an interlayer insulating film, etc. A sample in which a TEOS oxide film PE-TEOS was deposited by PE-CVD using (TEOS) as a silicon source was prepared.

図１Ｂは、３種類のサンプルに対して、酸化シリコン膜のウエハ内厚さ分布を測定した結果を示すグラフである。ＰＥ−ＣＶＤでＴＥＯＳ酸化膜を形成したサンプルＰＥ−ＴＥＯＳの膜厚分布はウエハのほぼ全面で約５８０ｎｍの値を示し、極めて均一性が高い。ＨＤＰ−ＣＶＤで酸化シリコン膜を形成した２つのサンプルＨＤＰ−ＵＳＧ，ＨＤＰ−ＰＳＧの膜厚分布はウエハレベルでほぼ同じ変動を示した。ウエハ中央部で約５７０ｎｍと薄く、周辺に向かって次第に厚くなり、最大値、約５９２ｎｍ、を示した後周縁部に向かって５８５ｎｍ以下まで薄くなる略Ｍ字型分布を示している。   FIG. 1B is a graph showing the results of measuring the in-wafer thickness distribution of the silicon oxide film for three types of samples. The film thickness distribution of the sample PE-TEOS in which the TEOS oxide film is formed by PE-CVD shows a value of about 580 nm over almost the entire surface of the wafer, and the uniformity is extremely high. The film thickness distributions of the two samples HDP-USG and HDP-PSG in which the silicon oxide film was formed by HDP-CVD showed almost the same fluctuation at the wafer level. A substantially M-shaped distribution is shown which is as thin as about 570 nm at the wafer central portion, gradually increases toward the periphery, and becomes thinner to 585 nm or less toward the rear peripheral portion showing the maximum value of about 592 nm.

このＭ字型分布は、ウエハレベルでの大きな緩やかな変化であり、局部的には変動していない。局部的な厚さ変化はＣＭＰで平坦化できるが、このような広い面積における緩やかな厚さ分布は、ＣＭＰで平坦化することはできないと予想される。   This M-shaped distribution is a large gradual change at the wafer level and does not fluctuate locally. Although local thickness variations can be planarized by CMP, it is expected that such a gradual thickness distribution over a large area cannot be planarized by CMP.

ウエハ中央部から作成したチップにおいては、層間絶縁膜が薄く、ウエハ周辺部から作成したチップにおいては層間絶縁膜が厚くなってしまう。層間絶縁膜を貫通するコンタクト孔をエッチングする場合は周辺部でもコンタクト孔が貫通するように、中央部では多めのオーバーエッチングをすることになる。コンタクト孔に導電性プラグを埋め込むと、中央部から作成したチップの導電性プラグは短く、接続抵抗は低く、周辺部から作成したチップの導電性プラグは長く、接続抵抗は高くなることになる。プロセス及び製品の信頼性を高めるためには、ウエハレベルの厚さ変動は、なるべく抑制することが望まれる。次に３種類のサンプルに対し、セリア砥粒と界面活性剤を含むスラリを用いて研磨を行った。   In a chip formed from the wafer central portion, the interlayer insulating film is thin, and in a chip formed from the wafer peripheral portion, the interlayer insulating film is thick. When etching a contact hole penetrating the interlayer insulating film, a large amount of over-etching is performed in the central portion so that the contact hole also penetrates in the peripheral portion. When the conductive plug is embedded in the contact hole, the conductive plug of the chip formed from the central portion is short, the connection resistance is low, the conductive plug of the chip formed from the peripheral portion is long, and the connection resistance is high. In order to increase the reliability of processes and products, it is desirable to suppress the wafer level thickness variation as much as possible. Next, the three types of samples were polished using a slurry containing ceria abrasive grains and a surfactant.

図２Ａは、研磨装置の構成を概略的に示す。研磨テーブル１０２の上には研磨パッド１０４が設けられている。ウエハＷＡＦは、酸化シリコン膜を下にして研磨ヘッド１１２に支持した。ノズル１２４ａから研磨テーブル上にスラリを滴下し、研磨ヘッドに圧力を印加し、研磨テーブル１０２、研磨ヘッド１１２を反時計回りに回転させて研磨を行った。   FIG. 2A schematically shows the configuration of the polishing apparatus. A polishing pad 104 is provided on the polishing table 102. The wafer WAF was supported by the polishing head 112 with the silicon oxide film facing down. Slurry was dropped from the nozzle 124a onto the polishing table, pressure was applied to the polishing head, and polishing was performed by rotating the polishing table 102 and the polishing head 112 counterclockwise.

図２Ｂは、同一のスラリを用いて３種類のサンプルを１分ＣＭＰした時の研磨レートを示す。縦軸が研磨レートを単位ｎｍ／ｍiｎで示す。研磨前後の膜厚を測定して、膜厚減少量を研磨時間で除算して研磨レートを算出した。研磨条件は以下の通りである。
研磨ヘッド圧力：２００ｇ重／ｃｍ２、
研磨ヘッド回転数：１００回転／分、
研磨テーブル回転数：１００回転／分、
セリアスラリ供給量：０．２リットル／分。 FIG. 2B shows the polishing rate when three types of samples are CMPed for 1 minute using the same slurry. The vertical axis represents the polishing rate in units of nm / min. The film thickness before and after polishing was measured, and the polishing rate was calculated by dividing the decrease in film thickness by the polishing time. The polishing conditions are as follows.
Polishing head pressure: 200 g weight / cm 2
Polishing head rotation speed: 100 rotations / minute,
Polishing table rotation speed: 100 rotations / minute,
Ceria slurry supply rate: 0.2 l / min.

なお、研磨パッドは、ニッタハース社製のＩＣ１４００Ｋ溝タイプ、セリアスラリはデュポンエアープロダクトナノマテリアル社製のマイクロプレーナＳＴＩ２１００ ＲＡ９を用いた。膜厚測定は、ＫＬＡ−ＴＥＮＣＯＲ社製の膜厚測定装置ＡＳＥＴ Ｆ５ｘを用いて行った。   The polishing pad used was an IC1400K groove type manufactured by Nitta Haas, and the ceria slurry used was a microplanar STI2100 RA9 manufactured by DuPont Air Products Nanomaterials. The film thickness measurement was performed using a film thickness measuring apparatus ASET F5x manufactured by KLA-TENCOR.

ＨＤＰ‐ＵＳＧ膜の研磨レートは、１２ｎｍ／ｍｉｎ、ＰＥ−ＴＥＯＳ膜の研磨レートは１４ｎｍ／ｍｉｎで、共に極めて低く、研磨はほとんど進行していない。平坦な被研磨膜を研磨した時の、ポリアクリル酸アンモニウム塩を含むセリアスラリの特徴である、オートストップ性が働いていることが判る。ＨＤＰ−ＰＳＧ膜の研磨レートは、平均値で２１０ｎｍ／ｍｉｎとなった。１２ｎｍ／ｍｉｎ、１４ｎｍ／ｍｉｎと比べると極めて高く、オートストップ性が働いていないことが判る。   The polishing rate of the HDP-USG film is 12 nm / min and the polishing rate of the PE-TEOS film is 14 nm / min, both of which are extremely low, and the polishing hardly progresses. It can be seen that the auto-stop property, which is a feature of the ceria slurry containing the ammonium polyacrylate, is worked when a flat film to be polished is polished. The average polishing rate of the HDP-PSG film was 210 nm / min. Compared to 12 nm / min and 14 nm / min, it is extremely high, and it can be seen that the auto-stop function does not work.

図２Ｃは、セリアスラリ中のポリアクリル酸アンモニウム塩の量を変えた時のＨＤＰ−ＰＳＧ膜の研磨レートを示す。左側の低濃度は図２Ｂの場合と同濃度の場合であり、右側の高濃度はポリアクリル酸アンモニウム塩の量を約１０倍程度に増加した場合である。ポリアクリル酸アンモニウム塩の量を１０倍程度に増加するとＨＤＰ−ＰＳＧ膜に対してもオートストップ性が働くようになる。   FIG. 2C shows the polishing rate of the HDP-PSG film when the amount of polyacrylic acid ammonium salt in the ceria slurry is changed. The low concentration on the left is the same as in FIG. 2B, and the high concentration on the right is when the amount of ammonium polyacrylate is increased about 10 times. When the amount of ammonium polyacrylate is increased to about 10 times, the auto-stopping property also works for the HDP-PSG film.

図２Ｂ，２Ｃの結果から、ＨＤＰ‐ＵＳＧ膜とＨＤＰ−ＰＳＧ膜とをポリアクリル酸アンモニウム塩を含むセリアスラリでＣＭＰしようとすると、ポリアクリル酸アンモニウム塩の量を大幅に変えなくてはならないことが判る。ＳＴＩの埋め込み酸化膜をＨＤＰ−ＵＳＧ膜で形成し、ゲート電極上の層間絶縁膜をＨＤＰ−ＰＳＧ膜で形成すると、それぞれに対するＣＭＰは異なるものとしなくてはならない。１つの研磨装置で行うＣＭＰを１種類に固定すると、２種類のＣＭＰを行うために２台の研磨装置が必要になってしまう。   From the results shown in FIGS. 2B and 2C, when the HDP-USG film and the HDP-PSG film are to be CMPed with ceria slurry containing ammonium polyacrylate, the amount of ammonium polyacrylate must be significantly changed. I understand. When the buried oxide film of STI is formed of an HDP-USG film and the interlayer insulating film on the gate electrode is formed of an HDP-PSG film, the CMP for each must be different. If CMP performed by one polishing apparatus is fixed to one type, two polishing apparatuses are required to perform two types of CMP.

ところで、ＰＥ−ＴＥＯＳ膜の研磨レートは、ＨＤＰ−ＵＳＧ膜の研磨レートとほとんど変わらない。ＨＤＰ−ＵＳＧ膜とＰＥ−ＴＥＯＳ膜とをＣＭＰするのであれば、同一種のセリアスラリを用いて同一条件で実行できる。しかし、ＰＥ−ＴＥＯＳ膜は、埋め込み特性が劣り、ゲート電極を埋め込む層間絶縁膜をＰＥ−ＴＥＯＳ膜で形成することはできない。   By the way, the polishing rate of the PE-TEOS film is almost the same as the polishing rate of the HDP-USG film. If the HDP-USG film and the PE-TEOS film are to be CMPed, the same kind of ceria slurry can be used under the same conditions. However, the PE-TEOS film has inferior embedding characteristics, and an interlayer insulating film for embedding the gate electrode cannot be formed of the PE-TEOS film.

そこで、ゲート電極を埋め込む層間絶縁膜をＨＤＰ−ＰＳＧ膜とＰＥ−ＴＥＯＳ膜との積層で形成することを考えた。ＨＤＰ−ＰＳＧ膜でゲート電極を埋め込み、その上にＰＥ−ＴＥＯＳ膜を積層し、研磨対象はＰＥ−ＴＥＯＳ膜とする。   In view of this, an interlayer insulating film for embedding the gate electrode was considered to be formed by stacking an HDP-PSG film and a PE-TEOS film. A gate electrode is embedded with an HDP-PSG film, a PE-TEOS film is laminated thereon, and a polishing target is a PE-TEOS film.

図３Ａ−３Ｇは本発明の実施例による半導体装置の製造方法を示す半導体ウエハの一部断面図である。   3A to 3G are partial cross-sectional views of a semiconductor wafer showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

図３Ａに示すように、シリコンウエハである半導体基板１０の表面を熱酸化し、厚さ１０ｎｍ程度の酸化シリコン膜１２を形成する。酸化シリコン膜１２上に、化学気相成長（ＣＶＤ）により、窒化シリコン膜１３を厚さ１００ｎｍ程度堆積する。ホトリソグラフィとエッチングにより、窒化シリコン膜１３、酸化シリコン膜１２に半導体基板１０表面を露出する開口１４を形成する。ここでホトリソグラフィで形成したレジストパターンを除去してもよい。少なくとも開口１４の形成された窒化シリコン膜１３をマスクとして、半導体基板１０をリアクティブイオンエッチング（ＲＩＥ）により異方的にエッチングし、例えば窒化シリコン膜１３表面からの深さ３００ｎｍ程度のトレンチ１５を形成する。トレンチ側面は傾斜させる条件でエッチングすることが好ましい。   As shown in FIG. 3A, the surface of the semiconductor substrate 10 which is a silicon wafer is thermally oxidized to form a silicon oxide film 12 having a thickness of about 10 nm. A silicon nitride film 13 is deposited on the silicon oxide film 12 to a thickness of about 100 nm by chemical vapor deposition (CVD). An opening 14 exposing the surface of the semiconductor substrate 10 is formed in the silicon nitride film 13 and the silicon oxide film 12 by photolithography and etching. Here, the resist pattern formed by photolithography may be removed. The semiconductor substrate 10 is anisotropically etched by reactive ion etching (RIE) using at least the silicon nitride film 13 in which the openings 14 are formed as a mask. For example, a trench 15 having a depth of about 300 nm from the surface of the silicon nitride film 13 is formed. Form. It is preferable to etch the side surface of the trench under an inclined condition.

図３Ｂに示すように、トレンチ表面に露出したシリコン表面を熱酸化し、例えば厚さ１〜５ｎｍ程度の酸化シリコン膜（ライナ）１７を形成する。酸化シリコン膜１７、窒化シリコン膜１３の表面を覆うように、例えば厚さ２〜８ｎｍ程度の窒化シリコン膜（ライナ）１８を低圧（ＬＰ）ＣＶＤにより堆積する。厚さ１〜５ｎｍ程度の酸化シリコン膜は、希フッ酸が浸入しにくい厚さであり、厚さ２〜８ｎｍ程度の窒化シリコン膜は、熱燐酸が浸入しにくい厚さである。窒化シリコン膜１８を形成した半導体基板上に、高密度プラズマ（ＨＤＰ）ＣＶＤにより、例えば厚さ４５０ｎｍ程度の酸化シリコン膜２０を堆積する。トレンチ１５内は酸化シリコン膜２０で埋め込まれる。窒化シリコン膜１３（及び窒化シリコン膜１８）表面より上の酸化シリコン膜２０が被研磨膜となる。   As shown in FIG. 3B, the silicon surface exposed on the trench surface is thermally oxidized to form a silicon oxide film (liner) 17 having a thickness of about 1 to 5 nm, for example. For example, a silicon nitride film (liner) 18 having a thickness of about 2 to 8 nm is deposited by low pressure (LP) CVD so as to cover the surfaces of the silicon oxide film 17 and the silicon nitride film 13. The silicon oxide film having a thickness of about 1 to 5 nm has a thickness that makes it difficult for dilute hydrofluoric acid to enter, and the silicon nitride film having a thickness of about 2 to 8 nm has a thickness that makes it difficult for hot phosphoric acid to enter. On the semiconductor substrate on which the silicon nitride film 18 is formed, a silicon oxide film 20 having a thickness of, for example, about 450 nm is deposited by high density plasma (HDP) CVD. The trench 15 is filled with a silicon oxide film 20. The silicon oxide film 20 above the surface of the silicon nitride film 13 (and the silicon nitride film 18) becomes a film to be polished.

なお、ウエハの大型化と共に、ＳＴＩ用の酸化シリコン膜をウエハ全面でＣＭＰにより除去することが必ずしも容易でなくなった。ウエハ中央部にＣＭＰ残が残り、欠陥チップとなることがある。   As the size of the wafer increases, it becomes not always easy to remove the silicon oxide film for STI by CMP on the entire surface of the wafer. A CMP residue may remain in the center of the wafer, resulting in a defective chip.

図２Ａに示す研磨装置を用い、半導体基板１０を、被研磨膜２０が下になるように、研磨ヘッド１１２により支持する。研磨ヘッド１１２を回転させながら降下させ、ノズル１２４ａからセリア砥粒と添加剤を含む研磨剤を供給しつつ、回転する研磨テーブル１０２の研磨パッド１０４上に半導体基板１０を押し付ける。   Using the polishing apparatus shown in FIG. 2A, the semiconductor substrate 10 is supported by the polishing head 112 so that the film to be polished 20 faces down. The polishing head 112 is lowered while rotating, and the semiconductor substrate 10 is pressed onto the polishing pad 104 of the rotating polishing table 102 while supplying a polishing agent containing ceria abrasive grains and additives from the nozzle 124a.

図３Ｃに示すように、表面の凹凸が消滅するまでのメイン研磨を行い、被研磨膜２０の表面を平坦化する。メイン研磨は、例えば以下の条件で行えばよい。
研磨ヘッドを研磨パッドに押し付ける圧力：１００〜５００ｇ重／ｃｍ２、例えば２１０ｇ重／ｃｍ２、
研磨ヘッドの回転数：７０〜１５０回転／分、例えば１４２回転／分、
研磨テーブルの回転数：７０〜１５０回転／分、例えば１４０回転／分、
研磨剤:純水中に、研磨砥粒としてセリア砥粒、添加剤としてポリアクリル酸アンモニウム塩を含む研磨剤（例えば、デュポンエアプロダクトナノマテリアル社製、型番Ｍｉｃｒｏ Ｐｌａｎｅｒ ＳＴＩ２１００）、
研磨剤の供給量：０．１〜０．３リットル／分、例えば０．１５リットル／分、
研磨剤の供給位置:研磨テーブル（研磨パッド）中央。 As shown in FIG. 3C, main polishing is performed until the surface unevenness disappears, and the surface of the polishing target film 20 is flattened. For example, the main polishing may be performed under the following conditions.
The pressure presses the polishing head to the polishing pad: 100 to 500 g weight / cm 2, for example, 210g weight / cm 2,
The number of revolutions of the polishing head: 70 to 150 revolutions / minute, for example 142 revolutions / minute,
The number of rotations of the polishing table: 70 to 150 rotations / minute, for example, 140 rotations / minute,
Abrasive: Abrasive containing pure ceria abrasive as polishing abrasive and ammonium polyacrylate as additive (for example, DuPont Air Product Nanomaterials, model number Micro Planer STI2100),
Abrasive supply amount: 0.1 to 0.3 liter / minute, for example 0.15 liter / minute,
Abrasive supply position: center of polishing table (polishing pad).

メイン研磨が終了し、酸化シリコン膜２０表面が平坦化したら、ノズル１２４ｂから純水を供給し、研磨剤を流し去る。半導体基板表面に付着した添加剤は、この純水洗い流し工程のみでは除去しきれない可能性がある。   When the main polishing is completed and the surface of the silicon oxide film 20 is flattened, pure water is supplied from the nozzle 124b and the polishing agent is poured away. There is a possibility that the additive adhering to the surface of the semiconductor substrate cannot be removed only by this pure water washing step.

次に、仕上げ研磨の予備研磨を行う。仕上げ研磨の予備研磨は、例えばノズル１２４ｃから研磨パッド中央上にシリカベースの研磨剤を供給して行う。シリカベースの研磨剤としては、例えばキャボット社製の型番ＳＥＭＩ ＳＰＲＥＳ ２５の研磨剤を用いることができる。研磨ヘッド１１２を回転させながら、回転する研磨テーブル１０２の研磨パッド１０４上に押し付ける。仕上げ研磨の予備研磨は、例えば以下の条件で行えばよい。
研磨圧力：１００〜５００ｇ重／ｃｍ２、たとえば２１０ｇ重／ｃｍ２、
研磨ヘッドの回転数：７０〜１５０回転／分、例えば１２２回転／分、
研磨テーブルの回転数：７０〜１５０回転／分、例えば１２０回転／分、
研磨剤の供給量：０．０５〜０．３リットル／分、例えば０．１リットル／分、
研磨量（時間）：膜厚１０ｎｍ以下、例えば５秒程度
仕上げ研磨の予備研磨は、被研磨膜表面を浅く除去することにより、付着している可能性のある添加剤を除去することであり、窒化シリコン膜１８，１３は露出させないことが好ましい。 Next, preliminary polishing for final polishing is performed. The preliminary polishing for the final polishing is performed, for example, by supplying a silica-based polishing agent from the nozzle 124c to the center of the polishing pad. As the silica-based abrasive, for example, an abrasive of model number SEMI SPRES 25 manufactured by Cabot Corporation can be used. While rotating the polishing head 112, the polishing head 112 is pressed onto the polishing pad 104 of the rotating polishing table 102. The preliminary polishing for the final polishing may be performed, for example, under the following conditions.
Polishing pressure: 100~500g heavy / cm 2, for example, 210g weight / cm 2,
The rotational speed of the polishing head: 70 to 150 revolutions / minute, for example, 122 revolutions / minute,
The number of rotations of the polishing table: 70 to 150 rotations / minute, for example, 120 rotations / minute,
Abrasive supply amount: 0.05 to 0.3 liter / minute, for example, 0.1 liter / minute,
Polishing amount (time): film thickness of 10 nm or less, for example, preliminary polishing for final polishing for about 5 seconds is to remove an additive that may be adhered by removing the surface of the film to be polished shallowly, The silicon nitride films 18 and 13 are preferably not exposed.

予備研磨の後、ノズル１２４ｂから純水を例えば１０秒程度供給し、シリカベースの研磨剤を流し去る。シリカベースの研磨剤が残ると、仕上げ研磨の選択性が劣化し得る。   After preliminary polishing, pure water is supplied from the nozzle 124b for about 10 seconds, for example, and the silica-based abrasive is poured away. If the silica-based abrasive remains, the selectivity of finish polishing can be degraded.

その後、図３Ｄに示すように、仕上げ研磨の本研磨を、ノズル１２４ａからセリアベースの研磨剤、ノズル１２４ｂから純水を供給して行う。例えば、セリアベースの研磨剤は研磨パッドの中央に、純水はそれより外側で供給する。但し、供給位置は、これに限定されない。研磨ヘッド、研磨パッドは共に回転させる。   Thereafter, as shown in FIG. 3D, final polishing for final polishing is performed by supplying a ceria-based abrasive from the nozzle 124a and pure water from the nozzle 124b. For example, the ceria-based abrasive is supplied in the center of the polishing pad, and the pure water is supplied outside. However, the supply position is not limited to this. Both the polishing head and the polishing pad are rotated.

仕上げ研磨の本研磨は、例えば以下の条件で行う。
研磨圧力：１００〜５００ｇ重／ｃｍ２、例えば２１０ｇ重／ｃｍ２、
研磨ヘッドの回転数：７０〜１５０回転／分、例えば１２２回転／分、
研磨テーブルの回転数：７０〜１５０回転／分、例えば１２０回転／分、
研磨剤の供給量：０．０５〜０．３リットル／分、例えば０．０５リットル／分、
純水供給量：０．０５〜０．３リットル／分、例えば０．１５リットル／分、
研磨量（時間）：窒化シリコン膜を露出させるまで、例えば６０秒程度。 For example, the final polishing is performed under the following conditions.
Polishing pressure: 100 to 500 g weight / cm 2, for example, 210g weight / cm 2,
The number of revolutions of the polishing head: 70 to 150 revolutions / minute, for example, 122 revolutions / minute,
The number of rotations of the polishing table: 70 to 150 rotations / minute, for example, 120 rotations / minute,
Abrasive supply amount: 0.05 to 0.3 liter / minute, for example 0.05 liter / minute,
Pure water supply amount: 0.05 to 0.3 liter / minute, for example, 0.15 liter / minute,
Polishing amount (time): For example, about 60 seconds until the silicon nitride film is exposed.

なお、仕上げ研磨の本研磨の条件は上記に限定されるものではない。窒化シリコン膜１３（窒化シリコン膜１８）上の酸化シリコン膜が除去され、窒化シリコン膜が露出する状態とできればよい。薄い窒化シリコン膜１８は除去されても、残ってもよい。   Note that the conditions of the final polishing of the final polishing are not limited to the above. It suffices if the silicon oxide film on the silicon nitride film 13 (silicon nitride film 18) is removed and the silicon nitride film is exposed. The thin silicon nitride film 18 may be removed or left.

図３Ｅに示すように、例えば熱燐酸で窒化シリコン膜１３（１８）をエッチングし、希フッ酸で酸化シリコン膜１２をエッチングする。埋め込み酸化シリコン膜２０、半導体基板１０に挟まれた酸化シリコン膜１７、窒化シリコン膜１８はエッチングしないことが。好ましい、上述の膜厚とすれば、エッチング液が進入しにくいのでエッチングを抑制できる。   As shown in FIG. 3E, the silicon nitride film 13 (18) is etched with, for example, hot phosphoric acid, and the silicon oxide film 12 is etched with dilute hydrofluoric acid. The embedded silicon oxide film 20, the silicon oxide film 17 and the silicon nitride film 18 sandwiched between the semiconductor substrates 10 may not be etched. If the above-described film thickness is preferable, etching can be suppressed because the etchant hardly enters.

このように、仕上げ研磨の本研磨前に仕上げ研磨の予備研磨を物理的研磨で行うことにより、ウエハ表面に添加剤が付着していても、その添加剤を確実に除去することができる。大口径ウエハでも全面の酸化シリコン膜を残なく除去できるようになる。   Thus, by performing the preliminary polishing of the final polishing by physical polishing before the final polishing of the final polishing, even if the additive is attached to the wafer surface, the additive can be surely removed. Even with a large-diameter wafer, the entire silicon oxide film can be removed.

図３Ｆに示すように、レジストマスクを用いて、半導体基板にイオン注入を行いｐチャネルトランジスタ用ｎ型ウェルＮＷ，ｎチャネルトランジスタ用ｐ型ウェルＰＷを作成する。ＳＴＩで画定された活性領域表面を熱酸化し、酸化シリコン膜を形成し、さらに窒素処理を行って窒素を導入し、窒化酸化シリコン膜とする。窒化酸化シリコン膜の上に厚さ１００〜２００ｎｍ、例えば厚さ１８０ｎｍの多結晶シリコン膜を熱ＣＶＤで堆積し、レジストパターンを用いてパターニングする。このようにして、絶縁ゲート電極が形成される。ｐチャネルトランジスタ領域にｐ型不純物、ｎチャネルトランジスタ領域にｎ型不純物を低加速エネルギ、低濃度でイオン注入し、浅いエクステンションを形成する。酸化シリコン等でサイドウォールＳＷを形成した後、ｐチャネルトランジスタ領域にｐ型不純物、ｎチャネルトランジスタ領域にｎ型不純物を高濃度でイオン注入し、低抵抗ソース／ドレイン領域Ｓ／Ｄｐ，Ｓ／Ｄｎを形成する。このようにして、ＣＭＯＳ構造が形成される。   As shown in FIG. 3F, using a resist mask, ions are implanted into the semiconductor substrate to form a p-channel transistor n-type well NW and an n-channel transistor p-type well PW. The surface of the active region defined by STI is thermally oxidized to form a silicon oxide film, and further nitrogen treatment is performed to introduce nitrogen to form a silicon nitride oxide film. A polycrystalline silicon film having a thickness of 100 to 200 nm, for example, 180 nm is deposited on the silicon nitride oxide film by thermal CVD and patterned using a resist pattern. In this way, an insulated gate electrode is formed. A p-type impurity is implanted into the p-channel transistor region and an n-type impurity is ion-implanted into the n-channel transistor region with a low acceleration energy and a low concentration to form a shallow extension. After the sidewall SW is formed of silicon oxide or the like, p-type impurities are implanted into the p-channel transistor region and n-type impurities are ion-implanted at a high concentration into the n-channel transistor region, so that the low resistance source / drain regions S / Dp, S / Dn Form. In this way, a CMOS structure is formed.

ゲート電極を埋め込むように、ゲート電極の厚さ以上の厚さ、例えば厚さ２００ｎｍのＰＳＧ膜４１をＨＤＰ−ＣＶＤで堆積し、ゲート電極間のスペースを埋め込む。ＰＥ−ＣＶＤでなく、ＨＤＰ−ＣＶＤを用いるので埋め込み特性がよく、ゲート電極間のスペースももれなく埋め込まれる。ＰＳＧ膜４１の表面は、ゲート電極を反映した凹凸を示す。   A PSG film 41 having a thickness equal to or greater than the thickness of the gate electrode, for example, a thickness of 200 nm is deposited by HDP-CVD so as to embed the gate electrode, and a space between the gate electrodes is buried. Since HDP-CVD is used instead of PE-CVD, the embedding characteristics are good, and the space between the gate electrodes is completely buried. The surface of the PSG film 41 shows irregularities reflecting the gate electrode.

図３Ｇに示すように、ＰＳＧ膜４１の上に、ＰＥ−ＣＶＤによりＴＥＯＳ酸化膜４２を例えば厚さ２５０ｎｍ堆積する。ＨＤＰ−ＰＳＧ膜４１表面は、下地表面の曲率やアスペクト比を緩和しているので、埋め込み特性の劣るＰＥ−ＣＶＤでも埋め込み特性で問題は生じない。ＨＤＰ−ＰＳＧ膜４１とＰＥ−ＴＥＯＳ膜４２の積層で層間絶縁膜４０が形成される。なお、比較例として、ＨＤＰ−ＰＳＧ膜単層で層間絶縁膜４０を形成したサンプルも作成した。この状態でウエハ上の層間絶縁膜の膜厚分布を調査した。   As shown in FIG. 3G, a TEOS oxide film 42 is deposited to a thickness of, for example, 250 nm on the PSG film 41 by PE-CVD. Since the surface of the HDP-PSG film 41 relaxes the curvature and aspect ratio of the underlying surface, there is no problem with the embedding characteristics even in PE-CVD having inferior embedding characteristics. An interlayer insulating film 40 is formed by stacking the HDP-PSG film 41 and the PE-TEOS film 42. As a comparative example, a sample in which the interlayer insulating film 40 was formed with a single HDP-PSG film was also prepared. In this state, the film thickness distribution of the interlayer insulating film on the wafer was investigated.

図３Ｈは、膜厚分布の測定結果を示す。ＨＤＰ−ＰＳＧ膜単層で層間絶縁膜４０を形成したサンプルの膜厚分布は、図１Ｂに示した膜厚分布同様のＭ字型分布を示し、ウエハ中央で約４４０ｎｍ、周辺に向かうに従って増大し最大値約４６２ｎｍを示した後、周縁に向かって減少し、約４５３ｎｍとなった。   FIG. 3H shows the measurement result of the film thickness distribution. The film thickness distribution of the sample in which the interlayer insulating film 40 is formed of a single HDP-PSG film film shows an M-shaped distribution similar to the film thickness distribution shown in FIG. 1B, and increases toward the periphery by about 440 nm at the wafer center. After showing the maximum value of about 462 nm, it decreased toward the periphery and became about 453 nm.

ＨＤＰ−ＰＳＧ膜４１とＰＥ−ＴＥＯＳ膜４２の積層で層間絶縁膜４０を形成したサンプルの膜厚分布は、ウエハのほぼ全面で約４５０ｎｍのほぼフラットな安定した値を示した。原因は不明であるが、ＨＤＰ−ＣＶＤ膜とＰＥ−ＣＶＤ膜とを積層することにより、平坦な表面を得ることができた。そこで、下層層間絶縁膜４１の厚さを変化させ、層間絶縁膜４０の膜厚分布を調べてみた。   The film thickness distribution of the sample in which the interlayer insulating film 40 was formed by stacking the HDP-PSG film 41 and the PE-TEOS film 42 showed a substantially flat and stable value of about 450 nm over almost the entire surface of the wafer. Although the cause is unknown, a flat surface could be obtained by laminating an HDP-CVD film and a PE-CVD film. Therefore, the thickness distribution of the interlayer insulating film 40 was examined by changing the thickness of the lower interlayer insulating film 41.

図４は、膜厚分布の測定結果を示すグラフである。配線(ゲート電極)の厚さを基準とし、配線高さ以上のＰＳＧ膜４１をＨＤＰ−ＰＳＧで堆積し、その上にＰＥ−ＣＶＤでＴＥＯＳ酸化膜を堆積した。横軸は、配線高さに対するＨＤＰ−ＰＳＧ膜厚の比を示す。縦軸は、膜厚のばらつきを任意単位で示す。配線高さに対する倍数が２．５以上の領域では倍数にほぼ比例してばらつきが増加するようである。倍数が２以下の領域では、倍数の減少と共に減少するばらつきが小さくなっている。膜厚のばらつきを抑制するためには、配線高さの２倍以下、好ましくは１．５倍以下の厚さのＨＤＰ―ＰＳＧ膜を形成するのが好ましいであろう。   FIG. 4 is a graph showing the measurement results of the film thickness distribution. Based on the thickness of the wiring (gate electrode), a PSG film 41 having a height higher than the wiring height was deposited by HDP-PSG, and a TEOS oxide film was deposited thereon by PE-CVD. The horizontal axis indicates the ratio of the HDP-PSG film thickness to the wiring height. The vertical axis shows the film thickness variation in arbitrary units. In the region where the multiple of the wiring height is 2.5 or more, the variation seems to increase almost in proportion to the multiple. In the region where the multiple is 2 or less, the variation that decreases as the multiple decreases is small. In order to suppress variations in the film thickness, it is preferable to form an HDP-PSG film having a thickness of 2 times or less, preferably 1.5 times or less the wiring height.

図５Ａに示すように、ＨＤＰ−ＰＳＧ膜４１とＰＥ−ＴＥＯＳ膜４２の積層で形成された層間絶縁膜４０を２ステップで研磨する。まず層間絶縁膜４０表面の凹凸が消滅するまでの第１のステップの研磨を行う。図中Ｐ１の面まで研磨される。この研磨は、オートストップ性の働くＣＭＰで行う。具体的な研磨の条件は以下の通りとした。
研磨ヘッド圧力：２００ｇ重；
研磨ヘッド回転数：１００回転／分；
研磨テーブル回転数：１００回転／分；
セリアスラリ供給量：０．２リットル／分。
なお、研磨に用いた研磨パッドはニッタハース社製のＩＣ１４００ Ｋ溝タイプ、セリアスラリはデュポンエアープロダクトナノマテリアル社製のマイクロプレーナＳＴＩ２１００ＲＡ ９を用いた。研磨時間は１００秒とした。 As shown in FIG. 5A, the interlayer insulating film 40 formed by stacking the HDP-PSG film 41 and the PE-TEOS film 42 is polished in two steps. First, polishing in the first step until the unevenness on the surface of the interlayer insulating film 40 disappears is performed. Polishing is performed up to the surface P1 in the figure. This polishing is performed by CMP with an auto-stop function. The specific polishing conditions were as follows.
Polishing head pressure: 200 g weight;
Polishing head rotation speed: 100 rotations / minute;
Polishing table rotation speed: 100 rotations / minute;
Ceria slurry supply rate: 0.2 l / min.
The polishing pad used for polishing was an IC1400 K groove type manufactured by Nitta Haas, and the ceria slurry used was a microplanar STI2100RA9 manufactured by DuPont Air Products Nanomaterials. The polishing time was 100 seconds.

研磨は、被研磨膜を消費すると共に、研磨面にスクラッチも与える。オートストップ性が働くと、被研磨面の消費は急激に減少する。しかし研磨面に与えるスクラッチはほとんど変化しない。被研磨面が消費されれば、一度形成されたスクラッチも消費されていくが、研磨面が消費されないと、スクラッチはどんどん蓄積されることになる。   Polishing consumes a film to be polished and also gives scratches to the polished surface. When the auto stop function is activated, the consumption of the surface to be polished decreases rapidly. However, the scratch applied to the polished surface hardly changes. If the surface to be polished is consumed, the scratch once formed is also consumed, but if the surface to be polished is not consumed, scratches are accumulated more and more.

第２の研磨ステップは、オートストップ性を緩和して、ある程度研磨レートの出る条件でスクラッチを減少させる研磨である。オートストップ性を緩和するため、セリアスラリの供給量を減少し、水を供給しながら面Ｐ２まで研磨を行った。具体的な研磨条件は以下の通りとした。
研磨ヘッド圧力：２００ｇ重；
研磨ヘッド回転数：１００回転／分；
研磨テーブル回転数：１００回転／分；
セリアスラリ供給量：０．１リットル／分；
水供給量：０．３５リットル／分。
なお、研磨に用いた研磨パッドはニッタハース社製のＩＣ１４００ Ｋ溝タイプ、セリアスラリはデュポンエアープロダクトナノマテリアル社製のマイクロプレーナＳＴＩ２１００ＲＡ ９を用いた。第１ステップで用いたセリアスラリと同一種のスラリである。研磨テーブル上でセリアスラリの希釈を行った。あらかじめ希釈したスラリを用いるよりもコストが安くなる。第２ステップの研磨レートは１００ｎｍ／分であった。 The second polishing step is polishing that reduces the scratches under conditions where a certain polishing rate is obtained by reducing the auto-stop property. In order to alleviate the auto-stop property, the amount of ceria slurry supplied was reduced, and polishing was performed to the surface P2 while supplying water. Specific polishing conditions were as follows.
Polishing head pressure: 200 g weight;
Polishing head rotation speed: 100 rotations / minute;
Polishing table rotation speed: 100 rotations / minute;
Ceria slurry supply rate: 0.1 liter / min;
Water supply: 0.35 liter / min.
The polishing pad used for polishing was an IC1400 K groove type manufactured by Nitta Haas, and the ceria slurry used was a microplanar STI2100RA9 manufactured by DuPont Air Products Nanomaterials. This is the same type of slurry as the ceria slurry used in the first step. The ceria slurry was diluted on the polishing table. Cost is lower than using pre-diluted slurry. The polishing rate in the second step was 100 nm / min.

図５Ｂに示すように、純水を供給するノズル１２４ｂを、セリアスラリを供給するノズル１２４ａより研磨テーブル中心からより外側に配置して、研磨テーブル上でセリアスラリを希釈した。   As shown in FIG. 5B, the nozzle 124b for supplying pure water was disposed more outward from the center of the polishing table than the nozzle 124a for supplying ceria slurry, and the ceria slurry was diluted on the polishing table.

図５Ｃは、第１ステップ終了後と第２ステップ終了後のスクラッチ数を示す。左側が、第１ステップの研磨後のスクラッチ数を示す。３００個とかなり多いスクラッチが形成されている。右側が、第２ステップ終了後のスクラッチ数を示す。第１ステップ後のスクラッチ数が約３００であったのに対し、第２ステップ後のスクラッチ数は約１０と大幅に減少した。   FIG. 5C shows the number of scratches after the first step and after the second step. The left side shows the number of scratches after polishing in the first step. As many as 300 scratches are formed. The right side shows the number of scratches after the end of the second step. While the number of scratches after the first step was about 300, the number of scratches after the second step was greatly reduced to about 10.

図５Ｄは、研磨終了後の膜厚分布を示す。比較サンプル（ＨＤＰ−ＣＶＤで形成したＰＳＧ単層の層間絶縁膜）の膜厚分布も示す。比較サンプルにおいては、ウエハ中央での膜厚は約３１６ｎｍであり、周辺に向かって約３３２ｎｍまで厚くなり、その後減少して約３２３ｎｍを示している。Ｍ字型分布が継続している。実施例による層間絶縁膜は、ウエハのほぼ全面で約３２０ｎｍの安定した膜厚を示している。実施例の積層層間絶縁膜によりウエハ全体としての厚さの変動が防止されることが判る。また、ＳＴＩのＣＭＰにもちいたセリアスラリと同一種のセリアスラリを用いて、ゲート電極上の層間絶縁膜のＣＭＰを好適に行うことができる。   FIG. 5D shows the film thickness distribution after polishing. The film thickness distribution of the comparative sample (PSG single-layer interlayer insulating film formed by HDP-CVD) is also shown. In the comparative sample, the film thickness at the wafer center is about 316 nm, increases toward the periphery to about 332 nm, and then decreases to about 323 nm. M-shaped distribution continues. The interlayer insulating film according to the example shows a stable film thickness of about 320 nm on almost the entire surface of the wafer. It can be seen that the thickness variation of the entire wafer is prevented by the laminated interlayer insulating film of the embodiment. Further, using the same type of ceria slurry as that used for STI CMP, CMP of the interlayer insulating film on the gate electrode can be suitably performed.

なお、第１ステップのＣＭＰと第２ステップのＣＭＰの間に純粋洗浄を挿入してもよい。さらに、必要に応じて物理的研磨を挿入するｋともできる。物理的研磨を挿入した時は、その後にも純水洗浄を行うことが好ましいであろう。下層層間絶縁膜を配線（ゲート電極）高さ以上に堆積する例を説明したが、下層層間絶縁膜の厚さは、埋め込みが容易でない下地の立体構造（段差、曲率など）を緩和するものであればよい。必ずしも下層層間絶縁膜表面が配線表面より上まで来なくてもよい。   A pure cleaning may be inserted between the first step CMP and the second step CMP. Furthermore, it is possible to insert physical polishing as necessary. When physical polishing is inserted, it may be preferable to perform pure water cleaning thereafter. The example in which the lower interlayer insulating film is deposited higher than the wiring (gate electrode) height has been described. However, the thickness of the lower interlayer insulating film relaxes the underlying three-dimensional structure (step, curvature, etc.) that is not easily embedded. I just need it. The surface of the lower interlayer insulating film does not necessarily have to come above the wiring surface.

図６Ａは、上記実施例の変形例を示す。ＨＤＰ−ＣＶＤで堆積するＰＳＧ下層層間絶縁膜４１の厚さをゲート電極Ｇの高さより小さくしている。堆積された下層層間絶縁膜は、表面に凹凸を有し、凹部はゲート電極の表面（頂面）より低い。ＨＤＰ−ＰＳＧ膜は埋め込み特性がよいが、膜厚の均一性は保証されない。ＨＤＰ−ＰＳＧの下層層間絶縁膜４１の厚さを制限することにより、下地の立体構造を緩和しつつ、積層層間絶縁膜４０全体としての膜厚分布の平坦性がより安定に保証できるであろうと期待される。   FIG. 6A shows a modification of the above embodiment. The thickness of the PSG lower interlayer insulating film 41 deposited by HDP-CVD is made smaller than the height of the gate electrode G. The deposited lower interlayer insulating film has irregularities on the surface, and the concave portions are lower than the surface (top surface) of the gate electrode. Although the HDP-PSG film has good embedding characteristics, the film thickness uniformity is not guaranteed. By limiting the thickness of the lower interlayer insulating film 41 of HDP-PSG, the flatness of the film thickness distribution of the entire laminated interlayer insulating film 40 can be more stably ensured while relaxing the underlying three-dimensional structure. Be expected.

図６Ｂは、他の変形例を示す。ゲート配線Ｇと同一層でローカルインターコネクト等の配線Ｗを形成する場合、配線Ｗ上の下層層間絶縁膜４１の高さが他の領域よりある程度高くなる可能性もあろう。そのような場所では、第１ステップのＣＭＰで下層層間絶縁膜４１の一部が露出することもあろう。第１ステップのＣＭＰにより下層層間絶縁膜が露出しても特に問題が生じない限り構わない。   FIG. 6B shows another modification. When the wiring W such as the local interconnect is formed in the same layer as the gate wiring G, there is a possibility that the height of the lower interlayer insulating film 41 on the wiring W is somewhat higher than the other regions. In such a place, a part of the lower interlayer insulating film 41 may be exposed by the first step CMP. Even if the lower interlayer insulating film is exposed by CMP in the first step, it does not matter as long as no particular problem occurs.

上記実施例においては下層層間絶縁膜をＨＤＰ−ＰＳＧ膜で形成したが、ＨＤＰ−ＵＳＧ膜で形成してもよい。ＨＤＰ−ＣＶＤを用いて埋め込み特性のよい絶縁膜を形成し、その上にＰＥ−ＣＶＤを用いて、ＴＥＯＳ酸化膜などの研磨用の酸化膜を形成する。ＨＤＰ−ＣＶＤによる成膜を制限し、その上に平坦性のよいＰＥ‐ＣＶＤによる成膜を行うことにより平坦性のよい積層絶縁膜が得られるであろう。ウエハ全体での膜厚の均一性のみを対象とするのであれば、上層層間絶縁膜の材料もＴＥＯＳ酸化膜に限らない。成膜方法もＰＥ−ＣＶＤに限らない。膜厚の均一性のよい成膜であればよい。また、配線はゲート電極と同一層から形成されるものに限らない。   In the above embodiment, the lower interlayer insulating film is formed of an HDP-PSG film, but may be formed of an HDP-USG film. An insulating film with good embedding characteristics is formed using HDP-CVD, and a polishing oxide film such as a TEOS oxide film is formed thereon using PE-CVD. By limiting the film formation by HDP-CVD and performing the film formation by PE-CVD with good flatness thereon, a laminated insulating film with good flatness will be obtained. If only the film thickness uniformity over the entire wafer is targeted, the material of the upper interlayer insulating film is not limited to the TEOS oxide film. The film forming method is not limited to PE-CVD. Any film may be used as long as the film thickness is uniform. Further, the wiring is not limited to being formed from the same layer as the gate electrode.

図７Ａ，７Ｂは、配線がゲート配線以外の場合を含む例を示す。   7A and 7B show an example including the case where the wiring is other than the gate wiring.

図7Ａ、７Ｂは、ダイナミックランダムアクセスメモリ（ＤＲＡＭ）の製造方法を示す。図7Ａに示すように、図３Ａ〜３Ｇ同様の工程により、半導体基板のメモリセル領域にｎチャネルＭＯＳトランジスタを形成する。図では２つのｎチャネルＭＯＳトランジスタが中央のソース／ドレイン領域を共有し、両側のソース／ドレイン領域にメモリキャパシタを接続する構成を示す。ＭＯＳトランジスタを形成した後、ゲート電極を埋め込むように層間絶縁膜４０を形成する。   7A and 7B show a method for manufacturing a dynamic random access memory (DRAM). As shown in FIG. 7A, an n-channel MOS transistor is formed in the memory cell region of the semiconductor substrate by a process similar to that shown in FIGS. The figure shows a configuration in which two n-channel MOS transistors share a central source / drain region and memory capacitors are connected to the source / drain regions on both sides. After forming the MOS transistor, an interlayer insulating film 40 is formed so as to embed the gate electrode.

層間絶縁膜４０の表面をＣＭＰで平坦化した後、ホトリソグラフィとエッチングで各ソース／ドレイン領域に達するコンタクト孔を形成し、多結晶シリコン等を埋め込んで導電性プラグＰＬＧ１を形成する。ＣＭＰで表面上の導電層を除去した後、酸化シリコン膜を堆積して層間絶縁膜５０を形成する。   After planarizing the surface of the interlayer insulating film 40 by CMP, contact holes reaching the source / drain regions are formed by photolithography and etching, and polycrystalline silicon or the like is buried to form a conductive plug PLG1. After removing the conductive layer on the surface by CMP, a silicon oxide film is deposited to form an interlayer insulating film 50.

層間絶縁膜５０を貫通して、図中中央の導電性プラグＰＬＧ１に達する接続孔を形成し、スパッタリング等でアルミニウム合金等の配線層を堆積し、ホトリソグラフィとエッチングで配線層をパターニングしてビット線ＢＬを形成する。   A connection hole that penetrates the interlayer insulating film 50 and reaches the conductive plug PLG1 in the center of the figure is formed, a wiring layer such as an aluminum alloy is deposited by sputtering or the like, and the wiring layer is patterned by photolithography and etching. A line BL is formed.

ビット線ＢＬを覆うように、ＨＤＰ−ＰＳＧ膜６１、ＰＥ−ＴＥＯＳ膜６２を形成する。前述同様の２ステップＣＭＰにより表面を平坦化して、層間絶縁膜６０を形成する。   An HDP-PSG film 61 and a PE-TEOS film 62 are formed so as to cover the bit line BL. The interlayer insulating film 60 is formed by planarizing the surface by the same two-step CMP as described above.

図７Ｂに示すように、層間絶縁膜６０、５０を貫通して、両側の導電性プラグＰＬＧ１に達する接続孔を形成し、導電性プラグＰＬＧ２を埋め込む。導電性プラグＰＬＧ２の上に多結晶シリコン等の蓄積電極ＳＥ，熱酸化シリコン膜等のキャパシタ誘電体膜ＣＤＦ、多結晶シリコン膜等の対向電極ＯＥを形成する。なお、ＤＲＡＭキャパシタの製造方法は公知のいずれの方法を用いてもよい。キャパシタを埋め込んで、ＨＤＰ−ＰＳＧ膜７１、ＰＥ−ＴＥＯＳ膜７２を堆積して層間絶縁膜７０を形成する。下地のキャパシタを反映して、層間絶縁膜７０の表面は凹凸を有する。前述同様の２ステップＣＭＰにより、層間絶縁膜７０の表面を平坦化する。   As shown in FIG. 7B, a connection hole reaching the conductive plug PLG1 on both sides through the interlayer insulating films 60 and 50 is formed, and the conductive plug PLG2 is embedded. A storage electrode SE such as polycrystalline silicon, a capacitor dielectric film CDF such as a thermal silicon oxide film, and a counter electrode OE such as a polycrystalline silicon film are formed on the conductive plug PLG2. Any known method may be used as a method of manufacturing the DRAM capacitor. The capacitor is embedded, and an HDP-PSG film 71 and a PE-TEOS film 72 are deposited to form an interlayer insulating film 70. Reflecting the underlying capacitor, the surface of the interlayer insulating film 70 has irregularities. The surface of the interlayer insulating film 70 is planarized by the same two-step CMP as described above.

このように、配線構造により表面が凹凸を有する場合、まず埋め込み特性の優れたＨＤＰによる酸化シリコン膜で段差、曲率等を緩和し、次に膜厚の均一性がよく、安定したＣＭＰが可能なＰＥ−ＣＶＤによる酸化シリコン膜を堆積して、良好な層間絶縁膜を形成する。この層間絶縁膜を２ステップＣＭＰにより平坦化することにより、均一な厚さと平坦な表面を有する層間絶縁膜を得る。   Thus, when the surface is uneven due to the wiring structure, the step, curvature, etc. are first relaxed with a silicon oxide film of HDP having excellent embedding characteristics, and then the film thickness is uniform and stable CMP is possible. A silicon oxide film by PE-CVD is deposited to form a good interlayer insulating film. By planarizing this interlayer insulating film by two-step CMP, an interlayer insulating film having a uniform thickness and a flat surface is obtained.

以上実施例に従って本発明を説明したが、本発明はこれらに限定されるものではない。例えば、セリア系研磨剤に用いる添加剤は、ポリアクリル酸アンモニウム塩の他、ポリビニルピロリドン等を用いてもよい。被研磨膜は、酸化シリコン膜に限らず、酸化窒化シリコン膜等でもよい。埋め込み特性のよい成膜法であるＨＤＰ−ＣＶＤを用いて下層絶縁膜を形成し、その上に平坦性（厚さの均一性）のよい上層絶縁膜を形成すればよい。その他、種々の変更、改良、組み合わせなどが可能なことは、当業者に自明であろう。   Although the present invention has been described according to the embodiments, the present invention is not limited to these. For example, as the additive used for the ceria-based abrasive, polyvinyl pyrrolidone or the like may be used in addition to the ammonium polyacrylate. The film to be polished is not limited to a silicon oxide film, and may be a silicon oxynitride film or the like. A lower insulating film may be formed using HDP-CVD, which is a film formation method with good embedding characteristics, and an upper insulating film with good flatness (thickness uniformity) may be formed thereon. It will be apparent to those skilled in the art that other various modifications, improvements, combinations, and the like are possible.

図１Ａは予備実験で形成したサンプルの構成を示す断面図、図１Ｂは基板ＳＵＢ上に酸化シリコン膜ＯＸを堆積した後、測定した３種類の酸化シリコン膜の厚さ分布を示すグラフである。FIG. 1A is a cross-sectional view showing the configuration of a sample formed in a preliminary experiment, and FIG. 1B is a graph showing the thickness distribution of three types of silicon oxide films measured after the silicon oxide film OX is deposited on the substrate SUB. 図２Ａは研磨装置の構成を概略的に示す断面図、図２Ｂは同一種類のセリアスラリで３種類の酸化シリコン膜を研磨した時の研磨レートを示すグラフ、図２Ｃは、異なる濃度のポリアクリル酸アンモニウム塩を含むセリアスラリでＨＤＰ−ＰＳＧ膜を研磨した時の研磨レートを示すグラフである。2A is a cross-sectional view schematically showing the structure of the polishing apparatus, FIG. 2B is a graph showing polishing rates when three types of silicon oxide films are polished with the same type of ceria slurry, and FIG. 2C is a polyacrylic acid having different concentrations. It is a graph which shows the polishing rate when a HDP-PSG film | membrane is grind | polished with the ceria slurry containing an ammonium salt. 図３Ａ〜３Ｅは、実施例による半導体装置の製造方法を示す半導体ウエハの断面図である。3A to 3E are cross-sectional views of a semiconductor wafer showing a method of manufacturing a semiconductor device according to an embodiment. 図３Ｆ、３Ｇは、実施例による半導体装置の製造方法を示す半導体ウエハの断面図、図３Ｈは研磨後の層間絶縁膜の厚さ分布を示すグラフである。3F and 3G are cross-sectional views of a semiconductor wafer showing a method of manufacturing a semiconductor device according to an embodiment, and FIG. 3H is a graph showing a thickness distribution of an interlayer insulating film after polishing. 配線高さに対する下層層間絶縁膜の高さの比に対する膜厚ばらつきの変化を示すグラフである。It is a graph which shows the change of the film thickness dispersion | variation with respect to ratio of the height of a lower interlayer insulation film with respect to wiring height. 図５Ａは２ステップ研磨を説明するための半導体ウエハの断面図，図５Ｂは、研磨時のノズル配置を示す研磨装置の平面図である。FIG. 5A is a cross-sectional view of a semiconductor wafer for explaining two-step polishing, and FIG. 5B is a plan view of a polishing apparatus showing a nozzle arrangement during polishing. 図５Ｃは、第１ステップ後と第２ステップ後のスクラッチ数を示すグラフ、図５Ｄは研磨後の膜厚分布を示すグラフである。FIG. 5C is a graph showing the number of scratches after the first step and after the second step, and FIG. 5D is a graph showing the film thickness distribution after polishing. 図６Ａ，６Ｂは実施例の２つの変形例を示す半導体ウエハの断面図である。6A and 6B are cross-sectional views of a semiconductor wafer showing two modifications of the embodiment. 図７Ａ，７Ｂは、他の実施例によるＤＲＡＭの製造方法を示す半導体ウエハの断面図である。7A and 7B are cross-sectional views of a semiconductor wafer showing a method of manufacturing a DRAM according to another embodiment.

符号の説明Explanation of symbols

ＯＸ 酸化シリコン膜
ＳＵＢ 半導体基板
ＷＡＦ ウエハ
ＳＴＩ シャロートレンチアイソレーション
Ｇ ゲート電極
ＳＷ サイドウォール
Ｓ／Ｄ ソース／ドレイン
ＰＷ ｐ型ウェル
ＮＷ ｎ型ウェル
ＰＬＧ 導電性プラグ
ＢＬ ビット線
ＣＡＰ キャパシタ
１０ シリコンウエハ
１２ 酸化シリコン膜
１３ 窒化シリコン膜
１７ 酸化シリコン膜（ライナ）
１８ 窒化シリコン膜（ライナ）
２０ 酸化シリコン膜（素子分離領域）
４０ 層間絶縁膜
４１ 下層層間絶縁膜
４２ 上層層間絶縁膜
５０ 層間絶縁膜
６０ 層間絶縁膜
６１ 下層層間絶縁膜
６２ 上層層間絶縁膜
７０ 層間絶縁膜
７１ 下層層間絶縁膜
７２ 上層層間絶縁膜
１０２ 研磨テーブル
１０４ 研磨パッド
１１２ 研磨ヘッド
１２４ ノズル OX silicon oxide film SUB semiconductor substrate WAF wafer STI shallow trench isolation G gate electrode SW sidewall S / D source / drain PW p-type well NW n-type well PLG conductive plug BL bit line CAP capacitor 10 silicon wafer 12 silicon oxide film 13 Silicon nitride film 17 Silicon oxide film (liner)
18 Silicon nitride film (liner)
20 Silicon oxide film (element isolation region)
40 interlayer insulating film 41 lower interlayer insulating film 42 upper interlayer insulating film 50 interlayer insulating film 60 interlayer insulating film 61 lower interlayer insulating film 62 upper interlayer insulating film 70 interlayer insulating film 71 lower interlayer insulating film 72 upper interlayer insulating film 102 polishing table 104 Polishing pad 112 Polishing head 124 Nozzle

Claims (10)

（ａ）半導体基板上方に配線を形成する工程と、
（ｂ）工程（ａ）の後、前記配線を埋め込んで、高密度プラズマ（ＨＤＰ）化学的気相成長（ＣＶＤ）により第１の絶縁膜を堆積する工程と、
（ｃ）工程（ｂ）の後、ＨＤＰ−ＣＶＤ以外の堆積方法により、第１の絶縁膜上方に第２の絶縁膜を堆積する工程と、
（ｄ）工程(ｃ)の後、２酸化セリウム砥粒を含む研磨剤を用いた化学的機械的研磨により前記第２の絶縁膜を平坦化する工程と、
を含む半導体装置の製造方法。 (A) forming a wiring above the semiconductor substrate;
(B) After the step (a), a step of burying the wiring and depositing a first insulating film by high density plasma (HDP) chemical vapor deposition (CVD);
(C) After step (b), depositing a second insulating film above the first insulating film by a deposition method other than HDP-CVD;
(D) after the step (c), planarizing the second insulating film by chemical mechanical polishing using a polishing agent containing cerium dioxide abrasive grains;
A method of manufacturing a semiconductor device including: 工程（ｄ）が、表面の凹凸が平坦化されると研磨レートが大きく低下する、第１のスラリを用いた第１の研磨工程と、前記第１の研磨工程より研磨レートが速い、第２のスラリを用いた第２の研磨工程と、を含む請求項１記載の半導体装置の製造方法。   In the step (d), the polishing rate is greatly reduced when the surface irregularities are flattened, the first polishing step using the first slurry, and the polishing rate is faster than the first polishing step. A method of manufacturing a semiconductor device according to claim 1, further comprising: a second polishing step using a slurry of 前記第２のスラリは、第１のスラリを水で希釈したものである請求項２記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 2, wherein the second slurry is obtained by diluting the first slurry with water. 前記第２のスラリは、第１のスラリと水とを研磨テーブル上で混合することによって形成する請求項３記載の半導体装置の製造方法。   4. The method of manufacturing a semiconductor device according to claim 3, wherein the second slurry is formed by mixing the first slurry and water on a polishing table. 前記第２の絶縁膜を堆積する、ＨＤＰ−ＣＶＤ以外の堆積方法が、プラズマ（ＰＥ−）ＣＶＤである請求項１〜４のいずれか１項記載の半導体装置の製造方法。   5. The method of manufacturing a semiconductor device according to claim 1, wherein a deposition method other than HDP-CVD for depositing the second insulating film is plasma (PE-) CVD. 前記第１の絶縁膜が、ホスホシリケートガラス（ＰＳＧ）膜、又はボロホスホシリケートガラス（ＢＰＳＧ）膜である請求項１〜５のいずれか１項記載の半導体装置の製造方法。   The method for manufacturing a semiconductor device according to claim 1, wherein the first insulating film is a phosphosilicate glass (PSG) film or a borophosphosilicate glass (BPSG) film. 前記半導体基板がシリコン基板であり、工程（ａ）の前に、
（ｘ）前記シリコン基板に活性領域を分離するトレンチを形成する工程と、
（ｙ）前記シリコン基板上にＨＤＰ−ＣＶＤによりアンドープトシリケートガラス（ＵＳＧ）膜を堆積し、前記トレンチを前記ＵＳＧ膜で埋める工程と、
（ｚ）前記トレンチ外の前記ＵＳＧ膜を２酸化セリウム砥粒を含む研磨剤を用いた化学的機械的研磨により除去する工程と、
を含む請求項１〜６のいずれか１項記載の半導体装置の製造方法。 The semiconductor substrate is a silicon substrate, and before step (a),
(X) forming a trench separating the active region in the silicon substrate;
(Y) depositing an undoped silicate glass (USG) film on the silicon substrate by HDP-CVD and filling the trench with the USG film;
(Z) removing the USG film outside the trench by chemical mechanical polishing using a polishing agent containing cerium dioxide abrasive grains;
The manufacturing method of the semiconductor device of any one of Claims 1-6 containing these. 工程（ｃ）がシリコンソースとしてテトラエトキシシラン（ＴＥＯＳ）を用いたＰＥ−ＣＶＤにより前記第２の絶縁膜を成膜し、工程（ｚ）と工程(ｃ)において用いる研磨剤が同一組成である請求項７記載の半導体装置の製造方法。 In step (c), the second insulating film is formed by PE-CVD using tetraethoxysilane (TEOS) as a silicon source, and the abrasive used in step (z) and step (c) has the same composition. A method for manufacturing a semiconductor device according to claim 7. シリコン基板と、
前記シリコン基板に形成され、活性領域を画定するトレンチと、トレンチを埋め込むアンドープトシリケートガラス膜と、を含むシャロートレンチアイソレーション（ＳＴＩ）と、
前記活性領域上に形成されたゲート絶縁膜と、
前記ゲート絶縁膜上方に形成されたゲート電極と、
前記ゲート電極を覆って前記シリコン基板上方に形成され、凹凸のある表面を有する、ホスホシリケートガラス（ＰＳＧ）、又はボロホスホシリケートガラス（ＢＰＳＧ）の下層絶縁膜と、
前記下層絶縁膜上方に、ＴＥＯＳ酸化シリコン膜で形成され、平坦化された表面を有する上層絶縁膜と、
を有する半導体装置。 A silicon substrate;
A shallow trench isolation (STI) formed in the silicon substrate and including a trench defining an active region and an undoped silicate glass film filling the trench;
A gate insulating film formed on the active region;
A gate electrode formed above the gate insulating film;
A lower insulating film of phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG), which is formed above the silicon substrate so as to cover the gate electrode and has an uneven surface;
An upper insulating film formed of a TEOS silicon oxide film and having a planarized surface above the lower insulating film;
A semiconductor device. 前記下層絶縁膜の凹部は、前記ゲート電極の表面より低い請求項９記載の半導体装置。   The semiconductor device according to claim 9, wherein a recess of the lower insulating film is lower than a surface of the gate electrode.
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