CN100334731C - 内含沟道型肖特基整流器的沟道型dmos晶体管 - Google Patents

内含沟道型肖特基整流器的沟道型dmos晶体管 Download PDF

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CN100334731C
CN100334731C CNB018169554A CN01816955A CN100334731C CN 100334731 C CN100334731 C CN 100334731C CN B018169554 A CNB018169554 A CN B018169554A CN 01816955 A CN01816955 A CN 01816955A CN 100334731 C CN100334731 C CN 100334731C
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石甫渊
崔炎曼
苏根政
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General Semiconductor Inc
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Abstract

一种集成电路，其在一个或多个整流器区内具有多个沟道型肖特基势垒整流器，在一个或多个晶体管区内具有多个沟道型DMOS晶体管。该集成电路包含：(a)第一导电类型的衬底；(b)衬底上的第一导电类型的外延层，其中外延层具有比衬底低的掺杂度；(c)晶体管区的外延层内的第二导电类型的多个体区；(d)晶体管区和整流器区的外延层内的多个沟道；(e)衬贴沟道的第一绝缘层；(f)位于沟道内并覆盖第一绝缘层的多晶硅导体；(g)在与沟道相邻的体区内的多个第一导电类型的源极区；(h)晶体管区的掺杂多晶硅层上的第二绝缘层；以及(i)晶体管区和整流器区上的电极层。

Description

内含沟道型肖特基整流器的沟道型DMOS晶体管
技术领域
本发明涉及一种含有与肖特基势垒整流器并联的功率MOSFET的集成电路，尤其涉及一种单一衬底上的沟道型DMOSFET与沟道型肖特基整流器的集成。
背景技术
肖特基势垒整流器(也称为肖特基势垒二极管)用作DC-DC功率转换器中的同步整流器。名称为“具有MOS沟道的肖特基势垒整流器(Schottky Barrier Rectifier with MOS Trench)”的5,365,102号美国专利中公布了一种改进型肖特基势垒整流器。图1显示了该器件的剖视图。在该图中，整流器10包括：第一导电类型，通常为N型导电型的半导体衬底12，其有第一面12a和第二相对面12b。衬底12包含邻近第一面12a的相对高掺杂的阴极区12c(显示为N+)。第一导电类型的漂移区12d(显示为N)从阴极区12c向第二面12b延伸。因此，阴极区12c的掺杂浓度大于漂移区12d的掺杂浓度。在漂移区12d中形成了由相对侧面14a和14b限定的具有横截面宽度“Wm”的台面14。台面可以是条纹、矩形、圆柱形或其它的类似几何形状。在台面侧面也提供了绝缘区域16a和16b(例如SiO2)。该整流器还包括绝缘区16a与16b上的正极18。正极18与台面14形成了肖特基整流接触。在正极/台面界面上所形成的肖特基势垒的高度不仅取决于所使用的电极金属和半导体(例如：Si、Ge、GaAs与SiC)的类型，而且取决于台面14中的掺杂浓度。在第一面12a的阴极区12c附近有负极20。负极20与负极区12c是电阻性的接触。该沟道MOS肖特基势垒整流器在反向阻断电压方面具有显著的改善。通常，把两个或更多单独的沟道MOS肖特基势垒整流器制造为并联，多个整流器共用正极和负极触点。因此，各个沟道MOS肖特基势垒整流器作为单个的整流器。
遗憾的是，包含美国专利5,365,102中描述的肖特基势垒整流器具有相对高的导通电阻(正向偏压降)。此外，许多肖特基势垒整流器具有相对高的反向偏置泄漏电流。因此，在功率转换应用中经常用功率MOSFET(金属氧化物半导体场效应晶体管)来代替肖特基势垒整流器，这能解决上述问题。
DMOS晶体管(双扩散MOSFET)(即DMOSFET)是使用扩散来形成晶体管区域的一种MOSFET。典型的独立DMOS电路包括制成并联形式的两个或更多个单独的DMOS晶体管单元。各个DMOS晶体管单元共享公共的漏极触点(基底)，同时，其源极用金属短接，且栅极用多晶硅短接在一起。因此，虽然DMOS电路由一列较小的晶体管构成，但其表现得像是一个单个的大晶体管。
DMOS晶体管的一个特殊类型是“沟道型DMOS晶体管”，其中，沟道是垂直形成的，在源极和漏极之间延伸的沟道中形成有栅极。排列了薄氧化物层并填充了多晶硅的沟道使电流受到的限制更少，因此具有更低的单位导通电阻(正向偏压降)。在美国专利5,072,266、5,541,425与5,866,931中公开了沟道型DMOS晶体管的实例。
图2a至图2c显示了现有沟道型DMOS结构120的一个实施例，其中一个单元121在水平横截面上是矩形。应该注意，晶体管单元121不需具有用于基本晶体管运行的矩形形状，更多的可以具有任何多边形的形状。然而，为布局起见，规则的矩形形状和规则的六角形形状通常被认为是最便利的。在该实施例中，该结构包括其上生长有微量n-掺杂的外延层104的N+衬底100。在掺杂外延层104内部设置了相反导电性的体区116。覆盖了体区116大部分的n-掺杂外延层140充当源极。在外延层上设置了矩形沟道124，其在该结构的上表面敞开，并限定了该晶体管单元的周边。栅极氧化物层130排在沟道124的底部与侧壁。沟道124填充有多晶硅。漏极与半导体衬底100的背面相连，源极118与源极区140和体区116相连，并且栅极与填充沟道124的多晶硅相连。如图2A所示，沟道124内的多晶硅在结构120的表面上是连续连接的。另外，多晶硅触点129延伸出结构120的表面，以相互连接。应该注意，该晶体管单元可以不具有图示的封闭的单元几何形状，而具有敞开的或条状的几何形状。
如图2A至2C所示，DMOS晶体管的栅极位于垂直朝向的沟道中。该结构经常被称为沟道垂直DMOS。其是“垂直的”，因为漏极触点出现在衬底的背面或底面上，并且从源极到漏极的电流是近似垂直的。这减小了弯曲或曲线的电流路径或寄生场效应结构中的高电阻。该器件也是双扩散的(由前缀“D”表示)，因为源极区扩散进了相反导电类型的先扩散的体区一部分上的外延物质中。这种结构使用了沟道侧壁区以通过栅极控制电流，并具有与其相联系的大体上垂直的电流流动。如上所述，这种器件特别适于用作功率开关晶体管，这里需要使通过给定横向硅面积的电流最大。
遗憾的是，含有沟道型DMOS晶体管的功率MOSFET在高频应用中，表现出较低的开关速度，原因在于内建体二极管较长的恢复时间，因此，该功率MOSFET要比理想的差。
如图3A到图3F所示，这些问题己通过把功率MOSFET与肖特基势垒整流器进行并联组合而得到解决。
图3A示意性地显示了现有技术的沟道型DMOS晶体管的一部分。如图3A所示，这种晶体管好象具有内建的二极管Db。当置于电路中时，图3A所示的晶体管可以表示为图3B中由虚线所围绕的部分。在图3B中用D2表示内建体二极管，其中还包含与该晶体管相联系的开关S2。图3B的电路显示了开关S1和二极管D1、电感器L1、电容器C1和负载R1。在如图所示的电路上施加了电压Vin。
图3C显示了两个控制信号，在时间T1、T2、T3、T4和T5上，用于驱动开关S1的第一栅极驱动信号GDS1和用于驱动开关S2的第二栅极驱动信号GDS2。如图3B所示，在时间T1，信号GDS1和GDS2使开关S1处于导通状态，开关S2处于关闭状态。因此，如图3B中的箭头所示，电流从Vin流经上面的开关S1，流经电感器L1并流经负载R1，通向地。
转至图3D，在时间T2，信号GDS1和GDS2使两个开关S1和S2处于导通状态。因此，电流(如图3D中的箭头显示)流经电感器L1，流经负载R1并流经内建体二极管D2。
然后，如图3E所示，在时间T3，信号GDS1和GDS2使开关S1处于关闭状态，开关S2处于导通状态。因此，电流(由箭头所示)流经电感器L1，流经负载R1，并流经开关S2。
在时间T4，信号GDS1和GDS2使开关S1和S2处于关闭状态，产生了如图3D所示的电流流动。具体而言，电流流经电感器L1，流经负载R1并流经内建体二极管D2。
随后，在时间T5(一直到T6)，信号GDS1和GDS2使开关S1处于导通状态，开关S2处于关闭状态。在该点，电流流动如图3B所示。具体地说，如图3B中的箭头所示，电流流动从Vin开始，流经上面的开关S1，流经电感器L1，流经负载R1，通向地。
应该注意，如果两个开关S1和开关S2同时处于导通状态，则大电流将从Vin开始，流经开关S1和S2，通向地。为了避免这种结果，作为一个例子，在开关S2导通之前的短暂时间内(例如，在T2和T3之间)，关闭开关S1。然而，如上所述，在该时间内，电流将流经内建体二极管D2。对于典型的沟道型DMOS晶体管，该电流导致内建体二极管D2上的压降大约为0.65V。然而，如图3F所示，通过增加肖特基二极管Ds，该压降大约为0.3V，减少了功率损耗。
此外，在T4到T5期间内，电流经过内建体二极管D2。然而，在T5，由于体二极管D2的反向恢复时间较长，要在特定的时间里导通上面的开关S1，电流流经体二极管D2，通向地。另一方面，肖特基二极管具有相对短的反向恢复时间。因此，如图3F所示，如果提供了肖特基二极管，则由于反向恢复时间较短，只有非常少的电流流向了地。
因此，这种结构导致***效率较高，特别是对于要求功率消耗较低的高频***，例如便携式***。在美国专利5,915,179“半导体器件及其制造方法(Semiconductor Device and Method of Manufacturing theSame)”和美国专利4,811,065“具有高速体二极管的功率DMOS晶体管(Power DMOS Transistor with High Speed Body Diode)”中可见找到这种***的实例。在美国专利4,811,065中，在半导体结构内部肖特基势垒整流器与垂直DMOS晶体管结合，形成了等同于与N沟道垂直DMOS晶体管并联的肖特基势垒整流器的器件。
遗憾的是，MOS沟道型肖特基势垒整流器像那些在美国专利5,365,102种中所公开的一样，不利于沟道型DMOS晶体管的集成，其原因在于肖特基势垒整流器的MOS沟道填充了金属，潜在地导致了沟道区上金属覆盖的问题。目前，通过使用MCM(多芯片模块)方法来把沟道型DMOS晶体管和MOS沟道型肖特基势垒整流器集成在一个封装内，从而解决了该困难，值得注意的是，这样增加了这种器件的成本。
发明内容
因此，需要把MOS沟道型肖特基势垒整流器与沟道型DMOS晶体管集成在一个衬底上，同时在沟道区不存在金属覆盖问题。本发明提供了一种具有多晶硅氧化物半导体沟道的肖特基势垒整流器，而不是现有技术的MOS(金属氧化物半导体)沟道，并把该肖特基势垒整流器与沟道型DMOS晶体管集成在一个衬底上，从而满足了这种需要。
具体而言，根据本发明的一个实施例，提供了一种集成电路，其在一个或多个整流器区内具有多个沟道型肖特基势垒整流器，并在一个或多个晶体管区内具有多个沟道型DMOS晶体管，所述的集成电路还含有公共电极层，该电极层用作DMOS晶体管的公共源极并用作整流器的阳极。该集成电路包含：(a)第一导电类型的衬底；(b)衬底上的第一导电类型的外延层，其中外延层具有比衬底低的掺杂度；(c)多个第二导电类型的体区，其位于晶体管区中的外延层内；(d)多个沟道，其位于晶体管区和整流器区的外延层内；(e)衬在沟道上的第一绝缘层；(f)多晶硅导体，其位于沟道内并覆盖第一绝缘层；(g)体区内的多个第一导电类型的源极区，其位于与沟道相邻的位置；(h)第二绝缘层，其位于晶体管区中的掺杂多晶硅层上；以及(i)公共电极层，其连续地位于晶体管区和整流器区上。
最好在与体区相对的衬底的表面上提供电极层。
优选的，衬底是n-掺杂衬底，第一绝缘层是二氧化硅层，第二绝缘层是硼磷硅玻璃层。
优选的，沟道型肖特基势垒整流器和沟道型DMOS晶体管由公共氧化物层和该氧化物层上的公共多晶硅层制备。更为优选的，沟道型肖特基势垒整流器和沟道型DMOS晶体管使用公共衬底，衬底上的公共外延层，外延层上的公共氧化物层，以及氧化物层上的公共多晶硅层来制备。
此外，沟道型肖特基势垒整流器的正极和沟道型DMOS晶体管的源极最好共用一个公共电极，且沟道型肖特基势垒整流器的负极和沟道型DMOS晶体管的漏极最好共用一个公共电极。
根据本发明的另一个实施例，提供了一种制造集成电路的方法，该集成电路在一个或多个整流器区内含有多个沟道型肖特基势垒整流器，在一个或多个晶体管区内含有多个沟道型DMOS晶体管，该集成电路还含有公共电极层，该电极层用作DMOS晶体管的公共源极并用作整流器的阳极。该方法包含：(a)提供第一导电类型的衬底；(b)在衬底上形成第一导电类型的外延层，其中外延层具有比衬底低的掺杂度；(c)在晶体管区的外延层内形成一个或多个第二导电类型的体区；(d)在晶体管区和整流器区的外延层内形成多个沟道；(e)形成衬贴沟道的第一绝缘层；(f)在沟道内形成多晶硅导体并覆盖第一绝缘层；(g)在与沟道相邻的体区内形成多个第一导电类型的源极区；(h)在晶体管区的多晶硅导体上形成第二绝缘层；以及(i)连续地在晶体管区和整流器区上形成公共电极层。
此外，最好在与体区相对的衬底的表面上形成电极层。
根据几个优选实施例：(a)形成体区的步骤包括：在外延层上形成图案掩模层的步骤，及向外延层注入与扩散掺杂物质的步骤；(b)形成沟道的步骤包括：在外延层上形成图案掩模层的步骤，及通过掩模层蚀刻沟道的步骤；(c)形成源极区的步骤包括：形成图案掩模层的步骤，及向体区注入与扩散掺杂物的步骤；(d)在晶体管区的多晶硅层上形成第二绝缘层的步骤包含：至少在晶体管区上沉积BPSG层的步骤，在BPSG层上形成图案掩模层的步骤，以及在未被图案掩模层覆盖的区域上蚀刻BPSG层的步骤。
本发明具有优点，其原因在于本发明提供了一种沟道型肖特基势垒整流器与沟道型DMOS晶体管集成在单一衬底上的产品及其用于制造该产品的方法。因此，这种器件非常容易制备，迄今为止费用可能最少。
本领域技术熟练人员通过下文的详细描述、实例和权利要求书的记述，可以更加清楚地理解本发明的其它实施例与优点。
附图说明
图1显示了现有技术的MOS沟道型肖特基势垒整流器的剖视图；
图2A显示了现有沟道型DMOS晶体管的平面图；
图2B显示了图1所示的现有晶体管中的一个单元的放大平面图；
图2C显示了图2A和2B所示的DMOS晶体管沿图2B中的线A-A′的剖视图；
图3A示意性显示了现有技术的沟道型DMOS晶体管的一部分，其表现为好像具有一个内建体二极管Db；
图3B是电路图，其中包括图3A结构的等效电路，显示了在开关S1处于导通状态，开关S2处于关闭状态情况下的电流流动；
图3C显示了两个在时间T1、T2、T3、T4和T5驱动开关S1和S2(如图3B所示)的控制信号；
图3D显示了图3B所示电路在开关S1和S2处于关闭状态时的电流流动；
图3E显示了图3B所示电路在开关S1处于关闭状态，开关S2处于导通状态时的电流流动；
图3F是图3B添加了肖特基势垒二极管之后的电路图；
图4显示了本发明的沟道型DMOS晶体管和沟道型肖特基势垒整流器组合的实施例的剖视图；
图5A到图5J是剖面图，显示了根据本发明实施例的制造沟道型DMOS晶体管和沟道型肖特基势垒整流器组合的方法。
具体实施方式
参考附图，下文将更详细更充分地描述本发明，其中，附图显示了本发明的优选实施例。然而，本发明可以以不同形式来实施，并不被此处所陈述的实施例限制。
图4显示了本发明的一个实施例，显示了组合沟道型DMOS晶体管和沟道型肖特基势垒整流器的结构250。结构250在DMOS晶体管区220内具有DMOS晶体管器件，在整流器区222内具有肖特基势垒整流器器件。在该实施例中，结构250包括：其上形成有微量n-掺杂的外延层202的N+衬底200，其作为DMOS晶体管器件的漏极和整流器器件的负极/漂移区。导电层218作为DMOS晶体管器件的公共漏极触点，并作为整流器器件的公共负极。
在掺杂N外延层202的内部，相反导电性的P体区204作为DMOS晶体管器件的栅极区。还提供了N+区212，作为DMOS晶体管器件的源极。
导电层216作为DMOS晶体管器件的公共源极触点，把源极(即，N+区212)相互短接。导电层216作为整流器器件的正极。
还具有由氧化物层206衬贴并填充了多晶硅210的沟道区。在整流器器件内部，这些沟道区产生了台面结构，这导致了反向阻断电压的增加，另外还有其它效应。应该注意，多晶硅210与整流器器件的导电层216(正极)短接。
被填充的沟道206、210作为沟道型DMOS晶体管器件的栅极。和整流器器件相反，多晶硅210通过BPSG(硼磷硅玻璃)结构214与导电层216(源极触点)绝缘，容许栅极和源极有独立的偏压。
图5A到图5J显示了用于形成图4所示的具有内建沟道型肖特基整流器250的沟道型DMOS晶体管的步骤。
如图5A所示，在普通的N+掺杂衬底200上生长出N-掺杂外延层202。30V沟道型DMOS晶体管器件的外延层的厚度一般是5.5微米。
接下来，使用光阻掩模工艺来形成图案掩模层203。如图5B所示，图案掩模层203定义了由注入和扩散工艺形成的P-体区204。例如，P-体区可以在40到60keV下用5.5×1013/cm3的剂量来注入。P-体区204定义了该器件的DMOS晶体管区220。结构250的整流器区222没有这种P-体区。
然后，通过任何已知恰当的技术方法除去图案掩模层203。于是形成图5C所示的掩模部分205。如图5D所示，掩模部分限定了沟道207的位置。沟道最好通过反应离子蚀刻掩模部分205之间的空间来进行干蚀刻，典型的深度是1.5到2.5微米。
然后，如图5E所示，除去掩模部分205，且在整个结构的表面通过热氧化作用来形成氧化物层206。对于层206，氧化物厚度的范围一般为500到800埃。随后，使用例如CVD等已知技术，用多晶硅210覆盖该表面(填充沟道)，从而提供了图5F所示的结构。通常对多晶硅210进行掺杂，以减小其电阻率，典型的为20Ω/m数量级。例如，在用氯化磷进行CVD或注入砷或磷的期间，可以进行掺杂。
然后，蚀刻多晶硅210，例如，如图5G所示，通过反应离子蚀刻(RIE)，以优化其在沟道内的厚度，并暴露氧化物层的部分206。
接着，如图5H所示，利用光阻掩模工艺来形成图案掩模层211。图案掩模层211定义了DMOS晶体管区220内的源极区212。通常经过注入和扩散工艺来形成源极区212。例如，常常在80keV下使砷浓度达到8×1015到1.2×1016cm3的范围来注入源极区212。注入后，砷扩散到约0.5微米的深度。
然后，通过本技术领域的任何恰当技术来除去图案掩模层211。随后，例如，通过PECVD在整个结构上形成BPSG(硼磷硅玻璃)层214，其具有图案光阻层215，如图5I所示。
通常通过RIE来除去光阻层215，接着进行现有技术中公知的BPSG回流和后回流蚀刻步骤。最后，如图5J所示，通过金属溅射步骤来为该结构提供金属接触层216。此外，提供如图所示的金属接触层218以完成该器件。
尽管此处具体地显示和描述了多种实施例，但能够理解，上述内容涵盖本发明的各种修改和变化，并不脱离本发明的精神和保护范围，而被包括在所附权利要求的范围内。例如，本发明的方法可以用来形成各种半导体区的导电性与此处描述的相反的结构。

Claims (15)

1.一种集成电路的制造方法，所述的集成电路在一个或多个整流器区内含有多个沟道型肖特基势垒整流器，在一个或多个晶体管区内含有多个沟道型DMOS晶体管，所述的集成电路还含有公共电极层，该电极层用作DMOS晶体管的公共源极并用作整流器的阳极，该方法包含：
提供第一导电类型的衬底；
在上述衬底上形成所述第一导电类型的外延层，所述外延层具有比所述衬底低的掺杂度；
在所述晶体管区的所述外延层内形成第二导电类型的一个或多个体区；
在所述晶体管区和所述整流器区的外延层内形成多个沟道；
形成衬贴所述沟道的第一绝缘层；
在所述沟道内形成多晶硅导体，并覆盖第一绝缘层；
在与所述沟道相邻的所述体区内形成所述第一导电类型的多个源极区；
形成位于所述晶体管区内的所述多晶硅导体之上并与之接触的第二绝缘层；以及
形成连续位于所述晶体管区和所述整流器区之上，并与所述第二绝缘层接触的公共电极层。
2.根据权利要求1所述的方法，其中，形成体区的步骤包括：在外延层上形成图案掩模层，并向外延层内注入和扩散掺杂物质。
3.根据权利要求1所述的方法，其中，形成沟道的步骤包括：在外延层上形成图案掩模层，并通过所述掩模层蚀刻所述沟道。
4.根据权利要求1所述的方法，其中，形成源极区的步骤包括：形成图案掩模层，并向体区内注入和扩散掺杂物质。
5.根据权利要求1所述的方法，其中，在所述晶体管区的多晶硅层上形成第二绝缘层的步骤包含：至少在晶体管区上沉积BPSG层，在所述BPSG层上形成图案掩模层，并在没有被图案掩模层覆盖的区域上蚀刻所述BPSG层。
6.根据权利要求1所述的方法，还包含：在与体区相对的衬底的表面上形成电极层。
7.一种集成电路，该集成电路在一个或多个整流器区内具有多个沟道型肖特基势垒整流器，在一个或多个晶体管区内具有多个沟道型DMOS晶体管，该集成电路还含有公共电极层，该电极层用作DMOS晶体管的公共源极并用作整流器的阳极，所述集成电路包含：
第一导电类型的衬底；
所述衬底上的所述第一导电类型的外延层，所述外延层具有比所述衬底更低的掺杂度；
所述晶体管区的所述外延层内的第二导电类型的多个体区；
所述晶体管区和所述整流器区的外延层内的多个沟道；
衬贴所述沟道的第一绝缘层；
所述沟道内的多晶硅导体，其覆盖第一绝缘层；
与所述沟道相邻的所述体区内的所述第一导电类型的多个源极区；
位于所述晶体管区内的所述多晶硅导体之上并与之接触的第二绝缘层；以及
连续位于所述晶体管区和所述整流器区之上，并与所述第二绝缘层接触的公共电极层。
8.根据权利要求7所述的集成电路，其中，所述衬底是n-掺杂衬底。
9.根据权利要求7所述的集成电路，其中，第一绝缘层是二氧化硅层。
10.根据权利要求7所述的集成电路，其中，第二绝缘层是硼磷硅玻璃层。
11.根据权利要求7所述的集成电路，还包含：与体区相对的衬底表面上的电极层。
12.根据权利要求7所述的集成电路，其中，所述沟道型肖特基势垒整流器和所述沟道型DMOS晶体管是由一个公共氧化物层和所述氧化物层上的公共多晶硅层制备而成的。
13.根据权利要求12所述的集成电路，其中，所述沟道型肖特基势垒整流器和所述沟道型DMOS晶体管是用一个公共衬底、所述衬底上的公共外延层、所述外延层上的公共氧化物层、以及所述氧化物层上的公共多晶硅层制备的。
14.根据权利要求12所述的集成电路，其中，所述沟道型肖特基势垒整流器的正极和所述沟道型DMOS晶体管的源极共用一个公共电极，所述沟道型肖特基势垒整流器的负极和所述沟道型DMOS晶体管的漏极共用一个公共电极。
15.根据权利要求14所述的集成电路，其中，所述导电层在所述沟道型肖特基势垒整流器与所述沟道型DMOS晶体管上连续地延伸。
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