CA1038967A - Transistor a effet de champ mos et mode de fabrication - Google Patents

Transistor a effet de champ mos et mode de fabrication

Info

Publication number
CA1038967A
CA1038967A CA221,639A CA221639A CA1038967A CA 1038967 A CA1038967 A CA 1038967A CA 221639 A CA221639 A CA 221639A CA 1038967 A CA1038967 A CA 1038967A
Authority
CA
Canada
Prior art keywords
source
drain
type
phosphorous
regions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA221,639A
Other languages
English (en)
Other versions
CA221639S (en
Inventor
Willis G. Watrous (Jr.)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of CA1038967A publication Critical patent/CA1038967A/fr
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/04—Dopants, special
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/06—Gettering
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/133—Reflow oxides and glasses
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/167—Two diffusions in one hole
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/978—Semiconductor device manufacturing: process forming tapered edges on substrate or adjacent layers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/53—Means to assemble or disassemble
    • Y10T29/53909—Means comprising hand manipulatable tool
    • Y10T29/53913—Aligner or center

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
CA221,639A 1974-03-13 1975-03-06 Transistor a effet de champ mos et mode de fabrication Expired CA1038967A (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/450,773 US3986903A (en) 1974-03-13 1974-03-13 Mosfet transistor and method of fabrication

Publications (1)

Publication Number Publication Date
CA1038967A true CA1038967A (fr) 1978-09-19

Family

ID=23789430

Family Applications (1)

Application Number Title Priority Date Filing Date
CA221,639A Expired CA1038967A (fr) 1974-03-13 1975-03-06 Transistor a effet de champ mos et mode de fabrication

Country Status (7)

Country Link
US (2) US3986903A (fr)
JP (1) JPS50127581A (fr)
CA (1) CA1038967A (fr)
DE (1) DE2509315A1 (fr)
FR (1) FR2264398B1 (fr)
GB (1) GB1496413A (fr)
NL (1) NL159815B (fr)

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4193080A (en) * 1975-02-20 1980-03-11 Matsushita Electronics Corporation Non-volatile memory device
JPS5946107B2 (ja) * 1975-06-04 1984-11-10 株式会社日立製作所 Ｍｉｓ型半導体装置の製造法
JPS5232277A (en) * 1975-09-05 1977-03-11 Toshiba Corp Insulated gate type field-effect transistor
JPS5232680A (en) * 1975-09-08 1977-03-12 Toko Inc Manufacturing process of insulation gate-type field-effect semiconduct or device
US4028717A (en) * 1975-09-22 1977-06-07 Ibm Corporation Field effect transistor having improved threshold stability
JPS52115665A (en) * 1976-03-25 1977-09-28 Oki Electric Ind Co Ltd Semiconductor device and its production
JPS53128281A (en) * 1977-04-15 1978-11-09 Hitachi Ltd Insulated gate field effect type semiconductor device for large power
JPS5917529B2 (ja) * 1977-11-29 1984-04-21 富士通株式会社 半導体装置の製造方法
JPS5492175A (en) * 1977-12-29 1979-07-21 Fujitsu Ltd Manufacture of semiconductor device
JPS54147789A (en) * 1978-05-11 1979-11-19 Matsushita Electric Ind Co Ltd Semiconductor divice and its manufacture
JPS5534444A (en) * 1978-08-31 1980-03-11 Fujitsu Ltd Preparation of semiconductor device
JPS5553462A (en) * 1978-10-13 1980-04-18 Int Rectifier Corp Mosfet element
US5191396B1 (en) * 1978-10-13 1995-12-26 Int Rectifier Corp High power mosfet with low on-resistance and high breakdown voltage
DE2902665A1 (de) * 1979-01-24 1980-08-07 Siemens Ag Verfahren zum herstellen von integrierten mos-schaltungen in silizium-gate- technologie
DE2923995C2 (de) * 1979-06-13 1985-11-07 Siemens AG, 1000 Berlin und 8000 München Verfahren zum Herstellen von integrierten MOS-Schaltungen mit MOS-Transistoren und MNOS-Speichertransistoren in Silizium-Gate-Technologie
US4261772A (en) * 1979-07-06 1981-04-14 American Microsystems, Inc. Method for forming voltage-invariant capacitors for MOS type integrated circuit device utilizing oxidation and reflow techniques
JPS56165338A (en) * 1980-05-23 1981-12-18 Nec Corp Semiconductor device and manufacture thereof
JPS5787174A (en) * 1980-11-20 1982-05-31 Seiko Epson Corp Semiconductor integrated circuit device
JPS5827363A (ja) * 1981-08-10 1983-02-18 Fujitsu Ltd 電界効果トランジスタの製造法
US4743564A (en) * 1984-12-28 1988-05-10 Kabushiki Kaisha Toshiba Method for manufacturing a complementary MOS type semiconductor device
KR890004962B1 (ko) * 1985-02-08 1989-12-02 가부시끼가이샤 도오시바 반도체장치 및 그 제조방법
KR900000065B1 (ko) * 1985-08-13 1990-01-19 가부시끼가이샤 도오시바 독출전용 반도체기억장치와 그 제조방법
US4878100A (en) * 1988-01-19 1989-10-31 Texas Instruments Incorporated Triple-implanted drain in transistor made by oxide sidewall-spacer method
JP2675572B2 (ja) * 1988-03-31 1997-11-12 株式会社東芝 半導体集積回路の製造方法
US5021851A (en) * 1988-05-03 1991-06-04 Texas Instruments Incorporated NMOS source/drain doping with both P and As
US5047820A (en) * 1988-09-14 1991-09-10 Micrel, Inc. Semi self-aligned high voltage P channel FET
US4885627A (en) * 1988-10-18 1989-12-05 International Business Machines Corporation Method and structure for reducing resistance in integrated circuits
EP0439965B1 (fr) * 1989-12-29 1997-04-09 Sharp Kabushiki Kaisha Procédé pour la fabrication d'une mémoire semi-conductrice
IT1250233B (it) * 1991-11-29 1995-04-03 St Microelectronics Srl Procedimento per la fabbricazione di circuiti integrati in tecnologia mos.
US6780718B2 (en) * 1993-11-30 2004-08-24 Stmicroelectronics, Inc. Transistor structure and method for making same
ATE208536T1 (de) * 1994-03-03 2001-11-15 Rohm Corp Überlöschungsdetektion in einer niederspannungs- eintransistor-flash-eeprom-zelle unter verwendung von fowler-nordheim-programmierung und -löschung
US5817546A (en) * 1994-06-23 1998-10-06 Stmicroelectronics S.R.L. Process of making a MOS-technology power device
EP0689238B1 (fr) * 1994-06-23 2002-02-20 STMicroelectronics S.r.l. Procédé de manufacture d'un dispositif de puissance en technologie MOS
US5869371A (en) * 1995-06-07 1999-02-09 Stmicroelectronics, Inc. Structure and process for reducing the on-resistance of mos-gated power devices
US5994210A (en) * 1997-08-12 1999-11-30 National Semiconductor Corporation Method of improving silicide sheet resistance by implanting fluorine
US7043983B2 (en) * 2003-12-15 2006-05-16 Fling William F Horizontal liquid level measuring device
JP2015015384A (ja) * 2013-07-05 2015-01-22 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US9472570B2 (en) * 2014-02-18 2016-10-18 Globalfoundries Inc. Diode biased body contacted transistor

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3476619A (en) * 1966-09-13 1969-11-04 Motorola Inc Semiconductor device stabilization
US3594241A (en) * 1968-01-11 1971-07-20 Tektronix Inc Monolithic integrated circuit including field effect transistors and bipolar transistors,and method of making
FR2014382B1 (fr) * 1968-06-28 1974-03-15 Motorola Inc
DE2040180B2 (de) * 1970-01-22 1977-08-25 Intel Corp, Mountain View, Calif. (V.St.A.) Verfahren zur verhinderung von mechanischen bruechen einer duennen, die oberflaeche eines halbleiterkoerpers ueberdeckende isolierschichten ueberziehenden elektrisch leitenden schicht
US3737347A (en) * 1970-02-26 1973-06-05 Fairchild Camera Instr Co Graded impurity profile in epitaxial films to improve integrated circuit performance
US3756876A (en) * 1970-10-27 1973-09-04 Cogar Corp Fabrication process for field effect and bipolar transistor devices
US3699646A (en) * 1970-12-28 1972-10-24 Intel Corp Integrated circuit structure and method for making integrated circuit structure
US3967981A (en) * 1971-01-14 1976-07-06 Shumpei Yamazaki Method for manufacturing a semiconductor field effort transistor
US3725136A (en) * 1971-06-01 1973-04-03 Texas Instruments Inc Junction field effect transistor and method of fabrication
JPS4911583A (fr) * 1972-06-01 1974-02-01
JPS5528434B2 (fr) * 1974-01-29 1980-07-28

Also Published As

Publication number Publication date
DE2509315A1 (de) 1975-09-25
US4092661A (en) 1978-05-30
GB1496413A (en) 1977-12-30
FR2264398B1 (fr) 1979-03-16
FR2264398A1 (fr) 1975-10-10
JPS50127581A (fr) 1975-10-07
NL159815B (nl) 1979-03-15
NL7501529A (nl) 1975-09-16
US3986903A (en) 1976-10-19

Similar Documents

Publication Publication Date Title
CA1038967A (fr) Transistor a effet de champ mos et mode de fabrication
US4219835A (en) VMOS Mesa structure and manufacturing process
US4062699A (en) Method for fabricating diffusion self-aligned short channel MOS device
US3936858A (en) MOS transistor structure
US4476622A (en) Recessed gate static induction transistor fabrication
US4103415A (en) Insulated-gate field-effect transistor with self-aligned contact hole to source or drain
US3909306A (en) MIS type semiconductor device having high operating voltage and manufacturing method
US4883767A (en) Method of fabricating self aligned semiconductor devices
US3943542A (en) High reliability, low leakage, self-aligned silicon gate FET and method of fabricating same
US4586240A (en) Vertical IGFET with internal gate and method for making same
US4296429A (en) VMOS Transistor and method of fabrication
US4358891A (en) Method of forming a metal semiconductor field effect transistor
US3975752A (en) Junction field effect transistor
US4473941A (en) Method of fabricating zener diodes
US4200968A (en) VMOS transistor and method of fabrication
US4169270A (en) Insulated-gate field-effect transistor with self-aligned contact hole to source or drain
CA1179786A (fr) Transistor a structure laterale ayant une base auto-alignee et un contact de base et methode de fabrication
US3660732A (en) Semiconductor structure with dielectric and air isolation and method
US5395780A (en) Process for fabricating MOS transistor
US4804635A (en) Method of manufacture of galluim arsenide field effect transistors
US3892609A (en) Production of mis integrated devices with high inversion voltage to threshold voltage ratios
US4054989A (en) High reliability, low leakage, self-aligned silicon gate FET and method of fabricating same
JP2524370B2 (ja) 半導体デバイスの製造方法
JP3022714B2 (ja) 半導体装置およびその製造方法
JPS5982768A (ja) 半導体装置の製造方法