BR8303491A - Sistema multiprocessador a via condutora assincrona - Google Patents
Sistema multiprocessador a via condutora assincronaInfo
- Publication number
- BR8303491A BR8303491A BR8303491A BR8303491A BR8303491A BR 8303491 A BR8303491 A BR 8303491A BR 8303491 A BR8303491 A BR 8303491A BR 8303491 A BR8303491 A BR 8303491A BR 8303491 A BR8303491 A BR 8303491A
- Authority
- BR
- Brazil
- Prior art keywords
- asynchronous
- conductor
- multiprocessor system
- multiprocessor
- conductor multiprocessor
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
- G06F9/24—Loading of the microprogram
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Multi Processors (AREA)
- Bus Control (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IT22248/82A IT1151683B (it) | 1982-07-06 | 1982-07-06 | Sistema multiprocessore a bus asincrono con caricamento di microistruzioni da memoria di lavoro |
Publications (1)
Publication Number | Publication Date |
---|---|
BR8303491A true BR8303491A (pt) | 1984-02-07 |
Family
ID=11193634
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
BR8303491A BR8303491A (pt) | 1982-07-06 | 1983-06-30 | Sistema multiprocessador a via condutora assincrona |
Country Status (7)
Country | Link |
---|---|
US (1) | US4631667A (pt) |
EP (1) | EP0098494B1 (pt) |
JP (1) | JPS5941082A (pt) |
KR (1) | KR840005575A (pt) |
BR (1) | BR8303491A (pt) |
DE (1) | DE3380422D1 (pt) |
IT (1) | IT1151683B (pt) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4802120A (en) * | 1984-10-30 | 1989-01-31 | Tandy Corporation | Multistage timing circuit for system bus control |
EP0239827B1 (de) * | 1986-04-02 | 1993-05-26 | Siemens Aktiengesellschaft | Verfahren zum Ansteuern eines gemeinsamen Speichers eines aus einzelnen Mikroprozessorsystemen bestehenden Mehrprozessorsystems |
GB2194657B (en) * | 1986-08-29 | 1991-05-15 | Sun Microsystems Inc | Asynchronous micro-machine/interface |
US5053941A (en) * | 1986-08-29 | 1991-10-01 | Sun Microsystems, Inc. | Asynchronous micro-machine/interface |
EP0606102A1 (en) * | 1986-09-19 | 1994-07-13 | International Business Machines Corporation | An input output interface controller connecting a synchronous bus to an asynchronous bus and methods for performing operations on the buses |
US4839793A (en) * | 1987-07-01 | 1989-06-13 | Baytec, Inc. | Multiple computer interface |
JP2749819B2 (ja) * | 1987-10-26 | 1998-05-13 | 松下電工株式会社 | 共有メモリ制御方式 |
US5235684A (en) * | 1988-06-30 | 1993-08-10 | Wang Laboratories, Inc. | System bus having multiplexed command/id and data |
US5088025A (en) * | 1989-02-21 | 1992-02-11 | Unisys Corporation | Input/output processor control system with a plurality of staging buffers and data buffers |
US5155820A (en) * | 1989-02-21 | 1992-10-13 | Gibson Glenn A | Instruction format with designations for operand lengths of byte, half word, word, or double word encoded in address bits |
GB9008366D0 (en) * | 1990-04-12 | 1990-06-13 | British Aerospace | Data interaction architecture(dia)for real time embedded multi processor systems |
US5239639A (en) * | 1990-11-09 | 1993-08-24 | Intel Corporation | Efficient memory controller with an independent clock |
US5671430A (en) * | 1993-06-30 | 1997-09-23 | Gunzinger; Anton | Parallel data processing system with communication apparatus control |
US7743232B2 (en) | 2007-07-18 | 2010-06-22 | Advanced Micro Devices, Inc. | Multiple-core processor with hierarchical microcode store |
US11467838B2 (en) | 2018-05-22 | 2022-10-11 | Advanced Micro Devices, Inc. | Fastpath microcode sequencer |
US11016763B2 (en) | 2019-03-08 | 2021-05-25 | Advanced Micro Devices, Inc. | Implementing a micro-operation cache with compaction |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
IT993428B (it) * | 1973-09-26 | 1975-09-30 | Honeywell Inf Systems | Unita di controllo di calcolatore microprogrammato con microprogram mi residenti in memoria e sovrap posizioni delle fasi interpretati ve di una microistruzione con la fase esecutiva della precedente microistruzione |
IT995722B (it) * | 1973-10-10 | 1975-11-20 | Honeywell Inf Systems Italia | Calcolatore microprogrammato a interior decore espansibile mediante riconoscimento e interpre tazione di codici di operazione aggiunti |
US4204252A (en) * | 1978-03-03 | 1980-05-20 | Digital Equipment Corporation | Writeable control store for use in a data processing system |
IT1108732B (it) * | 1978-05-05 | 1985-12-09 | Honeywell Inf Systems | Sistema di trasmissione bidirezionale di segnali interbloccati |
IT1100916B (it) * | 1978-11-06 | 1985-09-28 | Honeywell Inf Systems | Apparato per gestione di richieste di trasferimento dati in sistemi di elaborazione dati |
IT1126475B (it) * | 1979-12-03 | 1986-05-21 | Honeywell Inf Systems | Apparato di comunicazione tra piu' processori |
-
1982
- 1982-07-06 IT IT22248/82A patent/IT1151683B/it active
-
1983
- 1983-06-27 US US06/507,854 patent/US4631667A/en not_active Expired - Fee Related
- 1983-06-27 DE DE8383106239T patent/DE3380422D1/de not_active Expired
- 1983-06-27 EP EP83106239A patent/EP0098494B1/en not_active Expired
- 1983-06-30 BR BR8303491A patent/BR8303491A/pt not_active IP Right Cessation
- 1983-07-01 KR KR1019830003048A patent/KR840005575A/ko not_active Application Discontinuation
- 1983-07-06 JP JP58123127A patent/JPS5941082A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
IT1151683B (it) | 1986-12-24 |
IT8222248A1 (it) | 1984-01-06 |
DE3380422D1 (en) | 1989-09-21 |
US4631667A (en) | 1986-12-23 |
EP0098494B1 (en) | 1989-08-16 |
KR840005575A (ko) | 1984-11-14 |
JPS5941082A (ja) | 1984-03-07 |
EP0098494A3 (en) | 1986-12-17 |
IT8222248A0 (it) | 1982-07-06 |
EP0098494A2 (en) | 1984-01-18 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM | Lapse due to non-payment of fees (art. 50) | ||
B21A | Patent or certificate of addition expired [chapter 21.1 patent gazette] |
Free format text: PATENTE EXTINTA EM 30/06/98 |