BR112017017345A2 - camadas de metal para uma célula de bit de três portas - Google Patents

camadas de metal para uma célula de bit de três portas

Info

Publication number
BR112017017345A2
BR112017017345A2 BR112017017345-0A BR112017017345A BR112017017345A2 BR 112017017345 A2 BR112017017345 A2 BR 112017017345A2 BR 112017017345 A BR112017017345 A BR 112017017345A BR 112017017345 A2 BR112017017345 A2 BR 112017017345A2
Authority
BR
Brazil
Prior art keywords
bit cell
metal layer
metal layers
door bit
coupled
Prior art date
Application number
BR112017017345-0A
Other languages
English (en)
Other versions
BR112017017345B1 (pt
Inventor
Narayan Mojumder Niladri
Chaba Ritu
Liu Ping
Seungchul Song Stanley
Wang Zhongze
Fei Yeap Choh
Original Assignee
Qualcomm Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Incorporated filed Critical Qualcomm Incorporated
Publication of BR112017017345A2 publication Critical patent/BR112017017345A2/pt
Publication of BR112017017345B1 publication Critical patent/BR112017017345B1/pt

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/418—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)

Abstract

trata-se de um aparelho que inclui uma primeira camada de metal acoplada a uma célula de bit. o aparelho também inclui uma terceira camada de metal que inclui uma linha de palavra de escrita que é acoplada à célula de bit. o aparelho inclui, adicionalmente, uma segunda camada de metal entre a primeira camada de metal e a terceira camada de metal. a segunda camada de metal inclui duas linhas de palavra de leitura acopladas à célula de bit.
BR112017017345-0A 2015-02-12 2015-11-25 Camadas de metal para uma célula de bit de três portas BR112017017345B1 (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/620,480 2015-02-12
US14/620,480 US9524972B2 (en) 2015-02-12 2015-02-12 Metal layers for a three-port bit cell
PCT/US2015/062644 WO2016130194A1 (en) 2015-02-12 2015-11-25 Metal layers for a three-port bit cell

Publications (2)

Publication Number Publication Date
BR112017017345A2 true BR112017017345A2 (pt) 2018-04-10
BR112017017345B1 BR112017017345B1 (pt) 2022-12-06

Family

ID=54834961

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112017017345-0A BR112017017345B1 (pt) 2015-02-12 2015-11-25 Camadas de metal para uma célula de bit de três portas

Country Status (9)

Country Link
US (3) US9524972B2 (pt)
EP (1) EP3257080B1 (pt)
JP (1) JP6884103B2 (pt)
KR (2) KR102504733B1 (pt)
CN (1) CN107210295B (pt)
BR (1) BR112017017345B1 (pt)
HK (1) HK1244354A1 (pt)
SG (1) SG11201705246UA (pt)
WO (1) WO2016130194A1 (pt)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9524972B2 (en) 2015-02-12 2016-12-20 Qualcomm Incorporated Metal layers for a three-port bit cell
US9793211B2 (en) * 2015-10-20 2017-10-17 Taiwan Semiconductor Manufacturing Co., Ltd. Dual power structure with connection pins
US10740531B2 (en) 2016-11-29 2020-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit, system for and method of forming an integrated circuit
US9887127B1 (en) 2016-12-15 2018-02-06 Globalfoundries Inc. Interconnection lines having variable widths and partially self-aligned continuity cuts
US10002786B1 (en) 2016-12-15 2018-06-19 Globalfoundries Inc. Interconnection cells having variable width metal lines and fully-self aligned variable length continuity cuts
US10043703B2 (en) * 2016-12-15 2018-08-07 Globalfoundries Inc. Apparatus and method for forming interconnection lines having variable pitch and variable widths
US9978682B1 (en) * 2017-04-13 2018-05-22 Qualcomm Incorporated Complementary metal oxide semiconductor (CMOS) standard cell circuits employing metal lines in a first metal layer used for routing, and related methods
CN112216323B (zh) 2017-09-04 2024-06-14 华为技术有限公司 一种存储单元和静态随机存储器
US10410714B2 (en) * 2017-09-20 2019-09-10 Qualcomm Incorporated Multi-level cell (MLC) static random access memory (SRAM) (MLC SRAM) cells configured to perform multiplication operations
CN111554336A (zh) * 2019-02-12 2020-08-18 联华电子股份有限公司 静态随机存取存储器单元
US11398274B2 (en) 2020-08-25 2022-07-26 Qualcomm Incorporated Pseudo-triple-port SRAM
US11302388B2 (en) 2020-08-25 2022-04-12 Qualcomm Incorporated Decoding for pseudo-triple-port SRAM
US11361817B2 (en) 2020-08-25 2022-06-14 Qualcomm Incorporated Pseudo-triple-port SRAM bitcell architecture
US11910587B2 (en) * 2021-02-26 2024-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Memory circuit having SRAM memory cells and method for forming a SRAM memory cell structure
US11955169B2 (en) * 2021-03-23 2024-04-09 Qualcomm Incorporated High-speed multi-port memory supporting collision

Family Cites Families (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3357382B2 (ja) * 1991-05-28 2002-12-16 株式会社日立製作所 多ポートメモリ
JP4885365B2 (ja) * 2000-05-16 2012-02-29 ルネサスエレクトロニクス株式会社 半導体装置
JP4171201B2 (ja) 2001-10-23 2008-10-22 松下電器産業株式会社 半導体記憶装置
KR100526884B1 (ko) * 2003-08-25 2005-11-09 삼성전자주식회사 듀얼 포트 에스램의 레이아웃 구조 및 그에 따른 형성방법
JP2005175415A (ja) 2003-12-05 2005-06-30 Taiwan Semiconductor Manufacturing Co Ltd 集積回路デバイスとその製造方法
SG115742A1 (en) * 2004-04-05 2005-10-28 Taiwan Semiconductor Mfg Sram device having high aspect ratio cell boundary
JP2006310467A (ja) * 2005-04-27 2006-11-09 Renesas Technology Corp 半導体記憶装置
US7324382B2 (en) * 2006-05-31 2008-01-29 Grace Semiconductor Manufacturing Corporation Current-mode sensing structure used in high-density multiple-port register in logic processing and method for the same
US7525868B2 (en) * 2006-11-29 2009-04-28 Taiwan Semiconductor Manufacturing Co., Ltd. Multiple-port SRAM device
JP5078338B2 (ja) * 2006-12-12 2012-11-21 ルネサスエレクトロニクス株式会社 半導体記憶装置
US20080291767A1 (en) * 2007-05-21 2008-11-27 International Business Machines Corporation Multiple wafer level multiple port register file cell
JP2009043304A (ja) * 2007-08-06 2009-02-26 Renesas Technology Corp 半導体装置
JP2009238332A (ja) * 2008-03-27 2009-10-15 Renesas Technology Corp 半導体記憶装置
JP2009260083A (ja) * 2008-04-17 2009-11-05 Renesas Technology Corp 半導体記憶装置
JP5231924B2 (ja) * 2008-10-03 2013-07-10 株式会社東芝 半導体記憶装置
US8675397B2 (en) * 2010-06-25 2014-03-18 Taiwan Semiconductor Manufacturing Company, Ltd. Cell structure for dual-port SRAM
JP5503480B2 (ja) * 2010-09-29 2014-05-28 ルネサスエレクトロニクス株式会社 半導体装置
JP5165040B2 (ja) 2010-10-15 2013-03-21 ルネサスエレクトロニクス株式会社 半導体集積回路
CN102385908A (zh) 2011-09-06 2012-03-21 复旦大学 一种多端口寄存器堆存储单元及其布局布线方法
US20130083591A1 (en) 2011-09-29 2013-04-04 John J. Wuu Alternating Wordline Connection in 8T Cells for Improving Resiliency to Multi-Bit SER Upsets
US8437166B1 (en) * 2011-11-16 2013-05-07 Taiwan Semiconductor Manufacturing Co., Ltd. Word line driver cell layout for SRAM and other semiconductor devices
US9831345B2 (en) * 2013-03-11 2017-11-28 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET with rounded source/drain profile
US9026973B2 (en) * 2013-03-14 2015-05-05 Taiwan Semiconductor Manufacturing Co., Ltd. System and method for arbitrary metal spacing for self-aligned double patterning
WO2015019411A1 (ja) * 2013-08-06 2015-02-12 ルネサスエレクトロニクス株式会社 半導体集積回路装置
US9281311B2 (en) * 2013-09-19 2016-03-08 Taiwan Semiconductor Manufacturing Co., Ltd. Memory cell array including a write-assist circuit and embedded coupling capacitor and method of forming same
US9202557B2 (en) * 2013-09-23 2015-12-01 Taiwan Semiconductor Manufacturing Co., Ltd. Three-dimensional two-port bit cell
US8929130B1 (en) * 2013-11-12 2015-01-06 Taiwan Semiconductor Manufacturing Company Limited Two-port SRAM cell structure
US9208854B2 (en) * 2013-12-06 2015-12-08 Taiwan Semiconductor Manufacturing Co., Ltd. Three dimensional dual-port bit cell and method of assembling same
US9312185B2 (en) * 2014-05-06 2016-04-12 International Business Machines Corporation Formation of metal resistor and e-fuse
US9412742B2 (en) * 2014-06-10 2016-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Layout design for manufacturing a memory cell
US9536596B2 (en) * 2014-08-26 2017-01-03 Qualcomm Incorporated Three-port bit cell having increased width
US9455026B2 (en) * 2014-11-18 2016-09-27 Qualcomm Incorporated Shared global read and write word lines
US9876017B2 (en) * 2014-12-03 2018-01-23 Qualcomm Incorporated Static random access memory (SRAM) bit cells with wordline landing pads split across boundary edges of the SRAM bit cells
US9368443B1 (en) * 2015-01-20 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Memory metal scheme
US9524972B2 (en) 2015-02-12 2016-12-20 Qualcomm Incorporated Metal layers for a three-port bit cell

Also Published As

Publication number Publication date
BR112017017345B1 (pt) 2022-12-06
EP3257080B1 (en) 2023-08-02
KR102504733B1 (ko) 2023-02-27
US20170062439A1 (en) 2017-03-02
EP3257080A1 (en) 2017-12-20
US9524972B2 (en) 2016-12-20
WO2016130194A1 (en) 2016-08-18
JP2018508991A (ja) 2018-03-29
SG11201705246UA (en) 2017-09-28
KR20220076545A (ko) 2022-06-08
EP3257080C0 (en) 2023-08-02
US10141317B2 (en) 2018-11-27
CN107210295A (zh) 2017-09-26
JP6884103B2 (ja) 2021-06-09
CN107210295B (zh) 2020-11-20
HK1244354A1 (zh) 2018-08-03
KR20170116021A (ko) 2017-10-18
US20160240539A1 (en) 2016-08-18
US20190035796A1 (en) 2019-01-31

Similar Documents

Publication Publication Date Title
BR112017017345A2 (pt) camadas de metal para uma célula de bit de três portas
AU201817098S (en) Convertible laptop computer
EP3497695A4 (en) WORD STREAM ANNOTATION
BR112018003885A2 (pt) método e sistema para estimar a porosidade associada à matéria orgânica, método para avaliar o potencial de produção de um poço ou formação, e, meio legível por computador não transitório
BR112017014901A2 (pt) sistema de empunhadura de paralelas retrátil para realizar execicíos de paralelas em um aparelho de exercícios
BR112017024256A2 (pt) meio de transmissão que tem múltiplos núcleos e métodos para uso com o mesmo.
BR112015007256A2 (pt) aparelho, método, e meio de armazenamento legível por computador não transitório.
BR112015019003A2 (pt) dispositivo para um sistema de construção de website, e método para um sistema de construção de website
BR112016015854A2 (pt) meio legível por computador, dispositivo de computação e método para seleção da precisão de vetor de movimento
JP2018531477A (ja) 完全空乏型シリコン・オン・インシュレータ・フラッシュメモリ設計
EP3422139A4 (en) LAPTOP
TW201614518A (en) Visualization suggestions
DK3779120T3 (da) Kemiske varmekilder til anvendelse i borehuloperationer
BR112015028732A2 (pt) método, e um ou mais meios legíveis por computador não transitórios tangíveis
DK3646404T3 (da) Brændselscellestakenhed
HK1249145A1 (zh) 用於ttk抑制劑化療的預後生物標記
ES1218754Y (es) Tapon para botellas
EP3245666A4 (en) Underlying absorbing or conducting layer for ebeam direct write (ebdw) lithography
SG11201805294VA (en) Insurance providing apparatus, insurance providing method, and computer readable recording medium with computer program recorded thereon
ES1215591Y (es) Tapon roscado
CL2015003606A1 (es) Combinación de derivado de imidazopiridazina y un agente mitotico para el tratamiento del cancer
UA39398S (uk) Ручка для письма
ECSDI19082871S (es) Tenka laptop
ES1197433Y (es) Tapon para botellas.
IT201800003315A1 (it) Dispositivo facilitatore di scrittura per tastiera informatica

Legal Events

Date Code Title Description
B06U Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]
B06A Patent application procedure suspended [chapter 6.1 patent gazette]
B09A Decision: intention to grant [chapter 9.1 patent gazette]
B16A Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]

Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 25/11/2015, OBSERVADAS AS CONDICOES LEGAIS