BR0105061A - Circuitos de processamento de dados de entrada - Google Patents

Circuitos de processamento de dados de entrada

Info

Publication number
BR0105061A
BR0105061A BR0105061-3A BR0105061A BR0105061A BR 0105061 A BR0105061 A BR 0105061A BR 0105061 A BR0105061 A BR 0105061A BR 0105061 A BR0105061 A BR 0105061A
Authority
BR
Brazil
Prior art keywords
input data
peps
synchronism
data processing
synchronisms
Prior art date
Application number
BR0105061-3A
Other languages
English (en)
Inventor
Hideaki Takahashi
Original Assignee
Nec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corp filed Critical Nec Corp
Publication of BR0105061A publication Critical patent/BR0105061A/pt

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/22—Arrangements for detecting or preventing errors in the information received using redundant apparatus to increase reliability
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1675—Temporal synchronisation or re-synchronisation of redundant processing components

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Communication Control (AREA)

Abstract

"CIRCUITOS DE PROCESSAMENTO DE DADOS DE ENTRADA". Um circuito de processamento de dados de entrada de acordo com um aspecto da presente invenção compreende um detector de fase 50 adaptado para detectar uma diferença de fase de sincronismo entre os primeiro e segundo sincronismos que são enviados a partir de circuitos duplicados. O conjunto de circuitos de leitura 60 seleciona um dentre os primeiro e segundo buffers PEPS (10 ou 30), se a diferença de fase de sincronismo for maior que um intervalo de tempo pré-determinado correspondente a metade do comprimento de dados do quadro, especificamente, "m" bites de conjuntos de dados de entrada. Neste caso, o buffer PEPS selecionado (10 ou 30) apresenta um sincronismo mais rápido pela diferença de fase de sincronismo que um outro sincronismo entre os primeiro e segundo sincronismos. Então, o conjunto de circuitos de leitura 60 lê o quadro somente a partir do buffer (PEPS) selecionado. Em conseq³ência, não haverá ocorrência de "falta de dados" no buffer PEPS mesmo se houver uma diferença de taxa de sincronismo entre os sincronismos gerados pelos circuitos duplicados.
BR0105061-3A 2000-09-06 2001-09-06 Circuitos de processamento de dados de entrada BR0105061A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000269549A JP3417476B2 (ja) 2000-09-06 2000-09-06 多入力データ同期回路

Publications (1)

Publication Number Publication Date
BR0105061A true BR0105061A (pt) 2002-05-21

Family

ID=18756134

Family Applications (1)

Application Number Title Priority Date Filing Date
BR0105061-3A BR0105061A (pt) 2000-09-06 2001-09-06 Circuitos de processamento de dados de entrada

Country Status (7)

Country Link
US (1) US6839863B2 (pt)
EP (1) EP1186994B1 (pt)
JP (1) JP3417476B2 (pt)
KR (1) KR100433079B1 (pt)
CN (1) CN1181431C (pt)
BR (1) BR0105061A (pt)
DE (1) DE60130177T2 (pt)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100381014C (zh) * 2002-08-09 2008-04-09 松下电器产业株式会社 遥控接收***
CN100337443C (zh) * 2003-07-02 2007-09-12 华为技术有限公司 一种先入先出存储器及快速产生存储标志的方法
ITMI20051749A1 (it) * 2005-09-21 2007-03-22 Marconi Comm Spa Adattamento delle frequenze nell'interfaccia di linee asincrone a livello fisico con linee sincrone a livello di connessione
JP6772479B2 (ja) * 2015-04-03 2020-10-21 株式会社デンソー 通信装置
CN105806399B (zh) * 2016-02-19 2018-02-16 西安航天动力技术研究所 一种弹载记录仪测量参数混合组帧方法
US10168731B2 (en) * 2016-07-13 2019-01-01 Advanced Micro Devices, Inc. Managing frequency changes of clock signals across different clock domains
CN106802133A (zh) * 2016-11-02 2017-06-06 北京信息科技大学 数据处理方法、数据处理***及应变测量装置

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6142079A (ja) 1984-08-02 1986-02-28 Toshiba Corp デ−タ収集装置
US5020023A (en) * 1989-02-23 1991-05-28 International Business Machines Corporation Automatic vernier synchronization of skewed data streams
JP2850366B2 (ja) * 1989-04-26 1999-01-27 ヤマハ株式会社 バッファメモリ回路
DE4227496A1 (de) 1992-08-20 1994-02-24 Philips Patentverwaltung Anordnung zur Erzeugung eines Multiplexsignals
US5626785A (en) * 1993-07-16 1997-05-06 Corning Incorporated Electrode assembly and method
DE4334650C1 (de) * 1993-10-12 1995-03-02 Uniroyal Englebert Gmbh Fahrzeugluftreifen mit Radialkarkasse
KR0177733B1 (ko) * 1994-08-26 1999-05-15 정장호 데이타 전송장치의 클럭동기 회로
US5619341A (en) * 1995-02-23 1997-04-08 Motorola, Inc. Method and apparatus for preventing overflow and underflow of an encoder buffer in a video compression system
DE19536518C2 (de) * 1995-09-29 1998-07-09 Siemens Ag Verfahren zur Aufrechterhaltung des mikrosynchronen Betriebs von gedoppelten informationsverarbeitenden Einheiten
KR100191724B1 (ko) 1995-12-21 1999-06-15 구자홍 데이타 수신 장치
US5822326A (en) 1996-05-10 1998-10-13 Tektronix, Inc. Synchronizing digital audio signals
US5931922A (en) * 1996-07-01 1999-08-03 Sun Microsystems, Inc. Media server system for preventing FIFO buffer underflow during multiple channel startup by waiting until buffer receives plurality of data blocks before enabling buffer to transmit received data
US5778221A (en) 1997-03-17 1998-07-07 International Business Machines Corporation System for executing asynchronous branch and link in parallel processor

Also Published As

Publication number Publication date
EP1186994A2 (en) 2002-03-13
CN1343050A (zh) 2002-04-03
DE60130177T2 (de) 2008-05-21
US20020029356A1 (en) 2002-03-07
KR20020020229A (ko) 2002-03-14
DE60130177D1 (de) 2007-10-11
EP1186994B1 (en) 2007-08-29
JP2002084263A (ja) 2002-03-22
KR100433079B1 (ko) 2004-05-28
JP3417476B2 (ja) 2003-06-16
CN1181431C (zh) 2004-12-22
EP1186994A3 (en) 2006-07-05
US6839863B2 (en) 2005-01-04

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Legal Events

Date Code Title Description
B06A Patent application procedure suspended [chapter 6.1 patent gazette]
B15K Others concerning applications: alteration of classification

Free format text: A CLASSIFICACAO ANTERIOR ERA: H04L 7/04

Ipc: H04L 1/22 (2006.01), H04L 7/00 (2006.01), G06F 11/

B11B Dismissal acc. art. 36, par 1 of ipl - no reply within 90 days to fullfil the necessary requirements