BE769731A - Procede permettant la fabrication d'un dispositif semiconducteur, et dispositif semiconducteur ainsi obtenu - Google Patents
Procede permettant la fabrication d'un dispositif semiconducteur, et dispositif semiconducteur ainsi obtenuInfo
- Publication number
- BE769731A BE769731A BE769731A BE769731A BE769731A BE 769731 A BE769731 A BE 769731A BE 769731 A BE769731 A BE 769731A BE 769731 A BE769731 A BE 769731A BE 769731 A BE769731 A BE 769731A
- Authority
- BE
- Belgium
- Prior art keywords
- semiconductor device
- manufacture
- process allowing
- allowing
- semiconductor
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title 2
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
- H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
- H01L21/7621—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region the recessed region having a shape other than rectangular, e.g. rounded or oblique shape
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/043—Dual dielectric
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/051—Etching
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/085—Isolated-integrated
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/103—Mask, dual function, e.g. diffusion and oxidation
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/106—Masks, special
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/117—Oxidation, selective
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/141—Self-alignment coat gate
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/143—Shadow masking
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/145—Shaped junctions
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/942—Masking
- Y10S438/944—Shadow
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Local Oxidation Of Silicon (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
NLAANVRAGE7010206,A NL170348C (nl) | 1970-07-10 | 1970-07-10 | Werkwijze voor het vervaardigen van een halfgeleiderinrichting, waarbij op een oppervlak van een halfgeleiderlichaam een tegen dotering en tegen thermische oxydatie maskerend masker wordt aangebracht, de door de vensters in het masker vrijgelaten delen van het oppervlak worden onderworpen aan een etsbehandeling voor het vormen van verdiepingen en het halfgeleiderlichaam met het masker wordt onderworpen aan een thermische oxydatiebehandeling voor het vormen van een oxydepatroon dat de verdiepingen althans ten dele opvult. |
Publications (1)
Publication Number | Publication Date |
---|---|
BE769731A true BE769731A (fr) | 1972-01-10 |
Family
ID=19810546
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
BE769731A BE769731A (fr) | 1970-07-10 | 1971-07-08 | Procede permettant la fabrication d'un dispositif semiconducteur, et dispositif semiconducteur ainsi obtenu |
Country Status (13)
Country | Link |
---|---|
US (1) | US3755001A (fr) |
JP (1) | JPS509390B1 (fr) |
AT (1) | AT344245B (fr) |
BE (1) | BE769731A (fr) |
BR (1) | BR7104397D0 (fr) |
CA (1) | CA925226A (fr) |
CH (1) | CH531254A (fr) |
DE (1) | DE2133978C3 (fr) |
ES (1) | ES393037A1 (fr) |
FR (1) | FR2098321B1 (fr) |
GB (1) | GB1353489A (fr) |
NL (1) | NL170348C (fr) |
SE (1) | SE361779B (fr) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3023410A1 (de) * | 1980-06-23 | 1982-01-07 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zur herstellung von mos-strukturen |
Families Citing this family (78)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7038290B1 (en) | 1965-09-28 | 2006-05-02 | Li Chou H | Integrated circuit device |
US5696402A (en) * | 1965-09-28 | 1997-12-09 | Li; Chou H. | Integrated circuit device |
US6979877B1 (en) * | 1965-09-28 | 2005-12-27 | Li Chou H | Solid-state device |
JPS5312158B1 (fr) * | 1971-06-05 | 1978-04-27 | ||
NL7113561A (fr) * | 1971-10-02 | 1973-04-04 | ||
US3968562A (en) * | 1971-11-25 | 1976-07-13 | U.S. Philips Corporation | Method of manufacturing a semiconductor device |
US3999213A (en) * | 1972-04-14 | 1976-12-21 | U.S. Philips Corporation | Semiconductor device and method of manufacturing the device |
US3810796A (en) * | 1972-08-31 | 1974-05-14 | Texas Instruments Inc | Method of forming dielectrically isolated silicon diode array vidicon target |
JPS5228550B2 (fr) * | 1972-10-04 | 1977-07-27 | ||
DE2251823A1 (de) * | 1972-10-21 | 1974-05-02 | Itt Ind Gmbh Deutsche | Halbleiterelement und herstellungsverfahren |
US3945030A (en) * | 1973-01-15 | 1976-03-16 | Signetics Corporation | Semiconductor structure having contact openings with sloped side walls |
JPS5317390B2 (fr) * | 1973-03-23 | 1978-06-08 | Mitsubishi Electric Corp | |
US3956527A (en) * | 1973-04-16 | 1976-05-11 | Ibm Corporation | Dielectrically isolated Schottky Barrier structure and method of forming the same |
JPS5918867B2 (ja) * | 1973-08-15 | 1984-05-01 | 日本電気株式会社 | 半導体装置 |
JPS5242634B2 (fr) * | 1973-09-03 | 1977-10-25 | ||
GB1437112A (en) * | 1973-09-07 | 1976-05-26 | Mullard Ltd | Semiconductor device manufacture |
GB1457139A (en) * | 1973-09-27 | 1976-12-01 | Hitachi Ltd | Method of manufacturing semiconductor device |
JPS604590B2 (ja) * | 1973-10-30 | 1985-02-05 | 三菱電機株式会社 | 半導体装置の製造方法 |
US3886000A (en) * | 1973-11-05 | 1975-05-27 | Ibm | Method for controlling dielectric isolation of a semiconductor device |
US4047195A (en) * | 1973-11-12 | 1977-09-06 | Scientific Micro Systems, Inc. | Semiconductor structure |
US3920482A (en) * | 1974-03-13 | 1975-11-18 | Signetics Corp | Method for forming a semiconductor structure having islands isolated by adjacent moats |
JPS50131490A (fr) * | 1974-04-03 | 1975-10-17 | ||
US3909304A (en) * | 1974-05-03 | 1975-09-30 | Western Electric Co | Method of doping a semiconductor body |
US3920481A (en) * | 1974-06-03 | 1975-11-18 | Fairchild Camera Instr Co | Process for fabricating insulated gate field effect transistor structure |
US3899363A (en) * | 1974-06-28 | 1975-08-12 | Ibm | Method and device for reducing sidewall conduction in recessed oxide pet arrays |
US3945857A (en) * | 1974-07-01 | 1976-03-23 | Fairchild Camera And Instrument Corporation | Method for fabricating double-diffused, lateral transistors |
DE2438256A1 (de) * | 1974-08-08 | 1976-02-19 | Siemens Ag | Verfahren zum herstellen einer monolithischen halbleiterverbundanordnung |
DE2445480A1 (de) * | 1974-09-24 | 1976-04-01 | Ibm Deutschland | Verfahren zur herstellung eines leistungstransistors |
US4046595A (en) * | 1974-10-18 | 1977-09-06 | Matsushita Electronics Corporation | Method for forming semiconductor devices |
US4023195A (en) * | 1974-10-23 | 1977-05-10 | Smc Microsystems Corporation | MOS field-effect transistor structure with mesa-like contact and gate areas and selectively deeper junctions |
JPS5171677A (en) * | 1974-12-18 | 1976-06-21 | Mitsubishi Electric Corp | Handotaisochino seizohoho |
JPS51113471A (en) * | 1975-03-31 | 1976-10-06 | Nec Corp | The manufacturing method of flat-shaped field-effect transistor |
US4044454A (en) * | 1975-04-16 | 1977-08-30 | Ibm Corporation | Method for forming integrated circuit regions defined by recessed dielectric isolation |
JPS51129181A (en) * | 1975-05-02 | 1976-11-10 | Toshiba Corp | Method of semiconductor device |
US3966514A (en) * | 1975-06-30 | 1976-06-29 | Ibm Corporation | Method for forming dielectric isolation combining dielectric deposition and thermal oxidation |
JPS5253679A (en) * | 1975-10-29 | 1977-04-30 | Hitachi Ltd | Productin of semiconductor device |
JPS5272189A (en) * | 1975-12-12 | 1977-06-16 | Matsushita Electric Ind Co Ltd | Production of semiconductor device |
US4137109A (en) * | 1976-04-12 | 1979-01-30 | Texas Instruments Incorporated | Selective diffusion and etching method for isolation of integrated logic circuit |
JPS52130572A (en) * | 1976-04-26 | 1977-11-01 | Nippon Telegr & Teleph Corp <Ntt> | Preparation of mis type semiconductor circuit device |
JPS6041470B2 (ja) * | 1976-06-15 | 1985-09-17 | 松下電器産業株式会社 | 半導体装置の製造方法 |
US4066473A (en) * | 1976-07-15 | 1978-01-03 | Fairchild Camera And Instrument Corporation | Method of fabricating high-gain transistors |
US4149177A (en) * | 1976-09-03 | 1979-04-10 | Fairchild Camera And Instrument Corporation | Method of fabricating conductive buried regions in integrated circuits and the resulting structures |
US4219369A (en) * | 1977-09-30 | 1980-08-26 | Hitachi, Ltd. | Method of making semiconductor integrated circuit device |
FR2422257A1 (fr) * | 1977-11-28 | 1979-11-02 | Silicium Semiconducteur Ssc | Procede de sillonnage et de glassiviation et nouvelle structure de sillon |
US4140558A (en) * | 1978-03-02 | 1979-02-20 | Bell Telephone Laboratories, Incorporated | Isolation of integrated circuits utilizing selective etching and diffusion |
US4170492A (en) * | 1978-04-18 | 1979-10-09 | Texas Instruments Incorporated | Method of selective oxidation in manufacture of semiconductor devices |
JPS5512743A (en) * | 1978-07-12 | 1980-01-29 | Nec Corp | Semiconductor integrated circuit manufacturing method |
US4256514A (en) * | 1978-11-03 | 1981-03-17 | International Business Machines Corporation | Method for forming a narrow dimensioned region on a body |
US4289550A (en) * | 1979-05-25 | 1981-09-15 | Raytheon Company | Method of forming closely spaced device regions utilizing selective etching and diffusion |
US4677456A (en) * | 1979-05-25 | 1987-06-30 | Raytheon Company | Semiconductor structure and manufacturing method |
FR2480502A1 (fr) * | 1980-04-14 | 1981-10-16 | Thomson Csf | Dispositif semi-conducteur a grille profonde, son application a une diode blocable, et procede de fabrication |
US4295266A (en) * | 1980-06-30 | 1981-10-20 | Rca Corporation | Method of manufacturing bulk CMOS integrated circuits |
JPS5773956A (en) * | 1980-10-27 | 1982-05-08 | Hitachi Ltd | Glass coated semiconductor device |
US4404579A (en) * | 1980-10-28 | 1983-09-13 | Inc. Motorola | Semiconductor device having reduced capacitance and method of fabrication thereof |
NL186886C (nl) * | 1980-11-28 | 1992-03-16 | Philips Nv | Halfgeleiderinrichting. |
US4454647A (en) * | 1981-08-27 | 1984-06-19 | International Business Machines Corporation | Isolation for high density integrated circuits |
US4372033A (en) * | 1981-09-08 | 1983-02-08 | Ncr Corporation | Method of making coplanar MOS IC structures |
US4563227A (en) * | 1981-12-08 | 1986-01-07 | Matsushita Electric Industrial Co., Ltd. | Method for manufacturing a semiconductor device |
US4403396A (en) * | 1981-12-24 | 1983-09-13 | Gte Laboratories Incorporated | Semiconductor device design and process |
JPS58132946A (ja) * | 1982-02-03 | 1983-08-08 | Toshiba Corp | 半導体装置の製造方法 |
DE3322669C2 (de) * | 1982-07-08 | 1986-04-24 | General Electric Co., Schenectady, N.Y. | Verfahren zum Herstellen einer Halbleitervorrichtung mit isolierten Gateelektroden |
US4591890A (en) * | 1982-12-20 | 1986-05-27 | Motorola Inc. | Radiation hard MOS devices and methods for the manufacture thereof |
FR2598557B1 (fr) * | 1986-05-09 | 1990-03-30 | Seiko Epson Corp | Procede de fabrication d'une region d'isolation d'element d'un dispositif a semi-conducteurs |
IT1225636B (it) * | 1988-12-15 | 1990-11-22 | Sgs Thomson Microelectronics | Metodo di scavo con profilo di fondo arrotondato per strutture di isolamento incassate nel silicio |
JPH039367U (fr) * | 1989-06-15 | 1991-01-29 | ||
JPH0770629B2 (ja) * | 1990-03-20 | 1995-07-31 | 株式会社東芝 | 不揮発性半導体記憶装置の製造方法 |
KR0138234B1 (ko) * | 1994-02-24 | 1998-04-28 | 김광호 | 고전압 모오스 트랜지스터의 구조 |
US5656510A (en) | 1994-11-22 | 1997-08-12 | Lucent Technologies Inc. | Method for manufacturing gate oxide capacitors including wafer backside dielectric and implantation electron flood gun current control |
US20040144999A1 (en) * | 1995-06-07 | 2004-07-29 | Li Chou H. | Integrated circuit device |
US6177333B1 (en) * | 1999-01-14 | 2001-01-23 | Micron Technology, Inc. | Method for making a trench isolation for semiconductor devices |
US6699775B2 (en) * | 2000-02-22 | 2004-03-02 | International Rectifier Corporation | Manufacturing process for fast recovery diode |
US9105790B2 (en) * | 2009-11-05 | 2015-08-11 | The Boeing Company | Detector for plastic optical fiber networks |
CN102637767B (zh) * | 2011-02-15 | 2015-03-18 | 上海凯世通半导体有限公司 | 太阳能电池的制作方法以及太阳能电池 |
CN102569492B (zh) * | 2010-12-17 | 2014-11-05 | 上海凯世通半导体有限公司 | 太阳能晶片的掺杂方法以及掺杂晶片 |
CN102637766B (zh) * | 2011-02-15 | 2014-04-30 | 上海凯世通半导体有限公司 | 太阳能晶片掺杂方法、掺杂晶片、太阳能电池及制作方法 |
CN102569491B (zh) * | 2010-12-17 | 2014-07-23 | 上海凯世通半导体有限公司 | 太阳能晶片的掺杂方法以及掺杂晶片 |
CN103208557A (zh) * | 2012-01-13 | 2013-07-17 | 上海凯世通半导体有限公司 | 太阳能电池的制作方法及太阳能电池 |
CN105225933B (zh) * | 2014-05-28 | 2018-06-26 | 上海凯世通半导体股份有限公司 | 掺杂方法 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CA826343A (en) * | 1969-10-28 | Kooi Else | Methods of producing a semiconductor device and a semiconductor device produced by said method | |
US3376172A (en) * | 1963-05-28 | 1968-04-02 | Globe Union Inc | Method of forming a semiconductor device with a depletion area |
US3386865A (en) * | 1965-05-10 | 1968-06-04 | Ibm | Process of making planar semiconductor devices isolated by encapsulating oxide filled channels |
GB1224562A (en) * | 1967-05-16 | 1971-03-10 | Texas Instruments Inc | An etching process |
GB1228754A (fr) * | 1967-05-26 | 1971-04-21 | ||
NL152707B (nl) * | 1967-06-08 | 1977-03-15 | Philips Nv | Halfgeleiderinrichting bevattende een veldeffecttransistor van het type met geisoleerde poortelektrode en werkwijze ter vervaardiging daarvan. |
US3649386A (en) * | 1968-04-23 | 1972-03-14 | Bell Telephone Labor Inc | Method of fabricating semiconductor devices |
-
1970
- 1970-07-10 NL NLAANVRAGE7010206,A patent/NL170348C/xx not_active IP Right Cessation
-
1971
- 1971-07-07 GB GB3184171A patent/GB1353489A/en not_active Expired
- 1971-07-07 CH CH1001071A patent/CH531254A/de not_active IP Right Cessation
- 1971-07-07 SE SE08801/71A patent/SE361779B/xx unknown
- 1971-07-07 CA CA117584A patent/CA925226A/en not_active Expired
- 1971-07-08 ES ES393037A patent/ES393037A1/es not_active Expired
- 1971-07-08 BE BE769731A patent/BE769731A/fr unknown
- 1971-07-08 DE DE2133978A patent/DE2133978C3/de not_active Expired
- 1971-07-08 US US00160654A patent/US3755001A/en not_active Expired - Lifetime
- 1971-07-08 AT AT593971A patent/AT344245B/de not_active IP Right Cessation
- 1971-07-09 FR FR7125295A patent/FR2098321B1/fr not_active Expired
- 1971-07-10 JP JP46050734A patent/JPS509390B1/ja active Pending
- 1971-07-12 BR BR4397/71A patent/BR7104397D0/pt unknown
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3023410A1 (de) * | 1980-06-23 | 1982-01-07 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zur herstellung von mos-strukturen |
Also Published As
Publication number | Publication date |
---|---|
JPS509390B1 (fr) | 1975-04-12 |
GB1353489A (en) | 1974-05-15 |
US3755001A (en) | 1973-08-28 |
ATA593971A (de) | 1977-11-15 |
JPS472519A (fr) | 1972-02-07 |
BR7104397D0 (pt) | 1973-04-05 |
FR2098321A1 (fr) | 1972-03-10 |
AT344245B (de) | 1978-07-10 |
ES393037A1 (es) | 1973-08-16 |
CA925226A (en) | 1973-04-24 |
DE2133978B2 (de) | 1979-09-06 |
DE2133978C3 (de) | 1985-06-27 |
NL7010206A (fr) | 1972-01-12 |
FR2098321B1 (fr) | 1976-05-28 |
CH531254A (de) | 1972-11-30 |
NL170348C (nl) | 1982-10-18 |
NL170348B (nl) | 1982-05-17 |
DE2133978A1 (de) | 1972-01-13 |
SE361779B (fr) | 1973-11-12 |
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