AU621788B2 - Total sum calculation circuit capable of rapidly calculating a total sum of more than two input data represented by a floating point representation - Google Patents
Total sum calculation circuit capable of rapidly calculating a total sum of more than two input data represented by a floating point representation Download PDFInfo
- Publication number
- AU621788B2 AU621788B2 AU47282/89A AU4728289A AU621788B2 AU 621788 B2 AU621788 B2 AU 621788B2 AU 47282/89 A AU47282/89 A AU 47282/89A AU 4728289 A AU4728289 A AU 4728289A AU 621788 B2 AU621788 B2 AU 621788B2
- Authority
- AU
- Australia
- Prior art keywords
- exponent
- parts
- total sum
- fraction
- shift
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
- G06F7/509—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination for multiple operands, e.g. digital integrators
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/01—Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
- G06F5/012—Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising in floating-point computations
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
- G06F7/485—Adding; Subtracting
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/499—Denomination or exception handling, e.g. rounding or overflow
- G06F7/49936—Normalisation mentioned as feature only
Landscapes
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Analysis (AREA)
- Pure & Applied Mathematics (AREA)
- Computing Systems (AREA)
- Computational Mathematics (AREA)
- Mathematical Optimization (AREA)
- General Engineering & Computer Science (AREA)
- Nonlinear Science (AREA)
- Complex Calculations (AREA)
- Medicines That Contain Protein Lipid Enzymes And Other Medicines (AREA)
- Error Detection And Correction (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63-334316 | 1988-12-28 | ||
JP63334316A JP2693800B2 (ja) | 1988-12-28 | 1988-12-28 | 浮動小数点データ総和演算回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
AU4728289A AU4728289A (en) | 1990-07-05 |
AU621788B2 true AU621788B2 (en) | 1992-03-19 |
Family
ID=18275991
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU47282/89A Ceased AU621788B2 (en) | 1988-12-28 | 1989-12-28 | Total sum calculation circuit capable of rapidly calculating a total sum of more than two input data represented by a floating point representation |
Country Status (6)
Country | Link |
---|---|
US (1) | US5021986A (ja) |
EP (1) | EP0376266B1 (ja) |
JP (1) | JP2693800B2 (ja) |
AU (1) | AU621788B2 (ja) |
CA (1) | CA2006704C (ja) |
DE (1) | DE68923606T2 (ja) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5166898A (en) * | 1990-09-07 | 1992-11-24 | Nec Corporation | Shift amount floating-point calculating circuit with a small amount of hardware and rapidly operable |
ES2109336T3 (es) | 1990-11-26 | 1998-01-16 | Genetics Inst | Expresion de pace en celulas huesped y metodos de utilizacion de la misma. |
US5247471A (en) * | 1991-12-13 | 1993-09-21 | International Business Machines Corporation | Radix aligner for floating point addition and subtraction |
EP0593073A1 (en) * | 1992-10-16 | 1994-04-20 | Matsushita Electric Industrial Co., Ltd. | A processor incorporating shifters |
GB2275355B (en) * | 1993-02-19 | 1997-06-18 | Motorola Inc | Detection of exponent underflow and overflow in a floating point adder |
JP2919386B2 (ja) * | 1996-09-19 | 1999-07-12 | 甲府日本電気株式会社 | 浮動小数点数検出装置および浮動小数点数検出回路 |
GB2323189B (en) * | 1997-03-14 | 2001-11-21 | Nokia Mobile Phones Ltd | Processing multi-bit signals representing floating-point numbers |
JP4086459B2 (ja) * | 2000-11-13 | 2008-05-14 | Necエレクトロニクス株式会社 | 固定小数点データ生成方法及び固定小数点データ生成回路 |
US6751638B2 (en) * | 2001-05-11 | 2004-06-15 | Sun Microsystems, Inc. | Min and max operations for multiplication and/or division under the simple interval system |
US7543013B2 (en) * | 2006-08-18 | 2009-06-02 | Qualcomm Incorporated | Multi-stage floating-point accumulator |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
AU589049B2 (en) * | 1986-10-31 | 1989-09-28 | International Business Machines Corporation | Method and circuit arrangement for adding floating point numbers |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4335372A (en) * | 1980-03-28 | 1982-06-15 | Motorola Inc. | Digital scaling apparatus |
JPS59188740A (ja) * | 1983-04-11 | 1984-10-26 | Hitachi Ltd | フロ−テイング加算器 |
US4562553A (en) * | 1984-03-19 | 1985-12-31 | Analogic Corporation | Floating point arithmetic system and method with rounding anticipation |
AU4490185A (en) * | 1984-07-30 | 1986-02-25 | Kumarasena, A.K. | The multi input fast adder |
US4734876A (en) * | 1985-12-18 | 1988-03-29 | Motorola, Inc. | Circuit for selecting one of a plurality of exponential values to a predetermined base to provide a maximum value |
AU606559B2 (en) * | 1987-12-24 | 1991-02-07 | Nec Corporation | Circuit for comparing a plurality of binary inputs |
-
1988
- 1988-12-28 JP JP63334316A patent/JP2693800B2/ja not_active Expired - Fee Related
-
1989
- 1989-12-27 CA CA002006704A patent/CA2006704C/en not_active Expired - Fee Related
- 1989-12-27 US US07/456,667 patent/US5021986A/en not_active Expired - Lifetime
- 1989-12-27 EP EP89123982A patent/EP0376266B1/en not_active Expired - Lifetime
- 1989-12-27 DE DE68923606T patent/DE68923606T2/de not_active Expired - Fee Related
- 1989-12-28 AU AU47282/89A patent/AU621788B2/en not_active Ceased
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
AU589049B2 (en) * | 1986-10-31 | 1989-09-28 | International Business Machines Corporation | Method and circuit arrangement for adding floating point numbers |
Also Published As
Publication number | Publication date |
---|---|
DE68923606T2 (de) | 1996-01-04 |
AU4728289A (en) | 1990-07-05 |
US5021986A (en) | 1991-06-04 |
EP0376266B1 (en) | 1995-07-26 |
EP0376266A3 (en) | 1992-03-04 |
CA2006704C (en) | 1993-12-21 |
EP0376266A2 (en) | 1990-07-04 |
CA2006704A1 (en) | 1990-06-28 |
DE68923606D1 (de) | 1995-08-31 |
JPH02178769A (ja) | 1990-07-11 |
JP2693800B2 (ja) | 1997-12-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
AU621788B2 (en) | Total sum calculation circuit capable of rapidly calculating a total sum of more than two input data represented by a floating point representation | |
US5508950A (en) | Circuit and method for detecting if a sum of two multibit numbers equals a third multibit constant number prior to availability of the sum | |
KR100241076B1 (ko) | 조정및정규화클래스를구비한부동소수점승산및누산장치 | |
JP3312155B2 (ja) | 浮動小数点加算器用の正確な先行ゼロ予測のための方法及び装置 | |
AU606559B2 (en) | Circuit for comparing a plurality of binary inputs | |
US6366943B1 (en) | Adder circuit with the ability to detect zero when rounding | |
US5771183A (en) | Apparatus and method for computation of sticky bit in a multi-stage shifter used for floating point arithmetic | |
CA1099007A (en) | Resolving angular ambiguity | |
EP0135290B1 (en) | Analog-to-digital-converter and related encoding technique | |
US5166898A (en) | Shift amount floating-point calculating circuit with a small amount of hardware and rapidly operable | |
US5408426A (en) | Arithmetic unit capable of performing concurrent operations for high speed operation | |
US6557021B1 (en) | Rounding anticipator for floating point operations | |
GB2149538A (en) | Digital multiplier | |
US4823300A (en) | Performing binary multiplication using minimal path algorithm | |
US6571264B1 (en) | Floating-point arithmetic device | |
CA2215719C (en) | Sticky bit determination in floating point arithmetic system | |
US5754458A (en) | Trailing bit anticipator | |
Yehia et al. | A redundant decimal floating-point adder | |
US6317772B1 (en) | Split remainder divider | |
EP0520298A2 (en) | Arithmetic circuit | |
US5432727A (en) | Apparatus for computing a sticky bit for a floating point arithmetic unit | |
JPS6126088B2 (ja) | ||
JP3187824B2 (ja) | 正規化回路 | |
US3470363A (en) | Hybrid multiplier apparatus | |
JP2555577B2 (ja) | 演算装置 |