AU4490185A - The multi input fast adder - Google Patents

The multi input fast adder

Info

Publication number
AU4490185A
AU4490185A AU44901/85A AU4490185A AU4490185A AU 4490185 A AU4490185 A AU 4490185A AU 44901/85 A AU44901/85 A AU 44901/85A AU 4490185 A AU4490185 A AU 4490185A AU 4490185 A AU4490185 A AU 4490185A
Authority
AU
Australia
Prior art keywords
multi input
input fast
fast adder
adder
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU44901/85A
Inventor
Kumarasena Arya Keerthi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
KUMARASENA AK
Original Assignee
Kumarasena A K
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kumarasena A K filed Critical Kumarasena A K
Publication of AU4490185A publication Critical patent/AU4490185A/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/509—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination for multiple operands, e.g. digital integrators

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
AU44901/85A 1984-07-30 1985-07-01 The multi input fast adder Abandoned AU4490185A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
LK942584 1984-07-30
LK9425 1984-07-30

Publications (1)

Publication Number Publication Date
AU4490185A true AU4490185A (en) 1986-02-25

Family

ID=19720948

Family Applications (1)

Application Number Title Priority Date Filing Date
AU44901/85A Abandoned AU4490185A (en) 1984-07-30 1985-07-01 The multi input fast adder

Country Status (3)

Country Link
EP (1) EP0188458A1 (en)
AU (1) AU4490185A (en)
WO (1) WO1986001017A1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2693800B2 (en) * 1988-12-28 1997-12-24 甲府日本電気株式会社 Floating point data sum operation circuit
ES2071556B1 (en) * 1992-12-31 1996-01-16 Alcatel Standard Electrica DEVICE TO REDUCE THE NUMBER OF DATA WORDS IN BINARY ARITHMETIC OPERATIONS.
ES2944296T3 (en) 2017-07-27 2023-06-20 Procter & Gamble Method and system for reducing the fluctuation of the auto-dosage of an automatic cleaning machine
EP3668961A1 (en) 2017-08-17 2020-06-24 The Procter and Gamble Company Method for reducing gelling between a liquid laundry detergent and a liquid fabric enhancer

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1145676A (en) * 1966-09-28 1969-03-19 Nippon Electric Co High speed adder circuit
US3675001A (en) * 1970-12-10 1972-07-04 Ibm Fast adder for multi-number additions
US3723715A (en) * 1971-08-25 1973-03-27 Ibm Fast modulo threshold operator binary adder for multi-number additions
NL7601785A (en) * 1976-02-23 1977-08-25 Philips Nv MULTI-FIGURE CALCULATOR.
US4157590A (en) * 1978-01-03 1979-06-05 International Business Machines Corporation Programmable logic array adder
US4348736A (en) * 1978-10-05 1982-09-07 International Business Machines Corp. Programmable logic array adder
US4241414A (en) * 1979-01-03 1980-12-23 Burroughs Corporation Binary adder employing a plurality of levels of individually programmed PROMS
US4399517A (en) * 1981-03-19 1983-08-16 Texas Instruments Incorporated Multiple-input binary adder

Also Published As

Publication number Publication date
EP0188458A1 (en) 1986-07-30
WO1986001017A1 (en) 1986-02-13

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