ATE70918T1 - Methode und vorrichtung fuer die fehlerpruefung eines taktverteilungsnetzwerks eines prozessors. - Google Patents

Methode und vorrichtung fuer die fehlerpruefung eines taktverteilungsnetzwerks eines prozessors.

Info

Publication number
ATE70918T1
ATE70918T1 AT84111866T AT84111866T ATE70918T1 AT E70918 T1 ATE70918 T1 AT E70918T1 AT 84111866 T AT84111866 T AT 84111866T AT 84111866 T AT84111866 T AT 84111866T AT E70918 T1 ATE70918 T1 AT E70918T1
Authority
AT
Austria
Prior art keywords
clock signal
distribution network
signal line
clock distribution
test latch
Prior art date
Application number
AT84111866T
Other languages
English (en)
Inventor
Gregory Scott Buchanan
John Joseph Defazio
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of ATE70918T1 publication Critical patent/ATE70918T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/273—Tester hardware, i.e. output processing circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30—Marginal testing, e.g. by varying supply voltage
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2273—Test methods

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Tests Of Electronic Circuits (AREA)
AT84111866T 1983-10-31 1984-10-04 Methode und vorrichtung fuer die fehlerpruefung eines taktverteilungsnetzwerks eines prozessors. ATE70918T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/547,179 US4542509A (en) 1983-10-31 1983-10-31 Fault testing a clock distribution network
EP84111866A EP0140205B1 (de) 1983-10-31 1984-10-04 Methode und Vorrichtung für die Fehlerprüfung eines Taktverteilungsnetzwerks eines Prozessors

Publications (1)

Publication Number Publication Date
ATE70918T1 true ATE70918T1 (de) 1992-01-15

Family

ID=24183635

Family Applications (1)

Application Number Title Priority Date Filing Date
AT84111866T ATE70918T1 (de) 1983-10-31 1984-10-04 Methode und vorrichtung fuer die fehlerpruefung eines taktverteilungsnetzwerks eines prozessors.

Country Status (6)

Country Link
US (1) US4542509A (de)
EP (1) EP0140205B1 (de)
JP (1) JPS60102575A (de)
AT (1) ATE70918T1 (de)
CA (1) CA1208699A (de)
DE (1) DE3485384D1 (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4653054A (en) * 1985-04-12 1987-03-24 Itt Corporation Redundant clock combiner
US4800564A (en) * 1986-09-29 1989-01-24 International Business Machines Corporation High performance clock system error detection and fault isolation
US4811343A (en) * 1987-03-02 1989-03-07 International Business Machines Corporation On-chip on-line AC and DC clock tree error detection system
DE3784496T2 (de) * 1987-06-11 1993-09-16 Ibm Taktgeneratorsystem.
NL8900151A (nl) * 1989-01-23 1990-08-16 Philips Nv Werkwijze voor het testen van een schakeling, alsmede schakeling geschikt voor een dergelijke werkwijze.
JP2632731B2 (ja) * 1989-08-02 1997-07-23 三菱電機株式会社 集積回路装置
US4972414A (en) * 1989-11-13 1990-11-20 International Business Machines Corporation Method and apparatus for detecting oscillator stuck faults in a level sensitive scan design (LSSD) system
EP0454320B1 (de) * 1990-04-20 1995-12-13 Texas Instruments Incorporated Abtasttestschaltung zur Verwendung mit Mehrfrequenzschaltungen
US5303246A (en) * 1991-07-03 1994-04-12 Hughes Aircraft Company Fault isolation diagnostics
WO1993006657A1 (en) * 1991-09-23 1993-04-01 Digital Equipment Corporation Update synchronizer
US5414714A (en) * 1992-03-26 1995-05-09 Motorola, Inc. Method and apparatus for scan testing an array in a data processing system
US5463338A (en) * 1993-06-07 1995-10-31 Vlsi Technology, Inc. Dual latch clocked LSSD and method
US5642069A (en) * 1994-04-26 1997-06-24 Unisys Corporation Clock signal loss detection and recovery apparatus in multiple clock signal system
JP2980304B2 (ja) * 1994-07-06 1999-11-22 沖電気工業株式会社 クロック障害検出回路
WO1997002493A2 (en) * 1995-07-06 1997-01-23 Philips Electronics N.V. A method for testing an electronic circuit by logically combining clock signals, and an electronic circuit provided with facilities for such testing
US5774474A (en) * 1996-03-14 1998-06-30 Sun Microsystems, Inc. Pipelined scan enable for fast scan testing
US6185723B1 (en) * 1996-11-27 2001-02-06 International Business Machines Corporation Method for performing timing analysis of a clock-shaping circuit
US6014510A (en) * 1996-11-27 2000-01-11 International Business Machines Corporation Method for performing timing analysis of a clock circuit
US6088830A (en) * 1998-07-28 2000-07-11 Evsx, Inc. Method and apparatus for logic circuit speed detection
US6272647B1 (en) * 1998-11-20 2001-08-07 Honeywell Inc. Fault tolerant clock voter with recovery
US7075365B1 (en) 2004-04-22 2006-07-11 Altera Corporation Configurable clock network for programmable logic device
US9330148B2 (en) * 2011-06-30 2016-05-03 International Business Machines Corporation Adapting data quality rules based upon user application requirements
FR3084488B1 (fr) 2018-07-24 2020-08-14 Stmicroelectronics (Grenoble 2) Sas Dispositif de detection d'une faute dans un circuit de propagation d'un signal d'horloge, et procede correspondant

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3056108A (en) * 1959-06-30 1962-09-25 Internat Bushiness Machines Co Error check circuit
US3783254A (en) * 1972-10-16 1974-01-01 Ibm Level sensitive logic system
IN146507B (de) * 1975-09-29 1979-06-23 Ericsson Telefon Ab L M
US4063078A (en) * 1976-06-30 1977-12-13 International Business Machines Corporation Clock generation network for level sensitive logic system
US4144448A (en) * 1977-11-29 1979-03-13 International Business Machines Corporation Asynchronous validity checking system and method for monitoring clock signals on separate electrical conductors
US4392226A (en) * 1981-09-28 1983-07-05 Ncr Corporation Multiple source clock encoded communications error detection circuit

Also Published As

Publication number Publication date
US4542509A (en) 1985-09-17
EP0140205A3 (en) 1988-03-23
DE3485384D1 (de) 1992-02-06
EP0140205B1 (de) 1991-12-27
JPS60102575A (ja) 1985-06-06
EP0140205A2 (de) 1985-05-08
CA1208699A (en) 1986-07-29

Similar Documents

Publication Publication Date Title
ATE70918T1 (de) Methode und vorrichtung fuer die fehlerpruefung eines taktverteilungsnetzwerks eines prozessors.
GB1478438A (en) Testing logic networks
DE3787431D1 (de) Verfahren zur Generierung einer Kandidatenliste von fehlerhaften Schaltungselementen und Verfahren zur Isolierung von Fehlern in einer logischen Schaltung unter Verwendung dieser Kandidatenliste.
CA2145403C (en) Robust delay fault built-in self-testing method and apparatus
DE2963143D1 (en) Method of and apparatus for testing electronic circuit assemblies and the like
Williams et al. Code coverage, what does it mean in terms of quality?
EP0297398B1 (de) Steuerkreis für Verarbeitungsimpulse
EP0093531A2 (de) Verfahren zum rechnergestützten "in-circuit"-Prüfen elektrischer Komponenten und dergleichen mit automatischer Nebensignalunterdrückung
MY112893A (en) Testing data processing apparatus
DK190785D0 (da) Fremgangsmaade til overvaagning af en databehandlingsenhed, samt anlaegtil udoevelse af fremgangsmaaden
EP0140155A3 (de) Prüfungseinrichtung zur Fehlererkennung bei gedoppelten Schaltungen, insbesondere Prozessoren eines Fernsprechvermittlungssystems
US20050038640A1 (en) Method and apparatus for automatically testing the design of a simulated integrated circuit
Sugiura et al. On the software reliability
EP1070297B1 (de) Verfahren und gerät zum automatischen test eines simulierten integrierten schaltkreises
KR970048581A (ko) 테스트 어댑터 보드 체크기
JPS6488266A (en) Testing system of semiconductor logic circuit
JPS58211672A (ja) 論理回路試験方法
JPS57712A (en) Decentralized train service control system
JPS61240173A (ja) 検査入力自動生成システム
Despotovic' A Quick Method for Developing a Transmission Loss Formula
Mamun et al. An automated methodology for the tracking of electrical performance for memory test systems
KOVIJANIC Automated testing and reliability and availability of digital systems[Ph. D. Thesis]
Rohlich The Technical Perspective(What is Quality Water)
Szygenda Simulation and test automation system for design verification and design error analysis, using automatic programming techniques
Fatemi et al. Automatic diagnosis of faults for digital hybrid circuits

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties