ATE549720T1 - Statische speichervorrichtungen - Google Patents

Statische speichervorrichtungen

Info

Publication number
ATE549720T1
ATE549720T1 AT08776503T AT08776503T ATE549720T1 AT E549720 T1 ATE549720 T1 AT E549720T1 AT 08776503 T AT08776503 T AT 08776503T AT 08776503 T AT08776503 T AT 08776503T AT E549720 T1 ATE549720 T1 AT E549720T1
Authority
AT
Austria
Prior art keywords
wells
biased
storage devices
static storage
globally
Prior art date
Application number
AT08776503T
Other languages
English (en)
Inventor
Villagra Luis Elvira
Rinze Meijer
De Gyvez Jose Pineda
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE549720T1 publication Critical patent/ATE549720T1/de

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0207Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B99/00Subject matter not provided for in other groups of this subclass
    • H10B99/22Subject matter not provided for in other groups of this subclass including field-effect components

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Static Random-Access Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
AT08776503T 2007-06-29 2008-06-25 Statische speichervorrichtungen ATE549720T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP07111407 2007-06-29
PCT/IB2008/052544 WO2009004535A2 (en) 2007-06-29 2008-06-25 Static memory devices

Publications (1)

Publication Number Publication Date
ATE549720T1 true ATE549720T1 (de) 2012-03-15

Family

ID=39764076

Family Applications (1)

Application Number Title Priority Date Filing Date
AT08776503T ATE549720T1 (de) 2007-06-29 2008-06-25 Statische speichervorrichtungen

Country Status (5)

Country Link
US (1) US8107288B2 (de)
EP (1) EP2162886B1 (de)
CN (1) CN101689399A (de)
AT (1) ATE549720T1 (de)
WO (1) WO2009004535A2 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8705300B1 (en) * 2007-02-27 2014-04-22 Altera Corporation Memory array circuitry with stability enhancement features
JP5197241B2 (ja) * 2008-09-01 2013-05-15 ルネサスエレクトロニクス株式会社 半導体装置
CN101635841B (zh) * 2009-09-04 2012-02-08 杭州华三通信技术有限公司 视频业务信息读写性能的调整方法和设备
US8625334B2 (en) * 2011-12-16 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Memory cell
US9053817B2 (en) * 2013-03-15 2015-06-09 Taiwan Semiconductor Manufacturing Company, Ltd. Amplifier
TWI698873B (zh) * 2017-03-28 2020-07-11 聯華電子股份有限公司 半導體記憶元件
TWI711159B (zh) * 2017-03-28 2020-11-21 聯華電子股份有限公司 半導體記憶元件
US10163493B2 (en) * 2017-05-08 2018-12-25 International Business Machines Corporation SRAM margin recovery during burn-in

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3204666B2 (ja) * 1990-11-21 2001-09-04 株式会社東芝 不揮発性半導体記憶装置
JPH1083689A (ja) * 1996-09-10 1998-03-31 Mitsubishi Electric Corp 不揮発性半導体記憶装置
JP2001338993A (ja) * 2000-03-24 2001-12-07 Toshiba Corp 半導体装置
JP2003132683A (ja) * 2001-10-23 2003-05-09 Hitachi Ltd 半導体装置
JP2005085349A (ja) * 2003-09-08 2005-03-31 Matsushita Electric Ind Co Ltd 半導体記憶装置
JP2006040495A (ja) * 2004-07-30 2006-02-09 Renesas Technology Corp 半導体集積回路装置
FR2878068A1 (fr) * 2004-11-15 2006-05-19 St Microelectronics Sa Memoire a cellule de memorisation polarisee par groupe
US20070091682A1 (en) * 2005-07-13 2007-04-26 Kang Sung-Taeg Byte-Erasable Nonvolatile Memory Devices
JP4822791B2 (ja) * 2005-10-04 2011-11-24 ルネサスエレクトロニクス株式会社 半導体記憶装置
US7733700B2 (en) * 2007-07-18 2010-06-08 Flashsilicon, Inc. Method and structures for highly efficient hot carrier injection programming for non-volatile memories
US7919368B2 (en) * 2009-05-29 2011-04-05 Texas Instruments Incorporated Area-efficient electrically erasable programmable memory cell

Also Published As

Publication number Publication date
US8107288B2 (en) 2012-01-31
CN101689399A (zh) 2010-03-31
WO2009004535A2 (en) 2009-01-08
US20100202192A1 (en) 2010-08-12
WO2009004535A3 (en) 2009-02-19
EP2162886B1 (de) 2012-03-14
EP2162886A2 (de) 2010-03-17

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