ATE278984T1 - Leistungssteuerung in einem asynchronen sender/empfänger - Google Patents

Leistungssteuerung in einem asynchronen sender/empfänger

Info

Publication number
ATE278984T1
ATE278984T1 AT95300444T AT95300444T ATE278984T1 AT E278984 T1 ATE278984 T1 AT E278984T1 AT 95300444 T AT95300444 T AT 95300444T AT 95300444 T AT95300444 T AT 95300444T AT E278984 T1 ATE278984 T1 AT E278984T1
Authority
AT
Austria
Prior art keywords
uart
clock
control unit
receiver
clock control
Prior art date
Application number
AT95300444T
Other languages
English (en)
Inventor
Scott C Johnson
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ATE278984T1 publication Critical patent/ATE278984T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G06F1/3215—Monitoring of peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Information Transfer Systems (AREA)
  • Dc Digital Transmission (AREA)
  • Communication Control (AREA)
  • Measuring Pulse, Heart Rate, Blood Pressure Or Blood Flow (AREA)
  • Circuits Of Receivers In General (AREA)
AT95300444T 1994-02-02 1995-01-25 Leistungssteuerung in einem asynchronen sender/empfänger ATE278984T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US19138894A 1994-02-02 1994-02-02

Publications (1)

Publication Number Publication Date
ATE278984T1 true ATE278984T1 (de) 2004-10-15

Family

ID=22705293

Family Applications (1)

Application Number Title Priority Date Filing Date
AT95300444T ATE278984T1 (de) 1994-02-02 1995-01-25 Leistungssteuerung in einem asynchronen sender/empfänger

Country Status (5)

Country Link
US (1) US5661751A (de)
EP (1) EP0666529B1 (de)
JP (1) JP3570762B2 (de)
AT (1) ATE278984T1 (de)
DE (1) DE69533599T2 (de)

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08202469A (ja) * 1995-01-30 1996-08-09 Fujitsu Ltd ユニバーサル非同期送受信回路を備えたマイクロ・コントローラユニット
US5787115A (en) * 1995-12-28 1998-07-28 Northern Telecom Limited Key telephone system without common control
US5918024A (en) * 1996-05-08 1999-06-29 Ericsson, Inc. Method and apparatus for providing single channel communications
KR100582112B1 (ko) * 1996-05-08 2006-09-11 에릭슨 인크. 단일채널양방향무선통신용반이중uart제어장치
US5903601A (en) * 1996-12-17 1999-05-11 Texas Instruments Incorporated Power reduction for UART applications in standby mode
TW455805B (en) * 1998-02-26 2001-09-21 Winbond Electronics Corp Converter allowing data communications equipment to transmit data to data terminal equipment through universal serial bus and the control method thereof
US6097243A (en) * 1998-07-21 2000-08-01 International Business Machines Corporation Device and method to reduce power consumption in integrated semiconductor devices using a low power groggy mode
US6378026B1 (en) * 1998-11-09 2002-04-23 Sipex Corporation Connection detection circuit and method
JP3565730B2 (ja) * 1999-01-13 2004-09-15 株式会社リコー Ａｔコマンド解析装置
US6317839B1 (en) * 1999-01-19 2001-11-13 International Business Machines Corporation Method of and apparatus for controlling supply of power to a peripheral device in a computer system
JP3266127B2 (ja) * 1999-01-25 2002-03-18 日本電気株式会社 同期式半導体記憶装置
US6232820B1 (en) * 1999-06-14 2001-05-15 Intel Corporation Method and apparatus for dynamic clock gating
US6944779B2 (en) * 1999-07-14 2005-09-13 Visteon Global Technologies, Inc. Power management fault strategy for automotive multimedia system
US6377071B1 (en) * 2000-03-31 2002-04-23 Cypress Semiconductor Corp. Composite flag generation for DDR FIFOs
US6675305B1 (en) * 2000-08-04 2004-01-06 Synopsys, Inc. Power saving in a USB peripheral by providing gated clock signal to CSR block in response to a local interrupt generated when an operation is to be performed
US6895518B2 (en) * 2001-05-31 2005-05-17 Koninklijke Philips Electronics N.V. Power and frequency adjustable UART device
JP4340536B2 (ja) * 2001-08-29 2009-10-07 メディアテック インコーポレーテッド 無線システムにおけるクロックおよび電力制御の方法および装置
FR2830956A1 (fr) * 2001-10-15 2003-04-18 St Microelectronics Sa Recepteur de donnees asynchrones comprenant des moyens de basculement en un mode veille
GB2386794A (en) * 2002-03-22 2003-09-24 Zarlink Semiconductor Ltd Power saving in a peripheral device
JP3749211B2 (ja) * 2002-09-06 2006-02-22 株式会社東芝 シリアルデータ受信回路
US6809570B2 (en) * 2003-01-21 2004-10-26 Hewlett-Packard Development Company, L.P. Clock gater circuit
US20050198542A1 (en) * 2004-03-08 2005-09-08 David Freker Method and apparatus for a variable memory enable deassertion wait time
EP1785809A1 (de) * 2005-11-14 2007-05-16 Texas Instruments Inc. Bereitschaftsmodus für Stromverwaltung
EP1785982A1 (de) * 2005-11-14 2007-05-16 Texas Instruments Incorporated Leistungsverwaltung einer Anzeige
EP1785810A1 (de) * 2005-11-14 2007-05-16 Texas Instruments Incorporated Ruhemodus für Stromverwaltung
US8458429B2 (en) * 2006-12-31 2013-06-04 Texas Instruments Incorporated Memory controller idle mode
US7667549B2 (en) 2007-04-26 2010-02-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and driving method thereof
CN101453315B (zh) * 2007-12-05 2011-06-22 中兴通讯股份有限公司 一种时钟跟随数据的数据传送方法
CN102687400B (zh) 2009-10-30 2016-08-24 株式会社半导体能源研究所 逻辑电路和半导体装置
KR102183102B1 (ko) 2009-11-27 2020-11-25 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 반도체 장치의 제작방법
KR102467172B1 (ko) 2016-01-25 2022-11-14 삼성전자주식회사 반도체 장치
US10209734B2 (en) 2016-01-25 2019-02-19 Samsung Electronics Co., Ltd. Semiconductor device, semiconductor system, and method of operating the semiconductor device
US10296065B2 (en) * 2016-01-25 2019-05-21 Samsung Electronics Co., Ltd. Clock management using full handshaking
DE102017110823A1 (de) 2016-01-25 2018-07-26 Samsung Electronics Co., Ltd. Halbleitervorrichtung, Halbleitersystem und Verfahren zum Betreiben der Halbleitervorrichtung
US10248155B2 (en) 2016-01-25 2019-04-02 Samsung Electronics Co., Ltd. Semiconductor device including clock generating circuit and channel management circuit
US10303203B2 (en) 2016-01-25 2019-05-28 Samsung Electronics Co., Ltd. Semiconductor device, semiconductor system and method for operating semiconductor device
TWI693498B (zh) * 2019-04-17 2020-05-11 方可成 多位元光運算系統
CN113448907B (zh) * 2021-08-31 2021-12-21 北京智联安科技有限公司 一种低功耗串行异步收发器及数据接收方法、介质
KR102454640B1 (ko) * 2022-01-04 2022-10-14 (주)파인디어칩 적응형 uart 시리얼 인터페이스를 구비한 집적회로

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4381552A (en) * 1978-12-08 1983-04-26 Motorola Inc. Stanby mode controller utilizing microprocessor
JPS59200327A (ja) * 1983-04-26 1984-11-13 Nec Corp 周辺装置の制御方式
US4665328A (en) * 1984-07-27 1987-05-12 National Semiconductor Corporation Multiple clock power down method and structure
US4851987A (en) * 1986-01-17 1989-07-25 International Business Machines Corporation System for reducing processor power consumption by stopping processor clock supply if a desired event does not occur
US4835737A (en) * 1986-07-21 1989-05-30 American Telephone And Telegraph Company, At&T Bell Laboratories Method and apparatus for controlled removal and insertion of circuit modules
US4878196A (en) * 1986-12-18 1989-10-31 Rose Frederick A Communications management system
US4949333A (en) * 1987-04-02 1990-08-14 Advanced Micro Devices, Inc. Enhanced universal asynchronous receiver-transmitter
EP0675425B1 (de) * 1989-06-30 1997-12-10 Fujitsu Personal Systems, Inc. Methode zur Reduzierung der Leistungsaufnahme eines Rechners
US5167024A (en) * 1989-09-08 1992-11-24 Apple Computer, Inc. Power management for a laptop computer with slow and sleep modes
JP2645163B2 (ja) * 1990-03-13 1997-08-25 三菱電機株式会社 非接触型ｉｃカード
US5237692A (en) * 1990-11-09 1993-08-17 Ast Research Inc. Internal interrupt controller for a peripheral controller
JP3701965B2 (ja) * 1991-05-17 2005-10-05 日本電気株式会社 保護モードマイクロプロセッサ及びハードディスクのための中断／再開機能とアイドルモードの実現
JP2842750B2 (ja) * 1992-04-07 1999-01-06 三菱電機株式会社 Ｉｃカード
JP2738229B2 (ja) * 1992-08-03 1998-04-08 日本電気株式会社 シリアル・データ通信制御装置
US5337285A (en) * 1993-05-21 1994-08-09 Rambus, Inc. Method and apparatus for power control in devices

Also Published As

Publication number Publication date
US5661751A (en) 1997-08-26
DE69533599T2 (de) 2005-10-13
EP0666529A1 (de) 1995-08-09
JPH07307765A (ja) 1995-11-21
JP3570762B2 (ja) 2004-09-29
EP0666529B1 (de) 2004-10-06
DE69533599D1 (de) 2004-11-11

Similar Documents

Publication Publication Date Title
DE69533599D1 (de) Leistungssteuerung in einem asynchronen Sender/Empfänger
US5086387A (en) Multi-frequency clock generation with low state coincidence upon latching
EP0579369B1 (de) Zentralprozessoreinheit mit verminderter Leistungsaufnahme
US6467042B1 (en) Method and/or apparatus for lowering power consumption in a peripheral device
EP0366250B1 (de) Modem mit reduzierbarer Versorgung
US6708278B2 (en) Apparatus and method for awakening bus circuitry from a low power state
EP0499440B1 (de) Schaltungsanordnung für mobiles Telefon
US6567921B1 (en) Asynchronous low power mode bus controller circuit and method of low power mode operation
US8332676B2 (en) Methods of preparing a power saving state, universal serial bus device and universal serial bus host
EP0624837A1 (de) Elektronisches Gerät mit verminderter Leistungsaufnahme
ATE262194T1 (de) Leistungssteuerungssystem für integrierten prozessor
KR20000069495A (ko) 전력 보존 동작 모드를 지원하는 방법 및 장치
WO2003096036A1 (en) Single-wire communication bus for miniature low-power systems
EP0662652A3 (de) Verfahren und Vorrichtung zur Reduzierung der Leistungsaufnahme in einem Rechnersystem
US7080269B2 (en) Method and apparatus for implementing power-saving sleep mode in design with multiple clock domains
JPH11112689A (ja) ホスト信号処理通信システム用ウエイクアップオンリング電力節約
JP2822986B2 (ja) Ｄｍａ内蔵シングルチップマイクロコンピュータ
US6269043B1 (en) Power conservation system employing a snooze mode
US7502635B1 (en) Method and computer for remote communication while operating in a power-saving mode
US5867718A (en) Method and apparatus for waking up a computer system via a parallel port
JP2000183894A (ja) 伝送制御装置
KR970016972A (ko) 정보 처리 시스템
EP0574177B2 (de) Verfahren und Gerät zur Änderung der Taktfrequenz eines Prozessors
KR930009768B1 (ko) 슬리프기능을 갖춘 컴퓨터 시스템 및 그 제어방법
TW248598B (en) Two clock microprocessor design with stall

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties