ATE142800T1 - Taktpuffer mit einstellbarer verzögerung und festem tastverhältnis-ausgang - Google Patents
Taktpuffer mit einstellbarer verzögerung und festem tastverhältnis-ausgangInfo
- Publication number
- ATE142800T1 ATE142800T1 AT91311830T AT91311830T ATE142800T1 AT E142800 T1 ATE142800 T1 AT E142800T1 AT 91311830 T AT91311830 T AT 91311830T AT 91311830 T AT91311830 T AT 91311830T AT E142800 T1 ATE142800 T1 AT E142800T1
- Authority
- AT
- Austria
- Prior art keywords
- buffer
- input
- clock
- differential
- clock signal
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
- H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
- H03K5/15026—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with asynchronously driven series connected output stages
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/10—Distribution of clock signals, e.g. skew
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Pulse Circuits (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Manipulation Of Pulses (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/635,721 US5157277A (en) | 1990-12-28 | 1990-12-28 | Clock buffer with adjustable delay and fixed duty cycle output |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE142800T1 true ATE142800T1 (de) | 1996-09-15 |
Family
ID=24548842
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT91311830T ATE142800T1 (de) | 1990-12-28 | 1991-12-19 | Taktpuffer mit einstellbarer verzögerung und festem tastverhältnis-ausgang |
Country Status (6)
Country | Link |
---|---|
US (1) | US5157277A (de) |
EP (1) | EP0493001B1 (de) |
JP (1) | JPH05216556A (de) |
AT (1) | ATE142800T1 (de) |
CA (1) | CA2057400C (de) |
DE (1) | DE69122068D1 (de) |
Families Citing this family (46)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5281861A (en) * | 1989-11-30 | 1994-01-25 | Compaq Computer Corporation | Sine wave clock distribution with high voltage output |
US6184736B1 (en) | 1992-04-03 | 2001-02-06 | Compaq Computer Corporation | Sinusoidal radio-frequency clock distribution system for synchronization of a computer system |
US5317202A (en) * | 1992-05-28 | 1994-05-31 | Intel Corporation | Delay line loop for 1X on-chip clock generation with zero skew and 50% duty cycle |
US5325400A (en) * | 1992-06-04 | 1994-06-28 | The Lan Guys, Inc. | Method and apparatus for predistortion of signals in digital transmission systems |
US5414745A (en) * | 1993-06-01 | 1995-05-09 | Advanced Micro Devices, Inc. | Synchronized clocking disable and enable circuit |
JP3487309B2 (ja) | 1993-06-30 | 2004-01-19 | 株式会社ルネサステクノロジ | 半導体集積回路装置 |
US5517532A (en) * | 1993-10-26 | 1996-05-14 | General Datacomm, Inc. | Standing sine wave clock bus for clock distribution systems |
US5537069A (en) * | 1995-03-30 | 1996-07-16 | Intel Corporation | Apparatus and method for selecting a tap range in a digital delay line |
US5604465A (en) * | 1995-06-07 | 1997-02-18 | International Business Machines Corporation | Adaptive self-calibration for fast tuning phaselock loops |
DE19653189C2 (de) * | 1996-12-19 | 1999-04-15 | Sgs Thomson Microelectronics | Analogsignal-Rechtecksignal-Umformvorrichtung mit Offset-Kompensation |
US5841305A (en) * | 1997-03-20 | 1998-11-24 | Cypress Semiconductor Corp. | Circuit and method for adjusting duty cycles |
US6247138B1 (en) * | 1997-06-12 | 2001-06-12 | Fujitsu Limited | Timing signal generating circuit, semiconductor integrated circuit device and semiconductor integrated circuit system to which the timing signal generating circuit is applied, and signal transmission system |
US6590901B1 (en) * | 1998-04-01 | 2003-07-08 | Mosaid Technologies, Inc. | Method and apparatus for providing a packet buffer random access memory |
KR100295045B1 (ko) * | 1998-06-23 | 2001-07-12 | 윤종용 | 지연동기루프(dll)를구비한반도체메모리장치 |
WO2001048919A1 (en) * | 1999-12-28 | 2001-07-05 | Mellanox Technologies Ltd. | Variable delay generator |
US6356132B1 (en) | 2000-01-31 | 2002-03-12 | Agere Systems Guardian Corp. | Programmable delay cell |
US6594806B1 (en) * | 2000-03-03 | 2003-07-15 | Nec Corporation | System and method for performing timing analysis, including error diagnosis, signal tracking and clock skew |
US6535986B1 (en) | 2000-03-14 | 2003-03-18 | International Business Machines Corporation | Optimizing performance of a clocked system by adjusting clock control settings and clock frequency |
US7884666B1 (en) * | 2000-10-11 | 2011-02-08 | Silicon Laboratories Inc. | Method and apparatus for reducing interference |
DE10056164C1 (de) * | 2000-11-13 | 2002-06-13 | Texas Instruments Deutschland | Schaltungsanordnung zur Erzeugung von mit Ausgangssignalen eines Taktgenerators flankensynchronen Taktsignalen für einen Halbleiterspeicher |
US6774692B2 (en) * | 2001-06-25 | 2004-08-10 | Hanyang Hak Won Co., Ltd. | Apparatus and method for providing square wave to atomic force microscope |
JP3502618B2 (ja) * | 2001-07-19 | 2004-03-02 | 松下電器産業株式会社 | 位相同期ループ回路、及びデータ再生装置 |
US7071757B2 (en) * | 2001-09-06 | 2006-07-04 | International Business Machines Corporation | Clock signal distribution utilizing differential sinusoidal signal pair |
US7106227B2 (en) * | 2001-09-28 | 2006-09-12 | Agilent Technologies, Inc. | Method and apparatus for synchronizing a multiple-stage multiplexer |
US6823466B2 (en) * | 2001-09-28 | 2004-11-23 | Agilent Technologies, Inc. | Circuit and method for adjusting the clock skew in a communications system |
US6509771B1 (en) | 2001-12-14 | 2003-01-21 | International Business Machines Corporation | Enhanced operational frequency for a precise and programmable duty cycle generator |
US6593789B2 (en) | 2001-12-14 | 2003-07-15 | International Business Machines Corporation | Precise and programmable duty cycle generator |
US6577202B1 (en) | 2001-12-14 | 2003-06-10 | International Business Machines Corporation | Multiple duty cycle tap points for a precise and programmable duty cycle generator |
US6603339B2 (en) | 2001-12-14 | 2003-08-05 | International Business Machines Corporation | Precision aligned multiple concurrent duty cycles from a programmable duty cycle generator |
US7194053B2 (en) * | 2001-12-18 | 2007-03-20 | Avago Technologies General Ip (Singapore) Pte. Ltd. | System and method for matching data and clock signal delays to improve setup and hold times |
US6897699B1 (en) * | 2002-07-19 | 2005-05-24 | Rambus Inc. | Clock distribution network with process, supply-voltage, and temperature compensation |
US6933759B1 (en) * | 2004-02-05 | 2005-08-23 | Texas Instruments Incorporated | Systems and methods of performing duty cycle control |
US7571406B2 (en) * | 2005-08-04 | 2009-08-04 | Freescale Semiconductor, Inc. | Clock tree adjustable buffer |
US7332983B2 (en) * | 2005-10-31 | 2008-02-19 | Hewlett-Packard Development Company, L.P. | Tunable delay line using selectively connected grounding means |
US7512019B2 (en) * | 2005-11-02 | 2009-03-31 | Micron Technology, Inc. | High speed digital signal input buffer and method using pulsed positive feedback |
US20080136468A1 (en) * | 2006-12-06 | 2008-06-12 | Dandan Li | Method and system for doubling phase-frequency detector comparison frequency for a fractional-n pll |
US7535272B1 (en) | 2007-11-23 | 2009-05-19 | Hong Kong Applied Science And Technology Research Institute Co. Ltd. | Zero-delay buffer with common-mode equalizer for input and feedback differential clocks into a phase-locked loop (PLL) |
CN101536315B (zh) * | 2007-11-23 | 2011-08-17 | 香港应用科技研究院有限公司 | 具有在锁相环输入和反馈差分时钟的共模均衡器的零延迟缓冲器 |
US7957412B2 (en) * | 2008-03-19 | 2011-06-07 | Cray Inc. | Lonely pulse compensation |
US20110292855A1 (en) * | 2010-05-28 | 2011-12-01 | Qualcomm Incorporated | Dynamic clock buffer power optimization based on modes of operation |
CN102173206B (zh) * | 2011-01-06 | 2013-04-10 | 珠海天威技术开发有限公司 | 耗材芯片及耗材容器 |
US8476947B2 (en) | 2011-11-14 | 2013-07-02 | Altera Corporation | Duty cycle distortion correction circuitry |
US8723572B1 (en) | 2012-03-30 | 2014-05-13 | Altera Corporation | Apparatus and methods to correct differential skew and/or duty cycle distortion |
US9237001B1 (en) | 2014-01-20 | 2016-01-12 | Altera Corporation | Method and apparatus to calibrate duty cycle distortion |
JP6981480B2 (ja) * | 2018-02-09 | 2021-12-15 | 富士通株式会社 | 受電器、電力伝送システム、及び受電方法 |
US11742856B2 (en) | 2021-11-26 | 2023-08-29 | Elite Semiconductor Microelectronics Technology Inc. | Digital buffer device with self-calibration |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4021740A (en) * | 1976-01-30 | 1977-05-03 | Communications Satellite Corporation (Comsat) | Sinewave clock driver with adjustable delay |
US4494021A (en) * | 1982-08-30 | 1985-01-15 | Xerox Corporation | Self-calibrated clock and timing signal generator for MOS/VLSI circuitry |
FR2582463B1 (fr) * | 1985-05-24 | 1995-01-06 | Thomson Video Equip | Dephaseur variable numerique et correcteur de velocite numerique pour magnetoscope utilisant un tel dephaseur |
JPS62136915A (ja) * | 1985-12-10 | 1987-06-19 | Victor Co Of Japan Ltd | パルス移相回路 |
IT1204395B (it) * | 1986-06-18 | 1989-03-01 | Sgs Microelettronica Spa | Circuito regolatore di fase,in particolare di fase orizzontale per visualizzatori di dati |
US4864160A (en) * | 1987-09-04 | 1989-09-05 | Schlumberger Systems And Services, Inc. | Timing signal generator |
US4891825A (en) * | 1988-02-09 | 1990-01-02 | Motorola, Inc. | Fully synchronized programmable counter with a near 50% duty cycle output signal |
-
1990
- 1990-12-28 US US07/635,721 patent/US5157277A/en not_active Expired - Lifetime
-
1991
- 1991-12-11 CA CA002057400A patent/CA2057400C/en not_active Expired - Fee Related
- 1991-12-19 EP EP91311830A patent/EP0493001B1/de not_active Expired - Lifetime
- 1991-12-19 AT AT91311830T patent/ATE142800T1/de not_active IP Right Cessation
- 1991-12-19 DE DE69122068T patent/DE69122068D1/de not_active Expired - Lifetime
- 1991-12-27 JP JP3359408A patent/JPH05216556A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
CA2057400A1 (en) | 1992-06-29 |
US5157277A (en) | 1992-10-20 |
CA2057400C (en) | 2001-03-13 |
EP0493001B1 (de) | 1996-09-11 |
DE69122068D1 (de) | 1996-10-17 |
EP0493001A3 (en) | 1992-10-21 |
EP0493001A2 (de) | 1992-07-01 |
JPH05216556A (ja) | 1993-08-27 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |