WO2024134842A1 - Appareil de commande d'attaque de grille et appareil onduleur - Google Patents

Appareil de commande d'attaque de grille et appareil onduleur Download PDF

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Publication number
WO2024134842A1
WO2024134842A1 PCT/JP2022/047452 JP2022047452W WO2024134842A1 WO 2024134842 A1 WO2024134842 A1 WO 2024134842A1 JP 2022047452 W JP2022047452 W JP 2022047452W WO 2024134842 A1 WO2024134842 A1 WO 2024134842A1
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Prior art keywords
gate
gate drive
signal
drive control
power
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PCT/JP2022/047452
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English (en)
Japanese (ja)
Inventor
拓也 荒船
武 幾山
慎太郎 田井
昌宏 土肥
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日立Astemo株式会社
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Priority to PCT/JP2022/047452 priority Critical patent/WO2024134842A1/fr
Publication of WO2024134842A1 publication Critical patent/WO2024134842A1/fr

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode

Definitions

  • the present invention relates to a gate drive control device and an inverter device.
  • An inverter device is a device that converts DC power into AC power.
  • an in-vehicle inverter device converts DC power supplied from a lithium-ion battery into AC power that is supplied to the motor that drives the vehicle. To drive the motor, it is necessary to generate a large amount of AC power, and so inverter devices are equipped with power devices, which are switching elements capable of handling large amounts of power.
  • Inverter devices also include a microcontroller and a gate drive control device to control the power device with high precision.
  • Patent Document 1 discloses a technology that uses a centralized power supply system in which an isolated power supply circuit is provided for gate driver circuits provided corresponding to each switching element, and an isolation transformer is used to supply power to each driver circuit, and one power supply circuit supplies power to multiple gate drive control devices.
  • Patent Document 1 for example, if a GND short fault occurs at the gate of one power device, when an attempt is made to drive the gate of the power device to a high level using the power supply voltage of the power supply circuit, the power supply voltage and GND are shorted, the power supply voltage drops below the minimum operating voltage, and the gate drive control device stops. Furthermore, if the power supply is shared with other gate drive control devices using a centralized power supply system, operation of non-faulty gate driver circuits also stops. As a result, the power device cannot be driven, safety control operations such as active short control cannot be performed, and it may be difficult to safely stop the vehicle.
  • the gate drive control device is a gate drive control device that drives a power device, and includes a gate drive unit that outputs a gate drive signal to the gate of the power device based on an input gate control command, and a gate diagnostic unit that detects an abnormality in the gate based on a comparison between the gate control command and the gate drive signal.
  • the present invention has the function of detecting an abnormality in the gate of a power device and outputs an abnormality notification signal when an abnormality is detected, making it possible to respond appropriately to the gate abnormality.
  • FIG. 1 is a diagram showing an example of an inverter device equipped with a gate drive control device.
  • FIG. 2 is a block diagram showing an example of the configuration of the gate drive control device according to the first embodiment.
  • FIG. 3 is a block diagram showing the configuration of the gate diagnosis unit when an abnormality is detected by voltage.
  • FIG. 4 is a timing chart illustrating the operation of the gate drive control device in the first embodiment.
  • FIG. 5 is a block diagram showing the configuration of a gate drive control device according to the second embodiment.
  • FIG. 6 is a block diagram showing the configuration of a gate diagnosis unit in the second embodiment.
  • FIG. 7 is a timing chart according to the second embodiment.
  • FIG. 8 is a diagram showing another circuit configuration of the gate diagnosis unit.
  • FIG. 1 is a diagram showing an example of an inverter device equipped with a gate drive control device.
  • FIG. 2 is a block diagram showing an example of the configuration of the gate drive control device according to the first embodiment.
  • FIG. 3 is a block
  • FIG. 9 is a diagram showing a configuration of an inverter device according to the third embodiment.
  • FIG. 10 is a diagram showing a configuration of a gate diagnosis unit in the fourth embodiment.
  • FIG. 11 is a timing chart according to the fourth embodiment.
  • FIG. 12 is a diagram showing a configuration of a gate diagnosis unit in the fifth embodiment.
  • FIG. 13 is a timing chart according to the fifth embodiment.
  • FIG. 14 is a diagram showing a configuration of an inverter device according to the sixth embodiment.
  • FIG. 15 is a diagram showing the configuration of a gate drive control device according to the sixth embodiment.
  • the names of the terminals of the power devices are standardized as gate terminal, drain terminal, and source terminal, but in the case of IGBTs, the drain terminal can be read as the collector terminal and the source terminal as the emitter terminal.
  • the power device is described as an IGBT, but it is possible to cover all power devices that control on and off switching by gate voltage, and it may be IGBT, SiC, Si-MOSFET, or GaN.
  • the isolator element is described as a transformer, but it is possible to cover all isolator elements, and it may be an isolator element using a photocoupler or capacitor.
  • a gate diagnostic unit provided in the gate drive control device compares a gate control command signal from a microcontroller with a gate signal from a power device, thereby detecting an abnormality occurring in the gate of the power device.
  • the following mainly describes the configuration and operation of the gate drive control device.
  • FIG. 1 is a diagram showing an example of an inverter device 8 equipped with a gate drive control device 1.
  • the inverter device 8 includes the gate drive control device 1, power device modules 2 that form the upper and lower arms of each of the U, V, and W phases, a power supply circuit 4 that supplies VCC voltage (VCC>GND) to the gate drive control device 1, a relay 5 that transmits and disconnects power from a high-voltage battery 6 to subsequent stages, a microcontroller 7, and a large-capacity capacitor 9 that stabilizes the power from the high-voltage battery 6.
  • VCC voltage VCC>GND
  • Each power device module 2 constituting the upper arm of each of the U, V, and W phases includes power devices 21u, 21v, and 21w, and free wheel diodes 23u, 23v, and 23w connected in parallel to each of the power devices 21u, 21v, and 21w.
  • each power device module 2 constituting the lower arm of each of the U, V, and W phases includes power devices 22u, 22v, and 22w, and free wheel diodes 24u, 24v, and 24w connected in parallel to the power devices 22u, 22v, and 22w of the lower arm.
  • the microcontroller 7 outputs a gate control command signal Sdrive to the gate drive control device 1 of each of the U, V, and W phases according to the rotation speed of the motor 3.
  • Each gate drive control device 1 controls the gate signal Sgate of the power device of the corresponding power device module 2 according to the gate control command signal Sdrive from the microcontroller 7.
  • the power devices 21u, 21v, and 21w of each power device module 2 in the upper arm connect and disconnect between the positive terminal of the high-voltage battery 6 and the motor 3 in response to the gate signal Sgate.
  • the power devices 22u, 22v, and 22w of each power device module 2 in the lower arm connect and disconnect between the negative terminal of the high-voltage battery 6 and the motor 3 in response to the gate signal Sgate.
  • the inverter device 8 generates the AC current required to rotate the motor 3 by alternately turning on and off the power devices of the upper and lower arms to receive the DC voltage supplied from the high-voltage battery 6 via the relay 5.
  • the power devices in the upper and lower arms are described as IGBTs.
  • the U, V, and W phases that drive the motor 3 differ only in phase, but their operation is the same.
  • the power devices in the upper and lower arms, including the gate drive control device 1 operate in the same way, but the connections between the drain and source terminals are different.
  • the following description focuses on the power devices in one power device module 2 in the lower arm and the gate drive control device 1, and explanations of the operation of the other phases and arms are omitted.
  • FIG. 2 is a block diagram showing an example of the configuration of the gate drive control device 1 in the first embodiment.
  • the gate drive control device 1 includes a gate drive unit 14 and a gate diagnosis unit 11.
  • a gate control command signal Sdrive from the microcontroller 7 is input to a gate control command signal line 111.
  • the microcontroller 7 is connected to the gate drive control device 1 via a transformer 73.
  • the gate driver 14 outputs a gate signal Sgate of the power device provided in the power device module 2 in response to the gate control command signal Sdrive.
  • the gate driver 14 in this embodiment includes a Pch-MOSFET 141 (hereinafter referred to as PMOS) connected between the positive power supply line 115 of the gate drive control device 1 and the gate signal line 112 of the power device, an Nch-MOSFET 142 (hereinafter referred to as NMOS) connected between the negative power supply line 116 of the inverter device 8 and the gate signal line 112 of the power device, and a NOT circuit 15 connected to the gates of the PMOS 141 and NMOS 142.
  • PMOS Pch-MOSFET 141
  • NMOS Nch-MOSFET 142
  • NOT circuit 15 connected to the gates of the PMOS 141 and NMOS 142.
  • the gate control command signal Sdrive input to the gate control command signal line 111 of the gate drive control device 1 is input to the gate drive unit 14 via the buffer circuit 17.
  • a gate control command signal Sdrive of a logical high level hereinafter referred to as "High”
  • the gate drive unit 14 outputs a High gate signal Sgate to the gate signal line 112 of the power device.
  • a gate control command signal Sdrive of a logical low level hereinafter referred to as "Low”
  • the gate drive unit 14 outputs a Low gate signal Sgate to the gate signal line 112.
  • the resistor 16 is a resistor that adjusts the slew rate of the gate signal Sgate when it is turned on and off.
  • the gate diagnostic unit 11 includes a comparison circuit 12 and a judgment circuit 13.
  • the gate diagnostic unit 11 monitors the gate control command signal Sdrive and the gate signal Sgate via the gate control command monitor line 113 and the power device gate monitor line 114.
  • the gate diagnostic unit 11 monitors the gate control command signal Sdrive and the gate signal Sgate of the gate signal line 112, respectively, and detects abnormalities in the gate signal Sgate.
  • the gate diagnostic unit 11 judges whether the gate signal Sgate is normal or abnormal depending on whether the states of the gate control command signal Sdrive and the gate signal Sgate match.
  • the state of the signal refers to the physical quantities (such as voltage and time) that the signal waveform possesses.
  • FIG. 3 is a block diagram showing an example of the configuration of the gate diagnostic unit 11 when detecting abnormalities based on voltage.
  • the gate diagnostic unit 11 includes a comparison circuit 12 and a judgment circuit 13.
  • the comparison circuit 12 includes an EXOR circuit 121, a filter circuit 122a that is composed of a delay circuit 123a, and an AND circuit 124.
  • the gate control command signal Sdrive and the gate signal Sgate are input to the EXOR circuit 121.
  • the comparison circuit 12 sets the mismatch detection signal Smismatch on the signal line 125 to High when the voltage levels (High or Low) of the gate control command signal Sdrive and the gate signal Sgate do not match for at least the delay time of the delay circuit 123a, i.e., the abnormality detection filter time Tfil1 (the delay time of the delay circuit).
  • the judgment circuit 13 judges whether the signal is abnormal or normal depending on whether the mismatch detection signal Smismatch output from the comparison circuit 12 is High or Low.
  • the judgment circuit 13 includes a simultaneous High input prevention circuit 126, a rising edge detection circuit 131 consisting of a JK flip-flop 133a and a delay circuit 123b, a NOT circuit 15, a filter circuit 122b, and a JK flip-flop 133b.
  • the output signal of the comparison circuit 12 is input to the rising edge detection circuit 131 and is also input to the K terminal of the JK flip-flop 133b via the NOT circuit 15 and the filter circuit 122b.
  • the output signal of the terminal Q of the rising edge detection circuit 131 is input to the J terminal of the JK flip-flop 133b via the simultaneous High input prevention circuit 126.
  • the abnormality notification signal output from the Q terminal of the JK flip-flop 133b is output to the abnormality notification signal line 118.
  • the abnormality notification signal line 118 is connected to the microcontroller 7, and the microcontroller 7 can execute safety measures upon receiving the abnormality notification signal.
  • the simultaneous high input prevention circuit 126 plays a role in preventing a high from being input simultaneously to the J terminal and the K terminal of the JK flip-flop 133. While a high is input to the K terminal, a low is input to one input of the AND circuit 124 via the NOT circuit 15, so a low is input to the J terminal.
  • the delay times of the delay circuits 123a and 123b may be the same or different.
  • the filter circuit 122b is composed of a delay circuit and an AND circuit, just like the filter circuit 122a, but the filter time Tfil2 for normal recovery is set longer than the filter time Tfil1.
  • the filter circuit is configured with a logic circuit, but it may also be configured using a timer or the like.
  • Timing chart shows the operation in the gate drive control device 1 when a gate control command signal Sdrive is input from the microcontroller 7 with a fixed period and a fixed pulse width.
  • the gate diagnostic unit 11 compares the voltage levels of the signals on the gate control command monitor line 113 and the gate monitor line 114 in the EXOR circuit 121. If the gate is normal, the gate signal Sgate will be High when the gate control command signal Sdrive is High, and the gate signal Sgate will be Low when the gate control command signal Sdrive is Low. Therefore, the EXOR circuit 121 always outputs Low, and the comparison circuit 12 outputs Low.
  • the gate signal line 112 When stuck at High level, the gate signal line 112 is fixed at a high level (hereinafter, fixed at H), the gate signal line 112 maintains a high level even if the gate control command signal Sdrive is low. Therefore, during the period when the gate control command signal Sdrive is low, the signal levels of the gate control command signal Sdrive (low) and the gate signal Sgate (high) input to the EXOR circuit 121 do not match, and the EXOR circuit 121 outputs a high level.
  • the filter circuit 122a of the comparison circuit 12 outputs High when the output of the EXOR circuit 121 has been High for the filter time Tfil1 or more for abnormality detection.
  • the filter time Tfil1 has elapsed after the gate signal line 112 is fixed at H (the output of the EXOR circuit 121 is High)
  • the signal level of the signal line 125 rises to High.
  • rising edge detection circuit 131 detects the rising edge of the mismatch detection signal Smismatch output from comparison circuit 12 to signal line 125, and outputs high to AND circuit 124 of simultaneous high input prevention circuit 126.
  • the input signal of filter circuit 122b changes from high to low, and the K terminal of JK flip-flop 133b also changes from high to low, so that the two inputs of AND circuit 124 become high, and AND circuit 124 outputs high to the J terminal of JK flip-flop 133b.
  • the Q terminal is set to high, and high (abnormality judgment) is output to abnormality notification signal line 118.
  • the gate control command signal Sdrive goes High
  • the signal levels of the gate control command signal Sdrive and the H-fixed gate signal Sgate match. Therefore, the output of the EXOR circuit 121 goes Low, and the mismatch detection signal Smismatch on the signal line 125 goes Low.
  • the J terminal of the rising edge detection circuit 131 goes Low
  • the K terminal goes High
  • a Low signal is output from the Q terminal of the rising edge detection circuit 131 to the J terminal of the JK flip-flop 133.
  • the input signal to the filter circuit 122b goes High, but the output of the filter circuit 122b remains Low until the filter time Tfil2 has elapsed. Therefore, the J terminal and K terminal of the JK flip-flop 133b go Low, Low, and the Q terminal and the abnormality notification signal line 118 remain High.
  • the mismatch detection signal Smismatch on the signal line 125 rises to high.
  • the gate control command signal Sdrive is low, the gate signal state returns to normal from fixed H, and the signal line 125 changes from high to low.
  • the Q terminal of the JK flip-flop 133b is reset, and Low is output to the abnormality notification signal line 118.
  • the timing chart is shown assuming that the filter time Tfil2 is set to the same value as one period of the gate control command signal Sdrive.
  • the gate signal line 112 When the gate signal line 112 is fixed at a low level (hereinafter, fixed at L), even if a high level is input to the gate control command signal line 111, the gate signal Sgate is output at a low level. Therefore, when the gate control command signal Sdrive becomes high, the voltage levels of the input signals (gate control command signal Sdrive and gate signal Sgate) of the EXOR circuit 121 do not match, and the EXOR circuit 121 outputs a high level.
  • the output of the filter circuit 122a changes from low to high after a filter time Tfil1 or more has elapsed, and the mismatch detection signal Smismatch (High) is output from the comparison circuit 12. Then, as in the case where a mismatch is detected due to the H fixation, a high level (abnormality determination) is output to the abnormality notification signal line 118. That is, an abnormality notification signal is output to the signal line 118.
  • abnormality notification signal output to the signal line 118 to the microcontroller 7 via communication or the like, control according to the detected abnormality becomes possible.
  • the abnormality notification signal may also be transmitted to an external element other than the microcontroller 7.
  • a PMOS is used for the high-side switching element and an NMOS is used for the low-side switching element, but an NMOS may be used for the high-side switching element and a PMOS for the low-side switching element.
  • a MOSFET is used for the switching element, but other switching elements such as a bipolar transistor may be used.
  • whether the gate control command signal Sdrive and the gate signal Sgate match is determined by voltage, but it may be determined by other physical quantities.
  • a threshold is set for the delay time, and if the threshold is exceeded, it is determined that an abnormality has occurred.
  • the filter time may be configured to change depending on the operation. For example, when the actual gate signal rises or falls, chattering may occur due to the influence of external noise, etc. Therefore, by making the filter time variable depending on the gate voltage, it is possible to prevent erroneous detection due to chattering during gate transition. Furthermore, by configuring the filter time to be rewritten from an external element, the filter time may be changed depending on the operation of the entire inverter.
  • the gate diagnostic unit 11 can detect an abnormality in the gate of the power device based on a comparison between the gate control command signal Sdrive from the microcontroller 7 and the gate signal Sgate of the power device, specifically, based on a mismatch between the high and low states of the signals. Therefore, by using this abnormality detection result, it is possible to deal with the gate abnormality through a safety control operation.
  • a gate in which an abnormality is detected can be cut off from the positive and negative power supplies to avoid adverse effects on other gate drive control devices that share the power supply.
  • safety control operations such as active short control can be performed under control from the microcontroller 7, allowing the vehicle to be stopped safely.
  • the second embodiment further includes a configuration in which, after detecting a mismatch between the gate control command signal Sdrive and the gate signal Sgate (gate abnormality), all circuits that control the gate signal Sgate are turned off to electrically cut off the positive power supply and the negative power supply from the gate signal Sgate in which an abnormality has occurred.
  • gate abnormality a mismatch between the gate control command signal Sdrive and the gate signal Sgate
  • all circuits that control the gate signal Sgate are turned off to electrically cut off the positive power supply and the negative power supply from the gate signal Sgate in which an abnormality has occurred.
  • FIG. 5 is a block diagram showing an example of the configuration of a gate drive control device 1B in the second embodiment. Focusing on a configuration different from that shown in FIG. 2 described above, the gate drive control device 1B has a gate drive stop signal line 117 between the gate diagnosis unit 11 and the gate drive unit 14, and has a function of stopping the gate drive of the power device of the power device module 2 (see FIG. 2) depending on the judgment result of the gate diagnosis unit 11.
  • the gate drive unit 14 receives the gate control command signal Sdrive and the stop signal output from the gate diagnosis unit 11.
  • An OR circuit 126 is provided on the PMOS gate signal line 143.
  • the gate control command signal Sdrive is input to one input terminal of the OR circuit 126 via the NOT circuit 15.
  • the gate stop signal of the gate drive stop signal line 117 is input to the other input terminal of the OR circuit 126.
  • An AND circuit 124 is connected to the NMOS gate signal line 144.
  • the gate control command signal Sdrive is input to one input terminal of the AND circuit 124 via the NOT circuit 15.
  • the gate stop signal of the gate drive stop signal line 117 is input to the other input terminal of the AND circuit 124 via the NOT circuit 15.
  • the gate diagnostic unit 11 shown in FIG. 6 differs from the gate diagnostic unit 11 in FIG. 3 in the configuration of the judgment circuit 13.
  • the judgment circuit 13 in the second embodiment further includes a NOT circuit 15, a filter circuit 122c having a filter time equal to the hold time Tstop_hold of the gate stop signal (High), a simultaneous High input prevention circuit 126, and a JK flip-flop 133c that outputs a gate drive stop signal that stops the gate drive of the gate drive unit 14.
  • the gate stop signal output from the JK flip-flop 133c is input to the K terminal of the JK flip-flop 133b via the NOT circuit 15, the filter circuit 122b, and the simultaneous High input prevention circuit 126, and is input to the gate drive unit 14 via the gate drive stop signal line 117.
  • gate signal line 112 is fixed at a low level (hereinafter referred to as L fixation).
  • L fixation When gate control command signal Sdrive is high, gate signal Sgate is fixed at low, so comparator circuit 12 detects a mismatch in the voltage levels of gate control command signal Sdrive and gate signal Sgate. Then, when filter time Tfil1 has elapsed since gate control command signal Sdrive of gate control command signal line 111 went high, mismatch detection signal Smismatch of signal line 125 is set to high. At this time, low is input to the K terminal of JK flip-flop 133c via NOT circuit 15, and high is input to the lower input terminal of AND circuit 124 of simultaneous high input prevention circuit 126.
  • a High signal is input to the upper input terminal of the AND circuit 124 of the simultaneous High input prevention circuit 126, and a High signal is output to the J terminal of the JK flip-flop 133c.
  • a High signal (gate stop signal) is output from the Q terminal of the JK flip-flop 133c to the gate drive stop signal line 117.
  • the gate drive unit 14 When the gate stop signal input from the gate drive stop signal line 117 to the gate drive unit 14 is low, the PMOS gate signal line 143 and the NMOS gate signal line 144 are low while the gate control command signal Sdrive is high. As a result, PMOS 141 is on and NMOS 142 is off. On the other hand, while the gate control command signal Sdrive is low, the PMOS gate signal line 143 and the NMOS gate signal line 144 are high, PMOS 141 is off and NMOS 142 is on. In other words, when the gate drive stop signal line 117 is low (normal), the gate drive unit 14 operates in the same way as the gate drive unit 14 shown in FIG. 2 in response to the high and low gate control command signal Sdrive.
  • the signal on the gate drive stop signal line 117 is High (gate stop signal)
  • a High signal is input to the lower input terminal of the OR circuit 126
  • a Low signal is input to the lower input terminal of the AND circuit 124.
  • the gate control command signal Sdrive is High
  • a Low signal is input to the upper input terminals of the OR circuit 126 and the AND circuit 124
  • the PMOS gate signal line 143 is High
  • the NMOS gate signal line 144 is Low.
  • the gate control command signal Sdrive is Low
  • a High signal is input to the upper input terminals of the OR circuit 126 and the AND circuit 124
  • the PMOS gate signal line 143 is High
  • the NMOS gate signal line 144 is Low.
  • both PMOS 141 and NMOS 142 are turned OFF, and the gate signal line 112 of the power device is electrically disconnected from the positive power supply line 115 of the gate drive control device 1B and the negative power supply line 116 of the inverter device 8.
  • FIG. 7 is a timing chart for the second embodiment.
  • the operation from detecting an abnormality in the gate signal to reporting the abnormality is the same as in the first embodiment described above, so a detailed explanation will be omitted here.
  • the gate signal line 112 is always low. Therefore, while the gate control command signal Sdrive is high, the voltage levels of the signals on the gate control command monitor line 113 in FIG. 6 and the gate monitor line 114 of the power device do not match.
  • the gate control command signal Sdrive is Low, so a mismatch is determined at the timing of the next High. If a mismatch is determined, the mismatch detection signal Smismatch on signal line 125 goes High after the abnormality detection filter time Tfil1 has elapsed. This causes the abnormality notification signal line 118 to go High in the same manner as in the first embodiment. In addition, the gate stop signal on gate drive stop signal line 117 goes High (stopped), so that both PMOS 141 and NMOS 142 are turned OFF as described above.
  • the gate control command signal Sdrive goes from a High state to Low ⁇ High ⁇ Low repeatedly, and then the gate signal state returns to normal.
  • the match state is maintained, so signal line 125 remains in the Low state.
  • the signal on signal line 125 is input to the K terminal of JK flip-flop 133c via filter circuit 122c. Therefore, JK flip-flop 133c outputs Low after the signal on signal line 125 finally falls to Low and outputs High (gate stop signal) for the gate stop signal hold time Tstop_hold. As a result, the signal on gate drive stop signal line 117 becomes Low.
  • JK flip-flop 133b When the output signal of JK flip-flop 133c returns from High (gate stopped) to Low (normal), JK flip-flop 133b outputs Low to signal line 118 after the normal return filter time Tfil2 has elapsed, as described above.
  • both PMOS 141 and NMOS 142 are turned OFF.
  • gate signal line 112 is fixed at L
  • when PMOS 141 is turned ON a short circuit occurs between positive power supply line 115 of gate drive controller 1B and GND, causing an instantaneous drop in VCC of gate drive controller 1B.
  • VCC is cut off before it falls below the minimum operating voltage Vope_min of gate drive controller 1B, and VCC returns to the normal voltage.
  • VEE ⁇ GND is used, but VEE and GND may be connected together to use the same potential.
  • the gate drive control device 1B of this embodiment turns off all circuits that control the gate signal line 112 of the power device.
  • the gate signal line 112 of the power device is electrically disconnected from the positive power supply line 115 of the gate drive control device 1B and the negative power supply line 116 of the inverter device 8.
  • a gate abnormality occurs, it is possible to prevent the gate drive control device 1B from stopping due to a drop in the power supply voltage.
  • Fig. 9 is a diagram showing the configuration of an inverter device 8B.
  • the inverter device 8B is configured using a centralized power supply system for supplying power to the gate drive control devices 1B.
  • a power supply circuit 41a is provided for the three gate drive control devices 1B on the upper arm side, and a power supply circuit 41b is provided for the three gate drive control devices 1B on the lower arm side. The following will mainly describe the configuration different from that of the inverter device 8 shown in Fig. 1.
  • Common safety controls include freewheel control, upper arm active short control, and lower arm active short control.
  • Freewheel control is a control in which all power devices in the upper and lower arms are controlled to be turned off, and the three-phase return current is regenerated to the high-voltage battery 6 by the return diode.
  • Upper arm active short control is a control in which all power devices in the upper arm of the three phases are controlled to be turned on, and all power devices in the lower arm of the three phases are controlled to be turned off, thereby regenerating current to the power devices in the upper arm.
  • lower arm active short control is a control in which all power devices in the lower arm of the three phases are controlled to be turned on, and all power devices in the upper arm of the three phases are controlled to be turned off, thereby regenerating current to the lower arm.
  • each power supply circuit 41a, 41b has three gate drive control devices 1B connected to the VCC output destination, and one power supply circuit 41a, 41b supplies power to the three gate drive control devices 1B.
  • each gate drive control device 1B of the lower arm when an L-fixed fault occurs in the gate signal line 112 of one phase of the power devices in the three power device modules 2 arranged in the lower arm.
  • the U-phase, V-phase, and W-phase are gate-driven with a phase shift of 120 degrees.
  • the positive power supply line 115 of the gate drive control device 1B shown in Figure 2 is connected to the L-fixed gate signal line 112, and the positive power supply voltage VCC drops instantaneously.
  • the gate drive control device 1B performs the same operation as that described in the second embodiment. That is, the gate diagnosis unit 11 detects a mismatch between the High gate control command signal Sdrive and the Low gate signal Sgate at the timing when the gate control command signal Sdrive goes High, and outputs a High (gate abnormality) signal to the abnormality notification signal line 118 shown in FIG. 6, and a High (stop signal) signal to the gate drive stop signal line 117.
  • the gate drive stop signal line 117 goes High, a High signal is output to the gate signal of PMOS 141 and a Low signal is output to the gate signal of NMOS 142, turning both PMOS 141 and NMOS 142 off.
  • the positive power supply line 115 of the gate drive controller 1B is electrically disconnected from the gate signal line 112 of the power device that is stuck low, and the voltage of the positive power supply line 115 of the gate drive controller 1B returns to the normal voltage. This prevents the common positive power supply voltage VCC from dropping below the minimum operating voltage, and other normal gate drive controllers 1B that share the positive power supply voltage VCC can continue to operate without stopping.
  • the abnormality notification signal line 118 goes high, the microcontroller 7 outputs high to the gate control command signal line 111 of all normal gate drive controllers 1B of the lower arm and low to the gate control command signal line 111 of all normal gate drive controllers 1B of the upper arm, thereby performing a lower arm active short control operation.
  • the power supply circuits 41a and 41b may be power supply circuits using a flyback system of an isolated DC-DC converter, a switching regulator, a linear regulator, a bandgap reference, or other power supply circuits.
  • the power supply circuits 41a and 41b may be configured to include one or more of these, or a combination of these.
  • two power supply circuits 41a, 41b are provided, and three gate drive control devices 1B for each upper arm and three gate drive control devices 1B for each lower arm are shared.
  • two or more of the gate drive control devices 1B mounted on the inverter device 8B can be shared in various combinations.
  • all of the gate drive control devices 1B for the upper arm and lower arm may be shared by one power supply circuit.
  • the third embodiment in a configuration that uses a centralized power supply system to supply power to the gate drive control device 1B, it is possible to perform a safety control operation when a failure occurs.
  • the gate drive control device employs a configuration similar to that of the gate drive control device 1B (Fig. 5) shown in the second embodiment, but the gate diagnosis unit 11 has the configuration shown in Fig. 10.
  • Fig. 11 is a timing chart in the fourth embodiment.
  • the gate diagnosis unit 11 detects the voltage difference between the gate control command signal Sdrive and the gate signal Sgate of the power device in an analog value. Then, based on the voltage difference, the amount of deterioration due to the time-dependent characteristic fluctuation is detected, and when the amount of deterioration exceeds a predetermined threshold, a sign diagnosis is performed to detect a sign before a failure occurs. Note that the following mainly describes the configuration and operation that are different from those of the gate drive control device 1B shown in the second embodiment.
  • FIG. 10 is a diagram showing an example of the gate diagnostic unit 11 in this embodiment.
  • the gate diagnostic unit 11 in this embodiment further includes a deterioration detection circuit 18 that detects changes over time in the gate characteristics of the power device.
  • the deterioration detection circuit 18 includes a differential amplifier 181, a switch element 182, a comparator 183, a latch circuit 184, and a filter circuit 122a.
  • the switch element 182 closes when the output of the AND circuit 124 is high, and opens when the output is low.
  • the gate control command signal Sdrive of the gate control command monitor line 113 is input to one input terminal of the AND circuit 124.
  • the mismatch detection signal Smismatch of the signal line 125 is input to the other input terminal of the AND circuit 124 via the NOT circuit 15.
  • the switch element 182 is in a closed state when the mismatch detection signal Smismatch of the signal line 125 is Low (match state) and the gate control command signal Sdrive is High, and is in an open state otherwise.
  • the switch element 182 transmits the voltage difference Vgate_aging to the voltage differential signal line 187.
  • the comparator 183 outputs either High or Low based on the difference between the voltage difference Vgate_aging and the pre-fault symptom determination threshold voltage Vth_aging.
  • the latch circuit 184 holds the output of the comparator 183.
  • the height of the High signal on the gate signal line 112 represents the magnitude of the voltage Vgate_h.
  • Vgate_aging Vref - Vgate_h
  • Vref Vgate_h
  • the height of the High signal corresponds to the expected voltage Vref.
  • the voltage Vgate_h has deteriorated
  • the height of the High signal (voltage Vgate_h) is lower than the expected voltage Vref
  • the difference between the expected voltage Vref and the height of the High signal is the voltage differential Vgate_aging.
  • the differential amplifier 181 outputs the voltage difference Vgate_aging regardless of the magnitude of the voltage difference Vgate_aging.
  • An analog filter circuit 127 having a filter time Tfil1 is provided on the output line 186 of the differential amplifier 181.
  • the analog filter circuit 127 outputs the voltage difference Vgate_aging because the voltage difference Vgate_aging has continued for more than the filter time Tfil1. Therefore, in FIG. 11, the rising edge of the signal on the voltage differential signal line 187 is delayed by the filter time Tfil1 relative to the rising edge of the signal on the gate signal line 112.
  • the switch element 182 closes only when no gate abnormality is detected and the gate control command signal Sdrive is High, and the voltage difference Vgate_aging is transmitted to the voltage differential signal line 187. Therefore, when the gate control command signal Sdrive switches from High to Low, the switch element 182 opens and the voltage differential signal line 187 becomes Low regardless of the gate signal state (see FIG. 11).
  • the switch element 182 opens to prevent the voltage difference Vgate_aging from being transmitted to the voltage differential signal line 187, and the gate drive control device 1B prioritizes the operation at the time of gate abnormality determination.
  • the comparator 183 compares the voltage difference Vgate_aging with the predictive judgment threshold voltage Vth_aging, and outputs Low (normal) to the latch circuit 184 if "Vgate_aging ⁇ Vth_aging", and outputs High (abnormal) to the latch circuit 184 if "Vgate_aging ⁇ Vth_aging". In other words, if the voltage difference Vgate_aging has not deteriorated or has deteriorated only slightly, the comparator 183 outputs Low (normal), and if the deterioration is significant, the comparator 183 outputs High (abnormal).
  • Vgate_aging ⁇ Vth_aging when a High (abnormal) signal is input to the J terminal of the JK flip-flop 133 of the latch circuit 184, a High signal is output from the Q terminal, and the pre-notification signal line 119 goes High, as shown in FIG. 11. If the deterioration is temporary and the voltage difference Vgate_aging subsequently returns to the normal range, the comparator 183 outputs Low again. In that case, the filter circuit 122b outputs High to the K terminal of the JK flip-flop 133b, since the output of the comparator 183 has been Low (normal) for the normal return filter time Tfil2 or more. As a result, the JK flip-flop 133b clears the pre-notification detection information it was holding, and outputs Low to the pre-notification signal line 119.
  • the early warning signal line 119 may be used within the gate drive control device 1B or may be sent to an external element for use. For example, by sending it to the microcontroller 7, it is possible to notify the user before a gate failure occurs. In addition, by using the early warning signal line 119 within the gate drive control device 1B, it is also possible to perform correction control against deterioration, such as increasing the voltage Vgate_h.
  • deterioration detection is performed by comparing voltage values, but this is merely one example, and similar diagnosis can be realized in various other forms.
  • a phase comparison circuit instead of the differential amplifier 181, it is possible to perform predictive diagnosis in terms of the time difference between the gate control command signal and the gate signal of the power device.
  • the gate drive control device 1B of the fourth embodiment detects the amount of deterioration due to characteristic fluctuations over time by detecting the voltage difference between the gate control command signal Sdrive and the gate signal Sgate of the power device in analog value in the gate diagnostic unit 11. Then, when the amount of deterioration exceeds a predetermined threshold, a predictive diagnosis can be performed to detect a precursor to a failure occurring. Therefore, by using the predictive diagnosis results, it is possible to prevent failures from occurring in the gate drive control device 1B.
  • the gate diagnostic unit 11 in the above-mentioned fourth embodiment is further provided with a configuration for detecting a time difference between a gate control command signal and a gate signal of a power device in an analog value, and detecting a sign of a failure before it occurs based on an amount of deterioration due to a characteristic change over time calculated from the detected time difference. Note that the following mainly describes the points that are different from the gate drive control device 1B shown in the fourth embodiment.
  • FIG. 12 is a diagram showing the configuration of the gate diagnostic unit 11 of the gate drive control device 1B in the fifth embodiment.
  • FIG. 13 is a timing chart in the fifth embodiment.
  • the deterioration detection circuit 18 in the fifth embodiment further includes a simultaneous high input prevention circuit 126, a JK flip-flop 133d, a switch element 182b, a filter circuit 122d having a pre-failure prediction value Tth_aging as a filter time, and a latch circuit 184b that holds the gate prediction warning signal Salert_aging, as a configuration for predicting the occurrence of a failure based on the amount of deterioration due to time-dependent characteristic fluctuation.
  • the switch element 182b opens and closes based on the output signal of the AND circuit 124, similar to the switch element 182.
  • the operation of the switch element 182b and the latch circuit 184b is the same as that of the switch element 182 and the latch circuit 184 described in the fourth embodiment, so the operation description will be omitted here.
  • the operation will be described with reference to the timing chart in FIG. 13. Note that in the timing chart in FIG. 13, it is assumed that no failure has occurred in the gate and no degradation of the gate voltage has occurred.
  • the gate control command signal Sdrive is input to the J terminal of the JK flip-flop 133d via the simultaneous high input prevention circuit 126, and the gate signal Sgate is input to the K terminal.
  • the time difference (phase difference) between the gate control command signal Sdrive and the gate signal Sgate is Tdiff
  • the threshold value for whether or not this time difference Tdiff has deteriorated is the above-mentioned sign determination value Tth_aging.
  • the time difference Tdiff is considered to be in a normal state. If the time difference Tdiff is Tth_aging > Tdiff > 0, the time deterioration is considered to be small. If the time difference Tdiff is Tdiff ⁇ Tth_aging, the time deterioration is considered to be large.
  • Tdiff if Tdiff>0, the following occurs.
  • a High gate control command signal Sdrive is input to the J terminal of the JK flip-flop 133d
  • the Q terminal goes High.
  • a High is input to the K terminal with the time difference Tdiff
  • the output of the Q terminal is inverted and goes Low.
  • a Low is input to one input of the AND circuit 124 in the simultaneous High input prevention circuit 126, so the AND circuit 124 outputs a Low to the J terminal.
  • the JK flip-flop 133d outputs a High signal when the gate control command signal Sdrive goes High, and then outputs a Low signal when the gate signal Sgate goes High. Therefore, the JK flip-flop 133 outputs a signal to the signal line 188, whose pulse width is the time difference Tdiff between when the gate control command signal Sdrive goes High and when the gate signal Sgate goes High.
  • the filter circuit 122d judges whether there is a pre-failure sign based on whether the time difference Tdiff is greater than the sign judgment value Tth_aging. If the time difference Tdiff (pulse width) is less than the sign judgment value Tth_aging (Tdiff ⁇ Tth_aging), the filter circuit 122d outputs Low to the latch circuit 184 in the subsequent stage. The latch circuit 184 outputs Low (normal) to the sign notification signal line 119. On the other hand, if the time difference Tdiff is large and is greater than or equal to the sign judgment value Tth_aging (Tdiff ⁇ Tth_aging), the filter circuit 122c outputs High to the latch circuit 184 in the subsequent stage. The latch circuit 184 outputs High (sign) to the sign notification signal line 119.
  • the early warning signal may be used within the gate drive control device 1B or may be sent to an external element for use. For example, by sending it to the microcontroller 7, it is possible to notify the user before a gate failure occurs. In addition, by using the early warning signal within the gate drive control device 1B, it is also possible to perform correction control for deterioration, such as shortening the time difference Tdiff.
  • the deterioration detection in the fifth embodiment is merely an example in which the amount of deterioration in voltage and time is detected separately and used for predictive judgment, and various other parameters may be used. It is also possible to detect from the perspective of the frequency difference or duty difference between the drive command and the gate signal. Also, as in the fourth embodiment ( Figure 10), it is also possible to perform predictive diagnosis only based on the time difference Tdiff.
  • the gate drive control device 1B of the fifth embodiment detects the amount of deterioration due to characteristic fluctuations over time by detecting the voltage difference between the gate control command signal Sdrive and the gate signal Sgate, and the time difference between the gate control command signal Sdrive and the gate signal Sgate, each in analog values in the gate diagnostic unit 11.
  • a predictive diagnosis can be performed to detect a precursor to a failure occurring.
  • FIG. 14 A sixth embodiment of the present invention will be described with reference to Figures 14 and 15.
  • an inverter device 8C in the sixth embodiment a plurality of power devices are electrically connected in parallel in each phase. Therefore, it is possible to handle large power while reducing the on-resistance of the power device module 2 in each phase.
  • the following description will focus on the differences from the inverter device 8B of the fourth embodiment shown in Figure 9.
  • FIG. 14 is a diagram showing an example of an inverter device 8C in the sixth embodiment.
  • FIG. 15 is a diagram showing the configuration of a gate drive control device 1C.
  • the inverter device 8C has two power device modules 2 in each arm of the U-phase, V-phase, and W-phase.
  • the power device modules 2 in each arm are electrically connected in parallel.
  • the two power device modules 2 connected in parallel are driven and controlled by one gate drive control device 1C.
  • gate drive units 14a, 14b and gate diagnosis units 11a, 11b are provided individually for each of the two power device modules 2 (see FIG. 5).
  • the two gate drivers 14a, 14b and the gate diagnostic units 11a, 11b each receive the same gate control command signal Sdrive.
  • the gate diagnostic units 11a, 11b receive the gate signal Sgate of the gate signal lines 112a, 112b via the gate monitor lines 114a, 114b.
  • the two gate diagnostic units 11a, 11b compare the gate control command signal Sdrive in the corresponding power device module 2 with the gate signal Sgate of the gate signal lines 112a, 112b to detect each gate abnormality.
  • the gate diagnostic unit 11a receives a gate drive stop signal via the gate drive stop signal line 117a to the gate driver 14a.
  • the gate diagnostic unit 11b receives a gate drive stop signal via the gate drive stop signal line 117b to the gate driver 14b.
  • the gate diagnostic unit 11a For example, if an abnormality is detected in one of the gates by the gate diagnostic unit 11a, the gate where the abnormality was detected is disconnected from the positive power supply line 115 of the gate drive control device 1C and the negative power supply line 116 of the inverter device 8C by stopping the operation of the gate drive unit 14a.
  • the other gate is normal and continues to operate normally.
  • the configuration of the gate drive control device 1C is described, which has the same number of gate drivers 14a, 14b and gate diagnostic units 11a, 11b as the power device modules 2.
  • the number of gate drivers 14 and gate diagnostic units 11 does not necessarily have to be the same as the number of power devices.
  • an operation was described in which if an abnormality is detected in one gate, the other gate continues normal operation, but other operations may also be used. For example, if an abnormality is detected in one gate, it is also possible to stop driving the other gate.
  • the power device of the power device module 2 is an IGBT, but in a configuration using a wide band gap power device such as SiC, the gate abnormality detection operation works more effectively.
  • the gate signal line 112 is fixed at L, when the PMOS 141 is turned on, the positive power supply line 115 of the gate drive control device 1, 1B, 1C and GND are shorted, and the VCC of the gate drive control device 1, 1B, 1C drops instantly.
  • the gate rises quickly in a wide band gap power device the abnormality can be detected and cut off more quickly, and the drop in VCC shown in the chart of the positive power supply line 115 in FIG. 7 can be suppressed to a smaller level.
  • the gate rise transition time is short, the diagnosis error due to the transition time is reduced, and more accurate diagnosis is possible.
  • the gate drive control device 1 that drives the power devices of the power device module 2 includes a gate drive unit 14 that outputs a gate drive signal (gate signal Sgate) to the gate of the power device based on an input gate control command (gate control command signal Sdrive), and a gate diagnostic unit 11 that detects gate abnormalities (e.g., abnormalities caused by abnormalities in the power device or the gate drive unit 14) based on a comparison between the gate control command and the gate drive signal.
  • gate abnormalities e.g., abnormalities caused by abnormalities in the power device or the gate drive unit 14
  • the gate diagnostic unit 11 can detect gate abnormalities, and upon detection of the abnormality, it becomes possible to deal with the gate abnormality through a safety control operation.
  • a gate in which an abnormality has been detected can be cut off from the positive and negative power supplies to avoid adverse effects on other gate drive control devices sharing the power supply.
  • the gate diagnostic unit 11 functions as a cutoff unit that electrically cuts off a gate in which an abnormality has been detected from the power supply (VCC, VEE) of the gate driver 14, and when the gate diagnostic unit 11 detects a gate abnormality, it electrically cuts off the gate in which the abnormality has been detected from the power supply (VCC, VEE) of the gate driver 14.
  • VCC, VEE power supply
  • the gate diagnostic unit 11 detects a gate abnormality, it electrically cuts off the gate in which the abnormality has been detected from the power supply (VCC, VEE) of the gate driver 14.
  • the gate diagnostic unit 11 when it detects an abnormality in the gate, it outputs an abnormality notification signal to the abnormality notification signal 118. Since the abnormality notification signal is configured to be output to the signal 118, for example, by inputting the abnormality notification signal to the microcontroller 7 via the signal line 118, the microcontroller 7 can perform a safety control operation. For example, when an abnormality is detected in the upper arm, the microcontroller 7 can perform a lower arm active short control operation by outputting High to the gate control command signal line 111 of all gate drive control devices 1 of the lower arm that are normal and Low to the gate control command signal line 111 of all gate drive control devices 1 of the upper arm.
  • the deterioration detection circuit 18 of the gate diagnostic unit 11 has a function as a detection unit that detects the time-dependent variation of the gate characteristics of the power device based on the gate control command (gate control command signal Sdrive) and the gate drive signal (gate signal Sgate), and a function as a sign determination unit that determines the gate failure sign of the power device based on the detected time-dependent variation. Therefore, by utilizing the determination result of the gate failure sign, it is possible to prevent the occurrence of a failure in the gate drive control device.
  • the deterioration detection circuit 18 of the gate diagnosis unit 11 functioning as a detection unit detects at least one of a first time variation based on voltage information of the gate control command (gate control command signal Sdrive) and the gate drive signal (gate signal Sgate) and a second time variation based on time information (time difference Tdiff) of the gate control command and the gate drive signal, and the sign determination unit (deterioration detection circuit 18) may determine whether or not there is a gate failure sign based on the detected time variation when at least one of the first and second time variations is detected by the detection unit.
  • the inverter device 8 includes a plurality of power devices 21u-21w, 22u-22w, a gate drive control device 1 described in (C1) above that is provided corresponding to each of the plurality of power devices 21u-21w, 22u-22w and drives the corresponding power device, and a power supply circuit 4 that is provided corresponding to each of the plurality of gate drive control devices 1 and supplies power to the corresponding gate drive control device 1.
  • Each gate drive control device 1 provided in the inverter device 8 has the same effect as that described in (C1) above. As a result, the safety controllability of the inverter device 8 can be improved.
  • the inverter device 8B includes a power device provided in each of the multiple power device modules 2, a gate drive control device 1B described in (C2) above that is provided corresponding to each of the multiple power devices and drives the corresponding power device, and one power supply circuit 41a, 41b that supplies power to each of the multiple gate drive control devices 1B.
  • Each gate drive control device 1B provided in the inverter device 8B has the same effect as the effect described in (C2) above. As a result, the safety controllability of the inverter device 8B can be improved.
  • the inverter device 8C includes a plurality of power devices electrically connected in parallel, and a gate drive control device 1C described in (C1) above that is provided for the plurality of power devices.
  • the gate drive control device 1C outputs a gate drive signal (gate signal Sgate) to each of the plurality of power devices connected in parallel based on a gate control command (gate control command signal Sdrive).
  • gate control command signal Sdrive As in the case of (C1) above, it is possible to detect gate abnormalities and to deal with the gate abnormality through a safety control operation.
  • the power device provided in the power device module 2 is a wide bandgap power device.
  • the gate abnormality detection operation in the gate drive control device of the inverter device functions more effectively.
  • a wide bandgap power device has a fast gate rise, abnormality detection and blocking can be performed more quickly, and the drop in VCC shown in the chart of the positive power supply line 115 in Figure 7 can be suppressed to a smaller level.
  • the gate rise transition time is short, diagnostic errors due to the transition time are reduced, making it possible to perform more accurate diagnosis.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Power Conversion In General (AREA)

Abstract

L'invention concerne un appareil de commande d'attaque de grille (1) comprenant : une unité d'attaque de grille (14) qui délivre un signal d'attaque de grille à une grille d'un dispositif d'alimentation (2) sur la base d'une instruction de commande de grille qui a été entrée ; et une unité de diagnostic de grille (11) qui détecte une anomalie de grille sur la base d'une comparaison entre l'instruction de commande de grille et le signal d'attaque de grille.
PCT/JP2022/047452 2022-12-22 2022-12-22 Appareil de commande d'attaque de grille et appareil onduleur WO2024134842A1 (fr)

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PCT/JP2022/047452 WO2024134842A1 (fr) 2022-12-22 2022-12-22 Appareil de commande d'attaque de grille et appareil onduleur

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06232719A (ja) * 1993-02-02 1994-08-19 Hitachi Ltd 半導体回路
JP2003070231A (ja) * 2001-08-28 2003-03-07 Toshiba Corp 電力変換装置及び電力変換用半導体スイッチング素子
US6917227B1 (en) * 2001-05-04 2005-07-12 Ixys Corporation Efficient gate driver for power device
JP2005312235A (ja) * 2004-04-23 2005-11-04 Toshiba Corp 電力変換装置
WO2017203666A1 (fr) * 2016-05-26 2017-11-30 三菱電機株式会社 Alimentation très haute tension par retour-ligne, onduleur et véhicule électrique
JP2020178393A (ja) * 2019-04-15 2020-10-29 株式会社デンソー 温度検出回路
JP2020182258A (ja) * 2019-04-23 2020-11-05 ルネサスエレクトロニクス株式会社 駆動装置、電力供給システム、及び、駆動装置のテスト方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06232719A (ja) * 1993-02-02 1994-08-19 Hitachi Ltd 半導体回路
US6917227B1 (en) * 2001-05-04 2005-07-12 Ixys Corporation Efficient gate driver for power device
JP2003070231A (ja) * 2001-08-28 2003-03-07 Toshiba Corp 電力変換装置及び電力変換用半導体スイッチング素子
JP2005312235A (ja) * 2004-04-23 2005-11-04 Toshiba Corp 電力変換装置
WO2017203666A1 (fr) * 2016-05-26 2017-11-30 三菱電機株式会社 Alimentation très haute tension par retour-ligne, onduleur et véhicule électrique
JP2020178393A (ja) * 2019-04-15 2020-10-29 株式会社デンソー 温度検出回路
JP2020182258A (ja) * 2019-04-23 2020-11-05 ルネサスエレクトロニクス株式会社 駆動装置、電力供給システム、及び、駆動装置のテスト方法

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