WO2024120173A1 - Rc振荡电路 - Google Patents

Rc振荡电路 Download PDF

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Publication number
WO2024120173A1
WO2024120173A1 PCT/CN2023/132791 CN2023132791W WO2024120173A1 WO 2024120173 A1 WO2024120173 A1 WO 2024120173A1 CN 2023132791 W CN2023132791 W CN 2023132791W WO 2024120173 A1 WO2024120173 A1 WO 2024120173A1
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Prior art keywords
field effect
circuit
output
input end
enable
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PCT/CN2023/132791
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English (en)
French (fr)
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李鹏浩
任小娇
郭嘉帅
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深圳飞骧科技股份有限公司
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Publication of WO2024120173A1 publication Critical patent/WO2024120173A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H03K3/0377—Bistables with hysteresis, e.g. Schmitt trigger

Definitions

  • the present invention relates to the field of electronic technology, and in particular to an RC oscillator circuit.
  • the basic principle of the RC oscillation circuit is to periodically charge or discharge the capacitor through a resistor. When the voltage on the capacitor reaches a certain level, its charging switch is disconnected and its discharging switch is opened through feedback control.
  • the charging and discharging of a capacitor is generally controlled by a hysteresis comparator or a Schmitt trigger.
  • the upper and lower limits of the capacitor's level during the charging and discharging process are the up and down flip levels of the Schmitt trigger. Therefore, during this process, the state of the Schmitt trigger is always in the critical area of conduction. Then, there will always be a large current from the power supply to the ground of the Schmitt trigger, and the power consumption is relatively large.
  • the object of the present invention is to provide a new RC oscillator circuit to solve the problem that the RC oscillator circuit uses a Schmitt trigger to control the charging and discharging of a capacitor, resulting in high power consumption.
  • the present invention provides an RC oscillator circuit, which includes a first group of inverters, an RC charging and discharging circuit, a delayed pulse generating circuit, an enabling controller and a second group of inverters;
  • the output end of the first set of inverters is connected to the input end of the RC charge and discharge circuit, and is used to drive the feedback signal and generate a secondary drive output signal of the feedback signal;
  • the RC charging and discharging circuit includes a first field effect transistor, a second field effect transistor, a first resistor, a first capacitor, a third field effect transistor, a fourth field effect transistor and a Schmitt trigger;
  • the gate of the first field effect tube and the gate of the second field effect tube are both used as the input end of the RC charge and discharge circuit, and are respectively connected to the output end of the first group of inverters.
  • the drain of the second field effect tube is connected to the drain of the first field effect tube
  • the first end of the first resistor is connected to the drain of the first field effect tube
  • the second end of the first resistor is connected to the input end of the Schmitt trigger
  • the first capacitor is connected in parallel between the second end of the first resistor and the source of the first field effect tube
  • the gate of the third field effect tube is connected to the normally low level output end of the delay pulse generating circuit
  • the source of the third field effect tube is connected to the source of the first field effect tube
  • the drain of the third field effect tube is connected to the input end of the Schmitt trigger
  • the gate of the fourth field effect tube is connected to the normally high level output end of the delay pulse generating circuit
  • the source of the fourth field effect tube is connected to the source of the second
  • the RC charge and discharge circuit and the delay pulse generating circuit jointly form a feedback oscillation loop, the first input end of the enable controller is connected to the output end of the Schmitt trigger, and the second input end of the enable controller is connected to an enable signal for closing the feedback oscillation loop;
  • the input end of the delay pulse generating circuit is connected to the output end of the enabling controller
  • the input end of the second group of inverters is connected to the output end of the enable controller, and the output end of the second group of inverters is used to output a clock signal.
  • the delayed pulse generating circuit includes a low-level output circuit and a high-level output circuit; the input ends of the low-level output circuit and the high-level output circuit both serve as the input ends of the delayed pulse generating circuit, the output end of the low-level output circuit serves as the normally low-level output end of the delayed pulse generating circuit to output a low-level pulse signal, and the output end of the high-level output circuit serves as the normally high-level output end of the delayed pulse generating circuit to output a high-level pulse signal.
  • the low-level output circuit includes a first delay inverter, a second resistor, a second capacitor, a second delay inverter, a first NAND gate and a third delay inverter;
  • the input end of the first delay inverter is used as the input end of the low level output circuit, and the first end of the second resistor is connected to the output end of the first delay inverter.
  • the second end of the second resistor is connected to the second delay inverter, the first end of the second capacitor is connected to the second end of the second resistor, and the second end of the second capacitor is grounded;
  • the output end of the second delay inverter is connected to the first input end of the first NAND gate, the second input end of the first NAND gate is connected to the output end of the first delay inverter, the output end of the first NAND gate is connected to the input end of the third delay inverter, and the output end of the third delay inverter serves as the output end of the low level output circuit.
  • the high level output circuit includes a fourth delay inverter and a second NAND gate;
  • the input end of the fourth delay inverter is connected to the output end of the second delay inverter, the output end of the fourth delay inverter is connected to the first input end of the second NAND gate, the second input end of the second NAND gate serves as the input end of the high level output circuit, and the output end of the second NAND gate serves as the output end of the high level output circuit.
  • the first group of inverters includes a plurality of first inverters connected in series.
  • the enable controller is an enable NAND gate; the first input end of the enable NAND gate serves as the first input end of the enable controller, the second input end of the enable NAND gate serves as the second input end of the enable controller and is connected to a high-level enable signal, and the output end of the enable NAND gate serves as the output end of the enable controller.
  • the enable controller is an enable OR gate; the first input end of the enable OR gate serves as the first input end of the enable controller, the second input end of the enable OR gate serves as the second input end of the enable controller and is connected to a low-level enable signal, and the output end of the enable OR gate serves as the output end of the enable controller.
  • the second group of inverters includes a plurality of second inverters connected in series.
  • the first group of inverters includes two first inverters
  • the second group of inverters includes two second inverters.
  • the first field effect transistor and the third field effect transistor are PMOS transistors
  • the second field effect transistor and the fourth field effect transistor are NMOS transistors.
  • the RC oscillator circuit of the present invention adds a first field effect transistor, a second field effect transistor, a third field effect transistor and a fourth field effect transistor, and uses a Schmitt trigger
  • the charging or discharging point of the RC charge and discharge circuit can be controlled by the conduction characteristics of the first field effect tube to the fourth field effect tube in cooperation with the delayed pulse generating circuit and the Schmitt trigger, so that the Schmitt trigger will not be in a large current state all the time, thereby reducing the power consumption of the RC oscillation circuit.
  • the RC oscillation circuit can resume oscillation by itself, without the need to add any additional dead state recovery circuit.
  • FIG1 is a circuit diagram of a first RC oscillator circuit provided by an embodiment of the present invention.
  • FIG2 is a timing principle diagram of a first RC oscillator circuit provided by an embodiment of the present invention.
  • FIG3 is a circuit diagram of a second RC oscillator circuit provided by an embodiment of the present invention.
  • RC oscillator circuit 1, first group of inverters; 2, RC charge and discharge circuit; 21, Schmitt trigger; 3, delay pulse generating circuit; 31, low level output circuit; 311, first delay inverter; 312, second delay inverter; 313, first NAND gate; 314, third delay inverter; 32, high level output circuit; 321, fourth delay inverter; 322, second NAND gate; 4, enable controller; 5, second group of inverters.
  • the embodiment of the present invention provides an RC oscillator circuit 100, as shown in FIG1, which includes The invention comprises a first group of inverters 1, an RC charging and discharging circuit 2, a delay pulse generating circuit 3, an enabling controller 4 and a second group of inverters 5.
  • the output end of the first group of inverters 1 is connected to the input end of the RC charge and discharge circuit 2, which is used to drive the feedback signal and generate a secondary drive output signal of the feedback signal;
  • the input end of the RC charge and discharge circuit 2 is connected to the output end of the first group of inverters 1, and the RC charge and discharge circuit 2 and the delay pulse generating circuit 3 together form a feedback oscillation loop;
  • the first input end of the enable controller 4 is connected to the output end of the RC charge and discharge circuit 2, and the second input end of the enable controller 4 is connected to the enable signal, which is used to close the feedback oscillation loop;
  • the input end of the delay pulse generating circuit 3 is connected to the output end of the enable controller 4;
  • the input end of the second group of inverters 5 is connected to the output end of the enable controller 4, and the output end of the second group of inverters 5 is used to output a clock signal.
  • the signal output by the enabling controller 4 is a feedback signal, and the first group of inverters 1 is used to drive the feedback signal and generate a secondary driving output signal of the feedback signal, that is, the input end of the first group of inverters 1 is connected to the output end of the enabling controller 4 .
  • the first group of inverters 1 includes a plurality of first inverters connected in series, specifically two.
  • the specific number can also be adaptively changed according to the flavor of the signal output or feedback of the enabling controller 4.
  • the input end of the first inverter serves as the input end of the first group of inverters 1 ; the output end of the last inverter serves as the output end of the first group of inverters 1 .
  • the RC charge and discharge circuit 2 includes a first field effect transistor MN1, a second field effect transistor MP1, a first resistor R1, a first capacitor C1, a third field effect transistor MN2, a fourth field effect transistor MP2 and a Schmitt trigger.
  • the gate of the first field effect transistor MN1 and the gate of the second field effect transistor MP1 are both used as input ends of the RC charge and discharge circuit 2, and are respectively connected to the output end of the first group of inverters 1, the drain of the second field effect transistor MP1 is connected to the drain of the first field effect transistor MN1, the first end of the first resistor R1 is connected to the drain of the first field effect transistor MN1, the second end of the first resistor R1 is connected to the input end of the Schmitt trigger, and the first capacitor C1 is connected in parallel to the second end of the first resistor R1.
  • the gate of the third field effect transistor MN2 is connected to the normally low level output terminal of the delay pulse generating circuit 3
  • the source of the third field effect transistor MN2 is connected to the source of the first field effect transistor MN1
  • the drain of the third field effect transistor MN2 is connected to the input terminal of the Schmitt trigger
  • the gate of the fourth field effect transistor MP2 is connected to the normally high level output terminal of the delay pulse generating circuit 3
  • the source of the fourth field effect transistor MP2 is connected to the source of the second field effect transistor MP1
  • the drain of the fourth field effect transistor MP2 is connected to the input terminal of the Schmitt trigger.
  • the first field effect transistor MN1 and the third field effect transistor MN2 are PMOS transistors, and the second field effect transistor MP1 and the fourth field effect transistor MP2 are NMOS transistors.
  • the delay pulse generating circuit 3 includes a low-level output circuit 31 and a high-level output circuit 32; the input ends of the low-level output circuit 31 and the high-level output circuit 32 are both used as the input ends of the delay pulse generating circuit 3 to be connected to the output end of the enable controller 4, the output end of the low-level output circuit 31 is used as the normally low-level output end of the delay pulse generating circuit 3 to output a low-level pulse signal and be connected to the gate of the third field effect transistor MN2, and the output end of the high-level output circuit 32 is used as the normally high-level output end of the delay pulse generating circuit 3 to output a high-level pulse signal and be connected to the gate of the fourth field effect transistor MP2.
  • the low level output circuit 31 includes a first delay inverter 311 , a second resistor R2 , a second capacitor C2 , a second delay inverter 312 , a first NAND gate 313 and a third delay inverter 314 .
  • the input end of the first delay inverter 311 serves as the input end of the low level output circuit 31, the first end of the second resistor R2 is connected to the output end of the first delay inverter 311, the second end of the second resistor R2 is connected to the second delay inverter 312, the first end of the second capacitor C2 is connected to the second end of the second resistor R2, and the second end of the second capacitor C2 is grounded.
  • the output end of the second delay inverter 312 is connected to the first input end of the first NAND gate 313, the second input end of the first NAND gate 313 is connected to the output end of the first delay inverter 311, the output end of the first NAND gate 313 is connected to the input end of the third delay inverter 314, and the output end of the third delay inverter 314 serves as the output end of the low level output circuit 31 to be connected to the gate of the third field effect transistor MN2.
  • the high level output circuit 32 includes a fourth delay inverter 321 and a second NAND gate 322 .
  • the input end of the fourth delay inverter 321 is connected to the output end of the second delay inverter 312, the output end of the fourth delay inverter 321 is connected to the first input end of the second NAND gate 322, the second input end of the second NAND gate 322 serves as the input end of the high level output circuit 32, and the output end of the second NAND gate 322 serves as the output end of the high level output circuit 32 to be connected to the gate of the fourth field effect transistor MP2.
  • the enable controller 4 is an enable NAND gate; the first input end of the enable NAND gate serves as the first input end of the enable controller 4, the second input end of the enable NAND gate serves as the second input end of the enable controller 4 and is connected to a high-level enable signal, and the output end of the enable NAND gate serves as the output end of the enable controller 4, which is respectively connected to the input end of the first group of inverters 1, the input end of the delay pulse generating circuit 3 and the input end of the second group of inverters 5.
  • the main function of the enable NAND gate is to force the feedback oscillation loop to be closed through a high-level enable signal.
  • the second group of inverters 5 includes a plurality of second inverters connected in series, specifically two.
  • the specific number can also be adaptively changed according to the phase of the output clock signal or the connected load.
  • the input end of the first inverter serves as the input end of the second group of inverters 5 ; the output end of the last inverter serves as the output end of the first group of inverters 5 .
  • the first group of inverters 1 is used to generate a secondary driving output signal (signal A) that enables a feedback signal (FB signal) output by the controller 4 , and outputs the signal to the RC charge and discharge circuit 2 .
  • the RC charge and discharge circuit 2 is used to process the signal A and enable the controller 4 with the output value of the processed signal (signal C); the gate of the third field effect transistor MN2 and the gate of the fourth field effect transistor MP2 are respectively used to cooperate with the normally low level signal (signal GN) output by the normally low level output end of the delay pulse generating circuit 3 and the normally high level signal (signal GP) output by the normally high level output end to process the level point (point B) of the first capacitor C1.
  • the delay pulse generating circuit 3 is used for receiving the FB signal, and providing the gate of the third field effect transistor MN2 and the gate of the fourth field effect transistor MP2 with the signal GN and the signal GP respectively through two output terminals.
  • the enabling controller 4 is used to receive the signal C and output the FB signal.
  • the second group of inverters 5 is used to drive the FB signal through two-stage inversion and output a clock signal (CLK signal).
  • the working mode of the delayed pulse generating circuit 3 is to utilize the delay characteristics of the charging and discharging of the second resistor R2 and the second capacitor C2, and the two output terminals provide the gate of the third field effect transistor MN2 and the gate of the fourth field effect transistor MP2 with the signal GN and the signal GP, respectively.
  • the signal GN is a high-level pulse signal
  • the signal GP is a high-level pulse signal.
  • the principle of the RC charge and discharge circuit 2 is as follows: when the first capacitor C1 is charged, the level at point B increases. When it reaches the upper flip voltage V SPH of the Schmitt trigger in the RC charge and discharge circuit 2, the Schmitt trigger output becomes a low level, the signal A in the feedback loop becomes high, and the signal GP of the delay pulse generating circuit 3 is a low-level pulse signal, turning on the second field effect transistor MP1 in the RC charge and discharge circuit 2, pulling the level at point B to the power supply voltage, and then the first capacitor C1 starts to discharge from the power supply voltage; when discharged to the lower flip voltage V SPL of the Schmitt trigger, the Schmitt trigger output becomes a low level, the signal A in the feedback loop becomes low, and the output normally low level signal GN of the delay pulse generating circuit 3 is a high-level pulse signal, turning on the first field effect transistor MN1 in the RC charge and discharge circuit 2, pulling the level at point B to 0 voltage, and then the capacitor starts to charge from
  • the speed of charging and discharging of the first resistor R1 and the first capacitor C1 determines the magnitude of the vibration frequency.
  • the charging and discharging time corresponds to the proportion of the high level and the low level of the output signal in one cycle, and the flip point voltage of the Schmitt trigger also affects the frequency and duty cycle of the output signal. For example, if the upper flip voltage V SPH is too high, the charging time will be too long, and if the lower flip voltage V SPL is too low, the discharge time will be too long. Therefore, the oscillation signal frequency and duty cycle of the output CLK signal can be adjusted.
  • the signal A in the RC charge and discharge circuit 2 changes with the same phase.
  • the signal GN is a high-level pulse signal, so that the voltage at point B is pulled to a low level.
  • the first field effect transistor MN1 is turned off and the second field effect transistor MP1 is turned on, so that the first capacitor C1 starts to charge, and the voltage at point B starts to increase from a low level.
  • the output C0 of the Schmitt trigger the FB signal changes to a high level, and the signal A changes with the same phase.
  • the signal GP is a low-level pulse signal, so that the voltage at point B is pulled to a high level.
  • the third field effect transistor MN2 is turned off and the fourth field effect transistor MP2 is turned on, so that the first capacitor C1 starts to discharge, and the voltage at point B starts to decrease from a high level.
  • tdA is the discharge time of the first capacitor C1
  • tdB is the charge time of the first capacitor C1 .
  • the duty cycle of the output CLK signal is tdA/(tdA+tdB).
  • the enable controller 4 can also use an enable NOR gate; the first input end of the enable NOR gate serves as the first input end of the enable controller 4, the second input end of the enable NOR gate serves as the second input end of the enable controller 4 and is connected to the low-level enable signal, and the output end of the enable NOR gate serves as the output end of the enable controller 4. Even if the enable controller 4 can use an enable NAND gate, it can also use an enable NOR gate, but the enable signals connected to the second input ends of the two groups need to be adaptively changed.
  • the enabling controller 4 can also change its position without changing its output terminal, such as placing it inside the Schmitt trigger.
  • the RC oscillator circuit 100 of the present embodiment is provided with a first field effect transistor MN1, a second field effect transistor MP1, a third field effect transistor MN2 and a fourth field effect transistor MP2, and uses a Schmitt trigger as a controller of the charge and discharge switch, so that the charge or discharge point of the RC charge and discharge circuit 2 can be controlled by the conduction characteristics of the first field effect transistor MN1 to the fourth field effect transistor MP2 in conjunction with the delay pulse generating circuit 3 and the Schmitt trigger, so that the Schmitt trigger will not always be in a large current state, thereby reducing the power consumption of the RC oscillator circuit 100.
  • the RC oscillator when any node is pulled to an abnormal level by an abnormal external force, such as forced to a high level or forced to a low level, when the external force disappears, the RC oscillator The oscillation circuit 100 can recover oscillation by itself, and no additional dead state recovery circuit is needed.
  • the signal FB when the signal FB is at a low level and the signal A level is at a low level, the voltage of the first capacitor C1 at point B will be charged. When it is charged to the flip voltage VSPH on the Schmitt trigger, the signal C will become a low level.
  • the signal GP is a low level pulse signal, which pulls the level of point B to a high level. At this time, the FB signal becomes a high level, the circuit resumes normal working state, and restarts oscillation.
  • Other nodes can also be analyzed in the same way.

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Abstract

本发明提供了一种RC振荡电路，其包括第一组反相器、RC充放电电路、延时脉冲发生电路、使能控制器以及第二组反相器；所述RC充放电电路包括第一场效应管、第二场效应管、第一电阻、第一电容、第三场效应管、第四场效应管以及施密特触发器。本发明中的RC振荡电路可以降低RC振荡电路的功耗，同时不需要额外添加任何死态恢复电路。

Description

RC振荡电路 【技术领域】
本发明涉及电子技术领域，尤其涉及一种RC振荡电路。
【背景技术】
RC振荡电路的基本原理即周期性的通过电阻，对电容进行充电或放电，当电容上电压达到一定电平时，通过反馈控制其充电开关断开，并且打开其放电开关，对于一个电容进行充放电，一般通过一个迟滞比较器或者一个施密特触发器进行控制。
当采用施密特触发器时，电容在充放电过程中，其电平上下限是施密特触发器的上下翻转电平，所以在此过程中，施密特触发器的状态一直处于导通的临界区域，那么施密特触发器从电源到地会一直有一个较大的电流，功耗较大。
因此，有必要提供一种新的RC振荡电路来解决上述问题。
【发明内容】
本发明的目的在于提供一种新的RC振荡电路，以解决RC振荡电路采用施密特触发器控制电容充放电导致功耗较大的问题。
本发明提供了一种RC振荡电路，其包括第一组反相器、RC充放电电路、延时脉冲发生电路、使能控制器以及第二组反相器；
所述第一组反相器的输出端连接至所述RC充放电电路的输入端，用于驱动反馈信号并产生反馈信号的二级驱动输出信号；
所述RC充放电电路包括第一场效应管、第二场效应管、第一电阻、第一电容、第三场效应管、第四场效应管以及施密特触发器；
所述第一场效应管的栅极和所述第二场效应管的栅极均作为所述RC充放电电路的输入端，分别与所述第一组反相器的输出端连接，所 述第二场效应管的漏极与所述第一场效应管的漏极连接，所述第一电阻的第一端连接至所述第一场效应管的漏极，所述第一电阻的第二端连接至所述施密特触发器的输入端，所述第一电容并联至所述第一电阻的第二端和所述第一场效应管的源极之间，所述第三场效应管的栅极与所述延时脉冲发生电路的常低电平输出端连接，所述第三场效应管的源极与所述第一场效应管的源极连接，所述第三场效应管的漏极连接至所述施密特触发器的输入端，所述第四场效应管的栅极与所述延时脉冲发生电路的常高电平输出端连接，所述第四场效应管的源极与所述第二场效应管的源极连接，所述第四场效应管的漏极连接至所述施密特触发器的输入端；
所述RC充放电电路与所述延时脉冲发生电路共同形成反馈振荡环路，所述使能控制器的第一输入端与所述施密特触发器的输出端连接，所述使能控制器的第二输入端连接至使能信号，用于将所述反馈振荡环路实现关闭；
所述延时脉冲发生电路的输入端与所述使能控制器的输出端连接；
所述第二组反相器的输入端与所述使能控制器的输出端连接，所述第二组反相器的输出端用于输出时钟信号。
更优的，所述延时脉冲发生电路包括低电平输出电路和高电平输出电路；所述低电平输出电路和所述高电平输出电路的输入端均作为所述延时脉冲发生电路的输入端，所述低电平输出电路的输出端作为所述延时脉冲发生电路的常低电平输出端，以输出低电平脉冲信号，所述高电平输出电路的输出端用于作为所述延时脉冲发生电路的常高电平输出端，以输出高电平脉冲信号。
更优的，所述低电平输出电路包括第一延时反相器、第二电阻、第二电容、第二延时反相器、第一与非门以及第三延时反相器；
所述第一延时反相器的输入端作为所述低电平输出电路的输入端，所述第二电阻的第一端与所述第一延时反相器的输出端连接，所 述第二电阻的第二端连接至所述第二延时反相器，所述第二电容的第一端与所述第二电阻的第二端连接，所述第二电容的第二端接地；
所述第二延时反相器的输出端连接至所述第一与非门的第一输入端，所述第一与非门的第二输入端与所述第一延时反相器的输出端连接，所述第一与非门的输出端连接至所述第三延时反相器的输入端，所述第三延时反相器的输出端作为所述低电平输出电路的输出端。
更优的，所述高电平输出电路包括第四延时反相器以及第二与非门；
所述第四延时反相器的输入端与所述第二延时反相器的输出端连接，所述第四延时反相器的输出端连接至所述第二与非门的第一输入端，所述第二与非门的第二输入端作为所述高电平输出电路的输入端，所述第二与非门的输出端作为所述高电平输出电路的输出端。
更优的，所述第一组反相器包括多个依次串联的第一反相器。
更优的，所述使能控制器为使能与非门；所述使能与非门的第一输入端作为所述使能控制器的第一输入端，所述使能与非门的第二输入端作为所述使能控制器的第二输入端并连接至高电平使能信号，所述使能与非门的输出端作为所述使能控制器的输出端。
更优的，所述使能控制器为使能或非门；所述使能或非门的第一输入端作为所述使能控制器的第一输入端，所述使能或非门的第二输入端作为所述使能控制器的第二输入端并连接至低电平使能信号，所述使能或非门的输出端作为所述使能控制器的输出端。
更优的，所述第二组反相器包括多个依次串联的第二反相器。
更优的，所述第一组反相器包括两个第一反相器，所述第二组反相器包括两个第二反相器。
更优的，所述第一场效应管和所述第三场效应管为PMOS管，所述第二场效应管和所述第四场效应管为NMOS管。
与现有技术相比，本发明的RC振荡电路通过增设第一场效应管、第二场效应管、第三场效应管以及第四场效应管，并将施密特触发器 作为充放电开关的控制器，从而可以通过第一场效应管至第四场效应管的导通特性配合延时脉冲发生电路和施密特触发器控制RC充放电电路的充电或放点，以使施密特触发器不会一直处于较大的电流状态，进而降低RC振荡电路的功耗，另外，还能使其任意结点被非正常外力拉至非正常电平时，当此外力消失后，该RC振荡电路可自行恢复振荡，不需要额外添加任何死态恢复电路。
【附图说明】
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图，其中：
图1为本发明实施例提供的第一种RC振荡电路的电路图；
图2为本发明实施例提供的第一种RC振荡电路的时序原理图；
图3为本发明实施例提供的第二种RC振荡电路的电路图。
100、RC振荡电路；1、第一组反相器；2、RC充放电电路；21、施密特触发器；3、延时脉冲发生电路；31、低电平输出电路；311、第一延时反相器；312、第二延时反相器；313、第一与非门；314、第三延时反相器；32、高电平输出电路；321、第四延时反相器；322、第二与非门；4、使能控制器；5、第二组反相器。
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本发明的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护的范围。
本发明实施例提供了一种RC振荡电路100，结合图1所示，其包 括第一组反相器1、RC充放电电路2、延时脉冲发生电路3、使能控制器4以及第二组反相器5。
具体地，第一组反相器1的输出端连接至RC充放电电路2的输入端，用于驱动反馈信号并产生反馈信号的二级驱动输出信号；RC充放电电路2的输入端与第一组反相器1的输出端连接，RC充放电电路2与延时脉冲发生电路3共同形成反馈振荡环路；使能控制器4的第一输入端与RC充放电电路2的输出端连接，使能控制器4的第二输入端连接至使能信号，用于将反馈振荡环路实现关闭；延时脉冲发生电路3的输入端与使能控制器4的输出端连接；第二组反相器5的输入端与使能控制器4的输出端连接，第二组反相器5的输出端用于输出时钟信号。
其中，使能控制器4输出的信号为反馈信号，而第一组反相器1用于驱动反馈信号并产生反馈信号的二级驱动输出信号，即第一组反相器1的输入端与使能控制器4的输出端连接。
本实施例中，第一组反相器1包括多个依次串联的第一反相器，具体为两个。当然，其具体的数量还可以根据使能控制器4输出或反馈的信号的香味进行适应性更改。
串联的多个第一反相器中：第一个反相器的输入端作为第一组反相器1的输入端；最后一个反相器的输出端作为第一组反相器1的输出端。
本实施例中，RC充放电电路2包括第一场效应管MN1、第二场效应管MP1、第一电阻R1、第一电容C1、第三场效应管MN2、第四场效应管MP2以及施密特触发器。
第一场效应管MN1的栅极和第二场效应管MP1的栅极均作为RC充放电电路2的输入端，分别与第一组反相器1的输出端连接，第二场效应管MP1的漏极与第一场效应管MN1的漏极连接，第一电阻R1的第一端连接至第一场效应管MN1的漏极，第一电阻R1的第二端连接至施密特触发器的输入端，第一电容C1并联至第一电阻R1的第二 端和第一场效应管MN1的源极之间，第三场效应管MN2的栅极与延时脉冲发生电路3的常低电平输出端连接，第三场效应管MN2的源极与第一场效应管MN1的源极连接，第三场效应管MN2的漏极连接至施密特触发器的输入端，第四场效应管MP2的栅极与延时脉冲发生电路3的常高电平输出端连接，第四场效应管MP2的源极与第二场效应管MP1的源极连接，第四场效应管MP2的漏极连接至施密特触发器的输入端。
第一场效应管MN1和第三场效应管MN2为PMOS管，第二场效应管MP1和第四场效应管MP2为NMOS管。
本实施例中，延时脉冲发生电路3包括低电平输出电路31和高电平输出电路32；低电平输出电路31和高电平输出电路32的输入端均作为延时脉冲发生电路3的输入端，以与使能控制器4的输出端连接，低电平输出电路31的输出端作为延时脉冲发生电路3的常低电平输出端，以输出低电平脉冲信号并与第三场效应管MN2的栅极连接，高电平输出电路32的输出端用于作为延时脉冲发生电路3的常高电平输出端，以输出高电平脉冲信号并与第四场效应管MP2的栅极连接。
本实施例中，低电平输出电路31包括第一延时反相器311、第二电阻R2、第二电容C2、第二延时反相器312、第一与非门313以及第三延时反相器314。
第一延时反相器311的输入端作为低电平输出电路31的输入端，第二电阻R2的第一端与第一延时反相器311的输出端连接，第二电阻R2的第二端连接至第二延时反相器312，第二电容C2的第一端与第二电阻R2的第二端连接，第二电容C2的第二端接地。
第二延时反相器312的输出端连接至第一与非门313的第一输入端，第一与非门313的第二输入端与第一延时反相器311的输出端连接，第一与非门313的输出端连接至第三延时反相器314的输入端，第三延时反相器314的输出端作为低电平输出电路31的输出端，以与第三场效应管MN2的栅极连接。
本实施例中，高电平输出电路32包括第四延时反相器321以及第二与非门322。
第四延时反相器321的输入端与第二延时反相器312的输出端连接，第四延时反相器321的输出端连接至第二与非门322的第一输入端，第二与非门322的第二输入端作为高电平输出电路32的输入端，第二与非门322的输出端作为高电平输出电路32的输出端，以与与第四场效应管MP2的栅极连接。
本实施例中，使能控制器4为使能与非门；使能与非门的第一输入端作为使能控制器4的第一输入端，使能与非门的第二输入端作为使能控制器4的第二输入端并连接至高电平使能信号，使能与非门的输出端作为使能控制器4的输出端，以分别连接至第一组反相器1的输入端、延时脉冲发生电路3的输入端和第二组反相器5的输入端。
使能与非门的主要作用是通过高电平使能信号将反馈振荡环路强制关闭。
本实施例中，第二组反相器5包括多个依次串联的第二反相器，具体为两个。当然，其具体的数量还可以根据输出的时钟信号的相位或连接的负载进行适应性更改。
串联的多个第二反相器中：第一个反相器的输入端作为第二组反相器5的输入端；最后一个反相器的输出端作为第一组反相器5的输出端。
本实施例中，第一组反相器1用于产生使能控制器4输出的反馈信号(FB信号)的二级驱动输出信号(信号A)，并输出至RC充放电电路2。
RC充放电电路2用于对信号A进行处理，并将处理后的信号(信号C)输出值使能控制器4；第三场效应管MN2的栅极和第四场效应管MP2的栅极分别用于配合延时脉冲发生电路3的常低电平输出端输出的常低电平信号(信号GN)和常高电平输出端输出的常高电平信号(信号GP)对第一电容C1的电平点(B点)进行处理。
延时脉冲发生电路3用接收FB信号，并分别通过两个输出端为第三场效应管MN2的栅极和第四场效应管MP2的栅极提供信号GN和信号GP。
使能控制器4用于接收信号C，并输出FB信号。
第二组反相器5用于将FB信号经过二级反相驱动，并输出时钟信号(CLK信号)。
本实施例中，延时脉冲发生电路3的工作方式是利用第二电阻R2和第二电容C2的充放电的延时特性，且两个输出端分别为第三场效应管MN2的栅极和第四场效应管MP2的栅极提供信号GN和信号GP。当B点电压放电至施密特触发器的下翻转电压VSPL时，信号GN则为高电平的脉冲信号；当B点电压充电至施密特触发器的上翻转电压VSPL时，信号GP则为高电平的脉冲信号。
本实施例中，RC充放电电路2的原理为：当第一电容C1充电时，B点电平升高，到达RC充放电电路2中的施密特触发器的上翻转电压VSPH时，施密特触发器输出变为低电平，反馈环路中的信号A变高，延时脉冲发生电路3的信号GP为低电平的脉冲信号，将RC充放电电路2中的第二场效应管MP1导通，将B点电平拉至电源电压，后第一电容C1从电源电压开始放电；当放电至施密特触发器的下翻转电压VSPL时，施密特触发器输出变为低电平，反馈环路中的信号A变低，延时脉冲发生电路3的输出常低电平信号GN为高电平的脉冲信号，将RC充放电电路2中的第一场效应管MN1导通，将B点电平拉至0电压，而后电容从0电压开始充电，循环反复。
本实施例中，第一电阻R1和第一电容C1的充放电的快慢决定了振动频率的大小，充放电的时间对应于输出信号在一个周期内高电平与低电平的占比，并且施密特触发器的翻转点电压也影响着输出信号的频率以及占空比，如上翻转电压VSPH过高会使充电时间过长，下翻转电压VSPL较低会使得放电时间边长，故输出CLK信号的振荡信号频率与占空比可以被调节。
本实施例中，如图2所示，当FB信号从高电平变为低电平时，使得在RC充放电电路2信号A以相同相位变化，此时，信号GN为高电平脉冲信号，使得B点电压被拉至低电平，而后由于信号A为低电平，第一场效应管MN1截止而第二场效应管MP1导通，使得第一电容C1开始充电，B点电压从低电平开始升高，当B点电压升高至施密特触发器上翻转电压VSPH后，施密特触发器的输出C0，FB信号变为高电平，信号A以相同相位变化，此时，信号GP为低电平脉冲信号，使得B点电压被拉至高电平，而后由于信号A为高电平，第三场效应管MN2截止而第四场效应管MP2导通，使得第一电容C1开始放电，B点电压从高电平开始变低。
如图2所示，tdA为第一电容C1的放电时间，tdB为第一电容C1的充电时间，本实施例中，输出CLK信号的占空比为tdA/(tdA+tdB)。
另外，如图3所示，使能控制器4还可以选用使能或非门；使能或非门的第一输入端作为使能控制器4的第一输入端，使能或非门的第二输入端作为使能控制器4的第二输入端并连接至低电平使能信号，使能或非门的输出端作为使能控制器4的输出端。即使能控制器4可以使用使能与非门，也能使用使能或非门，但两组的第二输入端连接的使能信号需要进行适应性更改。
同时，使能控制器4还能在不改变其输出端的情况下，改变其位置，如放至施密特触发器内部。
与现有技术相比，本实施例的RC振荡电路100通过增设第一场效应管MN1、第二场效应管MP1、第三场效应管MN2以及第四场效应管MP2，并将施密特触发器作为充放电开关的控制器，从而可以通过第一场效应管MN1至第四场效应管MP2的导通特性配合延时脉冲发生电路3和施密特触发器控制RC充放电电路2的充电或放点，以使施密特触发器不会一直处于较大的电流状态，进而降低RC振荡电路100的功耗，另外，还能使其任意结点被非正常外力拉至非正常电平时，如强制为高电平或强制为低电平，当此外力消失后，该RC振 荡电路100可自行恢复振荡，不需要额外添加任何死态恢复电路。
比如信号FB为低电平，信号A电平为低电平，B点为第一电容C1电压，将会被充电，充电至施密特触发器上翻转电压VSPH时，信号C将会变成低电平，信号GP为低电平脉冲信号，将B点电平拉至高电平，此时FB信号变成了高电平，电路恢复正常工作状态，重新起振；其他结点也可通过同样方法分析。
以上所述的仅是本发明的实施方式，在此应当指出，对于本领域的普通技术人员来说，在不脱离本发明创造构思的前提下，还可以做出改进，但这些均属于本发明的保护范围。

Claims (10)

  1. 一种RC振荡电路，其特征在于，包括第一组反相器、RC充放电电路、延时脉冲发生电路、使能控制器以及第二组反相器；
    所述第一组反相器的输出端连接至所述RC充放电电路的输入端，用于驱动反馈信号并产生反馈信号的二级驱动输出信号；
    所述RC充放电电路包括第一场效应管、第二场效应管、第一电阻、第一电容、第三场效应管、第四场效应管以及施密特触发器；
    所述第一场效应管的栅极和所述第二场效应管的栅极均作为所述RC充放电电路的输入端，分别与所述第一组反相器的输出端连接，所述第二场效应管的漏极与所述第一场效应管的漏极连接，所述第一电阻的第一端连接至所述第一场效应管的漏极，所述第一电阻的第二端连接至所述施密特触发器的输入端，所述第一电容并联至所述第一电阻的第二端和所述第一场效应管的源极之间，所述第三场效应管的栅极与所述延时脉冲发生电路的常低电平输出端连接，所述第三场效应管的源极与所述第一场效应管的源极连接，所述第三场效应管的漏极连接至所述施密特触发器的输入端，所述第四场效应管的栅极与所述延时脉冲发生电路的常高电平输出端连接，所述第四场效应管的源极与所述第二场效应管的源极连接，所述第四场效应管的漏极连接至所述施密特触发器的输入端；
    所述RC充放电电路与所述延时脉冲发生电路共同形成反馈振荡环路，所述使能控制器的第一输入端与所述施密特触发器的输出端连接，所述使能控制器的第二输入端连接至使能信号，用于将所述反馈振荡环路实现关闭；
    所述延时脉冲发生电路的输入端与所述使能控制器的输出端连接；
    所述第二组反相器的输入端与所述使能控制器的输出端连接，所述第二组反相器的输出端用于输出时钟信号。
  2. 如权利要求1所述的RC振荡电路，其特征在于，所述延时脉 冲发生电路包括低电平输出电路和高电平输出电路；所述低电平输出电路和所述高电平输出电路的输入端均作为所述延时脉冲发生电路的输入端，所述低电平输出电路的输出端作为所述延时脉冲发生电路的常低电平输出端，以输出低电平脉冲信号，所述高电平输出电路的输出端用于作为所述延时脉冲发生电路的常高电平输出端，以输出高电平脉冲信号。
  3. 如权利要求2所述的RC振荡电路，其特征在于，所述低电平输出电路包括第一延时反相器、第二电阻、第二电容、第二延时反相器、第一与非门以及第三延时反相器；
    所述第一延时反相器的输入端作为所述低电平输出电路的输入端，所述第二电阻的第一端与所述第一延时反相器的输出端连接，所述第二电阻的第二端连接至所述第二延时反相器，所述第二电容的第一端与所述第二电阻的第二端连接，所述第二电容的第二端接地；
    所述第二延时反相器的输出端连接至所述第一与非门的第一输入端，所述第一与非门的第二输入端与所述第一延时反相器的输出端连接，所述第一与非门的输出端连接至所述第三延时反相器的输入端，所述第三延时反相器的输出端作为所述低电平输出电路的输出端。
  4. 如权利要求3所述的RC振荡电路，其特征在于，所述高电平输出电路包括第四延时反相器以及第二与非门；
    所述第四延时反相器的输入端与所述第二延时反相器的输出端连接，所述第四延时反相器的输出端连接至所述第二与非门的第一输入端，所述第二与非门的第二输入端作为所述高电平输出电路的输入端，所述第二与非门的输出端作为所述高电平输出电路的输出端。
  5. 如权利要求1所述的RC振荡电路，其特征在于，所述第一组反相器包括多个依次串联的第一反相器。
  6. 如权利要求1所述的RC振荡电路，其特征在于，所述使能控制器为使能与非门；所述使能与非门的第一输入端作为所述使能控制器的第一输入端，所述使能与非门的第二输入端作为所述使能控制器 的第二输入端并连接至高电平使能信号，所述使能与非门的输出端作为所述使能控制器的输出端。
  7. 如权利要求1所述的RC振荡电路，其特征在于，所述使能控制器为使能或非门；所述使能或非门的第一输入端作为所述使能控制器的第一输入端，所述使能或非门的第二输入端作为所述使能控制器的第二输入端并连接至低电平使能信号，所述使能或非门的输出端作为所述使能控制器的输出端。
  8. 如权利要求5所述的RC振荡电路，其特征在于，所述第二组反相器包括多个依次串联的第二反相器。
  9. 如权利要求8所述的RC振荡电路，其特征在于，所述第一组反相器包括两个第一反相器，所述第二组反相器包括两个第二反相器。
  10. 如权利要求1所述的RC振荡电路，其特征在于，所述第一场效应管和所述第三场效应管为PMOS管，所述第二场效应管和所述第四场效应管为NMOS管。
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