WO2024119627A1 - 分区可变刷新率的显示面板以及驱动方法 - Google Patents

分区可变刷新率的显示面板以及驱动方法 Download PDF

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Publication number
WO2024119627A1
WO2024119627A1 PCT/CN2023/077890 CN2023077890W WO2024119627A1 WO 2024119627 A1 WO2024119627 A1 WO 2024119627A1 CN 2023077890 W CN2023077890 W CN 2023077890W WO 2024119627 A1 WO2024119627 A1 WO 2024119627A1
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transistor
coupled
electrode
node
input terminal
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PCT/CN2023/077890
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English (en)
French (fr)
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曾迎祥
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上海和辉光电股份有限公司
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Publication of WO2024119627A1 publication Critical patent/WO2024119627A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix

Definitions

  • the present invention relates to the field of display panel control circuits, and in particular to a display panel with a partitioned variable refresh rate and a driving method.
  • OLED Organic Light Emitting Diode
  • the refresh rate of a display refers to the number of times the image on the screen is repeatedly scanned from top to bottom. The higher the refresh rate, the more stable the displayed image is and the less eye fatigue is. In recent years, as people spend more and more time using mobile devices, the refresh rates of various mobile device displays have been gradually increased in order to provide a better user experience.
  • the present invention aims to provide a display panel with a variable refresh rate in different zones and a driving method, which overcomes the difficulties of the prior art and enables the display panel to update the screen in different zones, maintain a high refresh rate in the dynamic display area in the screen, and adjust the static display area in the screen. For low refresh rate, reduce the power consumption of the display panel and extend the service life of the display panel.
  • An embodiment of the present invention provides a display panel with a variable refresh rate of partitions, comprising:
  • an area classification module detecting row information corresponding to a static display area with unchanged images and a dynamic display area with changed images in the display area of the panel, and generating a control signal group of corresponding states;
  • a driving circuit receives a first control signal group corresponding to the static display area, so that the driving voltage of the relevant pixel row of the static display area is output to the next row driving circuit, and the output signal of the driving circuit maintains a high level; or receives a second control signal group corresponding to the dynamic display area, so that the driving voltage of the relevant pixel row of the dynamic display area is output to the next row driving circuit and the output signal of the driving circuit respectively.
  • the driving circuit includes a plurality of rows of driving units, and the driving units include:
  • a first transistor wherein a first electrode of the first transistor is coupled to a first power supply voltage, and a gate of the first transistor is coupled to a first node;
  • a second transistor wherein a first electrode of the second transistor is coupled to the second electrode of the first transistor, a second electrode of the second transistor is coupled to a second node, and a gate of the second transistor is coupled to a first input terminal;
  • a third transistor wherein a first electrode of the third transistor is coupled to the second node, a second electrode of the third transistor is coupled to a third input terminal, and a gate of the third transistor is coupled to a second input terminal;
  • a fourth transistor wherein a first electrode of the fourth transistor is coupled to the first node, a second electrode of the fourth transistor is coupled to the second input terminal, and a gate of the fourth transistor is coupled to the second node;
  • a fifth transistor wherein a first electrode of the fifth transistor is coupled to the first node, a second electrode of the fifth transistor is coupled to a second power supply voltage, and a gate of the fifth transistor is coupled to the second input terminal;
  • a sixth transistor wherein a first electrode of the sixth transistor is coupled to the first power supply voltage, a second electrode of the sixth transistor is coupled to a third node, and a gate of the sixth transistor is coupled to the first node;
  • a seventh transistor wherein a first electrode of the seventh transistor is coupled to the third node, a second electrode of the seventh transistor is coupled to the first input terminal, and a gate of the seventh transistor is coupled to the second node;
  • a ninth transistor wherein a first electrode of the ninth transistor is coupled to the third node, and a second electrode of the ninth transistor is coupled to an output terminal;
  • a tenth transistor a first electrode of the tenth transistor being coupled to the first power supply voltage, A diode is coupled to the output terminal;
  • a first capacitor wherein a first electrode of the first capacitor is coupled to the first power supply voltage, and a second electrode of the first capacitor is coupled to the first node;
  • a second capacitor wherein a first electrode of the second capacitor is coupled to the second node, and a second electrode of the second capacitor is coupled to the third node;
  • the gate of the ninth transistor is coupled to a fourth input terminal
  • the gate of the tenth transistor is coupled to a fifth input terminal.
  • the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the ninth transistor, and the tenth transistor are all P-type MOS transistors.
  • a gate of the ninth transistor and a gate of the tenth transistor respectively receive a first control signal and a second control signal of the first control signal group.
  • the first control signal and the second control signal are inverse signals of each other.
  • the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the tenth transistor are all P-type MOS transistors, and the ninth transistor is an N-type MOS transistor.
  • a gate of the ninth transistor and a gate of the tenth transistor respectively receive the same control signal of the first control signal group.
  • the driving circuit further includes a first signal lead, a second signal lead, a fourth signal lead and a fifth signal lead;
  • the driving voltage of the driving unit in the previous row is output to the third input terminal of the driving unit in the next row as a start signal;
  • the first input terminal is coupled to the first signal lead
  • the second input terminal is coupled to the second signal lead
  • the fourth input terminal is coupled to the fourth signal lead
  • the fifth input terminal is coupled to the fifth signal lead.
  • the driving circuit further includes a start signal lead.
  • the third input terminals of the driving units in the first row are coupled to the start signal lead.
  • An embodiment of the present invention further provides a driving method, which is applied to the driving circuit of the partitioned variable refresh rate display panel, comprising:
  • the driving unit of the relevant pixel row receives the first control signal group sent by the fourth signal lead and the fifth signal lead, the driving voltage of the driving unit is output to the driving unit of the next row, and the output signal of the driving unit is output at a high level to maintain the picture data of the previous frame of the pixel row;
  • the driving unit of the relevant pixel row receives the second control signal group sent jointly by the fourth signal lead and the fifth signal lead, and the driving voltage of the driving unit is output to the output signal of the driving unit and the next row of driving units respectively, updating the previous frame of picture data of the pixel row.
  • the partitioned variable refresh rate display panel and driving method of the present invention can update the screen in partitions of the display panel, maintain a high refresh rate in the dynamic display area of the screen, and adjust the static display area of the screen to a low refresh rate, thereby reducing the power consumption of the display panel and extending the service life of the display panel.
  • FIG1 is a block diagram of a display panel with a variable refresh rate in different zones according to the present invention.
  • FIG2 is a circuit diagram of a driving unit according to a first embodiment of the present invention.
  • FIG. 3 is a circuit diagram of a driving circuit according to a first embodiment of the present invention.
  • FIG4 is a waveform diagram of a driving circuit according to a first embodiment of the present invention.
  • FIG5 is a schematic diagram of the conduction state of the driving unit in phases A and C in FIG1 ;
  • FIG6 is a schematic diagram of a conduction state of a driving unit in phase B in FIG1 ;
  • FIG7 is a schematic diagram of the use effect of the present invention.
  • FIG. 8 is a circuit diagram of a driving unit according to a second embodiment of the present invention.
  • the representations with reference to the terms “one embodiment”, “some embodiments”, “examples”, “specific examples”, or “some examples” etc. mean that the specific features, structures, materials or characteristics represented in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. Moreover, the specific features, structures, materials or characteristics represented may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples represented in the present application and the features of the different embodiments or examples, unless they are contradictory.
  • first, second, etc. are used in some examples to indicate various elements in this document, these elements should not be limited by these terms and should not be understood to indicate or imply relative importance or implicitly indicate the number of technical features indicated. .
  • the features defined as “first” and “second” may explicitly or implicitly include at least one of the features. These terms are only used to distinguish one element from another. For example, the first interface and the second interface, etc. are indicated.
  • the singular forms “one”, “an”, and “the” are intended to also include plural forms, unless otherwise indicated in the context. In the representation of this application, the meaning of “multiple” is two or more, unless otherwise clearly and specifically defined.
  • FIG1 is a block diagram of a display panel with a variable refresh rate of a partition of the present invention.
  • a display panel with a variable refresh rate of a partition of the present invention is characterized in that it includes: a region classification module and a driving circuit.
  • the region classification module is mainly used to detect the row information corresponding to the static display area with unchanged pictures and the dynamic display area with changed pictures in the display area of the panel, and generate a control signal group of corresponding states.
  • the driving circuit is mainly used to receive the first control signal group corresponding to the static display area, so that the driving voltage of the relevant pixel row of the static display area is output to the next row driving circuit, and the output signal of the driving circuit maintains a high level; or, receive the second control signal group corresponding to the dynamic display area, so that the driving voltage of the relevant pixel row of the dynamic display area is output to the next row driving circuit and the output signal of the driving circuit respectively.
  • the display panel of the present invention can adjust the refresh rate of each picture area by the cooperation of the region classification module and the driving circuit, maintain a high refresh rate in the dynamic display area of the picture of the display panel, and adjust the static display area in the picture to a low refresh rate, thereby reducing the power consumption of the display panel and extending the service life of the display panel.
  • FIG2 is a circuit diagram of a driving unit of the first embodiment of the present invention.
  • the driving unit of the driving circuit of the first embodiment of the present invention comprises: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a A sixth transistor T6, a seventh transistor T7, a ninth transistor T9, a tenth transistor T10, a first capacitor C1 and a second capacitor C2.
  • the first electrode of the first transistor T1 is coupled to a first power supply voltage VDD, and the gate is coupled to a first node N1.
  • the first electrode of the second transistor T2 is coupled to the second electrode of the first transistor T1, the second electrode is coupled to a second node N2, and the gate is coupled to a first input terminal IN1.
  • the first electrode of the third transistor T3 is coupled to the second node N2, the second electrode is coupled to a third input terminal IN3, and the gate is coupled to a second input terminal IN2.
  • the first electrode of the fourth transistor T4 is coupled to the first node N1, the second electrode is coupled to the second input terminal IN2, and the gate is coupled to the second node N2.
  • the first electrode of the fifth transistor T5 is coupled to the first node N1, the second electrode is coupled to a second power supply voltage VEE, and the gate is coupled to the second input terminal IN2.
  • the first electrode of the sixth transistor T6 is coupled to the first power supply voltage VDD, the second electrode is coupled to a third node N3, and the gate is coupled to the first node N1.
  • the first electrode of the seventh transistor T7 is coupled to the third node N3, the second electrode is coupled to the first input terminal IN1, and the gate is coupled to the second node N2.
  • the first electrode of the ninth transistor T9 is coupled to the third node N3, and the second electrode is coupled to an output terminal Gout.
  • the first electrode of the tenth transistor T10 is coupled to the first power supply voltage VDD, and the second electrode is coupled to the output terminal Gout.
  • the first electrode of the first capacitor C1 is coupled to the first power supply voltage VDD, and the second electrode is coupled to the first node N1.
  • the first electrode of the second capacitor C2 is coupled to the second node N2, and the second electrode is coupled to the third node N3.
  • the gate of the ninth transistor T9 is coupled to a fourth input terminal IN4.
  • the gate of the tenth transistor T10 is coupled to a fifth input terminal IN5, but is not limited thereto.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the ninth transistor T9, and the tenth transistor T10 are all P-type MOS tubes.
  • the gate of the ninth transistor T9 and the gate of the tenth transistor T10 respectively receive the first control signal and the second control signal of the first control signal group, and the first control signal and the second control signal are inverse signals to each other.
  • FIG3 is a circuit diagram of a driving circuit of a first embodiment of the present invention.
  • the driving circuit of the present invention further includes a first signal lead CKV1, a second signal lead CKV2, a fourth signal lead TEP and a fifth signal lead TEN.
  • the driving voltage of the previous row driving unit is output to the third input terminal IN3 of the next row driving unit as a start signal.
  • the first input terminal IN1 is coupled to the first signal lead CKV1.
  • the second input terminal IN2 is coupled to the second signal lead CKV2.
  • the fourth input terminal IN4 is coupled to the fourth signal lead TEP.
  • the fifth input terminal IN5 is coupled to the fifth signal lead TEN.
  • the driving circuit further includes a start signal lead line STV, and the third input terminal IN3 of the first row driving unit is coupled to the start signal lead line STV.
  • Figures 4 to 7 are waveform diagram of the driving circuit of the first embodiment of the present invention.
  • Figure 5 is a schematic diagram of the conduction state of the driving unit in the A and C stages in Figure 1.
  • Figure 6 is a schematic diagram of the conduction state of the driving unit in the B stage in Figure 1.
  • Figure 7 is a schematic diagram of the use effect of the present invention. The use of " ⁇ " in Figures 5 to 6 indicates that the transistor is cut off.
  • the driving unit of the present invention is in the static display area 1 in the A phase, the fourth input terminal IN4 inputs a high level, and the fifth input terminal IN5 inputs a low level.
  • the first transistor T1 to the seventh transistor T7 are turned on, the ninth transistor T9 is turned off, and the tenth transistor T10 is turned on.
  • the driving voltage of the driving unit of the static display area 1 is normally output to the next stage Next, and the output terminal Gout outputs a high level, maintaining the previous frame image data of the relevant pixel row of the static display area 1 of the display panel without updating.
  • the driving unit of the present invention is in the dynamic display area 2 in the B stage, the fourth input terminal IN4 inputs a low level, and the fifth input terminal IN5 inputs a high level.
  • the first transistor T1 to the seventh transistor T7 are turned on, the ninth transistor T9 is turned on, and the tenth transistor T10 is turned off.
  • the driving voltage of the driving unit of the dynamic display area 2 is normally output to the next stage Next, and the output terminal Gout outputs a low level to update the previous frame image data of the relevant pixel row of the dynamic display area 2 of the display panel.
  • the driving unit of the present invention is in the static display area 1 in the C stage, the fourth input terminal IN4 inputs a high level, and the fifth input terminal IN5 inputs a low level.
  • the first transistor T1 to the seventh transistor T7 are turned on, the ninth transistor T9 is turned off, and the tenth transistor T10 is turned on.
  • the driving voltage of the driving unit of the static display area 1 is normally output to the next stage Next, and the output terminal Gout outputs a high level, maintaining the previous frame image data of the relevant pixel row of the static display area 1 of the display panel without updating.
  • the display panel completes a refresh process from top to bottom and enters the next refresh.
  • the present invention also provides a driving method, which is applied to the driving circuit of the above-mentioned partitioned variable refresh rate display panel, comprising:
  • the driving unit of the relevant pixel row receives the first control signal group sent by the fourth signal lead TEP and the fifth signal lead TEN, and the driving voltage of the driving unit is output to the driving unit of the next row, and the output signal Gout of the driving unit outputs a high level to maintain the picture data of the previous frame of the pixel row;
  • the driving unit of the relevant pixel row receives the second control signal group sent jointly by the fourth signal lead TEP and the fifth signal lead TEN, and the driving voltage of the driving unit is output to the output signal Gout of the driving unit and the next row of driving units respectively, updating the previous frame of picture data of the pixel row.
  • Fig. 8 is a circuit diagram of a driving unit of the second embodiment of the present invention. As shown in Fig. 8, the driving unit of the second embodiment of the present invention is different from the driving unit of the first embodiment as follows:
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the tenth transistor T10 are all P-type MOS transistors, and the ninth transistor T9 is an N-type MOS transistor.
  • the gate of the ninth transistor T9 and the gate of the tenth transistor T10 respectively receive the same control signal of the first control signal group, and the gate of the ninth transistor T9 and the gate of the tenth transistor T10 are respectively coupled to the fifth input terminal IN5, and the fifth input terminal IN5 is coupled to the fifth signal lead TEN.
  • This embodiment can accomplish the same functions as the first embodiment, and will not be described in detail here.
  • the partitioned variable refresh rate display panel and driving method of the present invention can enable the display panel to update the screen in partitions, maintain a high refresh rate in the dynamic display area of the screen, and adjust the static display area of the screen to a low refresh rate, thereby reducing the power consumption of the display panel and extending the service life of the display panel.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种分区可变刷新率的显示面板以及驱动方法，分区可变刷新率的显示面板包括：区域分类模块（11），检测面板的显示区域中画面不变的静态显示区域（1）与画面变化的动态显示区域（2）所对应的行信息，并生成对应状态的控制信号组；驱动电路（12），接收静态显示区域（1）对应的第一控制信号组，令静态显示区域（1）的相关像素行的驱动电压输出到下一行驱动电路（12），驱动电路（12）的输出信号维持高电平；或者，接收动态显示区域（2）对应的第二控制信号组，令动态显示区域（2）的相关像素行的驱动电压分别输出到下一行驱动电路（12）和驱动电路（12）的输出信号。能够降低显示面板的功耗，延长显示面板的使用寿命。

Description

分区可变刷新率的显示面板以及驱动方法 技术领域
本发明涉及显示面板控制电路领域，尤其涉及一种分区可变刷新率的显示面板以及驱动方法。
背景技术
作为新一代显示技术，OLED(Organic Light Emitting Diode，有机发光二极管)显示器具有低功耗、高色域、高亮度、高刷新率、宽视角、高响应速度等优点，尤其是高刷新率的优点使得OLED显示器更加适合移动装置的显示，因此受到越来越广泛的应用。
显示器的刷新率，表示屏幕上的图像从上到下重复扫描的次数，刷新率越高，显示的画面稳定性就越高，人眼疲劳程度就越低。近年来由于人对移动装置的使用时间逐渐增加，各种移动装置显示器为了更好地使用体验，因此刷新率都在逐渐提高。
但是，移动装置对功耗的要求较高，而其中显示器所占功耗比例尤为重要，显示器刷新率直接影响功耗。低刷新率虽拥有较低的功耗，但低刷新率动态画显示效果严重影响显示品质。
目前，移动装置的使用过程中，并非所有显示区域的画面均实时发生变化，尤其以短视频应用为代表的情形下，显示区域中存在大量长时间画面不发生变化的静态显示区域。但是目前移动装置显示器的所有显示区域均采用同一刷新率，即采用动态显示区域的高刷新率，造成了功耗的浪费。同时显示器一直以最高刷新率工作，会加速自身的老化。
发明内容
针对现有技术中的缺陷，本发明的目的在于提供分区可变刷新率的显示面板以及驱动方法，克服了现有技术的困难，使得显示面板分区更新画面，在画面中动态显示区域维持高刷新率，在画面中静态显示区域调整 为低刷新率，降低显示面板的功耗，延长显示面板的使用寿命。
本发明的实施例提供一种分区可变刷新率的显示面板，包括：
区域分类模块，检测所述面板的显示区域中画面不变的静态显示区域与画面变化的动态显示区域所对应的行信息，并生成对应状态的控制信号组；以及
驱动电路，接收所述静态显示区域对应的第一控制信号组，令所述静态显示区域的相关像素行的驱动电压输出到下一行驱动电路，所述驱动电路的输出信号维持高电平；或者，接收所述动态显示区域对应的第二控制信号组，令所述动态显示区域的相关像素行的驱动电压分别输出到下一行驱动电路和所述驱动电路的输出信号。
在一些实施例中，所述驱动电路包括多行驱动单元，所述驱动单元包括：
一第一晶体管，所述第一晶体管的第一极耦接一第一电源电压，栅极耦接一第一节点；
一第二晶体管，所述第二晶体管的第一极耦接所述第一晶体管的第二极，第二极耦接一第二节点，栅极耦接一第一输入端；
一第三晶体管，所述第三晶体管的第一极耦接所述第二节点，第二极耦接一第三输入端，栅极耦接一第二输入端；
一第四晶体管，所述第四晶体管的第一极耦接所述第一节点，第二极耦接所述第二输入端，栅极耦接所述第二节点；
一第五晶体管，所述第五晶体管的第一极耦接所述第一节点，第二极耦接一第二电源电压，栅极耦接所述第二输入端；
一第六晶体管，所述第六晶体管的第一极耦接所述第一电源电压，第二极耦接一第三节点，栅极耦接所述第一节点；
一第七晶体管，所述第七晶体管的第一极耦接所述第三节点，第二极耦接所述第一输入端，栅极耦接所述第二节点；
一第九晶体管，所述第九晶体管的第一极耦接所述第三节点，第二极耦接一输出端；
一第十晶体管，所述第十晶体管的第一极耦接所述第一电源电压，第 二极耦接所述输出端；
一第一电容，所述第一电容的第一极耦接所述第一电源电压，第二极耦接所述第一节点；
一第二电容，所述第二电容的第一极耦接所述第二节点，第二极耦接所述第三节点；
所述第九晶体管的栅极耦接一第四输入端；
所述第十晶体管的栅极耦接一第五输入端。
在一些实施例中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第七晶体管、所述第九晶体管、所述第十晶体管均为P型MOS管。
在一些实施例中，所述第九晶体管的栅极和所述第十晶体管的栅极各自接收所述第一控制信号组的第一控制信号和第二控制信号。
在一些实施例中，所述第一控制信号和第二控制信号互为反向信号。
在一些实施例中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第七晶体管、所述第十晶体管均为P型MOS管，所述第九晶体管为N型MOS管。
在一些实施例中，所述第九晶体管的栅极和所述第十晶体管的栅极分别接收第一控制信号组的同一控制信号。
在一些实施例中，所述驱动电路还包括一第一信号引线、一第二信号引线、一第四信号引线和一第五信号引线；
上一行所述驱动单元的驱动电压输出到下一行所述驱动单元的所述第三输入端作为启动信号；
所述第一输入端耦接所述第一信号引线；
所述第二输入端耦接所述第二信号引线；
所述第四输入端耦接所述第四信号引线；
所述第五输入端耦接所述第五信号引线。
在一些实施例中，所述驱动电路还包括一启动信号引线，
第一行所述驱动单元的所述第三输入端耦接所述启动信号引线。
本发明的实施例还提供一种驱动方法，应用于所述分区可变刷新率的显示面板的所述驱动电路，包括：
在静态显示区域，相关像素行的所述驱动单元接收第四信号引线和第五信号引线共同发送的第一控制信号组，所述驱动单元的驱动电压输出到下一行驱动单元，所述驱动单元的输出信号输出高电平，维持所述像素行上一帧画面资料；
在动态显示区域，相关像素行的所述驱动单元接收所述第四信号引线和所述第五信号引线共同发送的第二控制信号组，所述驱动单元的驱动电压分别输出到所述驱动单元的输出信号和下一行驱动单元，更新所述像素行上一帧画面资料。
本发明的分区可变刷新率的显示面板以及驱动方法，能够使得显示面板分区更新画面，在画面中动态显示区域维持高刷新率，在画面中静态显示区域调整为低刷新率，降低显示面板的功耗，延长显示面板的使用寿命。
附图说明
通过阅读参照以下附图对非限制性实施例所作的详细描述，本发明的其它特征、目的和优点将会变得更明显：
图1为本发明的分区可变刷新率的显示面板的结构框图；
图2为本发明的第一实施例的驱动单元的电路图；
图3为本发明的第一实施例的驱动电路的电路图；
图4为本发明的第一实施例的驱动电路的波形图；
图5为图1中A和C阶段的驱动单元的导通状态示意图；
图6为图1中B阶段的驱动单元的导通状态示意图；
图7为本发明的使用效果示意图；
图8为本发明的第二实施例的驱动单元的电路图。
附图标记
VDD        第一电源电压
VEE        第二电源电压
STV        传输启动信号
CKV1       第一时钟信号
CKV2       第二时钟信号
Gout       输出信号
N1         第一节点
N2         第二节点
N3         第三节点
T1         第一晶体管
T2         第二晶体管
T3         第三晶体管
T4         第四晶体管
T5         第五晶体管
T6         第六晶体管
T7         第七晶体管
T9         第九晶体管
T10        第十晶体管
C1         第一电容
C2         第二电容
IN1        第一输入端
IN2        第二输入端
IN3        第三输入端
IN4        第四输入端
IN5        第五输入端
11         区域分类模块
12         驱动电路
1          静态显示区域
2          动态显示区域
具体实施方式
以下以附图为参考，通过特定的具体实例说明本申请的实施方式，本领域技术人员可由本申请所揭露的内容轻易地了解本申请的其他优 点与功效。本申请还可以通过另外不同的具体实施方式加以实施或应用***，本申请中的各项细节也可以根据不同观点与应用***，在没有背离本申请的精神下进行各种修饰或改变。需说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。
在本申请的表示中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的表示意指结合该实施例或示例表示的具体特征、结构、材料或者特点包括于本申请的至少一个实施例或示例中。而且，表示的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本申请中表示的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
为了明确说明本申请，省略与说明无关的器件，对于通篇说明书中相同或类似的构成要素，赋予了相同的参照符号。
在通篇说明书中，当说某器件与另一器件“连接”时，这不仅包括“直接连接”的情形，也包括在其中间把其它元件置于其间而“间接连接”的情形。
当说某器件在另一器件“之上”时，这可以是直接在另一器件之上，但也可以在其之间伴随着其它器件。当对照地说某器件“直接”在另一器件“之上”时，其之间不伴随其它器件。
虽然在一些实例中术语“第一”、“第二”等在本文中用来表示各种元件，但是这些元件不应当被这些术语限制，且不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。。由此，限定有“第一”、“第二”的特征可以明示或隐含地包括至少一个该特征。这些术语仅用来将一个元件与另一个元件进行区分。例如，第一接口及第二接口等表示。再者，如同在本文中所使用的，单数形式“一”、“一个”和“该”旨在也包括复数形式，除非上下文中有相反的指示。在本申请的表示中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。应当进一步理解，术语“包含”、“包括”表明存在的特征、步骤、操作、元件、组件、项目、种类、和/或组，但不排除一个或多个其他特征、步骤、操作、元件、组件、项目、种类、和/或组的存在、出 现或添加。此处使用的术语“或”和“和/或”被解释为包括性的，或意味着任一个或任何组合。因此，“A、B或C”或者“A、B和/或C”意味着“以下任一个：A；B；C；A和B；A和C；B和C；A、B和C”。仅当元件、功能、步骤或操作的组合在某些方式下内在地互相排斥时，才会出现该定义的例外。
此处使用的专业术语只用于言及特定实施例，并非意在限定本申请。此处使用的单数形态，只要语句未明确表示出与之相反的意义，那么还包括复数形态。
虽然未不同地定义，但包括此处使用的技术术语及科学术语，所有术语均具有与本申请所属技术领域的技术人员一般理解的意义相同的意义。普通使用的字典中定义的术语追加解释为具有与相关技术文献和当前提示的内容相符的意义，只要未进行定义，不得过度解释为理想的或非常公式性的意义。
图1为本发明的分区可变刷新率的显示面板的结构框图。如图1所示，本发明的一种分区可变刷新率的显示面板，其特征在于，包括：区域分类模块和驱动电路。区域分类模块主要用于检测面板的显示区域中画面不变的静态显示区域与画面变化的动态显示区域所对应的行信息，并生成对应状态的控制信号组。驱动电路主要用于接收静态显示区域对应的第一控制信号组，令静态显示区域的相关像素行的驱动电压输出到下一行驱动电路，驱动电路的输出信号维持高电平；或者，接收动态显示区域对应的第二控制信号组，令动态显示区域的相关像素行的驱动电压分别输出到下一行驱动电路和驱动电路的输出信号。从而使得本发明的显示面板能够通过区域分类模块和驱动电路的配合，分区调整各画面区域的刷新率，在显示面板的画面中动态显示区域维持高刷新率，在画面中静态显示区域调整为低刷新率，降低显示面板的功耗，延长显示面板的使用寿命。
图2为本发明的第一实施例的驱动单元的电路图。如图2所示，本发明的第一实施例的驱动电路的驱动单元包括：一第一晶体管T1、一第二晶体管T2、一第三晶体管T3、一第四晶体管T4、一第五晶体管T5、一 第六晶体管T6、一第七晶体管T7、一第九晶体管T9、一第十晶体管T10、一第一电容C1以及一第二电容C2。其中，第一晶体管T1的第一极耦接一第一电源电压VDD，栅极耦接一第一节点N1。第二晶体管T2的第一极耦接第一晶体管T1的第二极，第二极耦接一第二节点N2，栅极耦接一第一输入端IN1。第三晶体管T3的第一极耦接第二节点N2，第二极耦接一第三输入端IN3，栅极耦接一第二输入端IN2。第四晶体管T4的第一极耦接第一节点N1，第二极耦接第二输入端IN2，栅极耦接第二节点N2。第五晶体管T5的第一极耦接第一节点N1，第二极耦接一第二电源电压VEE，栅极耦接第二输入端IN2。第六晶体管T6的第一极耦接第一电源电压VDD，第二极耦接一第三节点N3，栅极耦接第一节点N1。第七晶体管T7的第一极耦接第三节点N3，第二极耦接第一输入端IN1，栅极耦接第二节点N2。第九晶体管T9的第一极耦接第三节点N3，第二极耦接一输出端Gout。第十晶体管T10的第一极耦接第一电源电压VDD，第二极耦接输出端Gout。第一电容C1的第一极耦接第一电源电压VDD，第二极耦接第一节点N1。第二电容C2的第一极耦接第二节点N2，第二极耦接第三节点N3。第九晶体管T9的栅极耦接一第四输入端IN4。第十晶体管T10的栅极耦接一第五输入端IN5，但不以此为限。在本实施例中，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、第九晶体管T9、第十晶体管T10均为P型MOS管。在本实施例中，第九晶体管T9的栅极和第十晶体管T10的栅极各自接收第一控制信号组的第一控制信号和第二控制信号，第一控制信号和第二控制信号互为反向信号。
图3为本发明的第一实施例的驱动电路的电路图。如图3所示，本发明的驱动电路还包括一第一信号引线CKV1、一第二信号引线CKV2、一第四信号引线TEP和一第五信号引线TEN。上一行驱动单元的驱动电压输出到下一行驱动单元的第三输入端IN3作为启动信号。第一输入端IN1耦接第一信号引线CKV1。第二输入端IN2耦接第二信号引线CKV2。第四输入端IN4耦接第四信号引线TEP。第五输入端IN5耦接第五信号引线TEN。
在本实施例中，驱动电路还包括一启动信号引线STV，第一行驱动单元的第三输入端IN3耦接启动信号引线STV。
以下通过图4至图7来展示本发明的第一实施例的驱动电路中一驱动单元在第A阶段至第C阶段中具体的电路导通状况以及对应的脉冲波形图。图4为本发明的第一实施例的驱动电路的波形图。图5为图1中A和C阶段的驱动单元的导通状态示意图。图6为图1中B阶段的驱动单元的导通状态示意图。图7为本发明的使用效果示意图。图5至6中使用“×”表示该晶体管截止。
如图4、5和7所示，本发明的驱动单元在第A阶段时处于静态显示区域1，第四输入端IN4输入高电平；第五输入端IN5输入低电平。
则第一晶体管T1至第七晶体管T7导通，第九晶体管T9截止，第十晶体管T10导通。
最终，静态显示区域1的驱动单元的驱动电压正常输出至下一级Next，输出端Gout输出高电平，维持显示面板的静态显示区域1的相关像素行的上一帧画面资料不更新。
如图4、6和7所示，本发明的驱动单元在第B阶段时处于动态显示区域2，第四输入端IN4输入低电平；第五输入端IN5输入高电平。
则第一晶体管T1至第七晶体管T7导通，第九晶体管T9导通，第十晶体管T10截止。
最终，动态显示区域2的驱动单元的驱动电压正常输出至下一级Next，输出端Gout输出低电平，更新显示面板的动态显示区域2的相关像素行的上一帧画面资料。
如图4、5和7所示，本发明的驱动单元在第C阶段时处于静态显示区域1，第四输入端IN4输入高电平；第五输入端IN5输入低电平。
则第一晶体管T1至第七晶体管T7导通，第九晶体管T9截止，第十晶体管T10导通。
最终，静态显示区域1的驱动单元的驱动电压正常输出至下一级Next，输出端Gout输出高电平，维持显示面板的静态显示区域1的相关像素行的上一帧画面资料不更新。
至此，显示面板完成一次从上至下的刷新过程，进入下一次刷新。
本发明还提供一种驱动方法，应用于上述分区可变刷新率的显示面板的驱动电路，包括：
在静态显示区域，相关像素行的驱动单元接收第四信号引线TEP和第五信号引线TEN共同发送的第一控制信号组，驱动单元的驱动电压输出到下一行驱动单元，驱动单元的输出信号Gout输出高电平，维持像素行上一帧画面资料；
在动态显示区域，相关像素行的驱动单元接收第四信号引线TEP和第五信号引线TEN共同发送的第二控制信号组，驱动单元的驱动电压分别输出到驱动单元的输出信号Gout和下一行驱动单元，更新像素行上一帧画面资料。
图8为本发明的第二实施例的驱动单元的电路图。如图8所示，本发明的第二实施例的驱动单元和第一实施例的驱动单元具有如下区别：
在本实施例中，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、第十晶体管T10均为P型MOS管，第九晶体管T9为N型MOS管。
在本实施例中，第九晶体管T9的栅极和第十晶体管T10的栅极分别接收第一控制信号组的同一控制信号，第九晶体管T9的栅极和第十晶体管T10的栅极分别耦接第五输入端IN5，第五输入端IN5耦接第五信号引线TEN。
本实施例可以完成与第一实施例相同的功能，此处不再赘述。
综上可知，本发明的分区可变刷新率的显示面板以及驱动方法，能够使得显示面板分区更新画面，在画面中动态显示区域维持高刷新率，在画面中静态显示区域调整为低刷新率，降低显示面板的功耗，延长显示面板的使用寿命。
以上对本发明的具体实施例进行了描述。需要理解的是，本发明并不局限于上述特定实施方式，本领域技术人员可以在权利要求的范围内 做出各种变形或修改，这并不影响本发明的实质内容。

Claims (10)

  1. 一种分区可变刷新率的显示面板，其特征在于，包括：
    区域分类模块，检测所述面板的显示区域中画面不变的静态显示区域与画面变化的动态显示区域所对应的行信息，并生成对应状态的控制信号组；以及
    驱动电路，接收所述静态显示区域对应的第一控制信号组，令所述静态显示区域的相关像素行的驱动电压输出到下一行驱动电路，所述驱动电路的输出信号维持高电平；或者，接收所述动态显示区域对应的第二控制信号组，令所述动态显示区域的相关像素行的驱动电压分别输出到下一行驱动电路和所述驱动电路的输出信号。
  2. 如权利要求1所述的分区可变刷新率的显示面板，其特征在于，所述驱动电路包括多行驱动单元，所述驱动单元包括：
    一第一晶体管，所述第一晶体管的第一极耦接一第一电源电压，栅极耦接一第一节点；
    一第二晶体管，所述第二晶体管的第一极耦接所述第一晶体管的第二极，第二极耦接一第二节点，栅极耦接一第一输入端；
    一第三晶体管，所述第三晶体管的第一极耦接所述第二节点，第二极耦接一第三输入端，栅极耦接一第二输入端；
    一第四晶体管，所述第四晶体管的第一极耦接所述第一节点，第二极耦接所述第二输入端，栅极耦接所述第二节点；
    一第五晶体管，所述第五晶体管的第一极耦接所述第一节点，第二极耦接一第二电源电压，栅极耦接所述第二输入端；
    一第六晶体管，所述第六晶体管的第一极耦接所述第一电源电压，第二极耦接一第三节点，栅极耦接所述第一节点；
    一第七晶体管，所述第七晶体管的第一极耦接所述第三节点，第二极耦接所述第一输入端，栅极耦接所述第二节点；
    一第九晶体管，所述第九晶体管的第一极耦接所述第三节点，第二极耦接一输出端；
    一第十晶体管，所述第十晶体管的第一极耦接所述第一电源电压，第 二极耦接所述输出端；
    一第一电容，所述第一电容的第一极耦接所述第一电源电压，第二极耦接所述第一节点；
    一第二电容，所述第二电容的第一极耦接所述第二节点，第二极耦接所述第三节点；
    所述第九晶体管的栅极耦接一第四输入端；
    所述第十晶体管的栅极耦接一第五输入端。
  3. 如权利要求2所述的分区可变刷新率的显示面板，其特征在于，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第七晶体管、所述第九晶体管、所述第十晶体管均为P型MOS管。
  4. 如权利要求3所述的分区可变刷新率的显示面板，其特征在于，所述第九晶体管的栅极和所述第十晶体管的栅极各自接收所述第一控制信号组的第一控制信号和第二控制信号。
  5. 如权利要求4所述的分区可变刷新率的显示面板，其特征在于，所述第一控制信号和第二控制信号互为反向信号。
  6. 如权利要求2所述的分区可变刷新率的显示面板，其特征在于，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第七晶体管、所述第十晶体管均为P型MOS管，所述第九晶体管为N型MOS管。
  7. 如权利要求6所述的分区可变刷新率的显示面板，其特征在于，所述第九晶体管的栅极和所述第十晶体管的栅极分别接收第一控制信号组的同一控制信号。
  8. 如权利要求2所述的分区可变刷新率的显示面板，其特征在于，所述驱动电路还包括一第一信号引线、一第二信号引线、一第四信号引线和一第五信号引线；
    上一行所述驱动单元的驱动电压输出到下一行所述驱动单元的所述第三输入端作为启动信号；
    所述第一输入端耦接所述第一信号引线；
    所述第二输入端耦接所述第二信号引线；
    所述第四输入端耦接所述第四信号引线；
    所述第五输入端耦接所述第五信号引线。
  9. 如权利要求8所述的分区可变刷新率的显示面板，其特征在于，所述驱动电路还包括一启动信号引线，
    第一行所述驱动单元的所述第三输入端耦接所述启动信号引线。
  10. 一种驱动方法，其特征在于，应用于如权利要求1-9任一项所述的分区可变刷新率的显示面板的所述驱动电路，包括：
    在静态显示区域，相关像素行的所述驱动单元接收第四信号引线和第五信号引线共同发送的第一控制信号组，所述驱动单元的驱动电压输出到下一行驱动单元，所述驱动单元的输出信号输出高电平，维持所述像素行上一帧画面资料；
    在动态显示区域，相关像素行的所述驱动单元接收所述第四信号引线和所述第五信号引线共同发送的第二控制信号组，所述驱动单元的驱动电压分别输出到所述驱动单元的输出信号和下一行驱动单元，更新所述像素行上一帧画面资料。
PCT/CN2023/077890 2022-12-05 2023-02-23 分区可变刷新率的显示面板以及驱动方法 WO2024119627A1 (zh)

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