WO2024114182A1 - Highly integrated heterogeneous package substrate and module - Google Patents

Highly integrated heterogeneous package substrate and module Download PDF

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Publication number
WO2024114182A1
WO2024114182A1 PCT/CN2023/126189 CN2023126189W WO2024114182A1 WO 2024114182 A1 WO2024114182 A1 WO 2024114182A1 CN 2023126189 W CN2023126189 W CN 2023126189W WO 2024114182 A1 WO2024114182 A1 WO 2024114182A1
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Prior art keywords
heterogeneous
highly integrated
dielectric material
metal wiring
material layer
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PCT/CN2023/126189
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French (fr)
Chinese (zh)
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宣凯
郭嘉帅
龙华
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深圳飞骧科技股份有限公司
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Publication of WO2024114182A1 publication Critical patent/WO2024114182A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements

Definitions

  • the utility model relates to the technical field of packaging, and in particular to a highly integrated heterogeneous packaging substrate and module.
  • the products of the application core components of the related technology are formed by welding chips, capacitors, inductors, resistors and other components on a substrate.
  • the substrate of the related technology is generally an organic base substrate.
  • IPD filters integrated passive filters
  • Integrated passive filters i.e., IPD filters
  • SMD surface mount device packaging positions on the substrate to place capacitors, inductors, resistors, and IPD filters. Therefore, the cost is high and the required floor space is large, which is not conducive to the current increasingly miniaturized module design.
  • the heat generated by the chip soldered on the organic substrate during operation causes the temperature around the chip to rise.
  • the utility model proposes a highly integrated heterogeneous packaging substrate and module with high integration, small size and high reliability.
  • an embodiment of the utility model provides a highly integrated heterogeneous packaging substrate, the highly integrated heterogeneous packaging substrate comprising a glass substrate, two heterogeneous layers formed on opposite sides of the glass substrate, and a metal column penetrating the glass substrate;
  • the heterogeneous layer comprises a dielectric material layer attached to the glass substrate and a metal wire embedded in the dielectric material layer, the metal wire forms metal wiring, passive devices and a plurality of pads for welding with pins of an external chip and external wiring respectively in the dielectric material layer;
  • the metal wiring comprises N layers, N is a positive integer and satisfies, N ⁇ 2, the metal wiring in each of the heterogeneous layers is connected to the metal wiring in another heterogeneous layer through the metal column;
  • the passive device is made by the metal wire through an integrated passive device process, and the passive device comprises one or more of a capacitor, an inductor and a resistor;
  • the pad is arranged on a side of the dielectric material layer away from the glass
  • the pads and the passive components are respectively arranged in the heterogeneous layers on opposite sides of the glass substrate.
  • the highly integrated heterogeneous packaging substrate further comprises a back metal wiring layer arranged on a side of the heterogeneous layer away from the glass substrate.
  • At least two of the capacitor, the inductor and the resistor are connected within the dielectric material layer to form a circuit function module, and the circuit function module includes one or more of a radio frequency filter, an impedance matching circuit and a power decoupling circuit.
  • the dielectric material layer comprises a plurality of dielectric layers stacked in sequence; the metal wiring and the passive device are formed in the plurality of dielectric layers; and the pad is formed in one of the dielectric layers farthest from the glass substrate and exposed on the dielectric layer.
  • an embodiment of the present invention further provides a module, which includes a chip and the above-mentioned highly integrated heterogeneous packaging substrate provided in an embodiment of the present invention, wherein the pins of the chip are welded and connected to the pads.
  • the highly integrated heterogeneous packaging substrate and module of the utility model are
  • the highly integrated heterogeneous packaging substrate is provided with a glass substrate and two heterogeneous layers on opposite sides of the glass substrate.
  • the heterogeneous layers are provided with metal wires so that the metal wires form metal wiring, passive devices and multiple pads in the heterogeneous layers.
  • the highly integrated heterogeneous packaging substrate of the utility model adopts a glass substrate to replace the organic material substrate of the related technology, and forms passive matching components such as capacitors, inductors, resistors, etc. inside the glass substrate, which saves more space. Among them, the passive devices and the pads are electrically connected through the metal wiring.
  • the highly integrated heterogeneous packaging substrate can realize integrated capacitors, high-Q inductors and resistors through passive devices, and then electrically connected through metal wiring, so as to integrate the IPD filter in the dielectric material layer and realize the impedance matching circuit, RF filter and power supply decoupling circuit in the RF circuit, meet the miniaturized module design, and the device occupies a small substrate area, so that the highly integrated heterogeneous packaging substrate and module of the utility model have high integration and small volume.
  • the soldering pad and the passive device are respectively arranged in the heterogeneous layer on opposite sides of the glass substrate. This structure ensures that the heat generated by the external chip soldered to the soldering pad does not affect the operation of the passive device, thereby making the highly integrated heterogeneous packaging substrate and module of the present invention highly reliable.
  • FIG1 is a schematic structural diagram of a highly integrated heterogeneous packaging substrate according to a first embodiment of the present invention
  • FIG. 2 is a schematic diagram of the structure of a module according to a second embodiment of the present invention.
  • the present invention also provides a highly integrated heterogeneous packaging substrate 100.
  • Figure 1 is a structural schematic diagram of a highly integrated heterogeneous packaging substrate 100 according to a first embodiment of the present invention.
  • the highly integrated heterogeneous packaging substrate 100 includes a glass substrate 1 , two heterogeneous layers 2 formed on opposite sides of the glass substrate 1 , and a metal column 3 penetrating the glass substrate 1 .
  • heterogeneous layers 2 There are two heterogeneous layers 2 , and the two heterogeneous layers 2 are respectively arranged on two opposite sides of the glass substrate 1 away from the heterogeneous layers 2 .
  • the heterogeneous layer 2 includes a dielectric material layer 21 attached to the glass substrate 1 and a metal wire 22 embedded in the dielectric material layer 21 .
  • the dielectric material layer 21 includes a plurality of dielectric layers stacked in sequence.
  • the metal wires 22 form metal wirings 5, passive devices 6 and a plurality of pads 7 for welding with pins of external chips and external wirings in the dielectric material layer 21.
  • the metal wiring 5 is formed in a plurality of the dielectric layers.
  • the metal wiring 5 includes N layers, where N is a positive integer and satisfies N ⁇ 2.
  • the metal wiring 5 in each of the heterogeneous layers 2 is electrically connected to the metal wiring 5 in another heterogeneous layer 2 through the metal pillar 3 .
  • the passive device 6 is formed in the plurality of dielectric layers.
  • the passive device 6 is made by integrating the metal wire 22 with the passive device 6 process, and the passive device 6 includes one or more of a capacitor 61, an inductor 62 and a resistor (not shown).
  • At least two of the capacitor 61, the inductor 62 and the resistor are connected in the dielectric material layer 21 to form a circuit function module 8, and the circuit function module 8 includes one or more of a radio frequency filter 81, an impedance matching circuit 82 and a power decoupling circuit (not shown).
  • the circuit function module 8 is relatively large and has a high procurement cost. It also needs to be welded during assembly, which is a relatively complex process and is prone to process risks in welding assembly. Therefore, the circuit function module 8 is provided in the highly integrated heterogeneous packaging substrate 100, which can greatly reduce the overall volume of the module product and avoid complex assembly processes, thereby improving the working reliability of the internal circuit of the highly integrated heterogeneous packaging substrate 100.
  • the size of the 01005 capacitor commonly used in the module is 0.4*0.2mm
  • the layout area of a capacitor on the substrate is 0.08mm2
  • the capacitance density that can be achieved in multiple dielectric layers is 600pF/mm2.
  • the layout area of the surface mount device (SMD device) on the substrate in the related art is 0.08mm2 , and it only takes 1/300mm2 to achieve it in the second embodiment.
  • the traditional SMD placement requires spacing requirements and cannot be very close, so multiple SMD devices are placed, and the layout area is larger, including the spacing; while the passive devices in the first embodiment can be as small as 10um, and the layout area is very compact. More preferably, the passive devices in the second embodiment can be placed below the external chip.
  • the high-integration heterogeneous packaging substrate 100 of the utility model has high integration and small volume.
  • the pad 7 is formed in the dielectric layer farthest from the glass substrate 1 and exposed from the dielectric layer.
  • the pad 7 is arranged on a side of the dielectric material layer 21 farthest from the glass substrate 1 and exposed from the dielectric material layer 21 .
  • the pad 7 and the passive device 6 are respectively arranged in the heterogeneous layer 2 on opposite sides of the glass substrate 1.
  • the pad 7 is used to solder the pins of the external chip, so after soldering the external chip, the passive device 6 and the external chip are respectively arranged on opposite sides of the glass substrate 1.
  • This arrangement makes the space utilization rate of the highly integrated heterogeneous packaging substrate 100 high, so that the overall product volume of the highly integrated heterogeneous packaging substrate 100 is small.
  • this structure can also dissipate the heat generated by the passive device 6 and the heat generated by the external chip through the two sides of the highly integrated heterogeneous packaging substrate 100, so that the heat generated by the external chip soldered to the pad 7 does not affect the operation of the passive device 6, thereby improving the reliability of the highly integrated heterogeneous packaging substrate 100.
  • the pins of the external chip are welded to the pads 7 by means of a wire bonding process or a flip chip packaging process.
  • the passive device 6 and the pad 7 are electrically connected via the metal wiring 5 .
  • the highly integrated heterogeneous packaging substrate 100 further includes a back metal wiring layer 4 disposed on the side of the heterogeneous layer 2 away from the glass substrate 1.
  • the back metal wiring layer 4 is conducive to increasing the wiring of the highly integrated heterogeneous packaging substrate 100, and the overall product volume is small.
  • the back metal wiring layer 4 is arranged on one side close to the heterogeneous layer 2 having the passive device 6.
  • the outer surface of the heterogeneous layer 2 having the passive device 6 is not provided with the pad 7, so the arrangement of the back metal wiring layer 4 on the outer surface of the heterogeneous layer 2 is conducive to the rational use of space, thereby facilitating the rational layout of the highly integrated heterogeneous packaging substrate 100 and the overall product volume is small.
  • the metal routing and the pad 7 can be arranged and wired through reasonable layout to achieve the effect of optimized design, thereby achieving a better reasonable layout of the highly integrated heterogeneous packaging substrate 100 and the overall product volume is small.
  • the two back metal wiring layers 4 are arranged on opposite sides of the highly integrated heterogeneous packaging substrate 100, it is also conducive to reducing the influence of electromagnetic interference of the highly integrated heterogeneous packaging substrate 100, so that the internal circuit of the highly integrated heterogeneous packaging substrate 100 has higher working reliability.
  • Embodiment 2 provides a module 200 , which further includes a chip 9 and the highly integrated heterogeneous packaging substrate 100 .
  • FIG. 2 is a schematic structural diagram of a module 200 according to a second embodiment of the present invention.
  • the chip 9 includes a plurality of chips.
  • the chip 9 includes a gallium arsenide chip 91 and a silicon-based chip 92.
  • the chip 9 is not limited thereto, and may also include a filter chip, such as a surface acoustic wave filter (SAW), a bulk acoustic wave filter (BAW), and a film bulk acoustic resonance filter (BAW).
  • SAW surface acoustic wave filter
  • BAW bulk acoustic wave filter
  • BAW film bulk acoustic resonance filter
  • the module 200 of the utility model integrates semiconductor devices of different materials into one package, so that the module 200 of the utility model has high integration, small size, good economy, high flexibility and better system performance.
  • the module 200 of the second embodiment can realize various implementations of the embodiment of the highly integrated heterogeneous packaging substrate 100 of the first embodiment, as well as the corresponding beneficial effects, which will not be described again here to avoid repetition.
  • the high-integration heterogeneous packaging substrate and module of the utility model are provided with a glass substrate and two heterogeneous layers on opposite sides of the glass substrate through the high-integration heterogeneous packaging substrate.
  • the heterogeneous layer is provided with metal wires so that the metal wires form metal wiring, passive devices and multiple pads in the heterogeneous layer.
  • the high-integration heterogeneous packaging substrate of the utility model adopts a glass substrate to replace the organic material substrate of the related art, and forms passive matching components such as capacitors, inductors, resistors, etc. inside the glass substrate, which saves more space. Among them, the passive devices and the pads are electrically connected through the metal wiring.
  • the high-integration heterogeneous packaging substrate can realize integrated capacitors, high-Q inductors and resistors through passive devices, and then electrically connected through metal wiring, so as to integrate the IPD filter in the dielectric material layer and realize the impedance matching circuit, RF filter and power supply decoupling circuit in the RF circuit, meet the miniaturized module design, and the device occupies a small substrate area, so that the high-integration heterogeneous packaging substrate and module of the utility model have high integration and small volume.
  • the soldering pad and the passive device are respectively arranged in the heterogeneous layer on opposite sides of the glass substrate. This structure ensures that the heat generated by the external chip soldered to the soldering pad does not affect the operation of the passive device, thereby making the highly integrated heterogeneous packaging substrate and module of the present invention highly reliable.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

A highly integrated heterogeneous package substrate (100) and a module (200). The highly integrated heterogeneous package substrate (100) comprises a glass base (1), two heterogeneous layers (2) formed on two opposite sides of the glass base (1), and a metal pillar (3). Each heterogeneous layer (2) comprises a dielectric material layer (21) attached to the glass base (1) and metal wires (22) embedded in the dielectric material layer (21). The metal wires (22) form, in the dielectric material layer (21), a metal wiring (5), a passive device (6), and a plurality of pads (7) used for being respectively welded to pins of an external chip (9) and external connecting wires. The metal wiring (5) comprises N layers, wherein N is a positive integer, and N ≥ 2. The metal wiring (5) in each heterogeneous layer (2) is connected to the metal wiring (5) in the other heterogeneous layer (2) by means of the metal pillar (3). The passive device (6) is made of the metal wires (22) by means of a passive device (6) integration process. The pads (7) are arranged on the side of the dielectric material layer (21) away from the glass base (1), and are exposed out of the dielectric material layer (21). The passive device (6) and the pads (7) are electrically connected by means of the metal wiring (5). Compared with the related art, this solution has high integration level, small size, and high reliability.

Description

高集成异构封装基板和模组Highly integrated heterogeneous packaging substrates and modules 技术领域Technical Field
本实用新型涉及封装技术领域，尤其涉及一种高集成异构封装基板和模组。The utility model relates to the technical field of packaging, and in particular to a highly integrated heterogeneous packaging substrate and module.
背景技术Background technique
目前，移动通信技术的发展，5G时代的到来，以手机为代表的无线终端射频芯片的复杂度和技术难度都大幅增加，相较于4G来说，需要支持更多的频段、进行更复杂的信号处理，载波频率、通信带宽和连接速度也都显著提高，射频前端在5G时代的重要性更加凸显，相应的对核心器件的产品构架、芯片材质和工艺都提出了更高的要求。其中，集成射频功率放大器、低噪声放大器、射频开关、滤波器等多种材质的射频器件的芯片是重要的核心器件。At present, with the development of mobile communication technology and the advent of the 5G era, the complexity and technical difficulty of wireless terminal RF chips represented by mobile phones have increased significantly. Compared with 4G, it is necessary to support more frequency bands and perform more complex signal processing. The carrier frequency, communication bandwidth and connection speed have also increased significantly. The importance of RF front-end in the 5G era is more prominent, and higher requirements are put forward for the product architecture, chip materials and processes of core components. Among them, chips that integrate RF power amplifiers, low-noise amplifiers, RF switches, filters and other RF devices of various materials are important core components.
相关技术的应用核心器件的产品将芯片、电容、电感、电阻等器件焊接在基板上形成。相关技术的基板一般为有机基基材基板。The products of the application core components of the related technology are formed by welding chips, capacitors, inductors, resistors and other components on a substrate. The substrate of the related technology is generally an organic base substrate.
然而，相关技术的有机基材基板无法实现电容和高Q的电感，更无法实现集成无源滤波器(Integrated Passive Device，IPD)的功能，集成无源滤波器即IPD滤波器通常为砷化镓基、高阻硅基、玻璃基中任意一种材料制成。因此需要在基板上预留表面贴装器件(Surface Mounted Devices，SMD)封装位置放置电容、电感、电阻以及IPD滤波器，因此成本较高，需要的占地面积也大，不利于目前日益小型化的模组设计。另外，有机基基材基板上焊接的芯片在工作时产生的热量，使得芯片周边的温度升高，芯片周边的电容、电感、电阻以及IPD滤波器在性能上受到上升温度的影响而性能变差，从而影响到器件和电路的可靠性。在较小的尺寸上集成多模多频的十几个甚至是几十个的射频器件，用于产生尺寸小、经济性好、灵活性高、***性能更佳的模组，而将不同材料的半导体器件集成到一个封装内是个需要解决技术问题。However, the organic substrate of the related art cannot realize the function of capacitors and high-Q inductors, let alone the function of integrated passive filters (IPDs). Integrated passive filters, i.e., IPD filters, are usually made of any one of the following materials: gallium arsenide-based, high-resistance silicon-based, and glass-based. Therefore, it is necessary to reserve surface mount device (SMD) packaging positions on the substrate to place capacitors, inductors, resistors, and IPD filters. Therefore, the cost is high and the required floor space is large, which is not conducive to the current increasingly miniaturized module design. In addition, the heat generated by the chip soldered on the organic substrate during operation causes the temperature around the chip to rise. The performance of the capacitors, inductors, resistors, and IPD filters around the chip is affected by the rising temperature and deteriorates, thereby affecting the reliability of the device and circuit. Integrating a dozen or even dozens of multi-mode and multi-frequency RF devices in a smaller size is used to produce a module with small size, good economy, high flexibility, and better system performance. Integrating semiconductor devices of different materials into one package is a technical problem that needs to be solved.
因此，实有必要提供一种基板和模组解决上述问题。 Therefore, it is necessary to provide a substrate and a module to solve the above problems.
实用新型内容Utility Model Content
针对以上现有技术的不足，本实用新型提出一种集成度高、体积小且可靠性高的高集成异构封装基板和模组。In view of the above deficiencies in the prior art, the utility model proposes a highly integrated heterogeneous packaging substrate and module with high integration, small size and high reliability.
为了解决上述技术问题，第一方面，本实用新型实施例提供了一种高集成异构封装基板，所述高集成异构封装基板包括玻璃衬底、形成于所述玻璃衬底相对两侧的两个异构层以及贯穿所述玻璃衬底的金属柱；所述异构层包括贴合于所述玻璃衬底的介电材料层和嵌设于所述介电材料层的金属线，所述金属线在所述介电材料层内形成金属布线、无源器件以及用于分别与外部芯片的管脚和外部连线焊接的多个焊盘；所述金属布线包括N层，N为正整数且满足，N≥2，每一个所述异构层中的所述金属布线通过所述金属柱与另一个的所述异构层中的所述金属布线连接；所述无源器件为所述金属线通过集成无源器件工艺制成，所述无源器件包括电容、电感以及电阻中的一种或多种；所述焊盘设置于所述介电材料层远离所述玻璃衬底的一侧并外露于所述介电材料层；所述无源器件和焊盘通过所述金属布线电连接。In order to solve the above technical problems, in a first aspect, an embodiment of the utility model provides a highly integrated heterogeneous packaging substrate, the highly integrated heterogeneous packaging substrate comprising a glass substrate, two heterogeneous layers formed on opposite sides of the glass substrate, and a metal column penetrating the glass substrate; the heterogeneous layer comprises a dielectric material layer attached to the glass substrate and a metal wire embedded in the dielectric material layer, the metal wire forms metal wiring, passive devices and a plurality of pads for welding with pins of an external chip and external wiring respectively in the dielectric material layer; the metal wiring comprises N layers, N is a positive integer and satisfies, N≥2, the metal wiring in each of the heterogeneous layers is connected to the metal wiring in another heterogeneous layer through the metal column; the passive device is made by the metal wire through an integrated passive device process, and the passive device comprises one or more of a capacitor, an inductor and a resistor; the pad is arranged on a side of the dielectric material layer away from the glass substrate and exposed to the dielectric material layer; the passive device and the pad are electrically connected through the metal wiring.
优选的，所述焊盘与所述无源器件分别设置于所述玻璃衬底的相对两侧的所述异构层中。Preferably, the pads and the passive components are respectively arranged in the heterogeneous layers on opposite sides of the glass substrate.
优选的，所述高集成异构封装基板还包括设置于所述异构层远离所述玻璃衬底一侧的背面金属布线层。Preferably, the highly integrated heterogeneous packaging substrate further comprises a back metal wiring layer arranged on a side of the heterogeneous layer away from the glass substrate.
优选的，所述电容、所述电感以及所述电阻中的至少两种在所述介电材料层内连接形成电路功能模块，所述电路功能模块包括射频滤波器、阻抗匹配电路以及电源去耦电路的一种或多种。Preferably, at least two of the capacitor, the inductor and the resistor are connected within the dielectric material layer to form a circuit function module, and the circuit function module includes one or more of a radio frequency filter, an impedance matching circuit and a power decoupling circuit.
优选的，所述介电材料层包括依次叠设的多个介电层；所述金属布线和所述无源器件在多个所述介电层中形成；所述焊盘形成于最远离所述玻璃衬底的一个所述介电层中并外露于所述介电层。Preferably, the dielectric material layer comprises a plurality of dielectric layers stacked in sequence; the metal wiring and the passive device are formed in the plurality of dielectric layers; and the pad is formed in one of the dielectric layers farthest from the glass substrate and exposed on the dielectric layer.
第二方面，本实用新型实施例还提供了一种模组，其包括芯片和如本实用新型实施例提供的上述高集成异构封装基板，所述芯片的管脚与所述焊盘焊接连接。In a second aspect, an embodiment of the present invention further provides a module, which includes a chip and the above-mentioned highly integrated heterogeneous packaging substrate provided in an embodiment of the present invention, wherein the pins of the chip are welded and connected to the pads.
与相关技术相比，本实用新型的高集成异构封装基板和模组通 过高集成异构封装基板设置玻璃衬底和玻璃衬底相对两侧的两个异构层，异构层通过设置金属线，使得金属线在异构层内形成金属布线、无源器件以及多个焊盘。本实用新型的高集成异构封装基板采用玻璃衬底取代相关技术的机材料衬底，并将电容、电感、电阻等无源匹配元件在玻璃衬底内部形成，更省空间。其中，无源器件和焊盘通过所述金属布线电连接。因此，高集成异构封装基板可以通过无源器件实现集成电容、高Q的电感和电阻，再通过金属布线电连接，从而在所述介电材料层内集成IPD滤波器和实现射频电路里面的阻抗匹配电路、射频滤波器和电源去耦电路，满足小型化的模组设计，器件占用基板面积小，从而使得本实用新型的高集成异构封装基板和模组的集成度高且体积小。更优的，所述焊盘与所述无源器件分别设置于所述玻璃衬底的相对两侧的所述异构层中，该结构使得与焊盘焊接的外部芯片产生的热量不影响到所述无源器件的工作，从而使得本实用新型的高集成异构封装基板和模组的可靠性高。Compared with the related art, the highly integrated heterogeneous packaging substrate and module of the utility model are The highly integrated heterogeneous packaging substrate is provided with a glass substrate and two heterogeneous layers on opposite sides of the glass substrate. The heterogeneous layers are provided with metal wires so that the metal wires form metal wiring, passive devices and multiple pads in the heterogeneous layers. The highly integrated heterogeneous packaging substrate of the utility model adopts a glass substrate to replace the organic material substrate of the related technology, and forms passive matching components such as capacitors, inductors, resistors, etc. inside the glass substrate, which saves more space. Among them, the passive devices and the pads are electrically connected through the metal wiring. Therefore, the highly integrated heterogeneous packaging substrate can realize integrated capacitors, high-Q inductors and resistors through passive devices, and then electrically connected through metal wiring, so as to integrate the IPD filter in the dielectric material layer and realize the impedance matching circuit, RF filter and power supply decoupling circuit in the RF circuit, meet the miniaturized module design, and the device occupies a small substrate area, so that the highly integrated heterogeneous packaging substrate and module of the utility model have high integration and small volume. More preferably, the soldering pad and the passive device are respectively arranged in the heterogeneous layer on opposite sides of the glass substrate. This structure ensures that the heat generated by the external chip soldered to the soldering pad does not affect the operation of the passive device, thereby making the highly integrated heterogeneous packaging substrate and module of the present invention highly reliable.
附图说明BRIEF DESCRIPTION OF THE DRAWINGS
下面结合附图详细说明本实用新型。通过结合以下附图所作的详细描述，本实用新型的上述或其他方面的内容将变得更清楚和更容易理解。附图中：The present invention will be described in detail below in conjunction with the accompanying drawings. The above and other aspects of the present invention will become clearer and easier to understand through the detailed description made in conjunction with the following drawings. In the accompanying drawings:
图1为本实用新型实施例一的高集成异构封装基板的结构示意图；FIG1 is a schematic structural diagram of a highly integrated heterogeneous packaging substrate according to a first embodiment of the present invention;
图2为本实用新型实施例二的模组的结构示意图。FIG. 2 is a schematic diagram of the structure of a module according to a second embodiment of the present invention.
具体实施方式Detailed ways
下面结合附图详细说明本实用新型的具体实施方式。The specific implementation of the utility model is described in detail below with reference to the accompanying drawings.
在此记载的具体实施方式/实施例为本实用新型的特定的具体实施方式，用于说明本实用新型的构思，均是解释性和示例性的，不应解释为对本实用新型实施方式及本实用新型范围的限制。除在此记载的实施例外，本领域技术人员还能够基于本申请权利要求书 和说明书所公开的内容采用显而易见的其它技术方案，这些技术方案包括采用对在此记载的实施例的做出任何显而易见的替换和修改的技术方案，都在本实用新型的保护范围之内。The specific implementation methods/examples described herein are specific implementation methods of the present invention, which are used to illustrate the concept of the present invention. They are all explanatory and exemplary and should not be interpreted as limiting the implementation methods and scope of the present invention. In addition to the examples described herein, those skilled in the art can also make their own inventions based on the claims of this application. Other obvious technical solutions adopted in accordance with the contents disclosed in the specification, including any obvious replacement and modification of the embodiments described herein, are within the protection scope of the present utility model.
(实施例一)(Example 1)
本实用新型还提供一种高集成异构封装基板100。请参考图1所示，图1为本实用新型实施例一的高集成异构封装基板100的结构示意图。The present invention also provides a highly integrated heterogeneous packaging substrate 100. Please refer to Figure 1, which is a structural schematic diagram of a highly integrated heterogeneous packaging substrate 100 according to a first embodiment of the present invention.
所述高集成异构封装基板100包括玻璃衬底1、形成于所述玻璃衬底1相对两侧的两个异构层2以及贯穿所述玻璃衬底1的金属柱3。The highly integrated heterogeneous packaging substrate 100 includes a glass substrate 1 , two heterogeneous layers 2 formed on opposite sides of the glass substrate 1 , and a metal column 3 penetrating the glass substrate 1 .
所述异构层2为两个，两个所述异构层2分别设置于所述玻璃衬底1远离所述异构层2的相对两侧。There are two heterogeneous layers 2 , and the two heterogeneous layers 2 are respectively arranged on two opposite sides of the glass substrate 1 away from the heterogeneous layers 2 .
所述异构层2包括贴合于所述玻璃衬底1的介电材料层21和嵌设于所述介电材料层21的金属线22。The heterogeneous layer 2 includes a dielectric material layer 21 attached to the glass substrate 1 and a metal wire 22 embedded in the dielectric material layer 21 .
所述介电材料层21包括依次叠设的多个介电层。The dielectric material layer 21 includes a plurality of dielectric layers stacked in sequence.
所述金属线22在所述介电材料层21内形成金属布线5、无源器件6以及用于分别与外部芯片的管脚和外部连线焊接的多个焊盘7。The metal wires 22 form metal wirings 5, passive devices 6 and a plurality of pads 7 for welding with pins of external chips and external wirings in the dielectric material layer 21.
所述金属布线5在多个所述介电层中形成。所述金属布线5包括N层，N为正整数且满足，N≥2。每一个所述异构层2中的所述金属布线5通过所述金属柱3与另一个的所述异构层2中的所述金属布线5电连接。The metal wiring 5 is formed in a plurality of the dielectric layers. The metal wiring 5 includes N layers, where N is a positive integer and satisfies N≥2. The metal wiring 5 in each of the heterogeneous layers 2 is electrically connected to the metal wiring 5 in another heterogeneous layer 2 through the metal pillar 3 .
所述无源器件6在多个所述介电层中形成。所述无源器件6为所述金属线22通过集成无源器件6工艺制成，所述无源器件6包括电容61、电感62以及电阻(图未示)中的一种或多种。The passive device 6 is formed in the plurality of dielectric layers. The passive device 6 is made by integrating the metal wire 22 with the passive device 6 process, and the passive device 6 includes one or more of a capacitor 61, an inductor 62 and a resistor (not shown).
所述电容61、所述电感62以及所述电阻中的至少两种在所述介电材料层21内连接形成电路功能模块8，所述电路功能模块8包括射频滤波器81、阻抗匹配电路82以及电源去耦电路(图未示)的一种或多种。相对于所述电路功能模块8，射频滤波器81、阻抗匹配电路82以及电源去耦电路在相关技术中焊接在基板上的面积 较大，而且采购成本较高，还需要在组装是进行焊接，工艺较为复杂，还容易出现焊接组装方面的工艺风险。因此，所述高集成异构封装基板100中设置所述电路功能模块8可以大大减少模组产品的整体体积，免去复杂的组装工艺，从而提高了所述高集成异构封装基板100的内部电路工作可靠性。At least two of the capacitor 61, the inductor 62 and the resistor are connected in the dielectric material layer 21 to form a circuit function module 8, and the circuit function module 8 includes one or more of a radio frequency filter 81, an impedance matching circuit 82 and a power decoupling circuit (not shown). Compared with the circuit function module 8, the area of the radio frequency filter 81, the impedance matching circuit 82 and the power decoupling circuit soldered on the substrate in the related art is The circuit function module 8 is relatively large and has a high procurement cost. It also needs to be welded during assembly, which is a relatively complex process and is prone to process risks in welding assembly. Therefore, the circuit function module 8 is provided in the highly integrated heterogeneous packaging substrate 100, which can greatly reduce the overall volume of the module product and avoid complex assembly processes, thereby improving the working reliability of the internal circuit of the highly integrated heterogeneous packaging substrate 100.
相对于相关技术中焊接在基板上的无源器件不论是电容还是电感电阻，其尺寸都是固定的。比如模组中常用的01005电容，其尺寸是0.4*0.2mm,一个电容在基板上的版图面积为0.08mm2，而多个所述介电层中可以实现的电容密度是600pF/mm2。如果我们要实现一个常用电容值，比如2pF,相关技术中的表面贴装器件(SMD器件)在基板上的版图面积为0.08mm2,在本实施例二中实现只要1/300mm2。传统的SMD摆放要求有间距的要求，并不能靠的很近，因此多个SMD器件摆放，算上间距，版图面积更大；而本实施例一中的无源器件，间距可以小到10um,版图面积非常紧凑。更优的是，本实施例二中的无源器件可以放置在所述外部芯片的下方。从而使得本实用新型的高集成异构封装基板100的集成度高且体积小。Compared with the passive devices soldered on the substrate in the related art, whether it is a capacitor or an inductor resistor, its size is fixed. For example, the size of the 01005 capacitor commonly used in the module is 0.4*0.2mm, and the layout area of a capacitor on the substrate is 0.08mm2 , while the capacitance density that can be achieved in multiple dielectric layers is 600pF/mm2. If we want to achieve a common capacitance value, such as 2pF, the layout area of the surface mount device (SMD device) on the substrate in the related art is 0.08mm2 , and it only takes 1/300mm2 to achieve it in the second embodiment. The traditional SMD placement requires spacing requirements and cannot be very close, so multiple SMD devices are placed, and the layout area is larger, including the spacing; while the passive devices in the first embodiment can be as small as 10um, and the layout area is very compact. More preferably, the passive devices in the second embodiment can be placed below the external chip. Thereby, the high-integration heterogeneous packaging substrate 100 of the utility model has high integration and small volume.
所述焊盘7形成于最远离所述玻璃衬底1的一个所述介电层中并外露于所述介电层。所述焊盘7设置于所述介电材料层21远离所述玻璃衬底1的一侧并外露于所述介电材料层21。The pad 7 is formed in the dielectric layer farthest from the glass substrate 1 and exposed from the dielectric layer. The pad 7 is arranged on a side of the dielectric material layer 21 farthest from the glass substrate 1 and exposed from the dielectric material layer 21 .
本实施例二中，所述焊盘7与所述无源器件6分别设置于所述玻璃衬底1的相对两侧的所述异构层2中。所述焊盘7用于焊接外部芯片的管脚，因此焊接外部芯片后，所述无源器件6和外部芯片分别设置于所述玻璃衬底1的相对两侧，该设置使得所述高集成异构封装基板100的空间利用率高，从而使得所述高集成异构封装基板100的整体产品体积小，更优的，该结构还可以将所述无源器件6产生的热量和外部芯片产生的热量分别通过所述高集成异构封装基板100的两侧进行散热，使得与焊盘7焊接的外部芯片产生的热量不影响到所述无源器件6的工作，从而提高了使得所述高集成异构封装基板100的可靠性。 In the second embodiment, the pad 7 and the passive device 6 are respectively arranged in the heterogeneous layer 2 on opposite sides of the glass substrate 1. The pad 7 is used to solder the pins of the external chip, so after soldering the external chip, the passive device 6 and the external chip are respectively arranged on opposite sides of the glass substrate 1. This arrangement makes the space utilization rate of the highly integrated heterogeneous packaging substrate 100 high, so that the overall product volume of the highly integrated heterogeneous packaging substrate 100 is small. More preferably, this structure can also dissipate the heat generated by the passive device 6 and the heat generated by the external chip through the two sides of the highly integrated heterogeneous packaging substrate 100, so that the heat generated by the external chip soldered to the pad 7 does not affect the operation of the passive device 6, thereby improving the reliability of the highly integrated heterogeneous packaging substrate 100.
所述外部芯片的管脚与所述焊盘7通过焊线工艺或倒晶封装工艺焊接。The pins of the external chip are welded to the pads 7 by means of a wire bonding process or a flip chip packaging process.
所述无源器件6和焊盘7通过所述金属布线5电连接。The passive device 6 and the pad 7 are electrically connected via the metal wiring 5 .
为了更进一步减少产品的体积，本实施例二中，所述高集成异构封装基板100还包括设置于所述异构层2远离所述玻璃衬底1一侧的背面金属布线层4。所述背面金属布线层4有利于增加所述高集成异构封装基板100的布线，整体产品体积小。In order to further reduce the volume of the product, in the second embodiment, the highly integrated heterogeneous packaging substrate 100 further includes a back metal wiring layer 4 disposed on the side of the heterogeneous layer 2 away from the glass substrate 1. The back metal wiring layer 4 is conducive to increasing the wiring of the highly integrated heterogeneous packaging substrate 100, and the overall product volume is small.
本实施方式中，所述背面金属布线层4为一个，所述背面金属布线层4设置于靠近具有所述无源器件6的一个所述异构层2的一侧。具有所述无源器件6的一个所述异构层2的外表面并未设置所述焊盘7，因此在该异构层2的外表面设置一个所述背面金属布线层4有利于合理利用空间，从而有利于所述高集成异构封装基板100的合理布局且整体产品体积小。当然，不限于此，在另一个实施例中，所述背面金属布线层电4为两个，其中一个所述背面金属布线层4布线设计时，可以让金属走线与所述焊盘7通过合理布局布线，达到优化设计的效果，从而实现了更好有利于所述高集成异构封装基板100的合理布局且整体产品体积小，另外，由于两个所述背面金属布线层4均设置于所述高集成异构封装基板100的相对两侧，还有利于减少所述高集成异构封装基板100的电磁干扰的影响，使得所述高集成异构封装基板100的内部电路工作可靠性更高。In this embodiment, there is one back metal wiring layer 4, and the back metal wiring layer 4 is arranged on one side close to the heterogeneous layer 2 having the passive device 6. The outer surface of the heterogeneous layer 2 having the passive device 6 is not provided with the pad 7, so the arrangement of the back metal wiring layer 4 on the outer surface of the heterogeneous layer 2 is conducive to the rational use of space, thereby facilitating the rational layout of the highly integrated heterogeneous packaging substrate 100 and the overall product volume is small. Of course, not limited to this, in another embodiment, there are two back metal wiring layers 4, and when designing the wiring of one of the back metal wiring layers 4, the metal routing and the pad 7 can be arranged and wired through reasonable layout to achieve the effect of optimized design, thereby achieving a better reasonable layout of the highly integrated heterogeneous packaging substrate 100 and the overall product volume is small. In addition, since the two back metal wiring layers 4 are arranged on opposite sides of the highly integrated heterogeneous packaging substrate 100, it is also conducive to reducing the influence of electromagnetic interference of the highly integrated heterogeneous packaging substrate 100, so that the internal circuit of the highly integrated heterogeneous packaging substrate 100 has higher working reliability.
(实施例二)(Example 2)
实施例二提供一种模组200，所述模组还包括芯片9和所述高集成异构封装基板100。Embodiment 2 provides a module 200 , which further includes a chip 9 and the highly integrated heterogeneous packaging substrate 100 .
请参考图2所示，图2为本实用新型实施例二的模组200的结构示意图。Please refer to FIG. 2 , which is a schematic structural diagram of a module 200 according to a second embodiment of the present invention.
其中，芯片9包括多个。本实施例二中，芯片9包括砷化镓芯片91和硅基芯片92。当然，不限于此，芯片9还可以包括滤波器芯片，例如声表面波滤波器(Saw Filter,简称SAW)、体声波滤波器(Baw-SMR Filter,简称BAW)以及薄膜腔声谐振滤波器(film bulk  acoustic resonator,简称FBAR)。本实用新型的模组200将不同材料的半导体器件集成到一个封装内，从而使得本实用新型的模组200的集成度高、尺寸小、经济性好、灵活性高、***性能更佳。The chip 9 includes a plurality of chips. In the second embodiment, the chip 9 includes a gallium arsenide chip 91 and a silicon-based chip 92. Of course, the chip 9 is not limited thereto, and may also include a filter chip, such as a surface acoustic wave filter (SAW), a bulk acoustic wave filter (BAW), and a film bulk acoustic resonance filter (BAW). The module 200 of the utility model integrates semiconductor devices of different materials into one package, so that the module 200 of the utility model has high integration, small size, good economy, high flexibility and better system performance.
本实施例二的模组200能够实现实施例一的高集成异构封装基板100的实施例中的各个实施方式，以及相应有益效果，为避免重复，这里不再赘述。The module 200 of the second embodiment can realize various implementations of the embodiment of the highly integrated heterogeneous packaging substrate 100 of the first embodiment, as well as the corresponding beneficial effects, which will not be described again here to avoid repetition.
需要指出的是，本实用新型采用的相关玻璃衬底、介电材料层以及金属线均为本领域常用的材料，具有指标和参数根据实际应用进行调整，在此，不作详细赘述。It should be pointed out that the relevant glass substrate, dielectric material layer and metal wire used in the present invention are all commonly used materials in the field, and their indicators and parameters are adjusted according to actual applications, which will not be described in detail here.
与相关技术相比，本实用新型的高集成异构封装基板和模组通过高集成异构封装基板设置玻璃衬底和玻璃衬底相对两侧的两个异构层，异构层通过设置金属线，使得金属线在异构层内形成金属布线、无源器件以及多个焊盘。本实用新型的高集成异构封装基板采用玻璃衬底取代相关技术的机材料衬底，并将电容、电感、电阻等无源匹配元件在玻璃衬底内部形成，更省空间。其中，无源器件和焊盘通过所述金属布线电连接。因此，高集成异构封装基板可以通过无源器件实现集成电容、高Q的电感和电阻，再通过金属布线电连接，从而在所述介电材料层内集成IPD滤波器和实现射频电路里面的阻抗匹配电路、射频滤波器和电源去耦电路，满足小型化的模组设计，器件占用基板面积小，从而使得本实用新型的高集成异构封装基板和模组的集成度高且体积小。更优的，所述焊盘与所述无源器件分别设置于所述玻璃衬底的相对两侧的所述异构层中，该结构使得与焊盘焊接的外部芯片产生的热量不影响到所述无源器件的工作，从而使得本实用新型的高集成异构封装基板和模组的可靠性高。Compared with the related art, the high-integration heterogeneous packaging substrate and module of the utility model are provided with a glass substrate and two heterogeneous layers on opposite sides of the glass substrate through the high-integration heterogeneous packaging substrate. The heterogeneous layer is provided with metal wires so that the metal wires form metal wiring, passive devices and multiple pads in the heterogeneous layer. The high-integration heterogeneous packaging substrate of the utility model adopts a glass substrate to replace the organic material substrate of the related art, and forms passive matching components such as capacitors, inductors, resistors, etc. inside the glass substrate, which saves more space. Among them, the passive devices and the pads are electrically connected through the metal wiring. Therefore, the high-integration heterogeneous packaging substrate can realize integrated capacitors, high-Q inductors and resistors through passive devices, and then electrically connected through metal wiring, so as to integrate the IPD filter in the dielectric material layer and realize the impedance matching circuit, RF filter and power supply decoupling circuit in the RF circuit, meet the miniaturized module design, and the device occupies a small substrate area, so that the high-integration heterogeneous packaging substrate and module of the utility model have high integration and small volume. More preferably, the soldering pad and the passive device are respectively arranged in the heterogeneous layer on opposite sides of the glass substrate. This structure ensures that the heat generated by the external chip soldered to the soldering pad does not affect the operation of the passive device, thereby making the highly integrated heterogeneous packaging substrate and module of the present invention highly reliable.
需要说明的是，以上参照附图所描述的各个实施例仅用以说明本实用新型而非限制本实用新型的范围，本领域的普通技术人员应当理解，在不脱离本实用新型的精神和范围的前提下对本实用新型进行的修改或者等同替换，均应涵盖在本实用新型的范围之内。此外，除上下文另有所指外，以单数形式出现的词包括复数形式，反 之亦然。另外，除非特别说明，那么任何实施例的全部或一部分可结合任何其它实施例的全部或一部分来使用。 It should be noted that the various embodiments described above with reference to the accompanying drawings are only used to illustrate the present invention rather than to limit the scope of the present invention. Those skilled in the art should understand that any modification or equivalent replacement of the present invention without departing from the spirit and scope of the present invention should be included in the scope of the present invention. In addition, unless the context otherwise requires, words appearing in the singular include the plural form, and the reverse is true. Additionally, unless otherwise stated, all or a portion of any embodiment may be used in combination with all or a portion of any other embodiment.

Claims (6)

  1. 一种高集成异构封装基板，其特征在于，A highly integrated heterogeneous packaging substrate, characterized in that:
    所述高集成异构封装基板包括玻璃衬底、形成于所述玻璃衬底相对两侧的两个异构层以及贯穿所述玻璃衬底的金属柱；The highly integrated heterogeneous packaging substrate comprises a glass substrate, two heterogeneous layers formed on opposite sides of the glass substrate, and a metal column penetrating the glass substrate;
    所述异构层包括贴合于所述玻璃衬底的介电材料层和嵌设于所述介电材料层的金属线，所述金属线在所述介电材料层内形成金属布线、无源器件以及用于分别与外部芯片的管脚和外部连线焊接的多个焊盘；The heterogeneous layer includes a dielectric material layer attached to the glass substrate and metal wires embedded in the dielectric material layer, wherein the metal wires form metal wiring, passive devices and a plurality of pads for welding with pins of external chips and external wirings in the dielectric material layer;
    所述金属布线包括N层，N为正整数且满足，N≥2，每一个所述异构层中的所述金属布线通过所述金属柱与另一个的所述异构层中的所述金属布线连接；The metal wiring includes N layers, N is a positive integer and satisfies N≥2, and the metal wiring in each of the heterogeneous layers is connected to the metal wiring in another heterogeneous layer through the metal pillar;
    所述无源器件为所述金属线通过集成无源器件工艺制成，所述无源器件包括电容、电感以及电阻中的一种或多种；The passive device is made by the metal wire through an integrated passive device process, and the passive device includes one or more of a capacitor, an inductor and a resistor;
    所述焊盘设置于所述介电材料层远离所述玻璃衬底的一侧并外露于所述介电材料层；The pad is disposed on a side of the dielectric material layer away from the glass substrate and exposed on the dielectric material layer;
    所述无源器件和焊盘通过所述金属布线电连接。The passive device and the pad are electrically connected through the metal wiring.
  2. 根据权利要求1所述的高集成异构封装基板，其特征在于，所述焊盘与所述无源器件分别设置于所述玻璃衬底的相对两侧的所述异构层中。The highly integrated heterogeneous packaging substrate according to claim 1 is characterized in that the pads and the passive devices are respectively arranged in the heterogeneous layers on opposite sides of the glass substrate.
  3. 根据权利要求2所述的高集成异构封装基板，其特征在于，所述高集成异构封装基板还包括设置于所述异构层远离所述玻璃衬底一侧的背面金属布线层。The highly integrated heterogeneous packaging substrate according to claim 2 is characterized in that the highly integrated heterogeneous packaging substrate also includes a back metal wiring layer arranged on a side of the heterogeneous layer away from the glass substrate.
  4. 根据权利要求1所述的高集成异构封装基板，其特征在于，所述电容、所述电感以及所述电阻中的至少两种在所述介电材料层内连接形成电路功能模块，所述电路功能模块包括射频滤波器、阻抗匹配电路以及电源去耦电路的一种或多种。The highly integrated heterogeneous packaging substrate according to claim 1 is characterized in that at least two of the capacitor, the inductor and the resistor are connected in the dielectric material layer to form a circuit function module, and the circuit function module includes one or more of a radio frequency filter, an impedance matching circuit and a power decoupling circuit.
  5. 根据权利要求1所述的高集成异构封装基板，其特征在于，所述介电材料层包括依次叠设的多个介电层；所述金属布线和所述无源器件在多个所述介电层中形成；所述焊盘形成于最远离所述玻璃衬底的一个所述介电层中并外露于所述介电层。 According to claim 1, the highly integrated heterogeneous packaging substrate is characterized in that the dielectric material layer includes a plurality of dielectric layers stacked in sequence; the metal wiring and the passive device are formed in the plurality of dielectric layers; the pad is formed in one of the dielectric layers farthest from the glass substrate and exposed on the dielectric layer.
  6. 一种模组，其包括芯片，其特征在于，所述模组还包括1如权利要求1至5中任意一项的所述的高集成异构封装基板，所述芯片的管脚与所述焊盘焊接连接。 A module, comprising a chip, characterized in that the module also comprises a highly integrated heterogeneous packaging substrate as described in any one of claims 1 to 5, and the pins of the chip are welded and connected to the pads.
PCT/CN2023/126189 2022-11-30 2023-10-24 Highly integrated heterogeneous package substrate and module WO2024114182A1 (en)

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