CN112234143A - On-chip integrated IPD packaging structure, packaging method thereof and three-dimensional packaging structure - Google Patents
On-chip integrated IPD packaging structure, packaging method thereof and three-dimensional packaging structure Download PDFInfo
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- CN112234143A CN112234143A CN202011462259.XA CN202011462259A CN112234143A CN 112234143 A CN112234143 A CN 112234143A CN 202011462259 A CN202011462259 A CN 202011462259A CN 112234143 A CN112234143 A CN 112234143A
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- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
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- H—ELECTRICITY
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Abstract
The invention discloses an on-chip integrated IPD packaging structure, a packaging method thereof and a three-dimensional packaging structure, wherein the on-chip integrated IPD packaging structure comprises a silicon substrate layer, a first metal wiring layer, a dielectric layer, a second metal wiring layer and a chip, wherein the first metal wiring layer is arranged on the upper surface and the lower surface of the silicon substrate layer and is communicated through a silicon through hole penetrating through the silicon substrate layer, the dielectric layer is arranged on the surface of the first metal wiring layer positioned on the upper surface of the silicon substrate layer, the second metal wiring layer is arranged on the surface of the first dielectric layer and is sequentially laminated with the dielectric layer and the first metal wiring layer to form the on. According to the invention, the silicon substrate is used as an integrated packaging substrate, passive components are integrated on the substrate, and the component manufacturing and the system integration are completed under the same process flow by adopting an integration mode of packaging substrate integrated manufacturing, so that the components do not need to be processed and manufactured separately, the processing integration is simple, the 3D integration is easy to realize, the advantages of high precision and good consistency are realized, the circuit area is saved, and the design is more flexible.
Description
Technical Field
The invention relates to the technical field of IPD (integrated passive device), in particular to an on-chip integrated IPD packaging structure, a packaging method thereof and a three-dimensional packaging structure.
Background
The radio frequency system mainly comprises an amplification chip, a control chip and a passive component, and the miniaturization and integration of the passive component are concerned. In the whole circuit, passive devices such as inductors, capacitors and filters account for more than 50% of the volume of the system, and the high-density integration and miniaturization technology of the passive elements becomes a core problem. At present passive components and parts are the separator mostly, adopt the mode integration of welding or bonding on the pcb board, need very big area be used for welding and through-hole, or adopt passive components such as integrated inductance, electric capacity on the LTCC base plate, but LTCC belongs to the thick film technology, and the minimum line width of present lines is about 80mm, line precision 10mm, and the size is big, and the precision is poor.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides an IPD (integrated product package) packaging structure on a chip, a packaging method thereof and a three-dimensional packaging structure.
In order to achieve the purpose of the invention, the invention adopts the technical scheme that:
in a first aspect, the present invention provides an integrated IPD package structure on a chip, including:
a silicon substrate layer;
the first metal wiring layer is arranged on the upper surface and the lower surface of the silicon substrate layer and is communicated with the silicon substrate layer through a silicon through hole penetrating through the silicon substrate layer;
the dielectric layer is arranged on the surface of the first metal wiring layer positioned on the upper surface of the silicon substrate layer;
the second metal wiring layer is arranged on the surface of the dielectric layer and is sequentially laminated with the dielectric layer and the first metal wiring layer to form an on-chip integrated IPD; and
a chip integrated on the silicon substrate layer.
Furthermore, the first metal wiring layer specifically comprises a continuous thickened metal layer manufactured on the upper surface and the lower surface of the silicon substrate layer by adopting a double-sided electroplating patterning process, and a metalized through hole manufactured on the inner wall of the silicon through hole.
Furthermore, the continuous graphic thickened metal layer made on the upper surface of the silicon substrate layer by the first metal wiring layer comprises a lower electrode of an on-chip integrated inductor and an on-chip integrated capacitor.
Furthermore, the first metal wiring layer is provided with a micro-bump structure connected with other substrates on the metal layer manufactured on the lower surface of the silicon substrate layer.
Further, an on-chip integrated resistor is manufactured on the silicon substrate layer by adopting a sputtering process.
Furthermore, the dielectric layer is laid on the surface of the first metal wiring layer on the upper surface of the silicon substrate layer by adopting a physical vapor deposition Parylene process, and a passivation layer is carried out on the lower electrode of the on-chip integrated capacitor to manufacture the capacitor dielectric material.
Furthermore, the second metal wiring layer adopts a double-sided electroplating patterning process to manufacture a continuously thickened metal layer on the surface of the dielectric layer, wherein the continuously thickened metal layer comprises an upper electrode of an on-chip integrated inductor and an upper electrode of an on-chip integrated capacitor.
Further, the chip is integrated on the silicon substrate layer in an on-chip integration or heterogeneous integration mode.
In a second aspect, the present invention further provides a packaging method for an integrated IPD package structure on a chip, including the following steps:
s1, manufacturing an on-chip integrated resistor on a silicon substrate layer by adopting a sputtering process;
s2, manufacturing a through silicon via on the silicon substrate layer by adopting a DRIE etching process;
s3, seed layers are sputtered on the upper surface and the lower surface of the silicon substrate layer, photoresist masks are manufactured, continuous thickened metal layers are manufactured on the upper surface and the lower surface of the silicon substrate layer by adopting a double-sided electroplating patterning process, metallized through holes are manufactured on the inner wall of each silicon through hole, and a first metal wiring layer which comprises a lower electrode of an on-chip integrated inductor and an on-chip integrated capacitor is formed after the photoresist and the seed layers are removed;
s4, manufacturing a dielectric layer on the surface of the first metal wiring layer on the upper surface of the silicon substrate layer by adopting a physical vapor deposition Parylene process;
s5, sputtering a seed layer on the surface of the dielectric layer and manufacturing a photoresist mask, manufacturing a continuous thickened metal layer on the surface of the dielectric layer by adopting a double-sided electroplating patterning process, and removing the photoresist and the seed layer to form a second metal wiring layer comprising an upper electrode of the on-chip integrated inductor and the on-chip integrated capacitor; the second metal wiring layer, the dielectric layer and the first metal wiring layer are sequentially stacked to form an on-chip integrated IPD;
and S6, integrating the chip on the silicon substrate layer by adopting an on-chip integration or heterogeneous integration mode.
In a third aspect, the present invention further provides an integrated IPD three-dimensional package structure on a chip, including:
the integrated IPD packaging structures are sequentially stacked up and down and are interconnected through a micro-bump structure;
the integrated IPD packaging structure on the chip specifically comprises:
a silicon substrate layer;
the first metal wiring layer is arranged on the upper surface and the lower surface of the silicon substrate layer and is communicated with the silicon substrate layer through a silicon through hole penetrating through the silicon substrate layer;
the dielectric layer is arranged on the surface of the first metal wiring layer positioned on the upper surface of the silicon substrate layer;
the second metal wiring layer is arranged on the surface of the dielectric layer and is sequentially laminated with the dielectric layer and the first metal wiring layer to form an on-chip integrated IPD; and
a chip integrated on the silicon substrate layer.
The invention has the following beneficial effects:
(1) the IPD process integrated on the silicon substrate is basically the same as the substrate process, is particularly suitable for connecting a complex multilayer wiring structure, does not need to add an additional process link, and the silicon substrate is a mainstream 3D integrated material, so that the silicon substrate can be integrated on a chip, has good compatibility with a gallium arsenide chip, and is favorable for system packaging integration;
(2) the integration mode of the invention is that the integrated manufacture of the packaging substrate is realized by adopting the MEMS process and the advanced semiconductor process, and due to the strict control characteristic of the process, the minimum line width size can reach the magnitude below 10mm, the line width precision is within 2mm, the control precision of element parameters is high, and the consistency is good;
(3) the passive devices occupy most of the whole area of the system, the passive elements which are not separated but integrated are adopted, and the manufacturing of the components and the integration of the system are finished under the same process flow, so that the components do not need to be processed and manufactured independently, the area occupied by installation is reduced, and the circuit area is saved;
(4) the transmission of signals on the chip avoids the 50 omega impedance requirement of off-chip impedance matching, so that the design of impedance matching is more flexible.
Drawings
FIG. 1 is a schematic diagram of an integrated IPD package structure on a chip according to the present invention;
FIG. 2 is a schematic diagram illustrating the fabrication of an on-chip integrated resistor according to an embodiment of the invention;
FIG. 3 is a schematic diagram illustrating a through silicon via fabrication in an embodiment of the invention;
FIG. 4 is a schematic diagram illustrating a first metal wiring layer according to an embodiment of the invention;
FIG. 5 is a schematic diagram illustrating the fabrication of a dielectric layer according to an embodiment of the present invention;
FIG. 6 is a schematic diagram illustrating a second metal wiring layer according to an embodiment of the invention;
FIG. 7 is a schematic diagram illustrating a chip fabrication process according to an embodiment of the invention;
FIG. 8 is a schematic diagram of a DC-6GHz superheterodyne broadband receiving module in an embodiment of the present invention;
FIG. 9 is a schematic diagram of a material and structure of an embodiment of the present invention;
FIG. 10 is a schematic diagram of a 2GHz-4GHz filter model in an embodiment of the invention;
FIG. 11 is a diagram illustrating the design result of a 2GHz-4GHz filter in an embodiment of the invention;
FIG. 12(a) shows the front surface of the underlying copper plating layer, and FIG. 12(b) shows the front surface of the SiO layer2Layer, fig. 12(c) is the front side top layer copper plating, and fig. 12(d) is the TSV location.
Detailed Description
The following description of the embodiments of the present invention is provided to facilitate the understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and it will be apparent to those skilled in the art that various changes may be made without departing from the spirit and scope of the invention as defined and defined in the appended claims, and all matters produced by the invention using the inventive concept are protected.
Example 1
Referring to fig. 1, an embodiment of the present invention provides an integrated IPD package structure on a chip, including:
a silicon substrate layer;
the first metal wiring layer is arranged on the upper surface and the lower surface of the silicon substrate layer and is communicated with the silicon substrate layer through a silicon through hole penetrating through the silicon substrate layer;
the dielectric layer is arranged on the surface of the first metal wiring layer positioned on the upper surface of the silicon substrate layer;
the second metal wiring layer is arranged on the surface of the dielectric layer and is sequentially laminated with the dielectric layer and the first metal wiring layer to form an on-chip integrated IPD; and
a chip integrated on the silicon substrate layer.
In this embodiment, a silicon substrate that is commonly used is used as the silicon substrate layer of the present invention, and a high-resistance silicon substrate is preferably used for a high-frequency system. Since the silicon substrate layer is naturally compatible with the chip in terms of size, material, process, etc., three-dimensional packaging integration of the system is facilitated.
When packaging integration is carried out, firstly, an on-chip integrated resistor is manufactured on a silicon substrate layer by adopting a sputtering process, wherein the resistor is made of TaN material or a plurality of layers of sequentially stacked Cu, NiFe and Cu materials, and SiO is deposited on the surface of the resistor by adopting PECVDx、SiNxAnd PI and BCB passivation films, thereby completing the manufacture of the on-chip integrated resistor.
In this embodiment, the first metal wiring layer of the present invention specifically includes a continuously thickened metal layer formed on the upper and lower surfaces of the silicon substrate layer by a double-sided electroplating patterning process, and a metalized through hole formed on the inner wall of the through hole, and the signal of the metal layer on the upper and lower surfaces of the silicon substrate layer is communicated by using the through hole structure.
Wherein the first metal wiring layer comprises a lower electrode of an on-chip integrated inductor and an on-chip integrated capacitor, and the continuous graphic thickened metal layer is formed on the upper surface of the silicon substrate layer.
The first metal wiring layer is provided with a micro-bump structure connected with other substrates on a metal layer manufactured on the lower surface of the silicon substrate layer. The micro-bump structure is connected with the upper layer silicon substrate and the lower layer silicon substrate in a signal mode in a welding mode, and the bottom of the micro-bump structure can be directly connected with an external substrate in a welding mode.
In this embodiment, the dielectric layer of the present invention adopts a physical vapor deposition Parylene process, or conformal coating of a novel organic material, or deposition of TiN and Al2O3And insulating materials such as TiN, silicon oxide and the like are manufactured on the surface of the silicon substrate layer, and a passivation layer is formed on the lower electrode of the on-chip integrated capacitor to manufacture the capacitor dielectric material.
In this embodiment, the present invention uses a redistribution layer structure to fabricate the on-chip integrated IPD, and specifically, uses a double-sided electroplating patterning process to fabricate a continuous thickened metal layer on the surface of the dielectric layer in a manner similar to that of the first metal wiring layer, so as to form a second metal wiring layer including the upper electrodes of the on-chip integrated inductor and the on-chip integrated capacitor. And the second metal wiring layer, the dielectric layer and the first metal wiring layer are sequentially stacked to form the on-chip integrated IPD.
The on-chip integrated IPD comprises structures such as an on-chip integrated capacitor, an on-chip integrated inductor, an on-chip integrated resistor, an on-chip integrated filter and the like, and is designed according to the requirements of a system in a simulation mode.
The on-chip integrated IPD processing technology is completely compatible with the packaging adapter plate self-technology, thereby realizing the processing integration of one-step molding, simplifying the process steps and ensuring the consistency of the system. The structure of the IPD is compatible with the adapter plate process, so that the capacitor is a common flat capacitor structure, and the upper layer and the lower layer of metal and the middle dielectric layer are arranged. The inductor is in a common plane spiral structure, the resistor is in a common square resistor structure, and the filter is in an LC filter structure.
In this embodiment, the chip of the present invention is integrated on the silicon substrate layer by on-chip integration or heterogeneous integration. Specifically, on-chip integration or integration in a heterogeneous integration manner can be selected according to system requirements, for example, due to material process compatibility of a cmos chip, a silicon substrate can be directly replaced by a processed cmos wafer, and a gallium arsenide chip and a gallium nitride chip can adopt a heterogeneous integration manner.
Example 2
Based on the integrated IPD package structure described in embodiment 1, an embodiment of the present invention further provides a package method for the integrated IPD package structure, including the following steps:
s1, manufacturing an on-chip integrated resistor on a silicon substrate layer by adopting a sputtering process;
s2, manufacturing a through silicon via on the silicon substrate layer by adopting a DRIE etching process;
s3, seed layers are sputtered on the upper surface and the lower surface of the silicon substrate layer, photoresist masks are manufactured, continuous thickened metal layers are manufactured on the upper surface and the lower surface of the silicon substrate layer by adopting a double-sided electroplating patterning process, metallized through holes are manufactured on the inner wall of each silicon through hole, and a first metal wiring layer which comprises a lower electrode of an on-chip integrated inductor and an on-chip integrated capacitor is formed after the photoresist and the seed layers are removed;
s4, manufacturing a dielectric layer on the surface of the first metal wiring layer on the upper surface of the silicon substrate layer by adopting a physical vapor deposition Parylene process;
s5, sputtering a seed layer on the surface of the dielectric layer and manufacturing a photoresist mask, manufacturing a continuous thickened metal layer on the surface of the dielectric layer by adopting a double-sided electroplating patterning process, and removing the photoresist and the seed layer to form a second metal wiring layer comprising an upper electrode of the on-chip integrated inductor and the on-chip integrated capacitor;
and S6, integrating the chip on the silicon substrate layer by adopting an on-chip integration or heterogeneous integration mode.
Example 3
Based on the integrated IPD package structure described in embodiment 1, an embodiment of the present invention further provides a three-dimensional package structure of an integrated IPD on a chip, including:
the integrated IPD packaging structure comprises a plurality of single-layer on-chip integrated IPD packaging structures which are sequentially stacked up and down, wherein the integrated IPD packaging structures on the chip are interconnected through a micro-bump structure;
the integrated IPD packaging structure on the chip specifically comprises:
a silicon substrate layer;
the first metal wiring layer is arranged on the upper surface and the lower surface of the silicon substrate layer and is communicated with the silicon substrate layer through a silicon through hole penetrating through the silicon substrate layer;
the dielectric layer is arranged on the surface of the first metal wiring layer positioned on the upper surface of the silicon substrate layer;
the second metal wiring layer is arranged on the surface of the dielectric layer and is sequentially laminated with the dielectric layer and the first metal wiring layer to form an on-chip integrated IPD; and
a chip integrated on the silicon substrate layer.
The following describes the structure and method of the integrated IPD package on chip according to the present invention with reference to the specific examples.
The technology of the on-chip integrated IPD packaging structure adopts the conventional MEMS technology and semiconductor technology, takes a high-resistance silicon adapter plate as an example:
the design mode of the on-chip integrated IPD packaging structure is as follows:
secondly, according to the system index requirements, determining the index requirements of the chip and the passive element.
Determining the type of the chip according to the index of the chip, and selecting a proper packaging substrate: a common silicon substrate, a high-resistance silicon substrate, a cmos substrate, or the like. When the frequency is high, a high-resistance silicon substrate should be selected.
And thirdly, completing element design according to the index requirements of the passive elements.
And fourthly, typesetting and wiring design are carried out according to system requirements, micro bumps are designed at the positions which are connected with the upper layer and the lower layer, and the wiring design method of the micro bumps is the same as that of the conventional multilayer packaging wiring design.
And fifthly, simulating the packaging structure of the wiring design to confirm the electromagnetic compatibility problem.
The packaging method of the on-chip integrated IPD packaging structure comprises the following steps:
a. the resistor is manufactured on the high-resistance silicon wafer by adopting a sputtering process, wherein the resistor is made of TaN material or a plurality of layers of sequentially stacked Cu, NiFe and Cu materials, and SiO is deposited on the surface of the resistor by adopting PECVD (plasma enhanced chemical vapor deposition)x、SiNxAnd PI and BCB passivation films, and finishing the manufacture of the on-chip integrated resistor at the moment, as shown in figure 2.
b. And (3) manufacturing the TSV on the high-resistance silicon wafer by adopting a DRIE etching process, as shown in figure 3.
c. Seed layers are sputtered on two surfaces of the high-resistance silicon substrate, photoresist masks are manufactured on the two surfaces, continuous graphical thickened metal layers are manufactured on the inner wall and the surface of the TSV through hole by adopting a double-sided electroplating process, the seed layers are removed, and at the moment, the first metal wiring layer on the chip is manufactured and comprises lower electrodes of a planar inductor and a traditional planar capacitor, as shown in figure 4.
d. Adopting physical vapor deposition Parylene process, or coating novel organic material in a protective mode, or depositing TiN and Al2O3And TiN, silicon oxide and the like, a dielectric layer is manufactured on the surface of the silicon chip, and a passivation layer is manufactured on the electrode under the capacitor, so that the capacitor dielectric material is obtained, as shown in figure 5.
e. And c, manufacturing an electroplating seed layer, manufacturing an electroplating photoresist mask, finishing a metal layer by adopting a double-sided electroplating patterning electroplating process, removing the photoresist and the seed layer, and finishing the manufacture of a second metal wiring layer on the chip, including the planar capacitor MIM and the inductor, as shown in the step c.
f. The chip is integrated on the interposer as shown in fig. 7.
As shown in fig. 8, which is a schematic diagram of a DC-6GHz superheterodyne wideband receiving module, the module includes three filters with different bandwidths and two switch chips, wherein the filters include a 6GHz low-pass filter, a 2-4GHz band-pass filter and a 4-6GHz band-pass filter.
By adopting an IPD integrated adapter plate packaging mode, the three filters can be designed into an on-chip integrated LC filter which mainly comprises a capacitor and an inductor, and a single-pole three-throw switch with DC-6GHz frequency is selected by a chip according to frequency and functions.
Next, filter simulation design is performed, and since the system frequency is High, a High resistance Si substrate (High resistance Si substrate) is selected, and material parameters are determined by the package structure, as shown in fig. 9, a front passivation layer (pad) metal is an Au material with a thickness of 1 μm, a front top metal layer is a Cu material with a thickness of 10 μm, and is marked as Cu2 in the drawing, which indicates that the front passivation layer metal layer belongs to the second metal wiring layer; the front top insulating layer is made of SiO with a thickness of 0.2 μm by Chemical Vapor Deposition (CVD)2The material is provided with a Via hole (Via), the front bottom metal layer is made of a Cu material with the thickness of 10 mu m, and is marked as Cu1 in the figure, which indicates that the front bottom metal layer belongs to a first metal wiring layer; the front bottom insulating layer is made of SiO with the thickness of 0.5 mu m2The back insulating layer is made of SiO 0.5 μm thick2The back metal layer is made of a Cu material with the thickness of 10 mu m, is marked as Cu2 in the figure, and belongs to the second metal wiring layer; the bottom of the back surface adopts a BCB passive film with the thickness of 8 mu m.
The parameters are shown in table 1:
TABLE 1 Material parameter Table
Filter modeling was done based on material parameters as shown in fig. 10. The filter is composed of a capacitor inductor on the substrate, and the grounded part is realized by TSV. The 2GHz-4GHz filter design results are shown in fig. 11, where m1 represents a bandwidth of 1.160dB at a frequency of 2.000 GHz, m2 represents a bandwidth of 1.338dB at a frequency of 4.016GHz, and m5 represents a bandwidth of 31.613dB at a frequency of 6.042GHz, and it can be seen that the filter has excellent filtering performance between m1 (2.000 GHz) and m2 (4.016 GHz).
The filters of other integrated IPD structures are designed by the same method, and the layout design of the adapter plate is completed together with the completed layout design of the wiring layer.
The filter, the chip arrangement, and the layout design of the silicon substrate are completed, as shown in fig. 12(a) -12 (d).
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The principle and the implementation mode of the invention are explained by applying specific embodiments in the invention, and the description of the embodiments is only used for helping to understand the method and the core idea of the invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
It will be appreciated by those of ordinary skill in the art that the embodiments described herein are intended to assist the reader in understanding the principles of the invention and are to be construed as being without limitation to such specifically recited embodiments and examples. Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.
Claims (10)
1. An integrated IPD package structure on a chip, comprising:
a silicon substrate layer;
the first metal wiring layer is arranged on the upper surface and the lower surface of the silicon substrate layer and is communicated with the silicon substrate layer through a silicon through hole penetrating through the silicon substrate layer;
the dielectric layer is arranged on the surface of the first metal wiring layer positioned on the upper surface of the silicon substrate layer;
the second metal wiring layer is arranged on the surface of the dielectric layer and is sequentially laminated with the dielectric layer and the first metal wiring layer to form an on-chip integrated IPD; and
a chip integrated on the silicon substrate layer.
2. The on-chip integrated IPD package structure according to claim 1, wherein the first metal wiring layer comprises a continuous thickened metal layer formed on the upper and lower surfaces of the silicon substrate layer by a double-sided plating patterning process, and a metalized via formed on the inner wall of the through-silicon via.
3. The on-chip integrated IPD package structure of claim 2, wherein the continuous patterned thickened metal layer made by the first metal wiring layer on the upper surface of the silicon substrate layer comprises the lower electrode of an on-chip integrated inductor and an on-chip integrated capacitor.
4. The integrated IPD package structure of any one of claims 1 to 3, wherein the first metal wiring layer is provided with a micro bump structure connected to other substrates on the metal layer formed on the lower surface of the silicon substrate layer.
5. The integrated IPD package structure as recited in claim 2, wherein the integrated resistor is formed on the silicon substrate layer by sputtering.
6. The on-chip integrated IPD package structure of claim 5, wherein the dielectric layer is deposited on the surface of the first metal wiring layer on the upper surface of the silicon substrate layer by using physical vapor deposition Parylene process, and a passivation layer is performed on the lower electrode of the on-chip integrated capacitor to form a capacitor dielectric material.
7. The on-chip integrated IPD package structure according to claim 6, wherein the continuous thickened metal layer formed on the surface of the dielectric layer by the second metal wiring layer using double-sided plating patterning process comprises an upper electrode of an on-chip integrated inductor and an on-chip integrated capacitor.
8. The integrated IPD package structure of claim 7, wherein the chip is integrated on the silicon substrate layer by on-chip integration or heterogeneous integration.
9. A packaging method for an IPD packaging structure integrated on a chip is characterized by comprising the following steps:
s1, manufacturing an on-chip integrated resistor on a silicon substrate layer by adopting a sputtering process;
s2, manufacturing a through silicon via on the silicon substrate layer by adopting a DRIE etching process;
s3, seed layers are sputtered on the upper surface and the lower surface of the silicon substrate layer, photoresist masks are manufactured, continuous thickened metal layers are manufactured on the upper surface and the lower surface of the silicon substrate layer by adopting a double-sided electroplating patterning process, metallized through holes are manufactured on the inner wall of each silicon through hole, and a first metal wiring layer which comprises a lower electrode of an on-chip integrated inductor and an on-chip integrated capacitor is formed after the photoresist and the seed layers are removed;
s4, manufacturing a dielectric layer on the surface of the first metal wiring layer on the upper surface of the silicon substrate layer by adopting a physical vapor deposition Parylene process;
s5, sputtering a seed layer on the surface of the dielectric layer and manufacturing a photoresist mask, manufacturing a continuous thickened metal layer on the surface of the dielectric layer by adopting a double-sided electroplating patterning process, and removing the photoresist and the seed layer to form a second metal wiring layer comprising an upper electrode of the on-chip integrated inductor and the on-chip integrated capacitor; the second metal wiring layer, the dielectric layer and the first metal wiring layer are sequentially stacked to form an on-chip integrated IPD;
and S6, integrating the chip on the silicon substrate layer by adopting an on-chip integration or heterogeneous integration mode.
10. An integrated IPD three-dimensional packaging structure on a chip, comprising:
the integrated IPD packaging structures are sequentially stacked up and down and are interconnected through a micro-bump structure;
the integrated IPD packaging structure on the chip specifically comprises:
a silicon substrate layer;
the first metal wiring layer is arranged on the upper surface and the lower surface of the silicon substrate layer and is communicated with the silicon substrate layer through a silicon through hole penetrating through the silicon substrate layer;
the dielectric layer is arranged on the surface of the first metal wiring layer positioned on the upper surface of the silicon substrate layer;
the second metal wiring layer is arranged on the surface of the dielectric layer and is sequentially laminated with the dielectric layer and the first metal wiring layer to form an on-chip integrated IPD; and
a chip integrated on the silicon substrate layer.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113629020A (en) * | 2021-06-25 | 2021-11-09 | 北京大学 | Millimeter wave packaging structure and preparation method thereof |
| CN114725068A (en) * | 2022-02-24 | 2022-07-08 | 中国电子科技集团公司第二十九研究所 | Low-profile three-dimensional integrated radio frequency module capable of keeping high Q value of element |
| WO2024114182A1 (en) * | 2022-11-30 | 2024-06-06 | 深圳飞骧科技股份有限公司 | Highly integrated heterogeneous package substrate and module |
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| WO2024114182A1 (en) * | 2022-11-30 | 2024-06-06 | 深圳飞骧科技股份有限公司 | Highly integrated heterogeneous package substrate and module |
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