WO2024113664A1 - 显示驱动电路及其控制方法、显示装置 - Google Patents

显示驱动电路及其控制方法、显示装置 Download PDF

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Publication number
WO2024113664A1
WO2024113664A1 PCT/CN2023/090508 CN2023090508W WO2024113664A1 WO 2024113664 A1 WO2024113664 A1 WO 2024113664A1 CN 2023090508 W CN2023090508 W CN 2023090508W WO 2024113664 A1 WO2024113664 A1 WO 2024113664A1
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Prior art keywords
display
driving circuit
control signal
transistor
signal
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PCT/CN2023/090508
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English (en)
French (fr)
Inventor
解红军
苏伟
于泳
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云谷（固安）科技有限公司
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Publication of WO2024113664A1 publication Critical patent/WO2024113664A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Definitions

  • the present application relates to the field of display technology, and in particular to a display driving circuit and a control method thereof, and a display device.
  • the present application provides a display driving circuit and a control method thereof, and a display device, so that a display panel has a partitioned multi-frequency display function.
  • the embodiments of the present application provide:
  • a display driving circuit comprises: at least one first scanning driving circuit
  • the at least one first scan driving circuit comprises:
  • a plurality of first shift registers arranged in cascade, wherein the first shift registers include a register input end and a register output end, and the plurality of first shift registers are arranged to output a plurality of scanning signals;
  • At least one cascade control module the at least one cascade control module is connected between the output end of the register at this level and the input end of the register at a lower level, and the at least one cascade control module is connected to a cascade control signal, and the at least one cascade control module controls the transmission of the conduction potential of the scanning signal from the output end of the register at this level to the input end of the register at a lower level in response to the cascade control signal, so as to realize multi-frequency display of the display panel in a first direction.
  • the at least one cascade control module includes a plurality of cascade control modules, and the plurality of cascade control modules are connected to at least part of the first shift registers in the at least one first scan driving circuit.
  • the cascade control modules are respectively arranged correspondingly, and each of the cascade control modules is respectively arranged between the corresponding first shift register of the current level and the corresponding first shift register of the next level in the at least part of the first shift register; the cascade control signal adjusts the position where the transmission of the conduction potential of the scanning signal to the input end of the next level register in a frame display is cut off by controlling the switching state of the cascade control module.
  • the cascade control signal includes: a first cascade control signal
  • the cascade control module comprises: a first transistor, a first electrode of the first transistor is electrically connected to a corresponding output terminal of a register at the same level, and a second electrode of the first transistor is electrically connected to a corresponding input terminal of a register at a lower level; a gate of the first transistor is connected to the first cascade control signal;
  • the shutdown time of the cascade control module in one frame of display is determined according to the potential jump time of the first cascade control signal in one frame of display, thereby determining the partition position of the display panel for frequency reduction display in the first direction.
  • the cascade control signal includes: a plurality of second cascade control signals respectively corresponding to the plurality of cascade control modules;
  • the cascade control module comprises: a second transistor; the gate of the second transistor is connected to the corresponding second cascade control signal, and the second transistor is connected between the corresponding output terminal of the current-level register and the corresponding input terminal of the next-level register;
  • the at least one first scan driving circuit further comprises: a first power supply terminal and a second power supply terminal; and the at least one first scan driving circuit further comprises:
  • the first resistor string includes a plurality of first resistors connected in series between the first power supply terminal and the second power supply terminal; a plurality of first output terminals are drawn out from the first resistor string, and the first output terminals output the second cascade control signal; the plurality of first output terminals are respectively connected to the plurality of cascade control modules, and at least one first resistor is arranged between two adjacent first output terminals.
  • the cascade control signal further includes: a plurality of third cascade control signals respectively corresponding to the plurality of cascade control modules;
  • the cascade control module further includes: a third transistor; the gate of the third transistor is connected to the corresponding third cascade control signal, and the third transistor and the corresponding second transistor are connected in series between the corresponding output end of the current-level register and the corresponding input end of the next-level register;
  • the at least one first scan driving circuit further includes: a third power supply terminal and a fourth power supply terminal; and the at least one first scan driving circuit further includes:
  • the second resistor string includes a plurality of second resistors connected in series between the third power supply terminal and the fourth power supply terminal; a plurality of second output terminals are drawn out from the second resistor string, and the second output terminals output the third cascade control signal; the plurality of second output terminals are respectively connected to the plurality of cascade control modules, At least one second resistor is arranged between two adjacent second output terminals;
  • the cascade control module at the preset position is shut down in response to the cascade control signal to control the partition position of the display panel for down-converting display in the first direction; the adjustment of the preset position is achieved based on the potential adjustment of the first power supply terminal, the second power supply terminal, the third power supply terminal and the fourth power supply terminal.
  • the at least one first scan driving circuit further includes:
  • At least one auxiliary cut-off module is arranged corresponding to the at least one cascade control module; the control end of the auxiliary cut-off module is connected to the switch control signal, the input end of the auxiliary cut-off module is connected to the auxiliary cut-off signal, and the output end of the auxiliary cut-off module and the cascade control module corresponding to the auxiliary cut-off module are connected to the same register input end;
  • the at least one auxiliary cut-off module includes a plurality of auxiliary cut-off modules
  • the at least one cascade control module includes a plurality of cascade control modules
  • the plurality of auxiliary cut-off modules are respectively arranged corresponding to the plurality of cascade control modules
  • the auxiliary cut-off modules are connected to the same switch control signal; according to the potential jump time of the switch control signal in one frame display, the conduction time of the auxiliary cut-off module in one frame display is determined;
  • a cascade control module and an auxiliary cut-off module are provided between each two adjacent first shift registers.
  • the first shift register of this stage and the first shift register of the next stage are respectively the first shift register of the i-th stage and the first shift register of the i+a-th stage, and i and a are both positive integers;
  • the cascade control signal controls the cascade control module between the i-th-stage first shift register and the i+a-th-stage first shift register to be turned on, and the switch control signal controls the auxiliary cutoff module between the i-th-stage first shift register and the i+a-th-stage first shift register to be turned off;
  • the cascade control signal controls the cascade control module between the i-th-level first shift register and the i+a-th-level first shift register to be turned off
  • the switch control signal controls the auxiliary cut-off module between the i-th-level first shift register and the i+a-th-level first shift register to be turned on.
  • the display driving circuit further comprises: a first potential signal line and a second potential signal line;
  • the first potential signal line is configured to provide a first potential signal to the plurality of first shift registers, and the second potential signal line is configured to provide a second potential signal to the plurality of first shift registers;
  • the first potential signal When the potential of the first potential signal is the cut-off potential, the first potential signal is multiplexed as the auxiliary cut-off signal; when the potential of the second potential signal is the cut-off potential, the second potential signal is multiplexed as the auxiliary cut-off signal.
  • the cascade control signal includes: a first cascade control signal;
  • the cascade control module includes: a first transistor, a gate of the first transistor is connected to the first cascade control signal, a first electrode of the first transistor is electrically connected to a corresponding output terminal of a register at the same level, and a second electrode of the first transistor is electrically connected to a corresponding input terminal of a register at a lower level;
  • the auxiliary cut-off module includes: a fourth transistor, a gate of the fourth transistor is connected to the switch control signal, a first electrode of the fourth transistor is connected to the auxiliary cut-off signal, and a second electrode of the fourth transistor is electrically connected to the corresponding lower-level register input terminal.
  • the first transistor and the fourth transistor have the same channel type, and the first cascade control signal and the switch control signal have opposite phases; or,
  • the first transistor and the fourth transistor have different channel types, and the first cascade control signal is multiplexed as the switch control signal.
  • the first transistor and the fourth transistor have the same channel type, and the first cascade control signal is multiplexed as the auxiliary cut-off signal.
  • the display driving circuit further includes: a plurality of pixel driving circuits and a plurality of first scan lines, the plurality of pixel driving circuits are arranged in an array, each row of pixel driving circuits is electrically connected to at least one first scan line among the plurality of first scan lines; and a register output terminal in the at least one first scan driving circuit is electrically connected to the first scan line.
  • the pixel driving circuit includes: a driving module, a data writing module, a threshold compensation module and a light emitting control module;
  • the driving module is connected between the light emitting control module and the light emitting device, and the driving module is configured to generate a driving current;
  • the data writing module is electrically connected to a first end of the driving module, and the data writing module is configured to transmit a data voltage to the driving module;
  • the threshold compensation module is connected between a control end and a second end of the driving module, and the threshold compensation module is configured to compensate for a threshold voltage of the driving module;
  • the first scanning line is electrically connected to a control end of the threshold compensation module in a corresponding row pixel driving circuit;
  • the pixel driving circuit further comprises: a first reset module electrically connected to the control end of the driving module, wherein the first reset module is configured to reset the control end of the driving module;
  • the display driving circuit further includes: a plurality of second scanning lines, wherein the second scanning lines are electrically connected to the control terminals of the first reset modules in the corresponding row pixel driving circuits;
  • the register output terminal in the at least one first scanning driving circuit is electrically connected to the second scanning line; wherein the second scanning line connected to the j-th row pixel driving circuit is electrically connected to the j-th level register output terminal, and the first scanning line connected to the j-th row pixel driving circuit is electrically connected to the j+b-th level register output terminal; wherein j and b are both positive integers.
  • the at least one first scan driving circuit comprises a first-side first scan driving circuit and a second-side first scan driving circuit, wherein the first-side first scan driving circuit and the second-side first scan driving circuit are respectively arranged on both sides of the plurality of pixel driving circuits; first shift registers of corresponding stages in the first-side first scan driving circuit and the second-side first scan driving circuit are connected to the same first scan line;
  • Each of at least some of the plurality of first scan lines comprises at least two sub-scan lines
  • the display driving circuit also includes: at least one split-screen control module; the at least one split-screen control module includes a plurality of split-screen switch units; the plurality of split-screen switch units are respectively arranged corresponding to at least part of the plurality of first scan lines; each of the split-screen switch units is connected between two adjacent sub-scan lines in the same first scan line; when each of the split-screen switch units is turned off in response to the split-screen control signal, the first-side first scan driving circuit and the second-side first scan driving circuit respectively transmit scan signals to the sub-scan lines on both sides of each of the split-screen switch units.
  • the number of split-screen switch units in the off state on the same first scan line is less than or equal to 1;
  • the multiple split-screen switch units in the same split-screen control module are connected to the same split-screen control signal;
  • the cascade control signal connected to the first side first scan driving circuit is a first side cascade control signal
  • the cascade control signal connected to the second side first scan driving circuit is a second side cascade control signal
  • the first side cascade control signal is different from the second side cascade control signal
  • the split-screen control signal controls the one of the multiple split-screen switch units to be turned on.
  • each of the at least some of the first scan lines comprises a first sub-scan line and a second sub-scan line, the first sub-scan line is connected to the first-side first scan driving circuit, and the second sub-scan line is connected to the second-side first scan driving circuit;
  • Each of the split screen control units is electrically connected to the corresponding first sub-scanning line and the second sub-scanning line. catch;
  • the first sub-scanning line and the second sub-scanning line have the same length.
  • each of the at least some of the first scan lines includes a third sub-scan line, a fourth sub-scan line and a fifth sub-scan line;
  • the at least one split-screen control module includes: a first split-screen control module and a second split-screen control module;
  • the third sub-scan line is connected to the first-side first scan driving circuit
  • the first split-screen control module is connected between the third sub-scan line and the fourth sub-scan line
  • the second split-screen control module is connected between the fourth sub-scan line and the fifth sub-scan line
  • the fifth sub-scan line is connected to the second-side first scan driving circuit
  • the first split screen control module is turned on and the second split screen control module is turned off, and during the data writing process of the pixel driving circuits of other rows, the first split screen control module is turned off and the second split screen control module is turned on;
  • the split-screen control signal includes a first split-screen control signal and a second split-screen control signal
  • the first split-screen control module is connected to the first split-screen control signal
  • the second split-screen control module is connected to the second split-screen control signal
  • the transistor in the split-screen switch unit in the first split-screen control module has a different channel type from the transistor in the split-screen switch unit in the second split-screen control module, and the first split-screen control signal is multiplexed into the second split-screen control signal.
  • the split-screen switch unit includes: a fifth transistor, a gate of the fifth transistor is connected to the split-screen control signal, and a first electrode of the fifth transistor and a second electrode of the fifth transistor are respectively connected to two adjacent sub-scan lines in the same first scan line.
  • an embodiment of the present application further provides a control method for a display driving circuit, which is used to control the display driving circuit provided by any embodiment of the present application; the control method includes:
  • a cascade control signal in each frame display is determined, and based on the cascade control signal, a switch state of the cascade control module in each frame display is controlled.
  • the at least one cascade control module includes a plurality of cascade control modules; the display panel includes at least one target partition position;
  • the display panel includes multiple types of display frames during display; the multiple types of display frames include a first refresh frame and at least one type of second refresh frame; the types of the second refresh frames correspond to the target partition positions respectively;
  • the cascade control signal controls all cascade control modules to remain turned on;
  • the cascade control signal controls the off time of all cascade control modules. Or control the cascade control module at the preset position to be turned off, so that the display panel displays based on the target partition position corresponding to the second refresh frame.
  • an embodiment of the present application further provides a display device, comprising: a display driving circuit as provided in any embodiment of the present application.
  • the display driving circuit provided in the embodiment of the present application is provided with at least one cascade control module in the first scanning driving circuit.
  • the cascade control signal can control whether the conduction potential of the scanning signal output by the first shift register can be transmitted step by step by controlling the switch state of the cascade control module.
  • the partition display of the display panel in the first direction in the same frame display can be realized, and the refresh frequencies of different display areas are different to enrich the display function of the display panel.
  • the embodiment of the present application can enable the display panel to have a partitioned multi-frequency display function.
  • FIG1 is a schematic diagram of the structure of a display driving circuit provided in an embodiment of the present application.
  • FIG2 is a schematic diagram of the structure of another display driving circuit provided in an embodiment of the present application.
  • FIG3 is a schematic diagram of the structure of another display driving circuit provided in an embodiment of the present application.
  • FIG4 is a schematic diagram of the structure of another display driving circuit provided in an embodiment of the present application.
  • FIG5 is a schematic diagram of the structure of another display driving circuit provided in an embodiment of the present application.
  • FIG6 is a schematic diagram of the structure of a display panel provided in an embodiment of the present application.
  • FIG7 is a timing diagram of a driving signal of a display frame provided by an embodiment of the present application.
  • FIG8 is another timing diagram of a driving signal for displaying a frame provided by an embodiment of the present application.
  • FIG9 is a timing diagram of a driving signal of another display frame provided in an embodiment of the present application.
  • FIG10 is a schematic diagram of a driving timing sequence of a display panel provided in an embodiment of the present application.
  • FIG11 is a schematic diagram of another driving timing sequence of a display panel provided in an embodiment of the present application.
  • FIG12 is a schematic diagram of the structure of another display driving circuit provided in an embodiment of the present application.
  • FIG13 is a schematic diagram of the structure of another display driving circuit provided in an embodiment of the present application.
  • FIG14 is a schematic diagram of a driving timing sequence of another display panel provided in an embodiment of the present application.
  • FIG15 is a schematic diagram of the structure of another display driving circuit provided in an embodiment of the present application.
  • FIG16 is a schematic diagram of a driving timing sequence of another display panel provided in an embodiment of the present application.
  • FIG17 is a schematic diagram of the structure of another display driving circuit provided in an embodiment of the present application.
  • FIG18 is a schematic diagram of a power supply terminal voltage setting mode provided in an embodiment of the present application.
  • FIG19 is a schematic diagram of another power supply terminal voltage setting mode provided in an embodiment of the present application.
  • FIG20 is a schematic diagram of the structure of a pixel driving circuit provided in an embodiment of the present application.
  • FIG21 is a driving timing diagram of a pixel driving circuit provided in an embodiment of the present application.
  • FIG22 is a schematic diagram of the structure of another display panel provided in an embodiment of the present application.
  • FIG23 is a schematic diagram of the structure of a first shift register provided in an embodiment of the present application.
  • FIG24 is a schematic diagram of a driving timing sequence of a first shift register provided in an embodiment of the present application.
  • FIG25 is a schematic diagram of the structure of another pixel driving circuit provided in an embodiment of the present application.
  • FIG26 is a driving timing diagram of another pixel driving circuit provided in an embodiment of the present application.
  • FIG27 is a schematic diagram of the structure of another first shift register provided in an embodiment of the present application.
  • FIG28 is a schematic diagram of another driving timing of a first shift register provided in an embodiment of the present application.
  • FIG29 is a driving timing diagram of another pixel driving circuit provided in an embodiment of the present application.
  • FIG30 is a schematic diagram of the structure of another display panel provided in an embodiment of the present application.
  • FIG31 is a schematic diagram of the structure of another display panel provided in an embodiment of the present application.
  • FIG32 is a schematic diagram of a driving timing sequence of another display panel provided in an embodiment of the present application.
  • FIG33 is a schematic diagram of a driving timing sequence of another display panel provided in an embodiment of the present application.
  • FIG34 is a schematic diagram of a driving timing sequence of another display panel provided in an embodiment of the present application.
  • FIG35 is a schematic diagram of a driving timing sequence of another display panel provided in an embodiment of the present application.
  • FIG36 is a schematic diagram of a driving timing sequence of another display panel provided in an embodiment of the present application.
  • FIG37 is a schematic diagram of a driving timing sequence of another display panel provided in an embodiment of the present application.
  • FIG38 is a schematic diagram of a driving timing sequence of another display panel provided in an embodiment of the present application.
  • FIG39 is a schematic diagram of the structure of another display panel provided in an embodiment of the present application.
  • FIG40 is a schematic diagram of a driving timing sequence of another display panel provided in an embodiment of the present application.
  • FIG. 41 is a schematic diagram of the structure of another display panel provided in an embodiment of the present application.
  • the display driving circuit in the display panel includes: a scanning driving circuit arranged in the non-display area and a pixel driving circuit arranged in an array in the display area.
  • the scanning driving circuit includes a shift register arranged in cascade, and the scanning driving circuit can adopt a single-side driving mode or a double-side driving mode.
  • the pixel driving circuit cooperates with the light-emitting device to form a sub-pixel.
  • Each sub-pixel is a minimum display unit, and multiple sub-pixels of different colors form a pixel to achieve color display.
  • Each level of shift register is connected to a scanning line, and a scanning signal is provided to the corresponding row sub-pixel through the scanning line.
  • Each column sub-pixel is connected to a data line.
  • each pixel driving circuit is written to each pixel driving circuit by scanning row by row, that is, the shift register provides a scanning signal to the pixel driving circuit through the scanning line, and the data voltage on the data line is transmitted to the corresponding pixel driving circuit corresponding to the on-potential duration of the scanning signal to realize data writing, and each sub-pixel is displayed according to the data voltage.
  • the scanning line provides an off-potential, the data voltage of the data line cannot be transmitted to the corresponding pixel driving circuit, and data writing is not performed.
  • the scanning line corresponding to the sub-pixels in the first row provides an on-potential to the pixel driving circuit in the first row, and the scanning lines corresponding to the sub-pixels in other rows provide an off-potential, and the data voltage on each data line is transmitted to the sub-pixels in the first row; at the same time, only one shift register outputs the on-potential of the scanning signal.
  • the display frame of a sub-pixel can be divided into a refresh frame (active frame) and a hold frame (idle frame).
  • the shift register provides an on-state potential to the corresponding row pixel drive circuit, so that the data voltage is written into the pixel drive circuit;
  • the shift register provides an off-state potential to the corresponding row pixel drive circuit, so that the pixel drive circuit no longer writes data.
  • the refresh rate can be understood as the number of refresh frames contained in a unit time.
  • high-frequency display can only include refresh frames
  • low-frequency display is achieved by skipping frames.
  • the display The display frames of the panel only include refresh frames.
  • the refresh frequency is reduced, a hold frame is inserted between adjacent refresh frames, and the number of display frames contained in a unit time remains unchanged, and the display duration of each display frame remains unchanged.
  • the refresh frequency is f/2, 1 hold frame is inserted between every two adjacent refresh frames, that is, odd frames are refresh frames and even frames are hold frames.
  • the refresh frequency is f/3, 2 hold frames are inserted between every two adjacent refresh frames.
  • N hold frames are inserted between every two adjacent refresh frames.
  • FIG. 1 is a schematic diagram of the structure of a display driving circuit provided by an embodiment of the present application.
  • the display driving circuit includes: at least one first scanning driving circuit 100.
  • FIG. 1 is an example of a display driving circuit including a first scanning driving circuit 100.
  • the first scanning driving circuit 100 includes: a plurality of first shift registers 10 arranged in cascade, and at least one cascade control module 20. Each first shift register 10 includes a register input terminal and a register output terminal.
  • Each cascade control module 20 is connected between the corresponding register output terminal of the current level and the register input terminal of the next level, and the control terminal of the cascade control module 20 is connected to the cascade control signal SJL.
  • Each cascade control module 20 controls the transmission of the conduction potential of the scan signal from the output end of the register at the current level to the input end of the register at the next level in response to the cascade control signal SJL, so as to realize multi-frequency display of the display panel in the first direction (ie, the sub-pixel column direction).
  • the on-state potential of the scanning signal at this level is transmitted to the next-level first shift register 10 as the start signal of the next-level first shift register 10, triggering the next-level first shift register 10 to continue to output the on-state potential of the scanning signal, thereby realizing the sequential shifting of the on-state pulse of the scanning signal.
  • the first shift register of this stage and the first shift register of the next stage are respectively the first shift register of the i-th stage and the first shift register of the i+a-th stage in the first scanning driving circuit 100, and i and a are both positive integers.
  • the shift registers of each stage are not cascaded in sequence, a>1, and the first shift register of the next stage is not the first shift register of the next stage of the first shift register of this stage.
  • the first shift registers of the odd-numbered stages are cascaded in sequence, and the first shift registers of the even-numbered stages are cascaded in sequence. If the first shift register of this stage is the first shift register 101 of the first stage, then the first shift register of the next stage is the first shift register 103 of the third stage.
  • the first shift register in FIG2 is used as an example.
  • the connection structure of first shift registers of each stage cascaded in sequence is taken as an example for explanation.
  • the multi-frequency display of the display panel in the first direction is realized by setting the cascade control module 20, and the driving scheme of the refresh frequency changing from high to low.
  • a driving scheme of the refresh frequency changing from low to high can also be realized.
  • the number of cascade control modules 20 may be the same as the number of target partition positions D, and may correspond to the target partition positions of the display panel one by one.
  • the number of cascade control modules 20 may be greater, so that the partition positions of the display panel in the first direction are adjustable.
  • At least one cascade control module 20 is set in the first scanning driving circuit 100, and the cascade control signal SJL can control whether the conduction potential of the scanning signal output by the first shift register 10 can be transmitted step by step by controlling the switching state of the cascade control module 20.
  • the partition display of the display panel in the first direction in the same frame display can be realized, and the refresh frequencies of different display areas are different, so as to enrich the display function of the display panel.
  • the embodiment of the present application can enable the display panel to have a partition multi-frequency display function.
  • At least one cascade control module 20 includes a plurality of cascade control modules 20.
  • the plurality of cascade control modules 20 are respectively arranged corresponding to at least part of the first shift registers 10 in the first scan drive circuit 100, for example, they are correspondingly connected to part or all of the first shift registers 10.
  • Each cascade control module 20 is respectively arranged between the corresponding first shift register 10 of the current level and the corresponding first shift register 10 of the next level in the at least part of the first shift registers 10.
  • Each of the plurality of cascade control modules 20 responds to the cascade control signal SJL, and the cascade control signal SJL adjusts the position where the transmission of the conduction potential of the scan signal to the input terminal 11 of the next level register is cut off in one frame display by controlling the switch state of each cascade control module 20, thereby adjusting the partition position of the display panel for frequency reduction display in the first direction.
  • the register output terminal 12 of the first-stage first shift register 101 and the register input terminal 11 of the second-stage first shift register 102 are connected.
  • the on-potential of the first-level scan signal SCAN1 cannot be transmitted to the second-level register input terminal, and cannot trigger the second-level first shift register 102 to output the on-potential, so the second-level first shift register 102 continues to output the off-potential in the frame display.
  • the sub-pixels of the row corresponding to the first-level shift register 101 are in the refresh frame, and the sub-pixels of the row corresponding to the second-level first shift register 102 are in the hold frame, and the area between the above two rows of sub-pixels is the frequency reduction display partition position of the display panel.
  • the cascade control signal SJL can change the position where the step-by-step transmission of the scanning signal is cut off by controlling the switching state of each cascade control module 20 in each frame display, thereby realizing the adjustment of the frequency reduction display partition position of the display panel.
  • the cascade control signal SJL controls the cascade control module 20 between the two first shift registers 10 respectively connected to the row of sub-pixels and the next row of sub-pixels in a frame display during the scanning time of the previous row of sub-pixels at the target display partition position to be disconnected, so as to realize the frequency reduction display based on the target display partition position in the display frame.
  • the cascade control signal SJL can control the time when each cascade control module 20 is switched from on to off, or control the cascade control module 20 corresponding to the target partition position to be turned off, so as to realize the above control process.
  • the position at which the transmission of the scanning signal conduction potential in each display frame is cut off can be adjusted, and then the frequency reduction display partition position of the display panel can be adjusted, so as to enrich the display function of the display panel and make the driving process of the display panel more flexible.
  • a cascade control module 20 can be set between each two adjacent first shift registers 10, so that the step-by-step transmission of the scanning signal can be interrupted at any row position of the display screen, thereby making the partition position not limited by the setting position of the cascade control module 20.
  • the working state of any cascade control module 20 can be controlled at any time according to demand, so that the partition position of the display panel can be adjusted arbitrarily.
  • the input terminal 11 of the lower register connected thereto is floating and has no voltage input, so that the output state of the lower first shift register 10 is at risk of being unstable.
  • FIG4 is a schematic diagram of the structure of another display driving circuit provided by an embodiment of the present application.
  • the first scanning driving circuit 100 is further provided with: at least one auxiliary cut-off module 30.
  • the auxiliary cut-off module 30 is provided corresponding to the cascade control module 20.
  • the control end of the auxiliary cut-off module 30 is connected to the switch control signal SW2, and the input end of the auxiliary cut-off module 30 is connected to the auxiliary cut-off signal VD.
  • the output end of the disconnection module 30 and the cascade control module 20 corresponding to the auxiliary disconnection module 30 are connected to the same register input end 11 .
  • the switch control signal SW2 can control the corresponding auxiliary cut-off module 30 to be turned on when the cascade control module 20 is turned off, so as to transmit the auxiliary cut-off signal VD to the lower register input terminal 11, so as to prevent the lower register input terminal 11 from floating, so that the lower first shift register 10 can stably output the cut-off potential of the scanning signal.
  • the auxiliary cut-off signal VD can be a DC voltage signal
  • the potential of the auxiliary cut-off signal VD can be the cut-off potential of the scanning signal.
  • the cascade control signal SJL and the switch control signal SW2 can be provided by the mainboard of the terminal device and enter the screen body via the driver integrated circuit (IC); or directly provided by the driver IC.
  • the mainboard of the terminal device can have the ability to detect each frame of picture information to determine the display state of the display panel in each frame display, and the refresh frequency corresponding to each sub-display area.
  • each display frame there are multiple control modes for the cascade control module 20, which are described below respectively.
  • the sub-pixel row corresponding to the i-th stage first shift register 10 may be the i-th row of sub-pixels, the i-1-th row of sub-pixels, or other rows of sub-pixels determined according to the connection relationship.
  • the i-th stage first shift register 10 corresponding to the connection of the i-th row of sub-pixels is taken as an example for explanation.
  • FIG5 is a schematic diagram of the structure of another display driving circuit provided by an embodiment of the present application.
  • the cascade control signal SJL includes: a first cascade control signal SW1, each cascade control module 20 is connected to the same first cascade control signal SW1, and each cascade control module 20 is turned on or off at the same time in response to the first cascade control signal SW1.
  • the first cascade control signal SW1 adjusts the potential jump time in a frame display and the off time of each cascade control module 20 in a frame display, thereby adjusting the frequency reduction display partition position of the display panel.
  • the on-time of the cascade control module 20 in a frame display determines the number of sub-pixel rows that transmit the scan signal and refresh.
  • all auxiliary cut-off modules 30 are turned on and off at the same time without affecting the normal driving of the display panel, and all auxiliary cut-off modules 30 can be connected to the same switch control signal SW2.
  • the potential jump time of the switch control signal SW2 in one frame of display determines the conduction time of each auxiliary cut-off module 30 in one frame of display.
  • the first cascade control signal SW1 cooperates with the switch control signal SW2 to realize the regulation of the multi-frequency display position of the partition of the display panel.
  • the cascade control signal SJL controls the cascade control module 20 between the i-th level first shift register and the i+a-th level first shift register to be turned on
  • the switch control signal SW2 controls the auxiliary cut-off module 30 between the i-th level first shift register and the i+a-th level first shift register to be turned off.
  • the cascade control signal SJL controls the cascade control module 20 between the i-th first shift register and the i+a-th first shift register to be turned off
  • the switch control signal SW2 controls the auxiliary cut-off module 30 between the i-th first shift register and the i+a-th first shift register to be turned on.
  • the switch states of other cascade control modules 20 may be the same as or different from the switch states of the cascade control modules 20 between the i-th first shift register and the i+a-th first shift register; and the switch states of other auxiliary cut-off modules 30 may be the same as or different from the switch states of the auxiliary cut-off modules 30 between the i-th first shift register and the i+a-th first shift register.
  • the first cascade control signal SW1 controls each cascade control module 20 to be turned on during the output process of the first shift register 10 from the 1st stage to the i-1st stage.
  • the switch control signal SW2 controls each auxiliary cut-off module 30 to be turned off.
  • the first shift registers 10 from the 1st stage to the i-1st stage can output the on-state potential step by step.
  • the i-th level first shift register 10 can receive the on-potential step by step.
  • the first cascade control signal SW1 undergoes a potential jump to control each cascade control module 20 to turn off, and the switch control signal SW2 also undergoes a potential jump to control each auxiliary cut-off module 30 to turn on, so that the on-potential of the i-th level scanning signal cannot be transmitted to the i+1-th level first shift register 10, and the input end of each register is connected to the auxiliary cut-off signal.
  • the first shift registers 10 from the 1st level to the i-th level can output the on-potential of the scanning signal step by step, and the first shift registers 10 from the i+1st level to the nth level can only continuously output the cut-off potential of the scanning signal.
  • the frequency reduction display partition position of the display panel is located between the two rows of sub-pixels corresponding to the i-th level and the i+1-th level first shift registers 10.
  • the first cascade control signal SW1 controls each cascade control module 20 to turn on again, because the first shift registers 10 of the i+1th level to the j-th level only output the cut-off potential, the j-th level scanning signal cannot provide the on-potential to the first shift register 10 of the j+1th level, then, the first shift registers 10 of the j+1th level to the nth level cannot restore the output on-potential.
  • the display panel in one frame of display, has a frequency-reducing display partition position; but by combining display frames with different frequency-reducing display partition positions, multi-partition multi-frequency display of the display panel can be realized.
  • the following is an example of a three-partition multi-frequency display of the display panel.
  • FIG6 is a schematic diagram of the structure of a display panel provided in an embodiment of the present application.
  • the first scanning driving circuit 100 includes an n-stage first shift register
  • the display area AA of the display panel includes an n-row pixel driving circuit 200 (i.e., n-row sub-pixels)
  • the i-th stage first shift register is connected to the i-th row sub-pixels.
  • the display panel includes two target frequency reduction display partition positions (indicated by dotted lines), including: a first target partition position D1, for example, between the k-th row sub-pixels and the k+1-th row sub-pixels; a second target partition position D2, for example, between the m-th row sub-pixels and the m+1-th row sub-pixels.
  • the above two target partition positions divide the display area AA of the display panel into a first sub-display area A1, a second sub-display area A2, and a third sub-display area A3 in the first direction.
  • the first sub-display area A1 to the third sub-display area A3 are sequentially displayed with frequency reduction.
  • the display panel may have display frames in the following three display states: a first display frame, in which each row of sub-pixels in the entire display area AA is in a refresh frame; a second display frame, in which the first target partition position D1 is used as the boundary, each row of sub-pixels in the first sub-display area A1 is in a refresh frame, and each row of sub-pixels in the second sub-display area A2 and the third sub-display area A3 are in a hold frame; a third display frame, in which the second target partition position D2 is used as the boundary, each row of sub-pixels in the first sub-display area A1 and the second sub-display area A2 are in a refresh frame, and each row of sub-pixels in the third sub-display area A3 are in a hold frame.
  • the on-potential of the scanning signal is a high potential
  • both the cascade control module 20 and the auxiliary cut-off module 30 are turned on in response to the high potential
  • the on-potential transmission time of the i-th level scanning signal that is, the scanning time of the i-th row of sub-pixels
  • the shaded filling indicates that each sub-pixel in the sub-display area is in the refresh frame
  • the blank filling indicates that each sub-pixel in the sub-display area is in the hold frame.
  • FIG7 is a driving signal timing diagram of a display frame provided by an embodiment of the present application.
  • the display frame corresponds to the first type of display frame, and each row of sub-pixels in the entire display area AA is in a refresh frame.
  • the first cascade control signal SW1 maintains a high potential
  • the switch control signal SW2 maintains a low potential.
  • Each cascade control module 20 is always turned on in the display frame, and each auxiliary cut-off module 30 is always turned off in the display frame.
  • the first shift registers of each level always maintain a cascade state in the display frame to realize the step-by-step transmission of the conduction potential of the scan signal.
  • Fig. 8 is a timing diagram of a driving signal of another display frame provided in an embodiment of the present application.
  • the display frame corresponds to the second type of display frame, and the frequency is reduced based on the first target partition position D1 as the boundary.
  • the first cascade control signal SW1 maintains a high potential, and the switch control signal SW2 maintains a low potential, so that each cascade control module 20 remains turned on and each auxiliary cut-off module 30 remains turned off.
  • the shift transmission of the scanning signal conduction potential can be realized between the first shift registers of the 1st to the kth stages.
  • each cascade control module 20 remains turned off, and each auxiliary cut-off module 30 remains turned on.
  • the connection between adjacent first shift registers is cut off, and the input terminals of the registers of the k+1-th to n-th levels are all connected to the auxiliary cut-off signal VD.
  • the first shift registers of the k+1-th to n-th levels continuously output the cut-off potential.
  • Fig. 9 is a timing diagram of a driving signal of another display frame provided in an embodiment of the present application.
  • the display frame corresponds to the third type of display frame, and the frequency is reduced based on the second target partition position D2 as the boundary.
  • the first cascade control signal SW1 maintains a high potential, and the switch control signal SW2 maintains a low potential, so that each cascade control module 20 remains turned on and each auxiliary cut-off module 30 remains turned off.
  • the shift transmission of the scanning signal on potential can be realized between the first shift registers of the 1st to the mth stages.
  • the first cascade control signal SW1 maintains a low potential
  • the switch control signal SW2 maintains a high potential
  • each cascade control module 20 remains off
  • each auxiliary cut-off module 30 remains on.
  • the connection between adjacent first shift registers is cut off, and the input terminals of the registers of the m+1-th to n-th stages are all connected to the auxiliary cut-off signal VD.
  • the first shift registers of the m+1-th to n-th stages continuously output the cut-off potential.
  • each display frame can be a refresh frame.
  • FIG10 exemplarily shows the waveform of the first-level scan signal SCAN1. It can be seen that in each frame display, the first-level scan signal SCAN1 includes a conduction pulse.
  • odd frames can be set as refresh frames and even frames as hold frames.
  • FIG10 exemplarily shows the waveform of the k+1th level scan signal SCANk+1. It can be seen that the k+1th level scan signal SCANk+1 includes a conduction pulse only in odd frames. For each row of sub-pixels in the third sub-display area A3, three holding frames can be set between two adjacent refresh frames.
  • FIG10 exemplarily shows the waveform of the m+1th level scan signal SCANm+1. It can be seen that the m+1th level scan signal SCANm+1 includes a conduction pulse in the display frame F1 and the display frame F5, that is, it only includes a conduction pulse in the 4i+1th display frame, and maintains the cut-off potential in other display frames.
  • the driving process in the cycle is repeated, and a stable partition multi-frequency display can be realized in which the first sub-display area A1 displays at a refresh frequency f, the second sub-display area A2 displays at a refresh frequency f/2, and the third sub-display area A3 displays at a refresh frequency f/4.
  • the display frame F1 corresponds to the first type of display frame
  • the display frames F2 and F4 correspond to the second type of display frames
  • the display frame F3 corresponds to the third type of display frame.
  • the first target partition position D1 can be moved up.
  • each sub-display area it can be achieved by controlling the order and number of various display frames in different cycles; for example, by adding multiple display frames that are identical to display frame F2 between display frame F1 and display frame F3 in Figure 10, the refresh frequencies of the second sub-display area A2 and the third sub-display area A3 can be reduced.
  • the refresh rate can be dynamically adjusted. Display scheme.
  • the data voltage on the data line can be controlled to update and switch according to the refresh state of each row of sub-pixels. Specifically, for the sub-pixel row in the refresh frame, the data voltage needs to be updated, and the data voltage is normally transmitted to each sub-pixel in the row through the data line during the on-potential duration of the row scanning signal.
  • the state of the data voltage can change with the change of the first cascade control signal SW1.
  • the first cascade control signal SW1 controls each cascade control module 20 to be turned on, the data voltage is updated; when the first cascade control signal SW1 controls each cascade control module 20 to be turned off, the data voltage stops being output.
  • the driving timing of the display panel can be as shown in FIG. 11.
  • the time of the current display frame continues until the blank stage ends, and then enters the next display frame.
  • the potential of the first cascade control signal SW1 and the switch control signal SW2 can be set arbitrarily, for example, continuing the potential of the previous stage, so as to reduce the number of potential jumps and simplify the control logic.
  • the above embodiments exemplarily provide the working modes of the cascade control module 20 and the auxiliary cut-off module 30 in the display process.
  • the specific structures of the cascade control module 20 and the auxiliary cut-off module 30 are described below.
  • each auxiliary cut-off module 30 includes: a fourth transistor T4; the gate of the fourth transistor T4 is connected to the switch control signal SW2, the first electrode of the fourth transistor T4 is connected to the auxiliary cut-off signal, and the second electrode of the fourth transistor T4 is electrically connected to the second electrode of the corresponding first transistor T1.
  • the auxiliary cut-off module 30 includes one transistor, so that the structure of the auxiliary cut-off module 30 is simple and easy to implement.
  • the display panel is provided with: a first clock signal line for transmitting a first clock signal CLK1; a second clock signal line for transmitting a second clock signal CLK2; a first potential signal line for transmitting a first potential signal VGH; a second potential signal line for transmitting a second potential signal VGL; a first cascade control signal line for transmitting a first cascade control signal SW1; a switch control signal line for transmitting a switch control signal SW2.
  • Each level of the first shift register 10 is connected to the second potential signal VGL and the first potential signal VGH; two adjacent levels of the first shift registers
  • the first clock terminal and the second clock terminal of 10 are alternately electrically connected to the first clock signal line and the second clock signal line, respectively.
  • the first potential signal VGH may be a high potential signal
  • the second potential signal VGL may be a low potential signal.
  • the potential of the first potential signal VGH or the second potential signal VGL serves as the on-potential of the scan signal, and the other serves as the off-potential.
  • the potential signal as the cut-off potential can be multiplexed as an auxiliary cut-off signal to reduce the wiring of the display panel.
  • the second potential signal VGL can be multiplexed as an auxiliary cut-off signal, and the first electrode of the fourth transistor T4 is electrically connected to the second potential signal line.
  • the first potential signal VGH can be multiplexed as an auxiliary cut-off signal, and the first electrode of the fourth transistor T4 is electrically connected to the first potential signal line.
  • each cascade control module 20 includes: a first transistor T1; a gate of the first transistor T1 is connected to a first cascade control signal SW1, a first electrode of the first transistor T1 is electrically connected to a register output terminal 12 of the same level, and a second electrode of the first transistor T1 is electrically connected to a register input terminal 11 of a lower level.
  • the cascade control module 20 includes one transistor, so that the structure of the cascade control module 20 is simple and easy to implement.
  • the first transistor T1 and the fourth transistor T4 have the same channel type, and the two transistors can be prepared in the same process to simplify the panel preparation process.
  • the first cascade control signal SW1 and the switch control signal SW2 can be set to be mutually inverted signals, and the jump time of the two control signals is consistent, so that when the cascade control module 20 is turned off, the auxiliary cut-off module 30 can be reliably turned on and transmit the auxiliary cut-off signal to the lower register input terminal 11.
  • the first transistor T1 and the fourth transistor T4 are both N-type transistors.
  • the first transistor T1 and the fourth transistor T4 include metal oxide semiconductor transistors. Compared with polysilicon transistors, N-type metal oxide semiconductor transistors can provide better turn-off effect.
  • FIG12 is a schematic diagram of the structure of another display driving circuit provided by an embodiment of the present application.
  • the first cascade control signal SW1 can be multiplexed as an auxiliary cut-off signal to simplify the circuit structure. Since the switch control signal SW2 controls the fourth transistor T4 to be turned on, the first cascade control signal SW1 is maintained at the cut-off potential of the fourth transistor T4 as the inverted signal of the switch control signal SW2, which is equivalent to being maintained at the cut-off potential of the scanning signal.
  • the switch control signal SW2 as the input signal of the fourth transistor T4 can ensure the normal operation of the auxiliary cut-off module 30.
  • FIG13 is a schematic diagram of the structure of another display driving circuit provided in an embodiment of the present application.
  • the first transistor T1 and the fourth transistor T4 can both be P-type transistors. Since the first shift register 10 is usually composed of P-type transistors, such a configuration allows the first transistor T1 and the fourth transistor T4 to be prepared in the same process as the transistors in the first shift register 10, so as to simplify the panel preparation process. In this case, the driving timing of the display panel can be seen in Figure 14. Compared with Figure 10, since the conduction potential of each transistor in this embodiment is a low potential, each switch control signal is transformed into an inverted signal of the corresponding switch control signal in Figure 10. The switch state changes of each functional module can still refer to the description of the display panel driving process in the above explanation, which will not be repeated.
  • FIG15 is a schematic diagram of the structure of another display driving circuit provided in an embodiment of the present application.
  • the channel types of the first transistor T1 and the fourth transistor T4 are different, and the first cascade control signal SW1 can be reused as the switch control signal SW2 to reduce the number of signal lines required for the display panel and simplify the wiring of the display panel.
  • the driving timing of the display panel can be seen in FIG16.
  • the two transistors can be controlled by the same switch control signal, and the switch state changes of each functional module can still refer to the description of the display panel driving process in the above explanation, which will not be repeated.
  • the cascade control module 20 may optionally have other structures, and the cascade control signal controls the cascade control module 20 at a preset position to remain in an off state in each frame display, thereby adjusting the frequency-reduced display partition position of the display panel.
  • FIG17 is a schematic diagram of the structure of another display driving circuit provided by an embodiment of the present application.
  • the first scan driving circuit 100 further includes: a first power supply terminal N1 and a second power supply terminal N2, wherein the first power supply terminal N1 is arranged at the far end of the driving IC, that is, close to one end of the first shift register of the first stage; the second power supply terminal N2 is arranged at the near end of the driving IC, that is, close to one end of the first shift register of the last stage.
  • the first scan driving circuit 100 further includes: a first resistor string.
  • the first resistor string includes a plurality of first resistors R1 connected in series between the first power supply terminal N1 and the second power supply terminal N2; a plurality of first output terminals NT are drawn out from the first resistor string, and the first output terminal NT outputs a second cascade control signal.
  • the plurality of first output terminals NT are respectively connected to the plurality of cascade control modules 20, and at least one first resistor R1 is arranged between two adjacent first output terminals NT.
  • the potentials of the second cascade control signals are the same; by setting the potentials of the first power terminal N1 and the second power terminal N2 to be different, the potentials of the second cascade control signals can be different.
  • the cascade control module 20 includes: a second transistor T2; the gate of the second transistor T2 is connected to the corresponding second cascade control signal, and the second transistor T2 is connected between the corresponding current-stage register output terminal 12 and the corresponding lower-stage register input terminal 11, for example, the first electrode of the second transistor T2 is electrically connected to the corresponding current-stage register output terminal 12, and the second electrode of the second transistor T2 is electrically connected to the corresponding lower-stage register input terminal 11.
  • the plurality of first output terminals NT are electrically connected to the gates of the first to the last second transistors T2 in sequence.
  • each second cascade control signal can be adjusted, thereby controlling the on and off of each second transistor T2.
  • the second transistors T2 above the partition position can be controlled to remain on in the display frame, and the second transistors T2 below the partition position can be controlled to remain off in the display frame, thereby realizing multi-frequency display.
  • part of the second transistors T2 when part of the second transistors T2 need to be turned on and part of the second transistors T2 need to be turned off, at the junction of the on and off states, part of the second transistors T2 may be in a weak on state, and their switching state is not stable enough.
  • the inventor provides an improved embodiment, which is described below.
  • the first scan driving circuit 100 further includes: a third power supply terminal P1 and a fourth power supply terminal P2.
  • the third power supply terminal P1 is disposed at the far end of the driving IC
  • the fourth power supply terminal P2 is disposed at the near end of the driving IC.
  • the first scan driving circuit 100 also includes: a second resistor string.
  • the second resistor string includes a plurality of second resistors R2 connected in series between the third power supply terminal P1 and the fourth power supply terminal P2; a plurality of second output terminals PT are drawn out from the second resistor string, and the second output terminals PT output a third cascade control signal; the plurality of second output terminals PT are respectively connected to the plurality of cascade control modules 20, and at least one second resistor R2 is arranged between two adjacent second output terminals PT.
  • the cascade control signal includes each second cascade control signal and each third cascade control signal.
  • the potential of each third cascade control signal is the same; by setting the potential of the third power supply terminal P1 and the fourth power supply terminal P2 to be different, the potential of each third cascade control signal can be made different.
  • each cascade control module 20 further includes: a third transistor T3; the gate of the third transistor T3 is connected to the corresponding third cascade control signal, and the third transistor T3 and the corresponding second transistor T2 are connected in series between the corresponding current-level register output terminal 12 and the corresponding lower-level register input terminal 11, for example, the first electrode of the third transistor T3 is electrically connected to the second electrode of the corresponding second transistor T2, and the second electrode of the third transistor T3 is electrically connected to the corresponding lower-level register input terminal 11.
  • the plurality of second output terminals PT are sequentially connected to the first to the last second power supply terminal P1.
  • the gates of the three transistors T3 are electrically connected.
  • each second cascade control signal can be adjusted, thereby controlling the on and off of each second transistor T2; by adjusting the potential of the third power supply terminal P1 and the fourth power supply terminal P2, the potential value of each third cascade control signal can be adjusted, thereby controlling the on and off of each third transistor T3.
  • the third transistor T3 corresponding to the second transistor T2 in the weak conduction state is also set in the weak conduction state, and a stable switching state can be superimposed to ensure that the boundary between the conduction and the off of the cascade control module 20 is clear, so that the display partition position of the display panel in the first direction is clear.
  • the second transistor T2 and the third transistor T3 above the partition position can be controlled to remain turned on in the display frame, and the second transistor T2 and the third transistor T3 below the partition position can be controlled to remain turned off in the display frame, thereby achieving multi-frequency display.
  • each first resistor R1 is the same as that of each second resistor R2, a first resistor R1 is spaced between two adjacent first output terminals NT, and a second resistor R2 is spaced between two adjacent second output terminals PT, so as to determine the potential value of each control signal.
  • the resistor can be implemented by screen wiring.
  • the channel types of the second transistor T2 and the third transistor T3 are different, for example, the second transistor T2 is an N-type transistor, and the third transistor T3 is a P-type transistor.
  • the control process of the cascade control module 20 of this structure is as follows:
  • FIG18 is a schematic diagram of a power supply terminal voltage setting mode provided by an embodiment of the present application, which corresponds to a state where the display panel displays at the same refresh rate at the full screen position.
  • the potential VN1 of the first power supply terminal and the potential VN2 of the second power supply terminal maintain the same high potential VH, and each first output terminal NT is at the same high potential, ensuring that each second transistor T2 is turned on.
  • the potential VP1 of the third power supply terminal and the potential VP2 of the fourth power supply terminal maintain the same low potential VL, and each second output terminal PT is at the same low potential, ensuring that each third transistor T3 is turned on.
  • the switch control signal SW2 is always high, so that each fourth transistor T4 remains turned off, and each level of the first shift register 10 can perform level transmission normally.
  • FIG19 is a schematic diagram of another power supply terminal voltage setting mode provided in an embodiment of the present application, corresponding to the state in which the upper half of the display panel is displayed at a high refresh rate and the lower half is displayed at a low refresh rate.
  • the potential VN1 of the first power supply terminal is set to a higher potential greater than 0V
  • the potential VN2 of the second power supply terminal is set to a potential less than 0V.
  • the state presents a trend of a conduction zone, a weak conduction zone and a cut-off zone from the far end of the IC to the near end of the IC.
  • the potential VP1 of the third power supply terminal is set to a potential less than 0V with a larger absolute value
  • the potential VP2 of the fourth power supply terminal is set to a potential greater than 0V. From the far end of the IC to the near end of the IC, the potential of each second control terminal PT gradually increases, so that the conduction state of each third transistor T3 presents a trend of a conduction zone, a weak conduction zone and a cut-off zone from the far end of the IC to the near end of the IC.
  • the state boundary position of the second transistor T2 and the third transistor T3 can be controlled to be the same.
  • the superposition of the weak conduction state of the second transistor T2 and the third transistor T3 can make the cascade control module 20 present a stable switching state as a whole. Therefore, by controlling the potential of the four power supply terminals, the position where the cascade control module 20 starts to shut down can be accurately controlled, thereby controlling the frequency reduction display partition position of the display panel.
  • the switch control signal SW2 is a high potential
  • the fourth transistor T4 is controlled to be turned off, so that the first shift register in the area realizes the normal level transmission of the scanning signal.
  • the switch control signal SW2 is at a low potential, so that the fourth transistor T4 is turned on, and the auxiliary cut-off signal VD is transmitted to the next first shift register 10, interrupting the stage transmission of the scanning signal.
  • the above embodiments exemplarily provide a driving scheme for the first scanning driving circuit to perform partitioned multi-frequency display on the display panel.
  • the following describes the applicable scenario of the first scanning driving circuit when the potential of the conduction pulse output by the first shift register is different.
  • the conduction potential of the scanning signal output by the first shift register is a low potential.
  • the auxiliary cut-off signal is a high potential.
  • FIG20 is a schematic diagram of the structure of a pixel driving circuit provided in an embodiment of the present application.
  • the pixel driving circuit 200 includes: a driving module 41, a data writing module 42, a threshold compensation module 43 and a light emitting control module 44.
  • the driving module 41, the light emitting control module 44 and the light emitting device L are connected in series, the data writing module 42 is electrically connected to the first end of the driving module 41, and the threshold compensation module 43 is connected between the control end and the second end of the driving module 41.
  • the control end of the data writing module 42 is connected to the third control signal Sp1
  • the control end of the threshold compensation module 43 is connected to the second control signal S2
  • the control end of the light emitting control module 44 is connected to the light emitting control signal EM.
  • the pixel driving circuit 200 may also include a first reset module 45, which is electrically connected to the control end of the driving module 41; a second reset module 46, which is electrically connected to the anode of the light emitting device L; and a storage capacitor Cst, which is electrically connected to the control end of the driving module 41.
  • the control end of the first reset module 45 is connected to the first control signal S1
  • the control end of the second reset module 46 is connected to the third control signal Sp1.
  • the driving module 41 includes a driving transistor M11
  • the data writing module 42 includes a transistor
  • the threshold compensation module 43 includes a transistor M13
  • the light emitting control module 44 includes a transistor M15 and a transistor M16
  • the first reset module 45 includes a transistor M14
  • the second reset module 46 includes a transistor M17, forming a pixel driving circuit including seven transistors and a capacitor.
  • the gate of each transistor serves as the control terminal of each functional module.
  • each transistor can be a P-type transistor, prepared by a low temperature polysilicon (Low Temperature Poly-Silicon, LTPS) process, to form an LTPS pixel driving circuit.
  • LTPS Low Temperature Poly-Silicon
  • FIG21 is a driving timing diagram of a pixel driving circuit provided in an embodiment of the present application.
  • the driving process of the pixel driving circuit 200 includes:
  • the first control signal S1 is low
  • the third control signal Sp1 the second control signal S2 and the light emitting control signal EM are high
  • the transistor M14 is turned on
  • the initialization voltage signal Vref is transmitted to the gate of the driving transistor M11 through the transistor M14 to initialize the gate of the driving transistor M11.
  • the third control signal Sp1 and the second control signal S2 are at a low potential, and the first control signal S1 and the light emitting control signal EM are at a high potential.
  • the transistor M12 and the transistor M13 are both turned on.
  • the data voltage Vdata is transmitted to the gate of the driving transistor M11 via the transistor M12, the driving transistor M11 and the transistor M13 until the gate voltage of the driving transistor M11 reaches Vdata+Vth1, and the driving transistor M11 is turned off.
  • Vth1 is the threshold voltage of the driving transistor M11.
  • the transistor M17 is turned on, and the initialization voltage signal Vref is transmitted to the anode of the light emitting device L through the transistor M17 to initialize the anode of the light emitting device L.
  • the light-emitting control signal EM is at a low potential, and the first control signal S1, the third control signal Sp1 and the second control signal S2 are at a high potential.
  • the transistor M15 and the transistor M16 are both turned on.
  • the driving transistor M11 generates a driving current based on the first power supply signal VDD and the gate potential of the driving transistor M11 to drive the light-emitting device L to emit light.
  • the above driving process is the driving timing of the pixel driving circuit 200 in the refresh frame (Active frame).
  • the driving process of the pixel driving circuit 200 also includes an idle frame
  • the driving process in the idle frame includes:
  • the light-emitting control signal EM is at a high potential.
  • the transistor M15 and the transistor M16 are both turned off.
  • the connection path between the driving transistor M11 and the light-emitting device L is disconnected, and the light-emitting device L does not emit light.
  • the on pulse of the third control signal Sp1 may exist, which can realize the reset of the anode of the light-emitting device L and the first electrode of the driving transistor M11, so as to correct the characteristic drift of the light-emitting device L and the driving transistor M11 during the light-emitting process.
  • the light emitting control signal EM is at a low potential.
  • the driving transistor M11 generates a driving current based on the first power signal VDD and the potential stored at the gate of the driving transistor M11 in the refresh frame, and drives the light emitting device L to emit light.
  • the first control signal S1, the third control signal Sp1, the second control signal S2 and the light-emitting control signal EM are all high-frequency signals.
  • the first control signal S1 and the second control signal S2 are low-frequency signals
  • the light-emitting control signal EM is a high-frequency signal
  • the third control signal Sp1 can be a low-frequency signal or a high-frequency signal.
  • the first scanning drive circuit provided in the embodiment of the present application is used to control the data writing process of each pixel driving circuit.
  • the scanning signal output by the first shift register of each level can be used as the second control signal S2 required in the pixel driving circuit to control the process of writing the data voltage to the gate of the driving transistor M11.
  • Other control signals required by the pixel driving circuit can be provided by other scanning drive circuits in the display panel.
  • the display driving circuit can also include: a second scanning drive circuit for providing a third control signal Sp1 to each row of pixel driving circuits; a light emitting control drive circuit for providing a light emitting control signal EM to each row of pixel driving circuits; and a third scanning drive circuit for providing a first control signal S1 to each row of pixel driving circuits.
  • the third scanning drive circuit can adopt the same structure as the first scanning drive circuit. Further, since the first control signal S1 and the second control signal S2 have the same conduction potential and conduction pulse width, and the same frequency, for the same row of sub-pixels, the two control signals only have different conduction potential action times. Then, in the display driving circuit, the first scanning drive circuit can be reused as the third scanning drive circuit to reduce the panel frame.
  • first shift registers can be connected to the same row of pixel driving circuits, the previous stage first shift register provides the pixel driving circuit with a first control signal S1, and the next stage (the next stage or several stages, which can be set according to actual needs) first shift register provides the pixel driving circuit with a second control signal S2.
  • FIG22 is a schematic diagram of the structure of another display panel provided in an embodiment of the present application.
  • the connection relationship that the first scanning drive circuit may have with the pixel drive circuit when applied to the display panel is described below.
  • the pixel drive circuit 200 is arranged in the display area AA of the display panel, and each scanning drive circuit and the light emitting control drive circuit 400 are arranged in the non-display area NAA of the display panel.
  • Each drive circuit in the non-display area NAA provides a control signal to each row of pixel drive circuits 200 through a signal line.
  • the display panel is provided with a first scanning driving circuit 100, a second scanning driving circuit 700 and a light emitting control driving circuit 400.
  • the second scanning driving circuit 700 includes a plurality of second shift registers 70 arranged in cascade connection;
  • the light emitting control driving circuit 400 includes a plurality of third shift registers 40 arranged in cascade connection.
  • the register output end of the j-th first shift register 10 is electrically connected to the second scanning line LS2 connected to the j-th row pixel driving circuit 200, and the register output end of the j+b-th first shift register 10 is electrically connected to the j-th row pixel driving circuit 200.
  • the j-th level second shift register 70 is electrically connected to the third scan line LS3 connected to the j-th row pixel driving circuit 200
  • the j-th level third shift register 40 is electrically connected to the light emitting control signal line LEM connected to the j-th row pixel driving circuit 200.
  • Each first scan line LS1 provides a second control signal S2 to each row pixel driving circuit 200
  • each second scan line LS2 provides a first control signal S1 to each row pixel driving circuit 200
  • each third scan line LS3 provides a third control signal Sp1 to each row pixel driving circuit 200
  • each light emitting control signal line LEM provides a light emitting control signal EM to each row pixel driving circuit 200.
  • FIG23 is a schematic diagram of the structure of a first shift register provided in an embodiment of the present application.
  • the first shift register may adopt a circuit architecture including eight transistors and two capacitors.
  • the first shift register includes: transistors M1 to M8, capacitor C3 and capacitor C4.
  • FIG24 is a schematic diagram of the driving timing of a first shift register provided in an embodiment of the present application. Referring to FIG23 and FIG24, the driving process of the shift register includes:
  • the first clock signal CLK1 and the scan input signal SIN are at a low potential, and the second clock signal CLK2 is at a high potential.
  • Transistors M1 and M2 are turned on, and transistor M5 is turned off; transistor M8 is turned on; the low potential of the scan input signal SIN is transmitted to node N1 through transistor M1, turning on transistor M3; the low potential of the first clock signal CLK1 is transmitted to node N2 through transistor M3, and at the same time, the low potential of the second potential signal VGL is transmitted to node N2 through transistor M2, turning on transistor M7; the high potential of the first potential signal VGH is transmitted to the output end of the shift register through transistor M7; the low potential of node N1 is transmitted to node N3 through transistor M8, turning on transistor M6; the high potential of the second clock signal CLK2 is transmitted to the output end of the shift register through transistor M6. Therefore, in the first stage T31, the output signal SOUT of the shift register is at a high potential.
  • the second clock signal CLK2 is at a low potential, and the first clock signal CLK1 and the scan input signal SIN are both at a high potential.
  • Transistors M1 and M2 are turned off, transistor M5 is turned on, and transistor M8 remains turned on. Due to the storage function of capacitor C3, node N3 maintains the low potential of the previous stage, so that transistor M6 is turned on; the low potential of node N3 is transmitted to node N1 through transistor M8, so that transistor M3 is turned on.
  • the high potential of the first clock signal CLK1 is transmitted to node N2 through transistor M3, so that transistor M7 is turned off.
  • the low potential of the second clock signal CLK2 is output through transistor M6, and the output signal SOUT is at a low potential.
  • the first clock signal CLK1 is at a low potential
  • the second clock signal CLK2 and the scan input signal SIN are at a high potential.
  • Transistors M1 and M2 are turned on, transistor M5 is turned off, and transistor M8 is turned on.
  • the high potential of the scan input signal SIN is transmitted to node N1 through transistor M1, so that The transistor M3 is turned off; the high potential of the node N1 is transmitted to the node N3 through the transistor M8, so that the transistor M6 is turned off.
  • the low potential of the second potential signal VGL is transmitted to the node N2 through the transistor M2, so that the transistor M7 is turned on; the high potential of the first potential signal VGH is output through the transistor M7, and the output signal SOUT is a high potential.
  • the second clock signal CLK2 is at a low potential, and the first clock signal CLK1 and the scan input signal SIN are both at a high potential.
  • the transistors M1 and M2 are turned off, the transistor M5 is turned on, and the transistor M8 is turned on. Due to the storage function of the capacitor C4, the node N2 maintains the low potential of the previous stage, so that the transistors M4 and M7 are turned on.
  • the high potential of the first potential signal VGH is transmitted to the node N3 through the transistors M4, M5 and M8, so that the transistor M6 is turned off.
  • the high potential of the first potential signal VGH is output through the transistor M7, and the output signal SOUT is at a high potential.
  • the third stage T43 and the fourth stage T44 are repeated, and the output signal SOUT maintains a high potential until the scan input signal SIN becomes a low potential again.
  • the conduction potential of the scanning signal output by the first shift register is a high potential.
  • the auxiliary cut-off signal is a low potential.
  • FIG. 25 is a schematic diagram of the structure of another pixel driving circuit provided in an embodiment of the present application.
  • the difference from the pixel driving circuit in FIG. 20 is that in FIG. 25, the transistor M13 in the threshold compensation module 43 and the transistor M14 in the first reset module 45 are replaced by N-type transistors, such as IGZO transistors, to form a low-temperature polycrystalline oxide (LTPO) pixel driving circuit.
  • N-type transistors such as IGZO transistors
  • the pixel driving circuit can suppress the leakage of the gate of the driving transistor M11 during the light emission process, which is conducive to achieving a display with a lower refresh rate.
  • FIG26 is a driving timing diagram of another pixel driving circuit provided by an embodiment of the present application.
  • the only difference between FIG26 and FIG21 is that the first control signal S1 and the second control signal S2 are both transformed into inverted signals of the corresponding control signals in FIG21, that is, the on-state potentials of the first control signal S1 and the second control signal S2 are both high potentials.
  • the aforementioned analysis of the driving process of the pixel driving circuit is also applicable to the pixel driving circuit, which will not be repeated here. Also, the pixel driving circuit and each scanning driving circuit can still adopt the same connection relationship as in FIG22, which will not be repeated here.
  • FIG27 is a schematic diagram of the structure of another first shift register provided in an embodiment of the present application.
  • the first shift register may adopt a circuit architecture including ten transistors and three capacitors to generate an output signal with a high conduction potential.
  • the first shift register includes transistors M21 to M30 and capacitors C5 to C7.
  • FIG28 is a driving timing diagram of another first shift register provided in an embodiment of the present application. Referring to FIG27 and FIG28 , the driving process of the shift register includes:
  • the first clock signal CLK1 is at a low potential
  • the second clock signal CLK2 and the scan input signal SIN are at a high potential.
  • the transistors M21 and M23 are turned on, and the transistors M25 and M27 are turned off; the high potential of the scan input signal SIN is transmitted to the node N4 through the transistor M21, so that the transistors M22, M28 and M30 are turned off.
  • the low potential of the second potential signal VGL is transmitted to the node N5 through the transistor M23, so that the transistors M24 and M26 are turned on. Due to the storage effect of the capacitor C7, the node N6 maintains the high potential of the previous stage, so that the transistor M29 is turned off. Therefore, the output signal SOUT maintains the low potential of the previous stage.
  • the second clock signal CLK2 is at a low potential, and the first clock signal CLK1 and the scan input signal SIN are at a high potential.
  • the transistor M25 and the transistor M27 are turned on, and the transistor M21 and the transistor M23 are turned off. Due to the storage effect of the capacitor C6, the node N5 maintains the low potential of the previous stage, so that the transistor M24 and the transistor M26 are turned on.
  • the high potential of the first potential signal VGH is transmitted to the node N4 through the transistor M24 and the transistor M25, so that the transistor M22, the transistor M28 and the transistor M30 maintain the cut-off state.
  • the low potential of the second clock signal CLK2 is transmitted to the node N6 through the transistor M26 and the transistor M27, so that the transistor M29 is turned on, the first potential signal VGH is transmitted through the transistor M29, and the output signal SOUT becomes a high potential.
  • the first clock signal CLK1 is at a low potential
  • the second clock signal CLK2 and the scan input signal SIN are at a high potential.
  • the transistors M21 and M23 are turned on, and the transistors M25 and M27 are turned off.
  • the high potential of the scan input signal SIN is transmitted to the node N4 through the transistor M21, so that the transistors M22, M28 and M30 are turned off.
  • the low potential of the second potential signal VGL is transmitted to the node N5 through the transistor M23, so that the transistors M24 and M26 are turned on. Due to the storage effect of the capacitor C7, the node N6 maintains the low potential of the previous stage, so that the transistor M29 remains turned on, and the output signal SOUT maintains a high potential.
  • the first clock signal CLK1 is at a high potential
  • the second clock signal CLK2 and the scan input signal SIN are at a low potential.
  • Transistors M21 and M23 are turned off, and transistors M25 and M27 are turned on. Due to the storage function of capacitor C6, node N5 maintains the low potential of the previous stage, so that transistors M24 and M26 are turned on.
  • the high potential of the first potential signal VGH is transmitted to node N4 through transistors M24 and M25, so that transistors M22, M28 and M30 are maintained in the cut-off state.
  • the low potential of the second clock signal CLK2 is transmitted to node N6 through transistors M26 and M27, so that transistor M29 is turned on, and the high potential of the first potential signal VGH is transmitted to transistor M29 through transistor M29. transmission, the output signal SOUT maintains a high level.
  • the second clock signal CLK2 is at a high potential, and the first clock signal CLK1 and the scan input signal SIN are at a low potential.
  • the transistors M21 and M23 are turned on, and the transistors M25 and M27 are turned off.
  • the low potential of the scan input signal SIN is transmitted to the node N4 through the transistor M21, so that the transistors M22, M28 and M30 are turned on.
  • the low potential of the first clock signal CLK1 is transmitted to the node N5 through the transistor M22, so that the transistors M24 and M26 are turned on.
  • the transistor M27 since the transistor M27 is turned off, the low potential of the node N5 cannot be transmitted to the node N6.
  • the high potential of the first potential signal VGH is transmitted to the node N6 through the transistor M28, so that the transistor M29 is turned off.
  • the low potential of the second potential signal VGL is transmitted through the transistor M30, and the output signal SOUT becomes a low potential.
  • the first clock signal CLK1 is at a high potential, and the second clock signal CLK2 and the scan input signal SIN are at a low potential.
  • Transistors M25 and M27 are turned on. Due to the coupling effect of capacitor C5, as the second clock signal CLK2 becomes a low potential, the potential of node N4 becomes a lower potential than that in the fifth stage 25, so that transistors M22, transistors M28 and transistors M30 remain turned on; the high potential of the first clock signal CLK1 is transmitted to node N5 through transistor M22, so that node N5 becomes a high potential; the high potential of the first potential signal VGH is transmitted to node N6 through transistor M28, so that transistor M29 remains turned off.
  • transistor M27 is turned on in this stage, since the potential of node N5 has become a high potential, transistor M26 is turned off and does not pull down the potential of node N6, and node N6 can maintain a high potential.
  • the low potential of the second potential signal VGL is transmitted through transistor M30, and the output signal SOUT remains at a low potential.
  • the fifth stage T25 and the sixth stage T26 are repeated subsequently, and the shift register continues to output a low potential until the scan input signal SIN becomes a high potential again.
  • the corresponding relationship between the scan input signal SIN and the output signal SOUT can be adjusted by adjusting the cutoff pulse width of the scan input signal SIN.
  • the application scenarios of different pulse widths are exemplarily described below.
  • each scan drive circuit and the pixel drive circuit may further adopt the connection method as shown in FIG. 22, and the scan drive circuit may provide the pixel drive circuit with the drive waveform shown in FIG. 26.
  • the cut-off pulse width of the scan input signal SIN includes multiple on-pulses of the first clock signal CLK1
  • the cut-off pulses of the scan input signal SIN overlap with the cut-off pulses of the output signal SOUT.
  • the cut-off pulse width of the scan input signal SIN includes two on-pulses of the first clock signal CLK1
  • the output signal of the first register of the jth stage can be used as the first control signal S1 of the pixel driving circuit of the jth row
  • the output signal of the first register of the j+3th stage can be used as the second control signal S2 of the pixel driving circuit of the jth row.
  • the situation where the cut-off pulses of the scan input signal SIN and the output signal SOUT overlap as shown in FIG. 28 is also applicable to the connection method shown in FIG. 22.
  • the drive timing provided by each scan drive circuit to the pixel circuit is shown in FIG. 29.
  • the on-pulses of the first control signal S1 and the second control signal S2 overlap.
  • both the transistor M13 and the transistor M14 are turned on, and the initialization voltage signal Vref is transmitted to the gate of the driving transistor M11 through the transistor M14, and then continues to be transmitted to the second pole of the driving transistor M11 through the transistor M13, so as to realize the initialization of the second pole of the driving transistor M11 and improve the initialization effect.
  • the data writing stage T52 is still carried out after the initialization stage T51 ends, that is, the on-pulse of the third control signal Sp1 is located after the on-pulse of the first control signal S1 ends, and overlaps with the on-pulse of the second control signal S2.
  • the structures of the shift registers given in the above embodiments are not intended to limit the present application.
  • the first shift register may be implemented by using a shift register circuit of any existing structure.
  • the above-mentioned embodiments exemplarily provide a solution for partitioning and multi-frequency driving of the display panel in the first direction, that is, the upper and lower partitions and multi-frequency driving, but it is not intended to limit the present application.
  • the display panel can also support split-screen driving in the second direction (that is, the sub-pixel row direction), that is, left and right partitions and multi-frequency driving, to achieve more flexible control of the display panel.
  • the first direction intersects with the second direction.
  • FIG30 is a schematic diagram of the structure of another display panel provided in an embodiment of the present application.
  • the non-display area of the display panel includes two non-display sub-areas NAA1 and NAA2; the two non-display sub-areas NAA1 and NAA2 are respectively arranged on both sides of the display area AA along the second direction.
  • At least one first scan drive circuit includes two first scan drive circuits 1001 and 1002.
  • the first-side first scan drive circuit 1001 is arranged in the first non-display sub-area NAA1
  • the second-side first scan drive circuit 1002 is arranged in the second non-display sub-area NAA2.
  • the corresponding-stage first shift registers 10 in the first-side first scan drive circuit 1001 and the second-side first scan drive circuit 1002 are connected to the same first scan line.
  • each first scan line in at least some of the first scan lines includes at least two sub-scan lines.
  • the display driving circuit also includes: at least one split screen control module 50, The split screen control module 50 is arranged in the display area AA.
  • Each split screen control module 50 may include a plurality of split screen switch units 51; the plurality of split screen switch units 51 in the same split screen control module 50 respectively correspond to each first scan line composed of sub-scan lines.
  • Each split screen switch unit 51 is connected between two adjacent sub-scan lines LS11 and LS12 in the same first scan line.
  • the first side first scan drive circuit 1001 and the second side first scan drive circuit 1002 respectively transmit scan signals to the sub-scan lines on both sides of the split screen switch unit 51.
  • the plurality of split screen switch units 51 on the same scan line are arranged in sequence along the second direction.
  • the number of split screen switch units in the off state on the same first scan line is less than or equal to 1.
  • the off split screen switch unit 51 divides the first scan line into two parts, and the sub-scan lines on both sides are transmitted with scan signals by different first scan drive circuits to ensure the normal drive of the sub-pixels on both sides.
  • the cascade control signal connected to the first side first scan drive circuit 1001 is a first side cascade control signal
  • the cascade control signal connected to the second side first scan drive circuit 1002 is a second side cascade control signal
  • the first side cascade control signal is different from the second side cascade control signal
  • the switch control signal connected to the first side first scan drive circuit 1001 is a first side switch control signal SW21
  • the switch control signal connected to the second side first scan drive circuit 1002 is a second side switch control signal SW22
  • the first side switch control signal SW21 is different from the second side switch control signal SW22.
  • the sub-display areas on both sides of the split-screen control module 50 can be displayed at different refresh frequencies and/or different upper and lower partition positions.
  • the control signals connected to the first scan drive circuits 1001 and 1002 on both sides can be provided by the driver IC 60 respectively.
  • the working process of the split screen control module 50 includes:
  • all the split-screen switch units 51 corresponding to the sub-pixels in the row are controlled to be turned on, and the scanning signals output by the first shift registers 10 on the left and right sides are connected together to realize bilateral driving of the sub-pixels in the row, so as to increase the driving capability of the scanning driving circuit, reduce the uneven display of the split-screen position due to RC delay during unilateral driving, avoid the risk of displaying the split-screen boundary, that is, avoid the phenomenon of brightness difference between the left and right half screens.
  • all the split-screen switch units 51 can be controlled to be turned on.
  • the split-screen switch unit 51 corresponding to the left and right split-screen positions of the sub-pixels in the row is turned off, and the other split-screen switch units in the row are turned on.
  • the scan signal on the left side of the split-screen position is provided by the first first scan drive circuit 1001
  • the scan signal on the right side of the split-screen position is provided by the second first scan drive circuit 1002, so that a drive mode with different refresh rates for the left and right screens can be realized.
  • FIG31 is a schematic diagram of the structure of another display panel provided by an embodiment of the present application.
  • all split-screen switch units 51 in the same split-screen control module 50 are connected to the same split-screen control signal SW3.
  • different split-screen control modules 50 are connected to different split-screen control signals; at most one split-screen control module 50 is turned off at the same time, and other split-screen control modules 50 are turned on.
  • the split-screen control signal SW3 can be provided by the driver IC 60. In one frame of display, the split-screen control signal SW3 can perform a potential jump or not perform a potential jump.
  • the split-screen control signal SW3 does not perform a potential jump in one frame of display, the left and right split-screen states of the display panel in the frame of display remain unchanged; when the split-screen control signal SW3 performs a potential jump in one frame of display, the left and right split-screen states of the display panel in the frame of display change, for example, the left and right split-screens are split for a period of time, and the left and right split-screens are not split at other times.
  • the following takes the display driving circuit including a split-screen control module 50 as an example to explain the driving mode of the display panel. It should be noted that when the setting position of the split screen switch unit 51 is determined, the left and right split screen positions of the display panel are fixed. In the following embodiments, the split screens with fixed positions are indicated by solid lines, and the split screens with adjustable positions are indicated by dotted lines.
  • the first scan line includes a first sub-scan line LS11 and a second sub-scan line LS12, and the first sub-scan line LS11 and the second sub-scan line LS12 are respectively connected to different first scan drive circuits.
  • the display drive circuit includes a split screen control module 50; each split screen control unit 51 is electrically connected to the corresponding first sub-scan line LS11 and the second sub-scan line LS12.
  • the first side first scan drive circuit 1001 is connected to the first side first cascade control signal SW11 and the first side switch control signal SW21
  • the second side first scan drive circuit 1002 is connected to the second side first cascade control signal SW12 and the second side switch control signal SW22.
  • the display panel can be flexibly controlled to use single-side drive or double-side drive in different scene modes.
  • the following takes the split screen switch unit responding to low potential conduction, and the cascade control module and the auxiliary cut-off module responding to high potential conduction as an example to explain each display mode.
  • FIG32 is a driving timing diagram of another display panel provided by an embodiment of the present application, which corresponds to a display mode of a full-screen uniform refresh frequency of the display panel.
  • the split-screen control signal SW3 maintains a low potential, and controls each split-screen switch unit 51 to remain turned on, so as to realize bilateral driving of the entire display panel.
  • the output states of the first scan drive modules on both sides remain consistent.
  • the first cascade control signals SW11 and SW12 maintain a high potential
  • the switch control signals SW21 and SW22 maintain a low potential, so that both first scan drive circuits can realize a step-by-step shift output of the on-potential of the scan signal.
  • the display frame When the full screen is refreshed at a low frequency, the display frame also includes a hold frame, as can be seen in display frame F2, the first cascade control signals SW11 and SW12 maintain a low potential, and the switch control signals SW21 and SW22 maintain a high potential.
  • the scan input signals connected to the two first scan drive circuits can maintain a cut-off potential, and the two first scan drive circuits can maintain a cut-off potential.
  • the stage transmission of a scanning driving circuit is cut off, and each scanning signal maintains the cut-off potential.
  • the first first scan drive circuit 1001 provides a scan signal according to the drive requirements of the left sub-display area
  • the second first scan drive circuit 1002 provides a scan signal according to the drive requirements of the right sub-display area.
  • the left sub-display area is displayed at a refresh frequency f1
  • the right sub-display area is displayed at a refresh frequency f1/2.
  • the first side first cascade control signal SW11 can maintain a high potential
  • the first side switch control signal SW21 can maintain a low potential, controlling the left sub-display area to refresh in each display frame.
  • the first cascade control signal SW12 on the second side maintains a high potential in odd frames and a low potential in even frames
  • the second side switch control signal SW22 maintains a low potential in odd frames and a high potential in even frames, controlling the right sub-display area to refresh only in odd frames.
  • the split-screen control signal SW3 does not serve as a limitation to the present application.
  • the split-screen control signal can control the split-screen switch unit to be turned on.
  • the split-screen control signal SW3 can be converted into a conduction potential to control the split-screen switch unit to be turned on, and during the scan time of the pixel drive circuit of the row, a bilateral drive of the pixel drive circuit of the row is formed to improve the data writing effect.
  • a bilateral drive of the pixel drive circuit of the row is formed to improve the data writing effect.
  • the split-screen control signal SW3 can be set to a low potential accordingly.
  • Figure 35 is a driving timing diagram of another display panel provided in an embodiment of the present application, corresponding to a display mode in which the display panel performs multi-frequency display only in the first direction, that is, a multi-frequency display mode of upper and lower split screens.
  • the split screen control signal SW3 maintains a low potential, controls each split screen switch unit 51 to remain turned on, and realizes bilateral driving of the entire display panel.
  • the output states of the first scanning drive modules on both sides remain consistent.
  • the upper sub-display area is displayed at a refresh frequency of f1
  • the lower sub-display area is displayed at a refresh frequency of f1/2.
  • the first cascade control signals SW11 and SW12 maintain a high potential, and the switch control signals SW21 and SW22 maintain a low potential, and all sub-pixels in the control display area are refreshed.
  • the first cascade control signals SW11 and SW12 before the scanning time of the previous row of sub-pixels at the target partition position arrives, the first cascade control signals SW11 and SW12 maintain a high potential, and the switch control signals SW21 and SW22 maintain a low potential, so that all sub-pixels in the upper sub-display area are controlled to be refreshed; when the scanning time of the previous row of sub-pixels at the target partition position arrives until the end of this frame, the first cascade control signals SW11 and SW12 maintain a low potential, and the switch control signals SW21 and SW22 maintain a low potential.
  • the control signals SW21 and SW22 are kept at high potential, and the sub-pixels in the lower sub-display area are controlled not to be refreshed.
  • the display frame F1 and the display frame F2 are used as a cycle, and the cycle is repeated, so that the sub-pixels in the upper sub-display area are refreshed in each display frame, and the sub-pixels in the lower sub-display area are refreshed only in odd frames.
  • FIG36 is a driving timing diagram of another display panel provided by an embodiment of the present application, corresponding to a display mode in which the display panel performs multi-frequency display in both the first direction and the second direction, such as a multi-frequency display of four split screens, top, bottom, left and right.
  • the split screen control signal SW3 can always maintain a high potential, control each split screen switch unit 51 to remain off, and realize the unilateral drive of the left and right sub-display areas, so as to reduce the potential jump of the split screen control signal SW3 and simplify the control logic.
  • the split screen control signal SW3 can be set to maintain a low potential during the scanning time of the corresponding row pixel driving circuit.
  • the upper left sub-display area is displayed at a refresh frequency of f1
  • the lower left sub-display area is displayed at a refresh frequency of f1/4
  • the upper right sub-display area is displayed at a refresh frequency of f1/2
  • the lower right sub-display area is displayed at a refresh frequency of f1/8.
  • the driving mode of the first first scanning driving circuit 1001 is based on a cycle of 4 display frames, and the sub-pixels in the upper left sub-display area are refreshed in each display frame through the first side first cascade control signal SW11 and the first side switch control signal SW21, and the sub-pixels in the lower left sub-display area are refreshed only in the first display frame of each cycle.
  • the driving mode of the second first scanning driving circuit 1002 is based on a cycle of 8 display frames, and the sub-pixels in the upper right sub-display area are refreshed in odd frames through the second side first cascade control signal SW12 and the second side switch control signal SW22, and the sub-pixels in the lower right sub-display area are refreshed only in the first display frame of each cycle.
  • FIG37 is a driving timing diagram of another display panel provided by an embodiment of the present application, corresponding to a display mode in which the display panel performs multi-frequency display in both the first direction and the second direction, such as a three-screen multi-frequency display in which the upper left and right sides are not split, and the lower left and right sides are split.
  • the split screen control signal SW3 performs a potential jump
  • the potential jump time is coordinated with the potential jump time of the first cascade control signal and the switch control signal.
  • the upper sub-display area is displayed at a refresh frequency f1
  • the lower left sub-display area is displayed at a refresh frequency f1/2
  • the lower right sub-display area is displayed at a refresh frequency f1/4.
  • the split screen control signal SW3 maintains a low potential, controls each split screen switch unit 51 to remain turned on, and realizes the bilateral driving of the upper sub-display area; during the driving process of the upper sub-display area, the outputs of the two first scanning drive circuits remain consistent, for example, the upper sub-display area is controlled to be refreshed in each display frame.
  • the split screen control signal SW3 maintains a high potential, controls each split screen switch unit 51 to remain turned off, and realizes the unilateral driving of the lower left and lower right sub-display areas; during the driving process of the two lower sub-display areas, the first side first cascade control signal SW11 and the first side switch control signal SW21 are used to control each sub-pixel of the lower left sub-display area to be refreshed in odd frames, and the sub-pixels of the lower left sub-display area are refreshed in odd frames.
  • the second-side first cascade control signal SW12 and the second-side switch control signal SW22 control each sub-pixel in the lower right sub-display area to be refreshed once every 4 display frames.
  • the display mode in which the upper left and right sub-display areas are not split can also be achieved by controlling the refresh frequencies of the upper left and upper right sub-display areas to be consistent in the four-split screen mode.
  • the split screen switch unit is controlled to be turned on, which can alleviate the display unevenness caused by unilateral driving and improve the display effect of the upper sub-display area.
  • the split screen control signal SW3 can also be controlled to maintain a low potential in the display frame in which all three sub-display areas are refreshed, so that the entire display screen can be driven on both sides to improve the display effect.
  • FIG38 is a driving timing diagram of another display panel provided in an embodiment of the present application, corresponding to a display mode in which the display panel performs multi-frequency display in both the first direction and the second direction, such as a three-screen multi-frequency display in which the upper side is split into left and right, and the lower side is not split into left and right.
  • the driving process in this mode is similar to that in FIG37.
  • the split screen control signal SW3 performs a potential jump.
  • the upper left sub-display area is displayed at a refresh frequency of f1
  • the upper right sub-display area is displayed at a refresh frequency of f1/2
  • the lower sub-display area is displayed at a refresh frequency of f1/4.
  • the split screen control signal SW3 maintains a high potential, controls each split screen switch unit 51 to remain turned off, and realizes the unilateral driving of the upper left and upper right sub-display areas; during the driving process of the upper two sub-display areas, the first side first cascade control signal SW11 and the first side switch control signal SW21 are used to control each sub-pixel in the upper left sub-display area to refresh every frame, and the second side first cascade control signal SW12 and the second side switch control signal SW22 are used to control each sub-pixel in the upper right sub-display area to refresh in odd frames.
  • the split screen control signal SW3 maintains a low potential, controls each split screen switch unit 51 to remain turned on, and realizes the bilateral driving of the lower sub-display area; during the driving process of the lower sub-display area, the outputs of the two first scanning drive circuits remain consistent, for example, each sub-pixel in the lower sub-display area is controlled to refresh once every 4 display frames.
  • the split-screen mode of the display panel can be controlled, so as to flexibly control the use of single-sided drive or double-sided drive in different scenario modes.
  • the upper and lower split screens are used as examples for explanation, but this is not a limitation of the present application.
  • the number of upper and lower split screens of the display panel and the refresh frequency of each partition can be set according to requirements.
  • the frequency combinations given in the above-mentioned embodiments are only for illustration. The actual frequency combinations can be defined according to the requirements and are not limited to the several cases shown in the figure.
  • the above embodiments exemplarily provide a control scheme in which the split screen control unit 51 corresponds to the first scan line, but this is not intended to limit the present application.
  • the split-screen multi-frequency display mode in FIG38 can also set the split-screen control unit 51 only at the position where the left and right screen split is required, and set the first scan line to be unsegmented at the position where the left and right screen split is not required.
  • the length of the first sub-scan line LS11 is the same as the length of the second sub-scan line LS12, so that the characteristic parameters such as parasitic resistance of the two sub-scan lines are the same, so that the charging time of the sub-pixels on the left and right sides is consistent, thereby improving the display uniformity of the display panel.
  • the above embodiments exemplarily provide a driving scheme of the display panel when one split-screen control module is set, but it is not intended to limit the present application.
  • multiple split-screen control modules may be set in the display panel, and the positions of the left and right split screens of the display panel may be made more flexible by controlling the on and off of each split-screen control module.
  • the following description takes the setting of two split-screen control modules as an example.
  • FIG39 is a schematic diagram of the structure of another display panel provided by an embodiment of the present application.
  • the first scan line includes three sub-scan lines, namely the third sub-scan line LS13, the fourth sub-scan line LS14 and the fifth sub-scan line LS15;
  • the display driving circuit includes: a first split screen control module 501 and a second split screen control module 502 arranged in sequence along the second direction.
  • the third sub-scan line LS13 is connected to the first side first scan driving circuit 1001
  • the first split screen control module 501 is connected between the third sub-scan line LS13 and the fourth sub-scan line LS14
  • the second split screen control module 502 is connected between the fourth sub-scan line LS14 and the fifth sub-scan line LS15
  • the fifth sub-scan line LS15 is connected to the second side first scan driving circuit 1002.
  • the split screen control signal includes a first split screen control signal SW31 and a second split screen control signal SW32. Among them, the first split screen control module 501 is connected to the first split screen control signal SW31, and the second split screen control module 502 is connected to the second split screen control signal SW32.
  • FIG40 is a driving timing diagram of another display panel provided by an embodiment of the present application, corresponding to a display mode in which the display panel performs multi-frequency display in both the first direction and the second direction, such as a multi-frequency display of four split screens in upper, lower, left and right directions.
  • the positions of the left and right split screens are optional for sub-pixels in different rows.
  • the first split screen control signal SW31 maintains a high potential
  • the second split screen control signal SW32 maintains a low potential, so that the first split screen control module 501 is turned off and the second split screen control module 502 is turned on, so the upper left and right split screen positions are located at the set position of the first split screen control module 501.
  • the first split screen control signal SW31 maintains a low potential
  • the second split screen control signal SW32 maintains a high potential, so that the first split screen control module 501 is turned on and the second split screen control module 502 is turned off, so the lower left and right split screen positions are located at the set position of the split screen control module 502.
  • the left and right partition positions of the display panel can be adjusted.
  • the specific implementation process is: in the same display frame, during the data writing process of the pixel driving circuit of some rows, the first split screen control module 501 is controlled to be turned on, and the second split screen control module 502 is turned off. During the data writing process of the pixel driving circuits of other rows, the first split-screen control module 501 is controlled to be turned off and the second split-screen control module 502 is controlled to be turned on.
  • the split-screen switch unit 51 includes: a fifth transistor T5; the gate of the fifth transistor T5 is connected to the split-screen control signal, and the first electrode and the second electrode of the fifth transistor T5 are respectively connected to two adjacent sub-scanning lines in the same first scan line.
  • the fifth transistor T5 can be a switching transistor so that its impedance is small when it is turned on, reducing the burden on the driving circuit caused by the setting of the fifth transistor T5.
  • the width-to-length ratio and other dimensions of the fifth transistor T5 can be designed with reference to the switching transistor in the pixel driving circuit.
  • each split-screen control module 50 when a plurality of split-screen control modules 50 are provided in the display driving circuit, transistors of the same channel type may be used in each split-screen control module 50, and each split-screen control module 50 is connected to a different split-screen control signal.
  • the two split-screen control modules 50 include transistors of different channel types, for example, as shown in FIG41 , the first split-screen control module 501 includes a P-type transistor, the second split-screen control module 502 includes an N-type transistor, and the switch states of the two split-screen control modules 50 are opposite, the two split-screen control modules 501 and 502 may be connected to the same split-screen control signal SW3 to reduce the output ports of the driver IC and reduce costs.
  • driver ICs 60 in the display panel can be set according to actual needs, for example, two driver ICs 60 are set as shown in FIG. 39 , or one driver IC 60 is set as shown in FIG. 41 .
  • the split-screen control module is set between each segment of the sub-scanning lines of the first scan line, but this is not a limitation of the present application.
  • the second scan line can also be set to include multiple sub-scanning lines, and corresponding to the connection method of the first scan line, a split-screen control module is also set between each sub-scanning line of the second scan line.
  • the embodiment of the present application also provides a control method of a display driving circuit, which is used to control the display driving circuit provided by any embodiment of the present application, and has corresponding beneficial effects.
  • the control method of the display driving circuit includes:
  • Obtaining a target partition position of the display panel in a first direction ie, a column direction of sub-pixels
  • the cascade control signal in each frame display is determined, and the switch state of the cascade control module in each frame display is controlled based on the cascade control signal.
  • the cascade control signal can control whether the conduction potential of the scanning signal output by the first shift register can be transmitted step by step by controlling the switch state of the cascade control module.
  • the setting of multiple cascade control modules makes the transmission of the conduction potential of the scanning signal in each display frame cut off.
  • the position is adjustable, so that the frequency reduction display partition position of the display panel is adjustable, so as to enrich the display function of the display panel and make the driving process of the display panel more flexible.
  • At least one cascade control module includes multiple cascade control modules, and the display panel includes at least one target partition position.
  • the display process of the display panel includes multiple types of display frames; the multiple types of display frames include a first refresh frame and at least one type of second refresh frame; the types of the second refresh frames correspond to the target partition positions respectively.
  • the cascade control signal controls all cascade control modules to remain turned on. Therefore, in this type of display frame, the display panel performs full-screen refresh.
  • the cascade control signal controls the shutdown time of all cascade control modules, or controls the cascade control module at a preset position to shut down, so that the display panel displays based on the target partition position corresponding to the second refresh frame, and the sub-pixels above the target partition position are in the refresh frame, and the sub-pixels below the target partition position are in the hold frame.
  • the embodiment of the present application also provides a display device, including a display driving circuit as provided in any embodiment of the present application, and having corresponding beneficial effects.
  • the display device includes a display panel provided in any of the above embodiments, and the display driving circuit is arranged in the display panel, and the display panel can be a display panel of the type of active matrix organic light emitting diode panel or micro light emitting diode display panel.
  • the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television or a monitor.

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Abstract

一种显示驱动电路及其控制方法、显示装置。显示驱动电路包括：至少一个第一扫描驱动电路（100）；至少一个第一扫描驱动电路（100）包括：级联设置的多个第一移位寄存器（10），第一移位寄存器（10）包括寄存器输入端（11）和寄存器输出端（12），多个第一移位寄存器（10）设置为输出多个扫描信号；至少一个级联控制模块（20），至少一个级联控制模块（20）连接于本级寄存器输出端（12）和下级寄存器输入端（11）之间，且至少一个级联控制模块（20）接入级联控制信号，至少一个级联控制模块（20）响应于级联控制信号控制扫描信号的导通电位从本级寄存器输出端（12）向下级寄存器输入端（11）的传输，以实现显示面板在第一方向上的多频显示。

Description

显示驱动电路及其控制方法、显示装置
本申请要求在2022年11月29日提交中国专利局、申请号为202211518363.5的中国专利申请的优先权，以上申请的全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种显示驱动电路及其控制方法、显示装置。
背景技术
随着显示技术的发展，显示面板的应用场景越来越多，用户对显示面板的显示需求也越来越多样化。对于用户对终端产品多应用同时显示的需求，显示屏中部分界面(例如游戏界面)需要进行高频显示以保证画面流畅性，部分界面采用低频即可满足显示需求，此部分期望采用低频显示以降低产品功耗。然而相关技术中的显示驱动电路，仅支持显示面板全屏切换频率，不能满足用户对终端产品在一个屏幕内显示多种场景的需求，无法在一个屏幕内实现分区多频显示。
发明内容
本申请提供了一种显示驱动电路及其控制方法、显示装置，以使显示面板具备分区多频显示功能。
为实现上述技术目的，本申请实施例提供了：
一种显示驱动电路，包括：至少一个第一扫描驱动电路；
所述至少一个第一扫描驱动电路包括：
级联设置的多个第一移位寄存器，所述第一移位寄存器包括寄存器输入端和寄存器输出端，所述多个第一移位寄存器设置为输出多个扫描信号；
至少一个级联控制模块，所述至少一个级联控制模块连接于本级寄存器输出端和下级寄存器输入端之间，且所述至少一个级联控制模块接入级联控制信号，所述至少一个级联控制模块响应于所述级联控制信号控制所述扫描信号的导通电位从本级寄存器输出端向下级寄存器输入端的传输，以实现显示面板在第一方向上的多频显示。
可选地，所述至少一个级联控制模块包括多个级联控制模块，所述多个级联控制模块与所述至少一个第一扫描驱动电路中的至少部分第一移位寄存器分 别对应设置，每个所述级联控制模块分别设置于所述至少部分第一移位寄存器中对应的本级第一移位寄存器和对应的下级第一移位寄存器之间；所述级联控制信号通过控制所述级联控制模块的开关状态，调整一帧显示中扫描信号的导通电位向下级寄存器输入端的传输被切断的位置。
可选地，所述级联控制信号包括：第一级联控制信号；
所述级联控制模块包括：第一晶体管，所述第一晶体管的第一极与对应的本级寄存器输出端电连接，所述第一晶体管的第二极与对应的下级寄存器输入端电连接；所述第一晶体管的栅极接入所述第一级联控制信号；
优选地，根据所述第一级联控制信号在一帧显示中的电位跳变时间，确定所述级联控制模块在一帧显示中的关断时间，从而确定显示面板在第一方向上降频显示的分区位置。
可选地，所述级联控制信号包括：与所述多个级联控制模块分别对应的多个第二级联控制信号；
所述级联控制模块包括：第二晶体管；所述第二晶体管的栅极接入对应的所述第二级联控制信号，所述第二晶体管连接在对应的本级寄存器输出端和对应的下级寄存器输入端之间；
优选地，所述至少一个第一扫描驱动电路还包括：第一电源端和第二电源端；以及，所述至少一个第一扫描驱动电路还包括：
第一电阻串，包括串联连接在所述第一电源端和所述第二电源端之间的多个第一电阻；所述第一电阻串中引出多个第一输出端，所述第一输出端输出所述第二级联控制信号；多个所述第一输出端与多个所述级联控制模块分别对应连接，相邻两个所述第一输出端之间设置有至少一个第一电阻。
可选地，所述级联控制信号还包括：与所述多个级联控制模块分别对应的多个第三级联控制信号；
所述级联控制模块中还包括：第三晶体管；所述第三晶体管的栅极接入对应的所述第三级联控制信号，所述第三晶体管和对应的所述第二晶体管串联连接在对应的本级寄存器输出端和对应的下级寄存器输入端之间；
优选地，所述至少一个第一扫描驱动电路还包括：第三电源端和第四电源端；以及，所述至少一个第一扫描驱动电路还包括：
第二电阻串，包括串联连接在第三电源端和第四电源端之间的多个第二电阻；所述第二电阻串中引出多个第二输出端，所述第二输出端输出所述第三级联控制信号；多个所述第二输出端与多个所述级联控制模块分别对应连接，相 邻两个所述第二输出端之间设置有至少一个第二电阻；
优选地，在一帧显示中，预设位置的级联控制模块响应于所述级联控制信号关断，以控制显示面板在第一方向上降频显示的分区位置；对所述预设位置的调整，基于对所述第一电源端、所述第二电源端、所述第三电源端和所述第四电源端的电位调整实现。
可选地，所述至少一个第一扫描驱动电路，还包括：
至少一个辅助切断模块，所述至少一个辅助切断模块与所述至少一个级联控制模块对应设置；所述辅助切断模块的控制端接入开关控制信号，所述辅助切断模块的输入端接入辅助切断信号，所述辅助切断模块的输出端与所述辅助切断模块对应的级联控制模块连接同一寄存器输入端；
优选地，所述至少一个辅助切断模块包括多个辅助切断模块，所述至少一个级联控制模块包括多个级联控制模块，所述多个辅助切断模块与所述多个级联控制模块分别对应设置，所述辅助切断模块接入同一开关控制信号；根据所述开关控制信号在一帧显示中的电位跳变时间，确定所述辅助切断模块在一帧显示中的导通时间；
优选地，每相邻的两个所述第一移位寄存器之间均设置有一个级联控制模块和一个辅助切断模块。
可选地，所述本级第一移位寄存器和下级第一移位寄存器分别为第i级第一移位寄存器和第i+a级第一移位寄存器，i和a均为正整数；
在第i级第一移位寄存器输出第i级扫描信号的导通电位，且第i+a级第一移位寄存器输出第i+a级扫描信号的导通电位的情况下，在第i级第一移位寄存器输出第i级扫描信号的导通电位的阶段，所述级联控制信号控制所述第i级第一移位寄存器和所述第i+a级第一移位寄存器之间的级联控制模块导通，且所述开关控制信号控制所述第i级第一移位寄存器和所述第i+a级第一移位寄存器之间的辅助切断模块关断；
在第i级第一移位寄存器输出第i级扫描信号的导通电位，且第i+a级第一移位寄存器输出第i+a级扫描信号的截止电位的情况下，在第i级第一移位寄存器输出第i级扫描信号的导通电位的阶段，所述级联控制信号控制所述第i级第一移位寄存器和所述第i+a级第一移位寄存器之间的级联控制模块关断，且所述开关控制信号控制所述第i级第一移位寄存器和所述第i+a级第一移位寄存器之间的辅助切断模块导通。
可选地，所述显示驱动电路还包括：第一电位信号线和第二电位信号线； 所述第一电位信号线设置为向所述多个第一移位寄存器提供第一电位信号，所述第二电位信号线设置为向所述多个第一移位寄存器提供第二电位信号；
当所述第一电位信号的电位为截止电位时，所述第一电位信号复用为所述辅助切断信号；当所述第二电位信号的电位为所述截止电位时，所述第二电位信号复用为所述辅助切断信号。
可选地，所述级联控制信号包括：第一级联控制信号；所述级联控制模块包括：第一晶体管，所述第一晶体管的栅极接入所述第一级联控制信号，所述第一晶体管的第一极与对应的本级寄存器输出端电连接，所述第一晶体管的第二极与对应的下级寄存器输入端电连接；
所述辅助切断模块包括：第四晶体管，所述第四晶体管的栅极接入所述开关控制信号，所述第四晶体管的第一极接入所述辅助切断信号，所述第四晶体管的第二极与对应的下级寄存器输入端电连接。
可选地，所述第一晶体管与所述第四晶体管的沟道类型相同，所述第一级联控制信号和所述开关控制信号的相位相反；或者，
所述第一晶体管与所述第四晶体管的沟道类型不同，所述第一级联控制信号复用为所述开关控制信号。
可选地，所述第一晶体管与所述第四晶体管的沟道类型相同，所述第一级联控制信号复用为所述辅助切断信号。
可选地，所述显示驱动电路，还包括：多个像素驱动电路和多条第一扫描线，所述多个像素驱动电路呈阵列排布，每行像素驱动电路与所述多条第一扫描线中的至少一条第一扫描线电连接；所述至少一个第一扫描驱动电路中的寄存器输出端与所述第一扫描线电连接。
可选地，所述像素驱动电路包括：驱动模块、数据写入模块、阈值补偿模块和发光控制模块；
所述驱动模块连接于所述发光控制模块和发光器件之间，所述驱动模块设置为产生驱动电流；所述数据写入模块与所述驱动模块的第一端电连接，所述数据写入模块设置为将数据电压传输至所述驱动模块；所述阈值补偿模块连接于所述驱动模块的控制端和第二端之间，所述阈值补偿模块设置为补偿所述驱动模块的阈值电压；所述第一扫描线与对应行像素驱动电路中阈值补偿模块的控制端电连接；
优选地，所述像素驱动电路还包括：第一复位模块，与所述驱动模块的控制端电连接，所述第一复位模块设置为对所述驱动模块的控制端进行复位；所 述显示驱动电路还包括：多条第二扫描线，所述第二扫描线与对应行像素驱动电路中第一复位模块的控制端电连接；
优选地，所述至少一个第一扫描驱动电路中的寄存器输出端与所述第二扫描线电连接；其中，第j行像素驱动电路连接的第二扫描线与第j级寄存器输出端电连接，第j行像素驱动电路连接的第一扫描线与第j+b级寄存器输出端电连接；其中，j，b均为正整数。
可选地，所述至少一个第一扫描驱动电路包括第一侧第一扫描驱动电路和第二侧第一扫描驱动电路，所述第一侧第一扫描驱动电路和所述第二侧第一扫描驱动电路分别设置于所述多个像素驱动电路的两侧；所述第一侧第一扫描驱动电路和所述第二侧第一扫描驱动电路中对应级的第一移位寄存器连接同一第一扫描线；
所述多条第一扫描线中的至少部分第一扫描线中的每条第一扫描线均包括至少两条子扫描线；
所述显示驱动电路还包括：至少一个分屏控制模块；所述至少一个分屏控制模块中包括多个分屏开关单元；所述多个分屏开关单元与所述多个第一扫描线中的所述至少部分第一扫描线分别对应设置；每个所述分屏开关单元连接于同一第一扫描线中相邻的两条子扫描线之间；每个所述分屏开关单元响应于分屏控制信号关断时，所述第一侧第一扫描驱动电路和所述第二侧第一扫描驱动电路分别向每个所述分屏开关单元两侧的子扫描线传输扫描信号。
可选地，同一时刻，同一第一扫描线上处于关断状态的分屏开关单元的数量小于或等于1个；
同一分屏控制模块中的所述多个分屏开关单元接入相同的分屏控制信号；
优选地，与所述第一侧第一扫描驱动电路连接的级联控制信号为第一侧级联控制信号，与所述第二侧第一扫描驱动电路连接的级联控制信号为第二侧级联控制信号；所述第一侧级联控制信号与所述第二侧级联控制信号不同。
可选地，与所述多个分屏开关单元中的一个分屏开关单元的两端分别对应连接的两条子扫描线上同时传输扫描信号的导通电位时，所述分屏控制信号控制所述多个分屏开关单元中的所述一个分屏开关单元导通。
可选地，所述至少部分第一扫描线中的每条第一扫描线包括第一子扫描线和第二子扫描线，所述第一子扫描线与所述第一侧第一扫描驱动电路连接，所述第二子扫描线与所述第二侧第一扫描驱动电路连接；
每个所述分屏控制单元分别与对应的第一子扫描线和第二子扫描线电连 接；
优选地，所述第一子扫描线与所述第二子扫描线的长度相同。
可选地，所述至少部分第一扫描线中的每个第一扫描线包括第三子扫描线、第四子扫描线和第五子扫描线；所述至少一个分屏控制模块包括：第一分屏控制模块和第二分屏控制模块；
所述第三子扫描线与所述第一侧第一扫描驱动电路连接，所述第一分屏控制模块连接于所述第三子扫描线和所述第四子扫描线之间，所述第二分屏控制模块连接于所述第四子扫描线和所述第五子扫描线之间，所述第五子扫描线与所述第二侧第一扫描驱动电路连接；
优选地，在同一显示帧中，部分行像素驱动电路的数据写入过程中，所述第一分屏控制模块导通，所述第二分屏控制模块关断，其他行像素驱动电路的数据写入过程中，所述第一分屏控制模块关断，所述第二分屏控制模块导通；
优选地，所述分屏控制信号包括第一分屏控制信号和第二分屏控制信号，所述第一分屏控制模块接入所述第一分屏控制信号，所述第二分屏控制模块接入所述第二分屏控制信号；所述第一分屏控制模块中分屏开关单元中的晶体管，与所述第二分屏控制模块中分屏开关单元中的晶体管的沟道类型不同，所述第一分屏控制信号复用为所述第二分屏控制信号。
可选地，所述分屏开关单元包括：第五晶体管，所述第五晶体管的栅极接入所述分屏控制信号，所述第五晶体管的第一极与所述第五晶体管的第二极分别与同一第一扫描线中相邻的两条子扫描线连接。
相应的，本申请实施例还提供了一种显示驱动电路的控制方法，用于控制本申请任意实施例所提供的显示驱动电路；所述控制方法包括：
获取显示面板在第一方向上的目标分区位置；
根据所述目标分区位置，确定每帧显示中的级联控制信号，并基于所述级联控制信号控制每帧显示中所述级联控制模块的开关状态。
可选地，所述至少一个级联控制模块包括多个级联控制模块；所述显示面板包括至少一个目标分区位置；
所述显示面板的显示过程中包括多类显示帧；所述多类显示帧中包括第一刷新帧和至少一类第二刷新帧；所述第二刷新帧的类别与所述目标分区位置分别对应；
在所述第一刷新帧中，级联控制信号控制所有级联控制模块均保持导通；
在所述第二刷新帧中，级联控制信号控制所有级联控制模块的关断时间， 或控制预设位置的级联控制模块关断，使所述显示面板基于所述第二刷新帧对应的目标分区位置进行显示。
相应的，本申请实施例还提供了一种显示装置，包括：如本申请任意实施例所提供的显示驱动电路。
本申请实施例所提供的显示驱动电路，在第一扫描驱动电路中设置至少一个级联控制模块，级联控制信号通过控制级联控制模块的开关状态，可以控制第一移位寄存器输出的扫描信号的导通电位是否能逐级传递。通过切断扫描信号的导通电位向下级第一移位寄存器的传输，可以实现同一帧显示中显示面板在第一方向上的分区显示，且不同显示区域的刷新频率不同，以丰富显示面板的显示功能。综上所述，相比于现有技术，本申请实施例可以使显示面板具备分区多频显示功能。
应当理解，本部分所描述的内容并非旨在标识本申请的实施例的关键或重要特征，也不用于限制本申请的范围。本申请的其它特征将通过以下的说明书而变得容易理解。
附图说明
为了更清楚地说明本申请实施例，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的一种显示驱动电路的结构示意图；
图2是本申请实施例提供的另一种显示驱动电路的结构示意图；
图3是本申请实施例提供的又一种显示驱动电路的结构示意图；
图4是本申请实施例提供的又一种显示驱动电路的结构示意图；
图5是本申请实施例提供的又一种显示驱动电路的结构示意图；
图6是本申请实施例提供的一种显示面板的结构示意图；
图7是本申请实施例提供的一种显示帧的驱动信号时序图；
图8是本申请实施例提供的另一种显示帧的驱动信号时序图；
图9是本申请实施例提供的又一种显示帧的驱动信号时序图；
图10是本申请实施例提供的一种显示面板的驱动时序示意图；
图11是本申请实施例提供的另一种显示面板的驱动时序示意图；
图12是本申请实施例提供的又一种显示驱动电路的结构示意图；
图13是本申请实施例提供的又一种显示驱动电路的结构示意图；
图14是本申请实施例提供的又一种显示面板的驱动时序示意图；
图15是本申请实施例提供的又一种显示驱动电路的结构示意图；
图16是本申请实施例提供的又一种显示面板的驱动时序示意图；
图17是本申请实施例提供的又一种显示驱动电路的结构示意图；
图18是本申请实施例提供的一种电源端电压设置模式示意图；
图19是本申请实施例提供的另一种电源端电压设置模式示意图；
图20是本申请实施例提供的一种像素驱动电路的结构示意图；
图21是本申请实施例提供的一种像素驱动电路的驱动时序示意图；
图22是本申请实施例提供的另一种显示面板的结构示意图；
图23是本申请实施例提供的一种第一移位寄存器的结构示意图；
图24是本申请实施例提供的一种第一移位寄存器的驱动时序示意图；
图25是本申请实施例提供的另一种像素驱动电路的结构示意图；
图26是本申请实施例提供的另一种像素驱动电路的驱动时序示意图；
图27是本申请实施例提供的另一种第一移位寄存器的结构示意图；
图28是本申请实施例提供的另一种第一移位寄存器的驱动时序示意图；
图29是本申请实施例提供的又一种像素驱动电路的驱动时序示意图；
图30是本申请实施例提供的又一种显示面板的结构示意图；
图31是本申请实施例提供的又一种显示面板的结构示意图；
图32是本申请实施例提供的又一种显示面板的驱动时序示意图；
图33是本申请实施例提供的又一种显示面板的驱动时序示意图；
图34是本申请实施例提供的又一种显示面板的驱动时序示意图；
图35是本申请实施例提供的又一种显示面板的驱动时序示意图；
图36是本申请实施例提供的又一种显示面板的驱动时序示意图；
图37是本申请实施例提供的又一种显示面板的驱动时序示意图；
图38是本申请实施例提供的又一种显示面板的驱动时序示意图；
图39是本申请实施例提供的又一种显示面板的结构示意图；
图40是本申请实施例提供的又一种显示面板的驱动时序示意图；
图41是本申请实施例提供的又一种显示面板的结构示意图。
具体实施方式
为了使本技术领域的人员更好地理解本申请实施例，下面将结合本申请实 施例中的附图，对本申请实施例进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分的实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都应当属于本申请保护的范围。
需要说明的是，本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本申请的实施例能够以除了在这里图示或描述的那些以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含。
为了更好地解释本申请的实施例，下面首先对显示面板中显示驱动电路的结构和驱动过程进行简要说明。
显示面板中的显示驱动电路包括：设置于非显示区的扫描驱动电路和阵列排布于显示区的像素驱动电路。其中，扫描驱动电路包括级联设置的移位寄存器，扫描驱动电路可采用单边驱动或双边驱动的模式。像素驱动电路配合发光器件构成一个子像素。每个子像素作为一个最小显示单元，多个不同颜色子像素组成一个像素，实现彩色显示。每级移位寄存器对应连接一条扫描线，并通过扫描线向对应行子像素提供扫描信号，每列子像素对应连接一条数据线。
在画面显示过程中，通过逐行扫描的方式对各像素驱动电路进行数据写入，即，移位寄存器通过扫描线为像素驱动电路提供扫描信号，对应于扫描信号的导通电位持续时间，数据线上的数据电压传输至对应的像素驱动电路，以实现数据写入，每个子像素根据数据电压进行显示。当扫描线提供截止电位时，数据线的数据电压无法传输至对应的像素驱动电路中，不进行数据写入。例如，当扫描第1行子像素时，第1行子像素对应的扫描线向第1行像素驱动电路提供导通电位，其他行子像素对应的扫描线提供截止电位，各数据线上的数据电压传输至第1行子像素；同一时间仅有一个移位寄存器输出扫描信号的导通电位。
对于能够切换显示频率的显示面板，子像素的显示帧可分为刷新帧(active frame)和保持帧(idle frame)。在刷新帧中，移位寄存器向对应行像素驱动电路提供导通电位，使数据电压写入像素驱动电路；在保持帧中，移位寄存器向对应行像素驱动电路提供截止电位，像素驱动电路不再进行数据写入。
刷新频率可以理解为单位时间内包含的刷新帧的数量。示例性地，高频显示中可以仅包括刷新帧，低频显示通过跳帧实现。例如，在刷新频率f下，显示 面板的显示帧仅包括刷新帧。示例性地，当f＝60Hz时，显示面板在1秒时间内刷新60个显示帧，每帧时间＝1s/60＝16.67ms。当刷新频率降低时，在相邻刷新帧之间***保持帧，单位时间内包含的显示帧数量不变，各显示帧的显示时长也不变。当刷新频率为f/2时，每相邻两个刷新帧之间***1个保持帧，即，奇数帧为刷新帧，偶数帧为保持帧。当刷新频率为f/3时，每相邻两个刷新帧之间***2个保持帧。以此类推，当刷新频率为f/(N+1)时，每相邻两个刷新帧之间***N个保持帧。
本申请实施例提供了一种显示驱动电路，以实现向显示面板不同显示区域提供不同刷新频率的驱动方案。图1是本申请实施例提供的一种显示驱动电路的结构示意图。参见图1，该显示驱动电路中包括：至少一个第一扫描驱动电路100。图1中以显示驱动电路中包括一个第一扫描驱动电路100为例进行说明。当显示驱动电路中包括多个第一扫描驱动电路100时，多个第一扫描驱动电路100可以具有相同的结构。第一扫描驱动电路100包括：级联设置的多个第一移位寄存器10，以及至少一个级联控制模块20。每个第一移位寄存器10均包括寄存器输入端和寄存器输出端。每个级联控制模块20连接于对应的本级寄存器输出端和下级寄存器输入端之间，且级联控制模块20的控制端接入级联控制信号SJL。每个级联控制模块20响应于级联控制信号SJL控制扫描信号的导通电位从本级寄存器输出端向下级寄存器输入端的传输，以实现显示面板在第一方向(即子像素列方向)上的多频显示。
可以理解的是，当各级第一移位寄存器10级联连接时，在各第一移位寄存器10逐级输出扫描信号的过程中，本级扫描信号的导通电位传输至下级第一移位寄存器10，作为下级第一移位寄存器10的启动信号，触发下级第一移位寄存器10继续输出扫描信号的导通电位，从而实现扫描信号导通脉冲的顺次移位。
需要说明的是，本级第一移位寄存器和下级第一移位寄存器分别为第一扫描驱动电路100中的第i级第一移位寄存器和第i+a级第一移位寄存器，i和a均为正整数。示例性地，如图2所示，当各级第一移位寄存器依次级联时，a＝1，若本级第一移位寄存器为第1级第一移位寄存器101，则下级第一移位寄存器为第2级第一移位寄存器102。而当各级移位寄存器并非依次级联时，a＞1，下级第一移位寄存器并不是本级第一移位寄存器的下一级第一移位寄存器。如图3所示，当a＝2时，奇数级第一移位寄存器依次级联，偶数级第一移位寄存器依次级联，若本级第一移位寄存器为第1级第一移位寄存器101，则下级第一移位寄存器为第3级第一移位寄存器103。以下实施例中为了便于说明，均以图2中 各级第一移位寄存器依次级联的连接结构为例进行说明。
设置于两级第一移位寄存器10之间的级联控制模块20，在响应级联控制信号SJL关断时，通过断开本级寄存器输出端12和下级寄存器输入端11之间的连接，阻断扫描信号的逐级传输路径，切断扫描信号导通电位的向下传输，从而使断开位置之前的子像素行基于导通电位的控制处于刷新帧，而断开位置之后的子像素行基于截止电位的控制处于保持帧，实现显示面板在第一方向上的多频显示。具体的，在本示例性的实施例中，通过设置级联控制模块20实现显示面板在第一方向上的多频显示，且刷新频率由高变低的驱动方案。在其他实施例中，在设置级联控制模块20的基础上，通过向下级寄存器输入端11传输启动信号，也可实现刷新频率由低变高的驱动方案。
示例性地，级联控制模块20的数量可以与目标分区位置D的数量相同，并一一对应于显示面板的目标分区位置设置。或者，级联控制模块20的数量可以更多，以使显示面板在第一方向上的分区位置可调。
对于本申请实施例所提供的显示驱动电路，在第一扫描驱动电路100中设置至少一个级联控制模块20，级联控制信号SJL通过控制级联控制模块20的开关状态，可以控制第一移位寄存器10输出的扫描信号的导通电位是否能逐级传递。通过切断扫描信号的导通电位向下级第一移位寄存器10的传输，可以实现同一帧显示中显示面板在第一方向上的分区显示，且不同显示区域的刷新频率不同，以丰富显示面板的显示功能。综上所述，相比于相关技术，本申请实施例可以使显示面板具备分区多频显示功能。
继续参见图2，在上述各实施方式的基础上，可选地，至少一个级联控制模块20包括多个级联控制模块20。多个级联控制模块20与第一扫描驱动电路100中的至少部分第一移位寄存器10分别对应设置，例如与部分或全部第一移位寄存器10对应连接。每个级联控制模块20分别设置于所述至少部分第一移位寄存器10中对应的本级第一移位寄存器10和对应的下级第一移位寄存器10之间。多个级联控制模块20中的每个响应于级联控制信号SJL，级联控制信号SJL通过控制各级联控制模块20的开关状态，调整一帧显示中扫描信号的导通电位向下级寄存器输入端11的传输被切断的位置，从而调整显示面板在第一方向上降频显示的分区位置。
具体地，以设置在第1级第一移位寄存器101和第2级第一移位寄存器102之间的级联控制模块201为例，当级联控制模块201关断时，第1级第一移位寄存器101的寄存器输出端12与第2级第一移位寄存器102的寄存器输入端11 之间断开。在一帧显示中，第1级扫描信号SCAN1的导通电位不能传输至第2级寄存器输入端，无法触发第2级第一移位寄存器102输出导通电位，因此第2级第一移位寄存器102在该帧显示中持续输出截止电位。那么，第1级第一移位寄存器101对应行的子像素处于刷新帧，第2级第一移位寄存器102对应行的子像素处于保持帧，上述两行子像素之间为显示面板的降频显示分区位置。
基于上述分析，当第一扫描驱动电路中设置有多个级联控制模块20时，级联控制信号SJL通过在每帧显示中控制各级联控制模块20的开关状态，可以改变扫描信号的逐级传输被切断的位置，从而实现对显示面板的降频显示分区位置的调整。具体地，级联控制信号SJL通过在一帧显示中，在目标显示分区位置的上一行子像素的扫描时间内，控制分别与该行子像素和下一行子像素连接的两个第一移位寄存器10之间的级联控制模块20断开，可在该显示帧实现基于目标显示分区位置的降频显示。示例性地，在一帧显示中，级联控制信号SJL可以控制各级联控制模块20由导通切换为关断的时间，或者控制目标分区位置对应的级联控制模块20关断，实现上述控制过程。
对于本申请实施例所提供的显示驱动电路，通过设置多个级联控制模块20，使得各显示帧中扫描信号导通电位的传输被切断的位置可调，进而使得显示面板的降频显示分区位置可调，以丰富显示面板的显示功能，使显示面板的驱动过程更灵活。
在上述各实施方式的基础上，可选地，可以在每相邻的两个第一移位寄存器10之间均设置一个级联控制模块20，使得扫描信号的逐级传递可在显示屏的任意行位置中断，进而使得分区位置不受级联控制模块20设置位置的限制，实际驱动过程中，可以根据需求在任意时间控制任意级联控制模块20的工作状态，使显示面板分区位置任意可调。
如图2所示的第一扫描驱动电路100，当某个级联控制模块20关断时，其连接的下级寄存器输入端11浮置(floating)，没有电压输入，使得下级第一移位寄存器10存在输出状态不稳定的风险。
为应对上述状况，发明人提出一种改进实施例。图4是本申请实施例提供的又一种显示驱动电路的结构示意图。参见图4，在上述各实施方式的基础上，可选地，第一扫描驱动电路100中还设置有：至少一个辅助切断模块30。辅助切断模块30与级联控制模块20对应设置。示例性地，辅助切断模块30可以有多个，且与各级联控制模块20分别对应设置。辅助切断模块30的控制端接入开关控制信号SW2，辅助切断模块30的输入端接入辅助切断信号VD，辅助切 断模块30的输出端与辅助切断模块30对应的级联控制模块20连接同一寄存器输入端11。
其中，开关控制信号SW2可以在级联控制模块20关断时，控制对应的辅助切断模块30导通，以将辅助切断信号VD传输至下级寄存器输入端11，避免下级寄存器输入端11浮置，使下级第一移位寄存器10稳定输出扫描信号的截止电位。示例性地，辅助切断信号VD可以是直流电压信号，辅助切断信号VD的电位可以是扫描信号的截止电位。
在上述各实施方式的基础上，可选地，级联控制信号SJL和开关控制信号SW2均可由终端设备的主板提供，经由驱动集成电路(integrated circuit，IC)进入屏体；或者直接由驱动IC提供。终端设备的主板可具备侦测每帧画面信息的能力，以判断每帧显示中显示面板的显示状态，以及各子显示区对应的刷新频率。
在上述各实施方式的基础上，可选地，在每个显示帧中，对级联控制模块20的控制方式有多种，下面分别进行说明。
需要说明的是，在显示面板中，当扫描驱动电路与像素驱动电路的对应连接关系不同时，第i级第一移位寄存器10对应连接的子像素行，可以是第i行子像素，也可以是第i-1行子像素，还可以是根据连接关系确定的其他行子像素。在以下描述中，为了方便解释显示驱动电路的工作过程，以第i级第一移位寄存器10对应连接第i行子像素为例进行说明。
图5是本申请实施例提供的又一种显示驱动电路的结构示意图。参见图5，在一种实施方式中，可选地，级联控制信号SJL包括：第一级联控制信号SW1，各级联控制模块20接入同一第一级联控制信号SW1，各级联控制模块20响应第一级联控制信号SW1同时导通或关断。这样设置，可以简化显示驱动电路的结构，减少驱动IC的输出端口，降低成本，使得该显示驱动电路易于实现和应用。第一级联控制信号SW1通过调整在一帧显示中的电位跳变时间，调整各级联控制模块20在一帧显示中的关断时间，从而实现对显示面板的降频显示分区位置的调整，级联控制模块20在一帧显示中的导通时长决定着传输扫描信号并进行刷新的子像素行数。
由于同一时刻仅有一个第一移位寄存器10输出导通电位，其他第一移位寄存器10均输出截止电位，即使第一级联控制信号SW1控制全部级联控制模块20同时导通，也只有输出导通电位的那一级第一移位寄存器10发挥作用，将该导通电位传输至下级第一移位寄存器10，而其他第一移位寄存器10仅能接收到 截止电位。因此，全部级联控制模块20同时导通，并不会造成同一时刻多个第一移位寄存器10接收到启动信号，不会造成同一时刻多个第一移位寄存器10均输出导通电位的情况，不影响显示面板的正常驱动。而全部级联控制模块20同时关断时，同样相当于仅针对正在输出导通电位的那一级第一移位寄存器10发挥作用，阻止该导通电位被传输至下级第一移位寄存器10，其他级第一移位寄存器10之间的连接切断与否，都不影响其他级第一移位寄存器10持续输出截止电位。因此全部级联控制模块20同时通断，均不影响显示面板的正常驱动，全部级联控制模块20可以接入同一第一级联控制信号SW1。
相应的，全部辅助切断模块30同时通断也不会影响显示面板的正常驱动，全部辅助切断模块30可以接入同一开关控制信号SW2。开关控制信号SW2在一帧显示中的电位跳变时间，决定各辅助切断模块30在一帧显示中的导通时间。第一级联控制信号SW1与开关控制信号SW2相配合，可以实现对显示面板分区多频显示位置的调控。在第i级第一移位寄存器输出第i级扫描信号的导通电位，且第i+a级第一移位寄存器(即第i级第一移位寄存器的下级第一移位寄存器)输出第i+a级扫描信号的导通电位的情况下，在第i级第一移位寄存器10输出第i级扫描信号的导通电位的阶段，级联控制信号SJL控制第i级第一移位寄存器和第i+a级第一移位寄存器之间的级联控制模块20导通，且开关控制信号SW2控制第i级第一移位寄存器和第i+a级第一移位寄存器之间的辅助切断模块30关断。在第i级第一移位寄存器输出第i级扫描信号的导通电位，且第i+a级第一移位寄存器(即第i级第一移位寄存器的下级第一移位寄存器)输出第i+a级扫描信号的截止电位的情况下，在第i级第一移位寄存器10输出第i级扫描信号的导通电位的阶段，级联控制信号SJL控制第i级第一移位寄存器和第i+a级第一移位寄存器之间的级联控制模块20关断，且开关控制信号SW2控制第i级第一移位寄存器和第i+a级第一移位寄存器之间的辅助切断模块30导通。在控制过程中，其他级联控制模块20的开关状态与第i级第一移位寄存器和第i+a级第一移位寄存器之间的级联控制模块20的开关状态可以相同或不同；以及，其他辅助切断模块30的开关状态与第i级第一移位寄存器和第i+a级第一移位寄存器之间的辅助切断模块30的开关状态可以相同或不同。
示例性地，假设第一扫描驱动电路中包括n级第一移位寄存器10，第一级联控制信号SW1在第1级至第i-1级第一移位寄存器10的输出过程中，控制各级联控制模块20导通，同一阶段，开关控制信号SW2控制各辅助切断模块30关断，第1级至第i-1级第一移位寄存器10可以逐级输出导通电位，第2级至 第i级第一移位寄存器10可以逐级接收导通电位。在第i级第一移位寄存器10开始输出导通电位时，第一级联控制信号SW1进行电位跳变，控制各级联控制模块20关断，开关控制信号SW2也进行电位跳变，控制各辅助切断模块30导通，使得第i级扫描信号的导通电位无法传输至第i+1级第一移位寄存器10，各寄存器输入端均接入辅助切断信号。那么，第1级至第i级第一移位寄存器10可以逐级输出扫描信号的导通电位，第i+1级至第n级第一移位寄存器10只能持续输出扫描信号的截止电位，该显示帧中，显示面板的降频显示分区位置位于第i级与第i+1级两级第一移位寄存器10对应的两行子像素之间。
需要说明的是，在第i级第一移位寄存器与第i+1级第一移位寄存器之间的连接被切断之后，直至本帧显示结束，即使第一级联控制信号SW1再次进行电位跳变，例如在第j行子像素的扫描时间内，第一级联控制信号SW1控制各级联控制模块20再次导通，由于第i+1级至第j级第一移位寄存器10都仅输出截止电位，第j级扫描信号无法向第j+1级第一移位寄存器10提供导通电位，那么，第j+1级至第n级第一移位寄存器10无法恢复输出导通电位。也就是说，在一帧显示中，显示面板存在一个降频显示分区位置；但将具有不同降频显示分区位置的显示帧进行组合，可以实现显示面板的多分区多频显示。下面以显示面板进行三分区多频显示为例进行说明。
图6是本申请实施例提供的一种显示面板的结构示意图。参见图6，示例性地，第一扫描驱动电路100中包括n级第一移位寄存器，显示面板的显示区AA中包括n行像素驱动电路200(即n行子像素)，第i级第一移位寄存器对应连接第i行子像素。示例性地，显示面板中包括2个目标降频显示分区位置(以点划线表示)，包括：第一目标分区位置D1，例如在第k行子像素和第k+1行子像素之间；第二目标分区位置D2，例如在第m行子像素和第m+1行子像素之间。上述两个目标分区位置将显示面板的显示区AA在第一方向上划分为第一子显示区A1、第二子显示区A2和第三子显示区A3。沿第一方向，第一子显示区A1至第三子显示区A3依次降频显示。那么，显示面板可能存在以下三类显示状态下的显示帧：第一类显示帧，整个显示区AA中的各行子像素均处于刷新帧；第二类显示帧，以第一目标分区位置D1为分界，第一子显示区A1中的各行子像素均处于刷新帧，第二子显示区A2和第三子显示区A3中的各行子像素均处于保持帧；第三类显示帧，以第二目标分区位置D2为分界，第一子显示区A1和第二子显示区A2中的各行子像素均处于刷新帧，第三子显示区A3中的各行子像素均处于保持帧。
下面以扫描信号的导通电位为高电位，且级联控制模块20和辅助切断模块30均响应高电位导通为例，结合图7-图9，对上述三类显示帧的驱动过程分别进行说明。其中，第i级扫描信号的导通电位传输时间，即第i行子像素的扫描时间，以hi表示。以及，图7-图9中，示例性地，以阴影填充表示子显示区的各子像素处于刷新帧，以空白填充表示子显示区的各子像素处于保持帧。
图7是本申请实施例提供的一种显示帧的驱动信号时序图，参见图6和图7，该显示帧对应第一类显示帧，整个显示区AA中的各行子像素均处于刷新帧。第一级联控制信号SW1维持高电位，开关控制信号SW2维持低电位。各级联控制模块20在该显示帧中始终导通，各辅助切断模块30在该显示帧中始终关断。各级第一移位寄存器在该显示帧中始终保持级联状态，实现扫描信号导通电位的逐级传输。
图8是本申请实施例提供的另一种显示帧的驱动信号时序图。参见图6和图8，该显示帧对应第二类显示帧，以第一目标分区位置D1为分界进行降频显示。
在第k行子像素的扫描时间hk之前，第一级联控制信号SW1维持高电位，开关控制信号SW2维持低电位，使各级联控制模块20保持导通，各辅助切断模块30保持关断。第1级至第k级第一移位寄存器之间可以实现扫描信号导通电位的移位传输。
在第k行子像素的扫描时间hk开始时，第一级联控制信号SW1跳变为低电位，开关控制信号SW2跳变为高电位，直至本帧结束，第一级联控制信号SW1维持低电位，开关控制信号SW2维持高电位。因此，自第k行子像素的扫描时间hk开始直至本帧结束，各级联控制模块20保持关断，各辅助切断模块30保持导通。对于第k级至第n级第一移位寄存器，相邻第一移位寄存器之间的连接被切断，且第k+1级至第n级寄存器输入端均接入辅助切断信号VD。第k+1级至第n级第一移位寄存器持续输出截止电位。
图9是本申请实施例提供的又一种显示帧的驱动信号时序图。参见图6和图9，该显示帧对应第三类显示帧，以第二目标分区位置D2为分界进行降频显示。
在第m行子像素的扫描时间hm之前，第一级联控制信号SW1维持高电位，开关控制信号SW2维持低电位，使各级联控制模块20保持导通，各辅助切断模块30保持关断。第1级至第m级第一移位寄存器之间可以实现扫描信号导通电位的移位传输。
自第m行子像素的扫描时间hm开始时直至本帧结束，第一级联控制信号SW1维持低电位，开关控制信号SW2维持高电位，各级联控制模块20保持关断，各辅助切断模块30保持导通。对于第m级至第n级第一移位寄存器，相邻第一移位寄存器之间的连接被切断，且第m+1级至第n级寄存器输入端均接入辅助切断信号VD。第m+1级至第n级第一移位寄存器持续输出截止电位。
在实际应用时，通过调整上述三类显示帧的顺序和数量，可以实现各分区各种显示频率的组合。
例如，当第一子显示区A1以刷新频率f进行显示，第二子显示区A2以刷新频率f/2进行显示，第三子显示区A3以刷新频率f/4进行显示时，各类显示帧的组合方式如图10所示。参见图10，对于第一子显示区A1的各行子像素，各显示帧可以均为刷新帧，图10中示例性地给出了第1级扫描信号SCAN1的波形，可以看出，每帧显示中，第1级扫描信号SCAN1均包含导通脉冲。对于第二子显示区A2的各行子像素，可以设置奇数帧为刷新帧，偶数帧为保持帧，图10中示例性地给出了第k+1级扫描信号SCANk+1的波形，可以看出，第k+1级扫描信号SCANk+1仅在奇数帧包含导通脉冲。对于第三子显示区A3的各行子像素，可以设置相邻两刷新帧之间间隔3个保持帧，图10中示例性地给出了第m+1级扫描信号SCANm+1的波形，可以看出，第m+1级扫描信号SCANm+1在显示帧F1和显示帧F5中包含导通脉冲，即仅在第4i+1个显示帧中包含导通脉冲，在其他显示帧保持截止电位。以F1至F4这4个显示帧为一个循环(CYCLE1)，重复该循环中的驱动过程，可实现第一子显示区A1以刷新频率f进行显示、第二子显示区A2以刷新频率f/2进行显示、第三子显示区A3以刷新频率f/4进行显示的稳定分区多频显示。其中，显示帧F1对应于第一类显示帧，显示帧F2和F4对应于第二类显示帧，显示帧F3对应于第三类显示帧。
若需要对各子显示区之间的分区位置进行调整，可以通过调整各类显示帧中第一级联控制信号SW1和开关控制信号SW2的电位跳变时间来实现；例如将图8中第一级联控制信号SW1和开关控制信号SW2的电位跳变时刻向前调整，可以将第一目标分区位置D1上移。
若需要对各子显示区的刷新频率进行调整，可以通过控制不同循环中各类显示帧的顺序和数量来实现；例如通过在图10中的显示帧F1和显示帧F3之间，再增加多个与显示帧F2相同的显示帧，可以使第二子显示区A2和第三子显示区A3的刷新频率都降低。
通过在不同时间段内采用不同循环进行显示，可以实现刷新频率动态调整 的显示方案。
其中，在各行子像素的扫描过程中，可以根据各行子像素的刷新状态相应控制数据线上的数据电压是否更新切换。具体地，对处于刷新帧的子像素行，数据电压需要更新，并在该行扫描信号的导通电位持续时间内，通过数据线将数据电压向该行中的各个子像素正常传输。对处于保持帧的子像素行，数据电压停止向子像素输出。其中，数据电压停止输出时，其状态可设定为保持高电位、保持低电位、保持上一行时的数据电压、或者保持在任意灰阶对应的电位值。保持帧中数据电压保持固定电位可降低面板功耗。实际应用时，数据电压的状态可以跟随第一级联控制信号SW1的变化而变化，在第一级联控制信号SW1控制各级联控制模块20导通时，数据电压更新；在第一级联控制信号SW1控制各级联控制模块20关断时，数据电压停止输出。
在实际应用时，考虑到各行子像素全部扫描完成后固有的空白阶段(Porch阶段)，显示面板的驱动时序可以如图11所示，在每帧显示中，在三个子显示区的扫描时间均结束之后，本显示帧的时间持续至空白阶段结束，再进入下一显示帧。其中，由于在空白阶段中不对子像素进行扫描，也就是在空白阶段中显示区中所有子像素行对应的扫描信号的电位为截止电位，第一级联控制信号SW1和开关控制信号SW2的电位可以任意设置，例如延续前一阶段的电位，以减少电位跳变的次数，简化控制逻辑。
上述各实施方式示例性地给出了级联控制模块20和辅助切断模块30在显示过程中的作用方式。下面对级联控制模块20和辅助切断模块30的具体结构进行说明。
继续参见图5，在一种实施方式中，可选地，每个辅助切断模块30包括：第四晶体管T4；第四晶体管T4的栅极接入开关控制信号SW2，第四晶体管T4的第一极接入辅助切断信号，第四晶体管T4的第二极与对应的第一晶体管T1的第二极电连接。本实施例设置辅助切断模块30包括一个晶体管，使得辅助切断模块30的结构简单，易于实现。
继续参见图5，在一种实施方式中，可选地，显示面板中设置有：第一时钟信号线，用于传输第一时钟信号CLK1；第二时钟信号线，用于传输第二时钟信号CLK2；第一电位信号线，用于传输第一电位信号VGH；第二电位信号线，用于传输第二电位信号VGL；第一级联控制信号线，用于传输第一级联控制信号SW1；开关控制信号线，用于传输开关控制信号SW2。各级第一移位寄存器10均接入第二电位信号VGL和第一电位信号VGH；相邻两级第一移位寄存器 10的第一时钟端和第二时钟端分别与第一时钟信号线和第二时钟信号线交替电连接。示例性地，第一电位信号VGH可以是高电位信号，第二电位信号VGL可以是低电位信号。第一电位信号VGH或第二电位信号VGL的电位作为扫描信号的导通电位，另一个作为截止电位。
可选地，可以将作为截止电位的电位信号复用为辅助切断信号，以减少显示面板的布线。例如，如图5所示，当扫描信号的导通电位为高电位时，可以将第二电位信号VGL复用为辅助切断信号，第四晶体管T4的第一极与第二电位信号线电连接。或者，扫描信号的导通电位为低电位，那么可以将第一电位信号VGH复用为辅助切断信号，第四晶体管T4的第一极与第一电位信号线电连接。
继续参见图5，在一种实施方式中，可选地，每个级联控制模块20包括：第一晶体管T1；第一晶体管T1的栅极接入第一级联控制信号SW1，第一晶体管T1的第一极与本级寄存器输出端12电连接，第一晶体管T1的第二极与下级寄存器输入端11电连接。本实施例设置级联控制模块20包括一个晶体管，使得级联控制模块20的结构简单，易于实现。
在上述各实施方式的基础上，可选地，第一晶体管T1与第四晶体管T4的沟道类型相同，两晶体管可以在同一工艺中制备，以简化面板制备过程。在此基础上，可以设置第一级联控制信号SW1和开关控制信号SW2互为反相信号，两控制信号的跳变时间一致，使级联控制模块20关断时，辅助切断模块30能可靠导通，向下级寄存器输入端11传输辅助切断信号。
示例性地，如图5所示，第一晶体管T1与第四晶体管T4均为N型晶体管，示例性的，第一晶体管T1与第四晶体管T4包括金属氧化物半导体晶体管，相较于多晶硅晶体管，N型的金属氧化物半导体晶体管可以提供更好的关断效果。
图12是本申请实施例提供的又一种显示驱动电路的结构示意图。参见图12，在一种实施方式中，可选地，当第一晶体管T1与第四晶体管T4的沟道类型相同，且第四晶体管T4的导通电位与扫描信号的导通电位相同时，可以将第一级联控制信号SW1复用为辅助切断信号，以简化电路结构。由于开关控制信号SW2控制第四晶体管T4导通时，第一级联控制信号SW1作为开关控制信号SW2的反相信号，保持在第四晶体管T4的截止电位，相当于保持在扫描信号的截止电位，将该开关控制信号SW2作为第四晶体管T4的输入信号，可以保证辅助切断模块30的正常工作。
图13是本申请实施例提供的又一种显示驱动电路的结构示意图。参见图13， 在一种实施方式中，可选地，第一晶体管T1与第四晶体管T4可以均为P型晶体管。由于第一移位寄存器10通常采用P型晶体管构成，这样设置，可以使得第一晶体管T1和第四晶体管T4均可以与第一移位寄存器10中的晶体管在同一工艺中制备，以简化面板制备过程。此种情况下显示面板的驱动时序可参见图14，相比于图10，由于本实施例中各晶体管的导通电位为低电位，各开关控制信号均变换为图10中相应开关控制信号的反相信号，各功能模块的开关状态变化仍可参见前述解释中对显示面板驱动过程的描述，不再赘述。
图15是本申请实施例提供的又一种显示驱动电路的结构示意图。参见图15，在一种实施方式中，可选地，第一晶体管T1与第四晶体管T4的沟道类型不同，第一级联控制信号SW1可复用为开关控制信号SW2，以减少显示面板所需的信号线数量，简化显示面板的布线。此种情况下显示面板的驱动时序可参见图16，相比于图10，由于本实施例中第一晶体管T1与第四晶体管T4的导通电位互为反相，且实际应用中两晶体管的开关状态相反，两晶体管可采用同一开关控制信号控制，各功能模块的开关状态变化仍可参见前述解释中对显示面板驱动过程的描述，不再赘述。
上述各实施方式示例性地给出了各级联控制模块统一控制方式下，显示面板的降频显示分区位置的调整方案，但不作为对本申请的限定。在其他实施方式中，可选地，级联控制模块20可以具有其他结构，级联控制信号通过在每帧显示中，控制预设位置的级联控制模块20保持关断状态，实现对显示面板的降频显示分区位置的调整。
图17是本申请实施例提供的又一种显示驱动电路的结构示意图。参见图17，在一种实施方式中，可选地，第一扫描驱动电路100还包括：第一电源端N1和第二电源端N2，其中，第一电源端N1设置于驱动IC远端，即靠近第1级第一移位寄存器的一端；第二电源端N2设置于驱动IC近端，即靠近最后一级第一移位寄存器的一端。以及，第一扫描驱动电路100中还包括：第一电阻串。第一电阻串包括串联连接在第一电源端N1和第二电源端N2之间的多个第一电阻R1；第一电阻串中引出多个第一输出端NT，第一输出端NT输出第二级联控制信号。多个第一输出端NT与多个级联控制模块20分别对应连接，相邻两个第一输出端NT之间设置有至少一个第一电阻R1。
当向第一电源端N1与第二电源端N2提供的电位相同时，各第二级联控制信号的电位相同；通过设置第一电源端N1与第二电源端N2的电位不同，可以使各第二级联控制信号的电位不同。
相应的，级联控制模块20包括：第二晶体管T2；第二晶体管T2的栅极接入对应的第二级联控制信号，第二晶体管T2连接在对应的本级寄存器输出端12和对应的下级寄存器输入端11之间，例如第二晶体管T2的第一极与对应的本级寄存器输出端12电连接，第二晶体管T2的第二极与对应的下级寄存器输入端11电连接。示例性地，沿第一电源端N1向第二电源端N2的方向，多个第一输出端NT依次与第1个至最后一个第二晶体管T2的栅极电连接。
通过调整第一电源端N1和第二电源端N2的电位，可以调整各第二级联控制信号的电位值，从而控制各第二晶体管T2的通断。在一帧显示中，通过设置上述两电源端的电位，可以控制分区位置以上的第二晶体管T2在该显示帧中保持导通，并控制分区位置以下的第二晶体管T2在该显示帧中保持关断，从而实现多频显示。
对于图17中的实施例，当需要部分第二晶体管T2导通，部分第二晶体管T2关断时，在导通与关断的交界位置，可能存在部分第二晶体管T2处于弱导通状态，其开关状态不够稳定。为了应对上述状况，发明人提供了一种改进实施例，下面进行说明。
继续参见图17，在上述各实施方式的基础上，可选地，第一扫描驱动电路100中还包括：第三电源端P1和第四电源端P2。第三电源端P1设置于驱动IC远端，第四电源端P2设置于驱动IC近端。
以及，第一扫描驱动电路100还包括：第二电阻串。第二电阻串包括串联连接在第三电源端P1和第四电源端P2之间的多个第二电阻R2；第二电阻串中引出多个第二输出端PT，第二输出端PT输出第三级联控制信号；多个第二输出端PT与多个级联控制模块20分别对应连接，相邻两个第二输出端PT之间设置有至少一个第二电阻R2。级联控制信号包括各第二级联控制信号和各第三级联控制信号。当向第三电源端P1与第四电源端P2提供的电位相同时，各第三级联控制信号的电位相同；通过设置第三电源端P1与第四电源端P2的电位不同，可以使各第三级联控制信号的电位不同。
相应的，每个级联控制模块20中还包括：第三晶体管T3；第三晶体管T3的栅极接入对应的第三级联控制信号，第三晶体管T3和对应的第二晶体管T2串联连接在对应的本级寄存器输出端12和对应的下级寄存器输入端11之间，例如第三晶体管T3的第一极与对应的第二晶体管T2的第二极电连接，第三晶体管T3的第二极与对应的下级寄存器输入端11电连接。具体地，沿第三电源端P1向第四电源端P2的方向，多个第二输出端PT依次与第1个至最后一个第 三晶体管T3的栅极电连接。
综合而言，通过调整第一电源端N1和第二电源端N2的电位，可以调整各第二级联控制信号的电位值，从而控制各第二晶体管T2的通断；通过调整第三电源端P1和第四电源端P2的电位，可以调整各第三级联控制信号的电位值，从而控制各第三晶体管T3的通断。在一帧显示中，当需要部分第二晶体管T2导通，部分第二晶体管T2关断时，设置与处于弱导通状态的第二晶体管T2对应的第三晶体管T3也处于弱导通状态，可以叠加实现稳定的开关状态，从而保证级联控制模块20导通与关断的分界明晰，使得显示面板在第一方向上的显示分区位置明晰。
总之，通过设置一帧显示中上述四个电源端的电位，可以控制分区位置以上的第二晶体管T2和第三晶体管T3在该显示帧中保持导通，并控制分区位置以下的第二晶体管T2和第三晶体管T3在该显示帧中保持关断，从而实现多频显示。
示例性地，各第一电阻R1与各第二电阻R2的阻值相同，相邻两个第一输出端NT之间间隔一个第一电阻R1，相邻两个第二输出端PT之间间隔一个第二电阻R2，以便于确定各控制信号的电位值。示例性地，电阻可以用屏体走线实现。
示例性地，如图17所示，第二晶体管T2与第三晶体管T3的沟道类型不同，例如第二晶体管T2为N型晶体管，第三晶体管T3为P型晶体管。该结构的级联控制模块20的控制过程如下：
图18是本申请实施例提供的一种电源端电压设置模式示意图，该模式对应于显示面板全屏位置以相同刷新率进行显示的状态，如图18所示，第一电源端的电位VN1和第二电源端的电位VN2保持相同的高电位VH，各个第一输出端NT都为相同的高电位，保证各第二晶体管T2导通。第三电源端的电位VP1和第四电源端的电位VP2保持相同的低电位VL，各个第二输出端PT都为相同的低电位，保证各第三晶体管T3导通，该显示帧中开关控制信号SW2信号常高，使得各第四晶体管T4保持关断，各级第一移位寄存器10可正常的进行级传。
图19是本申请实施例提供的另一种电源端电压设置模式示意图，对应显示面板上半部分以高刷新率进行显示，下半部分以低刷新率进行显示的状态，如图19所示，第一电源端的电位VN1设置为一个较高的大于0V的电位，第二电源端的电位VN2设置为一个小于0V的电位，随着第一电阻串的分压，从IC远端到IC近端，各第一输出端N1的电位逐渐降低，使得各第二晶体管T2的导通 状态自IC远端到IC近端呈现为导通区，弱导通区和截止区的趋势。以及，第三电源端的电位VP1设置为一个绝对值较大的小于0V的电位，第四电源端的电位VP2设置为一个大于0V的电位，从IC远端到IC近端，各第二控制端PT的电位逐渐升高，使得各第三晶体管T3的导通状态自IC远端到IC近端呈现为导通区，弱导通区和截止区的趋势。通过各电源端的电位调节可控制第二晶体管T2和第三晶体管T3的状态分界位置相同。第二晶体管T2和第三晶体管T3的弱导通状态叠加可使级联控制模块20整体呈现稳定的开关状态。因此通过控制四个电源端的电位可精确的控制级联控制模块20开始关断的位置，从而控制显示面板的降频显示分区位置。在高频显示区域的扫描时间内，开关控制信号SW2为高电位，控制第四晶体管T4关断，使该区域内的第一移位寄存器实现扫描信号的正常级传。在低频显示区域的扫描时间内，开关控制信号SW2为低电位，使得第四晶体管T4导通，将辅助切断信号VD传输至下级第一移位寄存器10，中断扫描信号的级传。
上述各实施例示例性地给出了第一扫描驱动电路对显示面板进行分区多频显示的驱动方案，下面对第一移位寄存器输出的导通脉冲的电位高低不同时，第一扫描驱动电路的适用场景进行说明。
在一种实施方式中，可选地，第一移位寄存器输出的扫描信号的导通电位为低电位。此时，辅助切断信号为高电位。下面对应用该类扫描信号的像素驱动电路的结构，产生该类扫描信号的移位寄存电路，以及像素驱动电路与第一扫描驱动电路的连接方式进行说明。
图20是本申请实施例提供的一种像素驱动电路的结构示意图。参见图20，在一种实施方式中，可选地，像素驱动电路200包括：驱动模块41、数据写入模块42、阈值补偿模块43和发光控制模块44。驱动模块41、发光控制模块44和发光器件L串联连接，数据写入模块42与驱动模块41的第一端电连接，阈值补偿模块43连接于驱动模块41的控制端和第二端之间。其中，数据写入模块42的控制端接入第三控制信号Sp1、阈值补偿模块43的控制端接入第二控制信号S2，发光控制模块44的控制端接入发光控制信号EM。另外，像素驱动电路200中还可以包括第一复位模块45，与驱动模块41的控制端电连接；第二复位模块46，与发光器件L的阳极电连接；存储电容Cst，与驱动模块41的控制端电连接。其中，第一复位模块45的控制端接入第一控制信号S1，第二复位模块46的控制端接入第三控制信号Sp1。
示例性地，驱动模块41包括驱动晶体管M11、数据写入模块42包括晶体 管M12、阈值补偿模块43包括晶体管M13、发光控制模块44包括晶体管M15和晶体管M16、第一复位模块45包括晶体管M14、第二复位模块46包括晶体管M17，构成包括七个晶体管和一个电容的像素驱动电路。其中，各晶体管的栅极作为各功能模块的控制端。示例性地，各晶体管可以均为P型晶体管，采用低温多晶硅(Low Temperature Poly-Silicon，LTPS)工艺制备，构成LTPS像素驱动电路。
图21是本申请实施例提供的一种像素驱动电路的驱动时序示意图。结合图20和图21，该像素驱动电路200的驱动过程包括：
初始化阶段T51，第一控制信号S1为低电位，第三控制信号Sp1、第二控制信号S2和发光控制信号EM为高电位。晶体管M14导通，初始化电压信号Vref通过晶体管M14传输至驱动晶体管M11的栅极，初始化驱动晶体管M11的栅极。
数据写入阶段T52，第三控制信号Sp1和第二控制信号S2为低电位，第一控制信号S1和发光控制信号EM为高电位。晶体管M12和晶体管M13均导通。数据电压Vdata经由晶体管M12、驱动晶体管M11和晶体管M13传输至驱动晶体管M11的栅极，直至驱动晶体管M11的栅极电压达到Vdata+Vth1，驱动晶体管M11关闭。其中，Vth1为驱动晶体管M11的阈值电压。同时，晶体管M17导通，初始化电压信号Vref通过晶体管M17传输至发光器件L的阳极，对发光器件L的阳极进行初始化。
第一发光阶段T53，发光控制信号EM为低电位，第一控制信号S1、第三控制信号Sp1和第二控制信号S2为高电位。晶体管M15和晶体管M16均导通。驱动晶体管M11基于第一电源信号VDD和驱动晶体管M11的栅极电位产生驱动电流，驱动发光器件L发光。
上述驱动过程为像素驱动电路200在刷新帧(Active frame)中的驱动时序。当像素驱动电路200的驱动过程中还包括保持帧(Idle frame)时，保持帧Idle frame中的驱动过程包括：
非发光阶段T54，发光控制信号EM为高电位。晶体管M15和晶体管M16均关断。驱动晶体管M11与发光器件L之间的连接通路被断开，发光器件L不发光。该阶段中，第三控制信号Sp1的导通脉冲可以存在，可实现对发光器件L的阳极和对驱动晶体管M11的第一极的复位，以修正发光器件L和驱动晶体管M11在发光过程中的特性漂移。
第二发光阶段T55，发光控制信号EM为低电位。晶体管M15和晶体管M16 均导通。驱动晶体管M11基于第一电源信号VDD和驱动晶体管M11的栅极在刷新帧中保存的电位产生驱动电流，驱动发光器件L发光。
由上述分析可知，像素驱动电路200在高频显示时，第一控制信号S1、第三控制信号Sp1、第二控制信号S2和发光控制信号EM均为高频信号。像素驱动电路200在低频显示时，第一控制信号S1和第二控制信号S2为低频信号，发光控制信号EM为高频信号，第三控制信号Sp1可以为低频信号或高频信号。
本申请实施例所提供的第一扫描驱动电路，用于控制各像素驱动电路的数据写入过程，各级第一移位寄存器输出的扫描信号可作为像素驱动电路中所需的第二控制信号S2，用于控制数据电压向驱动晶体管M11栅极写入的过程。像素驱动电路所需的其他控制信号，可以由显示面板中的其他扫描驱动电路分别提供。例如，显示驱动电路中还可以包括：第二扫描驱动电路，用于向各行像素驱动电路提供第三控制信号Sp1；发光控制驱动电路，用于向各行像素驱动电路提供发光控制信号EM；第三扫描驱动电路，用于向各行像素驱动电路提供第一控制信号S1。其中，由于第一控制信号S1的频率跟随显示刷新频率变动，第三扫描驱动电路可采用与第一扫描驱动电路相同的结构。进一步的，由于第一控制信号S1和第二控制信号S2的导通电位和导通脉宽相同，频率也相同，针对同一行子像素，两控制信号仅导通电位的作用时间不同，那么，显示驱动电路中，可以将第一扫描驱动电路复用为第三扫描驱动电路，以减小面板边框。具体地，可以将不同级第一移位寄存器连接至同一行像素驱动电路，前级第一移位寄存器为像素驱动电路提供第一控制信号S1，后级(后一级或后几级，可根据实际需求设置)第一移位寄存器为像素驱动电路提供第二控制信号S2。
图22是本申请实施例提供的另一种显示面板的结构示意图。下面结合图22，对第一扫描驱动电路在应用于显示面板中时，与像素驱动电路可能具有的连接关系进行说明。参见图22，在一种实施方式中，可选地，在显示面板中，像素驱动电路200设置于显示面板的显示区AA，各扫描驱动电路和发光控制驱动电路400设置于显示面板的非显示区NAA。非显示区NAA的各驱动电路通过信号线向各行像素驱动电路200提供控制信号。
具体地，显示面板中设置有第一扫描驱动电路100，第二扫描驱动电路700和发光控制驱动电路400。第二扫描驱动电路700包括级联设置的多级第二移位寄存器70；发光控制驱动电路400包括级联设置的多级第三移位寄存器40。第j级第一移位寄存器10的寄存器输出端与第j行像素驱动电路200连接的第二扫描线LS2电连接、第j+b级第一移位寄存器10的寄存器输出端与第j行像素驱 动电路200连接的第一扫描线LS1电连接。其中，j，b均为正整数，图22中示例性地，b＝1。第j级第二移位寄存器70与第j行像素驱动电路200连接的第三扫描线LS3电连接、第j级第三移位寄存器40与第j行像素驱动电路200连接的发光控制信号线LEM电连接。各条第一扫描线LS1分别向各行像素驱动电路200提供第二控制信号S2、各条第二扫描线LS2分别向各行像素驱动电路200提供第一控制信号S1、各条第三扫描线LS3分别向各行像素驱动电路200提供第三控制信号Sp1、各条发光控制信号线LEM分别向各行像素驱动电路200提供发光控制信号EM。
图23是本申请实施例提供的一种第一移位寄存器的结构示意图。参见图23，在一种实施方式中，可选地，第一移位寄存器可采用包括八个晶体管和两个电容的电路架构。该第一移位寄存器包括：晶体管M1至晶体管M8，电容C3和电容C4。图24是本申请实施例提供的一种第一移位寄存器的驱动时序示意图。参见图23和图24，该移位寄存器的驱动过程包括：
第一阶段T41，第一时钟信号CLK1和扫描输入信号SIN为低电位，第二时钟信号CLK2为高电位。晶体管M1和晶体管M2导通，晶体管M5截止；晶体管M8导通；扫描输入信号SIN的低电位通过晶体管M1传输至节点N1，使晶体管M3导通；第一时钟信号CLK1的低电位通过晶体管M3传输至节点N2，同时，第二电位信号VGL的低电位通过晶体管M2传输至节点N2，使晶体管M7导通；第一电位信号VGH的高电位通过晶体管M7传输至移位寄存器的输出端；节点N1的低电位通过晶体管M8传输至节点N3，使晶体管M6导通；第二时钟信号CLK2的高电位通过晶体管M6传输至移位寄存器的输出端。因此，在第一阶段T31中，移位寄存器的输出信号SOUT为高电位。
第二阶段T42，第二时钟信号CLK2为低电位，第一时钟信号CLK1和扫描输入信号SIN均为高电位。晶体管M1和晶体管M2截止，晶体管M5导通；晶体管M8保持导通。由于电容C3的存储作用，节点N3保持上一阶段的低电位，使晶体管M6导通；节点N3的低电位通过晶体管M8传输至节点N1，使晶体管M3导通。第一时钟信号CLK1的高电位通过晶体管M3传输至节点N2，使晶体管M7截止。第二时钟信号CLK2的低电位通过晶体管M6输出，输出信号SOUT为低电位。
第三阶段T43，第一时钟信号CLK1为低电位，第二时钟信号CLK2和扫描输入信号SIN均为高电位。晶体管M1和晶体管M2导通，晶体管M5截止；晶体管M8导通。扫描输入信号SIN的高电位通过晶体管M1传输至节点N1，使 晶体管M3截止；节点N1的高电位通过晶体管M8传输至节点N3，使晶体管M6截止。第二电位信号VGL的低电位通过晶体管M2传输至节点N2，使晶体管M7导通；第一电位信号VGH的高电位通过晶体管M7输出，输出信号SOUT为高电位。
第四阶段T44，第二时钟信号CLK2为低电位，第一时钟信号CLK1和扫描输入信号SIN均为高电位。晶体管M1和晶体管M2截止，晶体管M5导通；晶体管M8导通。由于电容C4的存储作用，节点N2保持上一阶段的低电位，使晶体管M4和晶体管M7导通。第一电位信号VGH的高电位通过晶体管M4、晶体管M5和晶体管M8传输至节点N3，使晶体管M6截止。第一电位信号VGH的高电位通过晶体管M7输出，输出信号SOUT为高电位。
重复第三阶段T43和第四阶段T44，输出信号SOUT保持高电位，直至扫描输入信号SIN再次变为低电位。
在另一种实施方式中，可选地，第一移位寄存器输出的扫描信号的导通电位为高电位。此时，辅助切断信号为低电位。下面对应用该类扫描信号的像素驱动电路的结构，产生该类扫描信号的移位寄存电路，以及像素驱动电路与第一扫描驱动电路的连接方式进行说明。
图25是本申请实施例提供的另一种像素驱动电路的结构示意图，与图20中像素驱动电路的不同之处在于，在图25中，将阈值补偿模块43中的晶体管M13和第一复位模块45中的晶体管M14替换为了N型晶体管，例如为IGZO晶体管，构成低温多晶氧化物(Low Temperature Polycrystalline Oxide，LTPO)像素驱动电路。基于N型IGZO晶体管漏电流低和长程均一性好的优点，该像素驱动电路可以抑制发光过程中驱动晶体管M11栅极的漏电，有利于实现更低刷新频率的显示。
图26是本申请实施例提供的另一种像素驱动电路的驱动时序示意图。图26与图21的不同之处仅在于，第一控制信号S1与第二控制信号S2均变为图21中对应控制信号的反相信号，即，第一控制信号S1与第二控制信号S2的导通电位均为高电位，前述对于像素驱动电路的驱动过程的分析同样适用于该像素驱动电路，不再赘述。以及，该像素驱动电路与各扫描驱动电路之间仍可采用与图22中相同的连接关系，不再赘述。
图27是本申请实施例提供的另一种第一移位寄存器的结构示意图。参见图27，在一种实施方式中，可选地，第一移位寄存器可采用包括十个晶体管和三个电容的电路架构，以产生导通电位为高电位的输出信号。该第一移位寄存器 包括：晶体管M21至晶体管M30，以及电容C5至电容C7。图28是本申请实施例提供的另一种第一移位寄存器的驱动时序示意图。参见图27和图28，该移位寄存器的驱动过程包括：
第一阶段T61，第一时钟信号CLK1为低电位，第二时钟信号CLK2和扫描输入信号SIN为高电位。晶体管M21和晶体管M23导通，晶体管M25和晶体管M27截止；扫描输入信号SIN的高电位通过晶体管M21传输至节点N4，使晶体管M22、晶体管M28和晶体管M30截止。第二电位信号VGL的低电位通过晶体管M23传输至节点N5，使晶体管M24和晶体管M26导通。由于电容C7的存储作用，节点N6保持前一阶段的高电位，使晶体管M29截止。因此，输出信号SOUT保持前一阶段的低电位。
第二阶段T62，第二时钟信号CLK2为低电位，第一时钟信号CLK1和扫描输入信号SIN为高电位。晶体管M25和晶体管M27导通，晶体管M21和晶体管M23截止。由于电容C6的存储作用，节点N5保持上一阶段的低电位，使晶体管M24和晶体管M26导通。第一电位信号VGH的高电位通过晶体管M24和晶体管M25传输至节点N4，使晶体管M22、晶体管M28和晶体管M30维持截止状态。第二时钟信号CLK2的低电位通过晶体管M26和晶体管M27传输至节点N6，使晶体管M29导通，第一电位信号VGH通过晶体管M29传输，输出信号SOUT变为高电位。
第三阶段T63，第一时钟信号CLK1为低电位，第二时钟信号CLK2和扫描输入信号SIN为高电位。晶体管M21和晶体管M23导通，晶体管M25和晶体管M27截止。扫描输入信号SIN的高电位通过晶体管M21传输至节点N4，使晶体管M22、晶体管M28和晶体管M30截止。第二电位信号VGL的低电位通过晶体管M23传输至节点N5，使晶体管M24和晶体管M26导通。由于电容C7的存储作用，节点N6保持上一阶段的低电位，使得晶体管M29保持导通，输出信号SOUT保持高电位。
第四阶段T64，第一时钟信号CLK1为高电位，第二时钟信号CLK2和扫描输入信号SIN为低电位。晶体管M21和晶体管M23截止，晶体管M25和晶体管M27导通。由于电容C6的存储作用，节点N5保持上一阶段的低电位，使晶体管M24和晶体管M26导通。第一电位信号VGH的高电位通过晶体管M24和晶体管M25传输至节点N4，使晶体管M22、晶体管M28和晶体管M30维持截止状态。第二时钟信号CLK2的低电位通过晶体管M26和晶体管M27传输至节点N6，使晶体管M29导通，第一电位信号VGH的高电位通过晶体管M29 传输，输出信号SOUT保持高电位。
第五阶段T65，第二时钟信号CLK2为高电位，第一时钟信号CLK1和扫描输入信号SIN为低电位。晶体管M21和晶体管M23导通，晶体管M25和晶体管M27截止。扫描输入信号SIN的低电位通过晶体管M21传输至节点N4，使晶体管M22、晶体管M28和晶体管M30导通。第一时钟信号CLK1的低电位通过晶体管M22传输至节点N5，使晶体管M24和晶体管M26导通，然而，由于晶体管M27截止，无法将节点N5的低电位传输至节点N6。第一电位信号VGH的高电位通过晶体管M28传输至节点N6，使晶体管M29截止。第二电位信号VGL的低电位通过晶体管M30传输，输出信号SOUT变为低电位。
第六阶段T66，第一时钟信号CLK1为高电位，第二时钟信号CLK2和扫描输入信号SIN为低电位。晶体管M25和晶体管M27导通。由于电容C5的耦合作用，随着第二时钟信号CLK2变为低电位，节点N4的电位变为一个比第五阶段25时更低的低电位，使晶体管M22、晶体管M28和晶体管M30维持导通；第一时钟信号CLK1的高电位通过晶体管M22传输至节点N5，使节点N5变为高电位；第一电位信号VGH的高电位通过晶体管M28传输至节点N6，使晶体管M29保持截止。相比于上一阶段，虽然此阶段晶体管M27已导通，但由于节点N5的电位已变为高电位，晶体管M26关闭，并不会拉低节点N6的电位，节点N6可保持高电位。第二电位信号VGL的低电位通过晶体管M30传输，输出信号SOUT保持低电位。
后续重复第五阶段T25和第六阶段T26，移位寄存器持续输出低电位。直至扫描输入信号SIN再次变为高电位。
需要说明的是，在本实施例提供的移位寄存器电路中，通过调节扫描输入信号SIN的截止脉冲宽度，可以调节扫描输入信号SIN与输出信号SOUT的对应关系。下面对不同脉冲宽度的应用场景进行示例性的说明。
在一种实施方式中，可选地，通过控制输入信号SIN的截止脉冲宽度与第一时钟信号CLK1的导通脉冲宽度相同，可使得扫描输入信号SIN与输出信号SOUT的截止脉冲不交叠。那么，各扫描驱动电路与像素驱动电路进可采用如图22中的连接方式，扫描驱动电路可向像素驱动电路提供图26中的驱动波形。
在另一种实施方式中，可选地，扫描输入信号SIN的截止脉冲宽度包含第一时钟信号CLK1的多个导通脉冲时，扫描输入信号SIN与输出信号SOUT的截止脉冲交叠。如图28中所示，扫描输入信号SIN的截止脉冲宽度包含第一时钟信号CLK1的两个导通脉冲时，想要对像素驱动电路提供图26中的驱动波形， 可将第j级第一寄存器的输出信号作为第j行像素驱动电路的第一控制信号S1，并将第j+3级第一寄存器的输出信号作为第j行像素驱动电路的第二控制信号S2。
在又一种实施方式中，可选地，图28中所示扫描输入信号SIN与输出信号SOUT的截止脉冲交叠的情况，也适用于如图22中的连接方式。此时，各扫描驱动电路向像素电路提供的驱动时序如图29所示。与图26中不同的是，在图29中，第一控制信号S1与第二控制信号S2的导通脉冲存在交叠。结合图25与图29，在第一控制信号S1与第二控制信号S2的导通脉冲交叠期间，晶体管M13和晶体管M14均导通，初始化电压信号Vref经晶体管M14传输至驱动晶体管M11的栅极后，继续经过晶体管M13传输至驱动晶体管M11的第二极，实现对驱动晶体管M11第二极的初始化，提高初始化效果。以及，数据写入阶段T52仍在初始化阶段T51结束后再进行，即，第三控制信号Sp1的导通脉冲位于第一控制信号S1的导通脉冲结束之后，并与第二控制信号S2的导通脉冲交叠。
需要说明的是，上述各实施例中给出的各移位寄存器的结构，并不作为对本申请的限定，在其他实施方式中，第一移位寄存器可采用现有的任意结构的移位寄存电路实现。
上述各实施方式示例性地给出了对显示面板在第一方向上进行分区多频驱动，即上下分区多频驱动的方案，但不作为对本申请的限定。在其他实施方式中，通过在显示区增设分屏控制模块，还可以使显示面板支持在第二方向(即子像素行方向)上的分屏驱动，即左右分区多频驱动，以实现对显示面板更灵活的控制。其中，第一方向与第二方向相交。
图30是本申请实施例提供的又一种显示面板的结构示意图。参见图30，在一种实施方式中，可选地，显示面板的非显示区包括两个非显示子区NAA1、NAA2；两个非显示子区NAA1、NAA2沿第二方向分别设置于显示区AA两侧。至少一个第一扫描驱动电路包括两个第一扫描驱动电路1001、1002。示例性地，第一侧第一扫描驱动电路1001设置于第一非显示子区NAA1，第二侧第一扫描驱动电路1002设置于第二非显示子区NAA2。第一侧第一扫描驱动电路1001和第二侧第一扫描驱动电路1002中的对应级第一移位寄存器10连接同一条第一扫描线。
在显示面板中所有第一扫描线中，至少部分第一扫描线中的每条第一扫描线包括至少两条子扫描线。显示驱动电路还包括：至少一个分屏控制模块50， 分屏控制模块50设置于显示区AA。每个分屏控制模块50中均可包括多个分屏开关单元51；同一分屏控制模块50中的多个分屏开关单元51与由子扫描线构成的各第一扫描线分别对应。每个分屏开关单元51连接于同一第一扫描线中相邻的两个子扫描线LS11、LS12之间。任意一个分屏开关单元51响应于分屏控制信号关断时，第一侧第一扫描驱动电路1001和第二侧第一扫描驱动电路1002分别向该分屏开关单元51两侧的子扫描线传输扫描信号。
其中，在同一扫描线上包括多个分屏开关单元51的情况下，同一扫描线上的多个分屏开关单元51沿第二方向依次排列。同一时刻，同一第一扫描线上处于关断状态的分屏开关单元的数量小于或等于1个。关断的分屏开关单元51将第一扫描线切分为两部分，两侧的子扫描线由不同的第一扫描驱动电路传输扫描信号，以保证两侧子像素的正常驱动。
可选地，与第一侧第一扫描驱动电路1001连接的级联控制信号为第一侧级联控制信号，与第二侧第一扫描驱动电路1002连接的级联控制信号为第二侧级联控制信号；第一侧级联控制信号与第二侧级联控制信号不同。以及，与第一侧第一扫描驱动电路1001连接的开关控制信号为第一侧开关控制信号SW21，与第二侧第一扫描驱动电路1002连接的开关控制信号为第二侧开关控制信号SW22；第一侧开关控制信号SW21与第二侧开关控制信号SW22不同。这样，在分屏控制模块50断开时，分屏控制模块50两侧的子显示区可以以不同刷新频率和/或不同上下分区位置进行显示。两侧第一扫描驱动电路1001、1002所接入的各控制信号可由驱动IC 60分别提供。
其中，分屏控制模块50的工作过程包括：
当同一行子像素的刷新频率相同时，控制该行子像素对应的所有分屏开关单元51导通，左右两侧的第一移位寄存器10输出的扫描信号连接在一起，实现该行子像素的双边驱动，以增加扫描驱动电路的驱动能力，减缓单边驱动时因RC延迟导致分屏位置显示不均，避免显示分屏分界风险，即避免左右半屏亮度存在差异的现象。在全屏刷新频率相同的情况下，可以控制所有分屏开关单元51均导通。
在某一行子像素的左侧和右侧的刷新频率不同时，在该行子像素的扫描信号的导通脉冲到达该行时，控制该行子像素对应的左右分屏位置的分屏开关单元51断开，并控制该行的其他分屏开关单元导通。分屏位置左侧的扫描信号由第1个第一扫描驱动电路1001提供，分屏位置右侧的扫描信号由第2个第一扫描驱动电路1002提供，可实现左右屏刷新率不同的驱动方式。
图31是本申请实施例提供的又一种显示面板的结构示意图。参见图31，在上述各实施方式的基础上，可选地，同一分屏控制模块50中的所有分屏开关单元51接入相同的分屏控制信号SW3。示例性地，不同分屏控制模块50接入不同的分屏控制信号；同一时间最多存在一个分屏控制模块50关断，其他分屏控制模块50导通。分屏控制信号SW3可以由驱动IC 60提供，在一帧显示中，分屏控制信号SW3可以进行电位跳变，或不进行电位跳变。当分屏控制信号SW3在一帧显示中不进行电位跳变时，显示面板在该帧显示中的左右分屏状态不变；当分屏控制信号SW3在一帧显示中进行电位跳变时，显示面板在该帧显示中的左右分屏状态改变，例如在一段时间内左右分屏，在其他时间内左右不分屏。下面以显示驱动电路中包括一个分屏控制模块50为例，对显示面板的驱动模式进行说明。需要说明的是，当分屏开关单元51的设置位置确定时，显示面板的左右分屏位置固定。在以下实施方式中，以实线表示固定位置的分屏，以虚线标示位置可调的分屏。
继续参见图31，在一种实施方式中，可选地，第一扫描线包括第一子扫描线LS11和第二子扫描线LS12，第一子扫描线LS11和第二子扫描线LS12分别与不同的第一扫描驱动电路连接。显示驱动电路中包括一个分屏控制模块50；每个分屏控制单元51分别与对应的第一子扫描线LS11和第二子扫描线LS12电连接。第一侧第一扫描驱动电路1001接入第一侧第一级联控制信号SW11和第一侧开关控制信号SW21，第二侧第一扫描驱动电路1002接入第二侧第一级联控制信号SW12和第二侧开关控制信号SW22。基于此结构，可以在不同的情景模式下灵活控制显示面板使用单边驱动或双边驱动，下面以分屏开关单元响应低电位导通，级联控制模块和辅助切断模块响应高电位导通为例，对各显示模式分别进行说明。
图32是本申请实施例提供的又一种显示面板的驱动时序示意图，对应于显示面板全屏统一刷新频率的显示模式，该模式下，分屏控制信号SW3保持低电位，控制各分屏开关单元51保持导通，实现整个显示面板的双边驱动，此时两侧第一扫描驱动模块的输出状态保持一致。在显示帧F1，对应于全屏刷新帧，第一级联控制信号SW11和SW12保持高电位，开关控制信号SW21和SW22保持低电位，使两个第一扫描驱动电路均可实现扫描信号导通电位的逐级移位输出。当全屏进行低频刷新时，显示帧还包括保持帧，可参见显示帧F2，第一级联控制信号SW11和SW12保持低电位，开关控制信号SW21和SW22保持高电位，两个第一扫描驱动电路接入的扫描输入信号可保持截止电位，两个第 一扫描驱动电路的级传均被切断，各扫描信号均保持截止电位。
图33是本申请实施例提供的又一种显示面板的驱动时序示意图，对应于显示面板仅在第二方向上进行分区，即左右分屏多频的显示模式，该模式下，分屏控制信号SW3保持高电位，控制各分屏开关单元51保持关断，实现左右两侧子显示区各自的单边驱动。此时，第1个第一扫描驱动电路1001根据左侧子显示区的驱动需求提供扫描信号，第2个第一扫描驱动电路1002根据右侧子显示区的驱动需求提供扫描信号。示例性地，左侧子显示区以刷新频率f1进行显示，右侧子显示区以刷新频率f1/2进行显示。例如，第一侧第一级联控制信号SW11可以保持高电位，第一侧开关控制信号SW21可以保持低电位，控制左侧子显示区在每个显示帧都进行刷新。第二侧第一级联控制信号SW12在奇数帧保持高电位，在偶数帧保持低电位，第二侧开关控制信号SW22在奇数帧保持低电位，在偶数帧保持高电位，控制右侧子显示区仅在奇数帧进行刷新。
上述分屏控制信号SW3的电位设置并不作为对本申请的限定。在其他实施方式中，在同一条第一扫描线上，与多个分屏开关单元中的一个分屏开关单元的两端分别对应连接的两条子扫描线上同时传输扫描信号的导通电位时，分屏控制信号可控制该分屏开关单元导通。以图31中的结构为例，在任一行像素驱动电路的扫描时间内，当分屏开关单元两侧的像素驱动电路同时进行数据写入时，分屏控制信号SW3均可变换为导通电位，控制分屏开关单元导通，在该行像素驱动电路的扫描时间内，形成对该行像素驱动电路的双边驱动，以提升数据写入效果。示例性地，如图34所示，在显示帧F1和F3中，左右两侧子显示区都进行刷新，相应的可设置分屏控制信号SW3为低电位。
图35是本申请实施例提供的又一种显示面板的驱动时序示意图，对应于显示面板仅在第一方向上进行多频显示，即上下分屏多频的显示模式。该模式下，分屏控制信号SW3保持低电位，控制各分屏开关单元51保持导通，实现整个显示面板的双边驱动，此时两侧第一扫描驱动模块的输出状态保持一致。示例性地，上侧子显示区以刷新频率f1进行显示，下侧子显示区以刷新频率f1/2进行显示。例如，在显示帧F1，第一级联控制信号SW11和SW12保持高电位，开关控制信号SW21和SW22保持低电位，控制显示区所有子像素都进行刷新。在显示帧F2，目标分区位置的前一行子像素的扫描时间到来之前，第一级联控制信号SW11与SW12保持高电位，开关控制信号SW21和SW22保持低电位，控制上侧子显示区的子像素都进行刷新；目标分区位置的前一行子像素的扫描时间到来直至本帧结束，第一级联控制信号SW11与SW12保持低电位，开关 控制信号SW21和SW22保持高电位，控制下侧子显示区的子像素都不刷新。以显示帧F1和显示帧F2为一个循环，重复该循环，可以使上侧子显示区各子像素在每个显示帧都刷新，下侧子显示区各子像素仅在奇数帧进行刷新。
图36是本申请实施例提供的又一种显示面板的驱动时序示意图，对应于显示面板在第一方向和第二方向上均进行多频的显示模式，例如上下左右四分屏多频显示。该模式下，分屏控制信号SW3可以始终保持高电位，控制各分屏开关单元51保持关断，实现左右两侧子显示区各自的单边驱动，以减少分屏控制信号SW3的电位跳变，简化控制逻辑。或者，在任一显示帧，当左右两侧的部分行像素驱动电路均刷新时，可设置对应行像素驱动电路的扫描时间内，分屏控制信号SW3保持低电位。示例性地，左上部子显示区以刷新频率f1进行显示，左下部子显示区以刷新频率f1/4进行显示，右上部子显示区以刷新频率f1/2进行显示，右下部子显示区以刷新频率f1/8进行显示。对于左侧的两个子显示区，第1个第一扫描驱动电路1001的驱动模式以4个显示帧为一个循环，通过第一侧第一级联控制信号SW11和第一侧开关控制信号SW21控制左上侧子显示区各子像素在每个显示帧都刷新，左下侧子显示区各子像素仅在每个循环的第一显示帧中进行刷新。对于右侧的两个子显示区，第2个第一扫描驱动电路1002的驱动模式以8个显示帧为一个循环，通过第二侧第一级联控制信号SW12和第二侧开关控制信号SW22控制右上侧子显示区各子像素在奇数帧进行刷新，右下侧子显示区各子像素仅在每个循环的第一显示帧中进行刷新。
图37是本申请实施例提供的又一种显示面板的驱动时序示意图，对应于显示面板在第一方向和第二方向上均进行多频的显示模式，例如上侧左右不分屏，下侧左右分屏的三分屏多频显示。该模式下，在每帧显示中，分屏控制信号SW3进行电位跳变，电位跳变时间与第一级联控制信号和开关控制信号的电位跳变时间相配合。示例性地，上侧子显示区以刷新频率f1进行显示，左下部子显示区以刷新频率f1/2进行显示，右下部子显示区以刷新频率f1/4进行显示。在上侧子显示区的扫描时间内，分屏控制信号SW3保持低电位，控制各分屏开关单元51保持导通，实现上侧子显示区的双边驱动；在上侧子显示区的驱动过程中，两个第一扫描驱动电路的输出保持一致，例如控制上侧子显示区在各显示帧都进行刷新。在下侧两子显示区的扫描时间内，分屏控制信号SW3保持高电位，控制各分屏开关单元51保持关断，实现下左和下右两子显示区各自的单边驱动；在下侧两子显示区的驱动过程中，通过第一侧第一级联控制信号SW11和第一侧开关控制信号SW21控制左下侧子显示区各子像素在奇数帧进行刷新，通过 第二侧第一级联控制信号SW12和第二侧开关控制信号SW22控制右下侧子显示区各子像素每4个显示帧刷新一次。
示例性地，该上侧左右子显示区不分屏的显示模式也可以通过在四分屏模式下控制左上和右上两个子显示区的刷新频率一致实现。但相比之下，如图37中所示，在左右侧子显示区刷新频率一致时控制分屏开关单元导通，可以减缓单边驱动导致的显示不均，改善上侧子显示区的显示效果。另外，在图37中的驱动模式中，还可以控制分屏控制信号SW3在三个子显示区均进行刷新的显示帧中保持低电位，使整个显示屏实现双边驱动，提高显示效果。
图38是本申请实施例提供的又一种显示面板的驱动时序示意图，对应于显示面板在第一方向和第二方向上均进行多频的显示模式，例如上侧左右分屏，下侧左右不分屏的三分屏多频显示。该模式下的驱动过程与图37中类似，在每帧显示中，分屏控制信号SW3进行电位跳变。示例性地，左上部子显示区以刷新频率f1进行显示，右上部子显示区以刷新频率f1/2进行显示，下侧子显示区以刷新频率f1/4进行显示。在上侧子显示区的扫描时间内，分屏控制信号SW3保持高电位，控制各分屏开关单元51保持关断，实现上左和上右两子显示区各自的单边驱动；在上侧两子显示区的驱动过程中，通过第一侧第一级联控制信号SW11和第一侧开关控制信号SW21控制左上侧子显示区各子像素每帧刷新，通过第二侧第一级联控制信号SW12和第二侧开关控制信号SW22控制右上侧子显示区各子像素在奇数帧刷新。在下侧子显示区的扫描时间内，分屏控制信号SW3保持低电位，控制各分屏开关单元51保持导通，实现下侧子显示区的双边驱动；在下侧子显示区的驱动过程中，两个第一扫描驱动电路的输出保持一致，例如控制下侧子显示区各子像素每4个显示帧刷新一次。
综上所述，通过在各显示帧中控制分屏控制信号SW3、两侧第一级联控制信号和两侧开关控制信号是否进行电位跳变，以及控制上述控制信号的电位跳变时间，可以实现对显示面板分屏模式的控制，以在不同的情景模式下灵活控制使用单边驱动或双边驱动。上述各实施方式中，均以上下二分屏为例进行说明，但不作为对本申请的限定，在实际应用时，可以根据需求设置显示面板上下分屏的数量，以及各分区的刷新频率。以及，上述各实施例中给出的频率组合仅作为示意，实际频率组合可以根据需求情况自行定义，不仅限于图示的几种情况。
上述各实施方式中示例性地给出了分屏控制单元51与第一扫描线一一对应的控制方案，但不作为对本申请的限定。在其他实施方式中，若要实现图37或 图38中的分屏多频显示方式，还可以仅在需要左右分屏的位置设置分屏控制单元51，而在不需要左右分屏的位置，设置第一扫描线不分段。
在上述各实施方式的基础上，可选地，第一子扫描线LS11与第二子扫描线LS12的长度相同，以使两个子扫描线的寄生电阻等特征参数都相同，使左右两侧子像素的充电时间一致，提高显示面板的显示均一性。
上述各实施方式中示例性地给出了设置一个分屏控制模块时，显示面板的驱动方案，但不作为对本申请的限定。在其他实施方式中，显示面板中还可以设置多个分屏控制模块，通过对各分屏控制模块的通断控制，可以使显示面板左右分屏的位置更灵活。下面以设置两个分屏控制模块为例进行说明。
图39是本申请实施例提供的又一种显示面板的结构示意图。参见图39，示例性地，第一扫描线包括三段子扫描线，分别为第三子扫描线LS13、第四子扫描线LS14和第五子扫描线LS15；显示驱动电路包括：沿第二方向依次排列的第一分屏控制模块501和第二分屏控制模块502。第三子扫描线LS13与第一侧第一扫描驱动电路1001连接，第一分屏控制模块501连接于第三子扫描线LS13和第四子扫描线LS14之间，第二分屏控制模块502连接于第四子扫描线LS14和第五子扫描线LS15之间，第五子扫描线LS15与第二侧第一扫描驱动电路1002连接。分屏控制信号包括第一分屏控制信号SW31和第二分屏控制信号SW32。其中，第一分屏控制模块501接入第一分屏控制信号SW31，第二分屏控制模块502接入第二分屏控制信号SW32。
图40是本申请实施例提供的又一种显示面板的驱动时序示意图，对应于显示面板在第一方向和第二方向上均进行多频的显示模式，例如上下左右四分屏多频显示。相较于图36中的显示模式，该模式中针对不同行子像素，左右分屏的位置可选。示例性地，每个显示帧中，在上侧两子显示区的扫描时间内，第一分屏控制信号SW31保持高电位，第二分屏控制信号SW32保持低电位，使得第一分屏控制模块501关断，第二分屏控制模块502导通，因此上侧左右分屏位置位于第一分屏控制模块501的设置位置。在下侧两子显示区的扫描时间内，第一分屏控制信号SW31保持低电位，第二分屏控制信号SW32保持高电位，使得第一分屏控制模块501导通，第二分屏控制模块502关断，因此下侧左右分屏位置位于分屏控制模块502的设置位置。
本实施例中通过设置多个分屏控制模块50，可实现显示面板的左右分区位置可调。具体实现过程为：在同一显示帧中，在部分行像素驱动电路的数据写入过程中，控制第一分屏控制模块501导通，第二分屏控制模块502关断，在 其他行像素驱动电路的数据写入过程中，控制第一分屏控制模块501关断，第二分屏控制模块502导通。
继续参见图39，在上述各实施方式的基础上，可选地，分屏开关单元51包括：第五晶体管T5；第五晶体管T5的栅极接入分屏控制信号，第五晶体管T5的第一极与第二极分别与同一第一扫描线中相邻的两条子扫描线连接。可选地，第五晶体管T5可以是开关晶体管，以使得其导通时的阻抗较小，减小因第五晶体管T5的设置给驱动电路带来的负担。示例性地，第五晶体管T5的宽长比等尺寸可以参照像素驱动电路中的开关晶体管设计。
示例性地，当显示驱动电路中设置多个分屏控制模块50，各分屏控制模块50中可使用沟道类型相同的晶体管，各分屏控制模块50接入不同的分屏控制信号。或者，若两分屏控制模块50包括沟道类型不同的晶体管，比如，如图41所示，第一分屏控制模块501中包括P型晶体管，第二分屏控制模块502中包括N型晶体管，且两分屏控制模块50的开关状态相反，可以将两分屏控制模块501，502接入同一分屏控制信号SW3，以减少驱动IC的输出端口，降低成本。
需要说明的是，显示面板中驱动IC 60的数量可以根据实际需求设置，例如图39中设置两颗驱动IC 60，或如图41中设置一颗驱动IC 60。
还需要说明的是，上述各实施方式示例性地示出了将分屏控制模块设置于第一扫描线的各段子扫描线之间，但不作为对本申请的限定。在其他实施方式中，当各第一寄存器还连接第二扫描线时，还可以设置第二扫描线包括多条子扫描线，并对应第一扫描线的连接方式，在第二扫描线的各子扫描线之间也设置分屏控制模块。
本申请实施例还提供了一种显示驱动电路的控制方法，用于控制如本申请任意实施例所提供的显示驱动电路，具有相应的有益效果。该显示驱动电路的控制方法包括：
获取显示面板在第一方向(即子像素的列方向)上的目标分区位置；
根据目标分区位置，确定每帧显示中的级联控制信号，并基于级联控制信号控制每帧显示中级联控制模块的开关状态。
本申请实施例提供的显示驱动电路的控制方法中，级联控制信号通过控制级联控制模块的开关状态，可以控制第一移位寄存器输出的扫描信号的导通电位是否能逐级传递。通过切断扫描信号的导通电位向下级第一移位寄存器的传输，可以实现同一帧显示中分区显示，且刷新频率由高转低的驱动方案。并且，多个级联控制模块的设置，使得各显示帧中扫描信号导通电位的传输被切断的 位置可调，进而使得显示面板的降频显示分区位置可调，以丰富显示面板的显示功能，使显示面板的驱动过程更灵活。
在上述各实施方式的基础上，可选地，至少一个级联控制模块包括多个级联控制模块，显示面板包括至少一个目标分区位置。那么，显示面板的显示过程中包括多类显示帧；多类显示帧中包括第一刷新帧和至少一类第二刷新帧；第二刷新帧的类别与目标分区位置分别对应。
在第一刷新帧中，级联控制信号控制所有级联控制模块均保持导通。因此该类显示帧中，显示面板进行全屏刷新。
在第二刷新帧中，级联控制信号控制所有级联控制模块的关断时间，或控制预设位置的级联控制模块关断，使显示面板基于第二刷新帧对应的目标分区位置进行显示，目标分区位置以上的子像素处于刷新帧，目标分区位置以下的子像素处于保持帧。
需要说明的是，在显示驱动电路的各实施例中，针对不同的驱动电路进行了控制方法的具体说明，这些控制方法均可以认为是本申请实施例提供的驱动电路的控制方法，重复内容此处不再赘述。
本申请实施例还提供了一种显示装置，包括如本申请任意实施例所提供的显示驱动电路，具有相应的有益效果。示例性地，显示装置包括上述任意实施例提供的显示面板，显示驱动电路设置于显示面板中，显示面板可以是有源矩阵有机发光二极管面板或微发光二极管显示面板等类型的显示面板。该显示装置可以是手机、平板电脑、电视机或显示器等任何具有显示功能的产品或部件。
应该理解，可以使用上面所示的各种形式的流程，重新排序、增加或删除步骤。例如，本申请中记载的各步骤可以并行地执行也可以顺序地执行也可以不同的次序执行，只要能够实现本申请的实施例所期望的结果，本文在此不进行限制。
上述具体实施方式，并不构成对本申请保护范围的限制。本领域技术人员应该明白的是，根据设计要求和其他因素，可以进行各种修改、组合、子组合和替代。任何在本申请的精神和原则之内所作的修改、等同替换和改进等，均应包含在本申请保护范围之内。

Claims (27)

  1. 一种显示驱动电路，包括：至少一个第一扫描驱动电路；
    所述至少一个第一扫描驱动电路包括：
    级联设置的多个第一移位寄存器，每个第一移位寄存器包括寄存器输入端和寄存器输出端，所述多个第一移位寄存器设置为输出多个扫描信号；
    至少一个级联控制模块，所述至少一个级联控制模块连接于本级寄存器输出端和下级寄存器输入端之间，且所述至少一个级联控制模块接入级联控制信号，所述至少一个级联控制模块响应于所述级联控制信号控制所述扫描信号的导通电位从本级寄存器输出端向下级寄存器输入端的传输，以实现显示面板在第一方向上的多频显示。
  2. 根据权利要求1所述的显示驱动电路，其中，所述至少一个级联控制模块包括多个级联控制模块，所述多个级联控制模块与所述至少一个第一扫描驱动电路中的至少部分第一移位寄存器分别对应设置，每个所述级联控制模块分别设置于所述至少部分第一移位寄存器中对应的本级第一移位寄存器和对应的下级第一移位寄存器之间；所述级联控制信号通过控制所述级联控制模块的开关状态，调整一帧显示中扫描信号的导通电位向下级寄存器输入端的传输被切断的位置。
  3. 根据权利要求1或2所述的显示驱动电路，其中，所述级联控制信号包括：第一级联控制信号；
    每个级联控制模块包括：第一晶体管，所述第一晶体管的第一极与对应的本级寄存器输出端电连接，所述第一晶体管的第二极与对应的下级寄存器输入端电连接；所述第一晶体管的栅极接入所述第一级联控制信号。
  4. 根据权利要求3所述的显示驱动电路，其中，根据所述第一级联控制信号在一帧显示中的电位跳变时间，确定所述至少一个级联控制模块在一帧显示中的关断时间，从而确定显示面板在第一方向上降频显示的分区位置。
  5. 根据权利要求2所述的显示驱动电路，其中，所述级联控制信号包括：与所述多个级联控制模块分别对应的多个第二级联控制信号；
    每个级联控制模块包括：第二晶体管；所述第二晶体管的栅极接入对应的所述第二级联控制信号，所述第二晶体管连接在对应的本级寄存器输出端和对应的下级寄存器输入端之间；
    其中，所述至少一个第一扫描驱动电路还包括：第一电源端和第二电源端；以及，所述至少一个第一扫描驱动电路还包括：
    第一电阻串，包括串联连接在所述第一电源端和所述第二电源端之间的多 个第一电阻；所述第一电阻串中引出多个第一输出端，所述多个第一输出端输出所述多个第二级联控制信号；多个所述第一输出端与多个所述级联控制模块分别对应连接，相邻两个所述第一输出端之间设置有至少一个第一电阻。
  6. 根据权利要求5所述的显示驱动电路，其中，所述级联控制信号还包括：与所述多个级联控制模块分别对应的多个第三级联控制信号；
    每个级联控制模块中还包括：第三晶体管；所述第三晶体管的栅极接入对应的所述第三级联控制信号，所述第三晶体管和对应的所述第二晶体管串联连接在对应的本级寄存器输出端和对应的下级寄存器输入端之间；
    其中，所述至少一个第一扫描驱动电路还包括：第三电源端和第四电源端；以及，所述至少一个第一扫描驱动电路还包括：
    第二电阻串，包括串联连接在第三电源端和第四电源端之间的多个第二电阻；所述第二电阻串中引出多个第二输出端，所述多个第二输出端输出所述多个第三级联控制信号；多个所述第二输出端与多个所述级联控制模块分别对应连接，相邻两个所述第二输出端之间设置有至少一个第二电阻；
    其中，在一帧显示中，预设位置的级联控制模块响应于所述级联控制信号关断，以控制显示面板在第一方向上降频显示的分区位置；对所述预设位置的调整，基于对所述第一电源端、所述第二电源端、所述第三电源端和所述第四电源端的电位调整实现。
  7. 根据权利要求1所述的显示驱动电路，其中，所述至少一个第一扫描驱动电路，还包括：
    至少一个辅助切断模块，所述至少一个辅助切断模块与所述至少一个级联控制模块对应设置；每个辅助切断模块的控制端接入开关控制信号，每个辅助切断模块的输入端接入辅助切断信号，每个辅助切断模块的输出端与每个辅助切断模块对应的级联控制模块连接同一寄存器输入端。
  8. 根据权利要求7所述的显示驱动电路，其中，所述至少一个辅助切断模块包括多个辅助切断模块，所述至少一个级联控制模块包括多个级联控制模块，所述多个辅助切断模块与所述多个级联控制模块分别对应设置，所述多个辅助切断模块接入同一开关控制信号；根据所述开关控制信号在一帧显示中的电位跳变时间，确定所述多个辅助切断模块在一帧显示中的导通时间。
  9. 根据权利要求7所述的显示驱动电路，其中，所述本级第一移位寄存器和下级第一移位寄存器分别为第i级第一移位寄存器和第i+a级第一移位寄存器，i和a均为正整数；
    在第i级第一移位寄存器输出第i级扫描信号的导通电位，且第i+a级第一移位寄存器输出第i+a级扫描信号的导通电位的情况下，在第i级第一移位寄存器输出第i级扫描信号的导通电位的阶段，所述级联控制信号控制所述第i级第一移位寄存器和所述第i+a级第一移位寄存器之间的级联控制模块导通，且所述开关控制信号控制所述第i级第一移位寄存器和所述第i+a级第一移位寄存器之间的辅助切断模块关断；
    在第i级第一移位寄存器输出第i级扫描信号的导通电位，且第i+a级第一移位寄存器输出第i+a级扫描信号的截止电位的情况下，在第i级第一移位寄存器输出第i级扫描信号的导通电位的阶段，所述级联控制信号控制所述第i级第一移位寄存器和所述第i+a级第一移位寄存器之间的级联控制模块关断，且所述开关控制信号控制所述第i级第一移位寄存器和所述第i+a级第一移位寄存器之间的辅助切断模块导通。
  10. 根据权利要求7所述的显示驱动电路，还包括：第一电位信号线和第二电位信号线；所述第一电位信号线设置为向所述多个第一移位寄存器提供第一电位信号，所述第二电位信号线设置为向所述多个第一移位寄存器提供第二电位信号；
    当所述第一电位信号的电位为截止电位时，所述第一电位信号复用为所述辅助切断信号；当所述第二电位信号的电位为所述截止电位时，所述第二电位信号复用为所述辅助切断信号。
  11. 根据权利要求7所述的显示驱动电路，其中，所述级联控制信号包括：第一级联控制信号；每个级联控制模块包括：第一晶体管，所述第一晶体管的栅极接入所述第一级联控制信号，所述第一晶体管的第一极与对应的本级寄存器输出端电连接，所述第一晶体管的第二极与对应的下级寄存器输入端电连接；
    每个辅助切断模块包括：第四晶体管，所述第四晶体管的栅极接入所述开关控制信号，所述第四晶体管的第一极接入所述辅助切断信号，所述第四晶体管的第二极与对应的下级寄存器输入端电连接。
  12. 根据权利要求11所述的显示驱动电路，其中，所述第一晶体管与所述第四晶体管的沟道类型相同，所述第一级联控制信号和所述开关控制信号的相位相反；或者，
    所述第一晶体管与所述第四晶体管的沟道类型不同，所述第一级联控制信号复用为所述开关控制信号；或者，
    所述第一晶体管与所述第四晶体管的沟道类型相同，所述第一级联控制信 号复用为所述辅助切断信号。
  13. 根据权利要求1-12中任一项所述的显示驱动电路，还包括：多个像素驱动电路和多条第一扫描线，所述多个像素驱动电路呈阵列排布，每行像素驱动电路与所述多条第一扫描线中的至少一条第一扫描线电连接；所述至少一个第一扫描驱动电路中的寄存器输出端与所述第一扫描线电连接。
  14. 根据权利要求13所述的显示驱动电路，其中，每个像素驱动电路包括：驱动模块、数据写入模块、阈值补偿模块和发光控制模块；
    所述驱动模块连接于所述发光控制模块和发光器件之间，所述驱动模块设置为产生驱动电流；所述数据写入模块与所述驱动模块的第一端电连接，所述数据写入模块设置为将数据电压传输至所述驱动模块；所述阈值补偿模块连接于所述驱动模块的控制端和第二端之间，所述阈值补偿模块设置为补偿所述驱动模块的阈值电压；所述第一扫描线与对应行像素驱动电路中阈值补偿模块的控制端电连接。
  15. 根据权利要求14所述的显示驱动电路，其中，每个像素驱动电路还包括：第一复位模块，与所述驱动模块的控制端电连接，所述第一复位模块设置为对所述驱动模块的控制端进行复位；所述显示驱动电路还包括：多条第二扫描线，每条第二扫描线与对应行像素驱动电路中第一复位模块的控制端电连接；
    其中，所述至少一个第一扫描驱动电路中的寄存器输出端与所述第二扫描线电连接；其中，第j行像素驱动电路连接的第二扫描线与第j级寄存器输出端电连接，第j行像素驱动电路连接的第一扫描线与第j+b级寄存器输出端电连接；其中，j，b均为正整数。
  16. 根据权利要求13所述的显示驱动电路，其中，所述至少一个第一扫描驱动电路包括第一侧第一扫描驱动电路和第二侧第一扫描驱动电路，所述第一侧第一扫描驱动电路和所述第二侧第一扫描驱动电路分别设置于所述多个像素驱动电路的两侧；所述第一侧第一扫描驱动电路和所述第二侧第一扫描驱动电路中对应级的第一移位寄存器连接同一第一扫描线；
    所述多条第一扫描线中的至少部分第一扫描线中的每条第一扫描线包括至少两条子扫描线；
    所述显示驱动电路还包括：至少一个分屏控制模块；所述至少一个分屏控制模块中包括多个分屏开关单元；所述多个分屏开关单元与所述多个第一扫描线中的所述至少部分第一扫描线分别对应设置；每个所述分屏开关单元连接于同一第一扫描线中相邻的两条子扫描线之间；每个所述分屏开关单元响应于分 屏控制信号关断时，所述第一侧第一扫描驱动电路和所述第二侧第一扫描驱动电路分别向每个所述分屏开关单元两侧的子扫描线传输扫描信号。
  17. 根据权利要求16所述的显示驱动电路，其中，同一时刻，同一第一扫描线上处于关断状态的分屏开关单元的数量小于或等于1个；
    同一分屏控制模块中的所述多个分屏开关单元接入相同的分屏控制信号。
  18. 根据权利要求17所述的显示驱动电路，其中，与所述第一侧第一扫描驱动电路连接的级联控制信号为第一侧级联控制信号，与所述第二侧第一扫描驱动电路连接的级联控制信号为第二侧级联控制信号；所述第一侧级联控制信号与所述第二侧级联控制信号不同。
  19. 根据权利要求16所述的显示驱动电路，其中，与所述多个分屏开关单元中的一个分屏开关单元的两端分别对应连接的两条子扫描线上同时传输扫描信号的导通电位时，所述分屏控制信号控制所述多个分屏开关单元中的所述一个分屏开关单元导通。
  20. 根据权利要求16所述的显示驱动电路，其中，所述至少部分第一扫描线中的每条第一扫描线包括第一子扫描线和第二子扫描线，所述第一子扫描线与所述第一侧第一扫描驱动电路连接，所述第二子扫描线与所述第二侧第一扫描驱动电路连接；
    每个所述分屏控制单元分别与对应的第一子扫描线和第二子扫描线电连接。
  21. 根据权利要求16所述的显示驱动电路，其中，所述至少部分第一扫描线中的每个第一扫描线包括第三子扫描线、第四子扫描线和第五子扫描线；所述至少一个分屏控制模块包括：第一分屏控制模块和第二分屏控制模块；
    所述第三子扫描线与所述第一侧第一扫描驱动电路连接，所述第一分屏控制模块连接于所述第三子扫描线和所述第四子扫描线之间，所述第二分屏控制模块连接于所述第四子扫描线和所述第五子扫描线之间，所述第五子扫描线与所述第二侧第一扫描驱动电路连接。
  22. 根据权利要求21所述的显示驱动电路，其中，在同一显示帧中，部分行像素驱动电路的数据写入过程中，所述第一分屏控制模块导通，所述第二分屏控制模块关断，其他行像素驱动电路的数据写入过程中，所述第一分屏控制模块关断，所述第二分屏控制模块导通。
  23. 根据权利要求22所述的显示驱动电路，其中，所述分屏控制信号包括第一分屏控制信号和第二分屏控制信号，所述第一分屏控制模块接入所述第一 分屏控制信号，所述第二分屏控制模块接入所述第二分屏控制信号；所述第一分屏控制模块中分屏开关单元中的晶体管，与所述第二分屏控制模块中分屏开关单元中的晶体管的沟道类型不同，所述第一分屏控制信号复用为所述第二分屏控制信号。
  24. 根据权利要求16所述的显示驱动电路，其中，每个分屏开关单元包括：第五晶体管，所述第五晶体管的栅极接入所述分屏控制信号，所述第五晶体管的第一极与所述第五晶体管的第二极分别与同一第一扫描线中相邻的两条子扫描线连接。
  25. 一种显示驱动电路的控制方法，用于控制权利要求1-24任一项所述的显示驱动电路；所述控制方法包括：
    获取显示面板在第一方向上的目标分区位置；
    根据所述目标分区位置，确定每帧显示中的级联控制信号，并基于所述级联控制信号控制每帧显示中所述级联控制模块的开关状态。
  26. 根据权利要求25所述的显示驱动电路的控制方法，其中，所述至少一个级联控制模块包括多个级联控制模块；所述显示面板包括至少一个目标分区位置；
    所述显示面板的显示过程中包括多类显示帧；所述多类显示帧中包括第一刷新帧和至少一类第二刷新帧；所述至少一类第二刷新帧的类别与所述至少一个目标分区位置分别对应；
    在所述第一刷新帧中，级联控制信号控制所有级联控制模块均保持导通；
    在所述第二刷新帧中，级联控制信号控制所有级联控制模块的关断时间，或控制预设位置的级联控制模块关断，使所述显示面板基于所述第二刷新帧对应的目标分区位置进行显示。
  27. 一种显示装置，包括：如权利要求1-24任一项所述的显示驱动电路；显示面板；其中，所述显示驱动电路设置于所述显示面板中。
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