WO2024113477A1 - 一种发光元件及其制备方法 - Google Patents

一种发光元件及其制备方法 Download PDF

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Publication number
WO2024113477A1
WO2024113477A1 PCT/CN2023/073196 CN2023073196W WO2024113477A1 WO 2024113477 A1 WO2024113477 A1 WO 2024113477A1 CN 2023073196 W CN2023073196 W CN 2023073196W WO 2024113477 A1 WO2024113477 A1 WO 2024113477A1
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layer
light
electrode
type
emitting element
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PCT/CN2023/073196
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English (en)
French (fr)
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孙雷蒙
徐晓丽
刘芳
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华引芯（武汉）科技有限公司
华引芯(张家港)半导体有限公司
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Publication of WO2024113477A1 publication Critical patent/WO2024113477A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to the field of semiconductor technology, and in particular to a light-emitting element and a preparation method thereof.
  • LED Light Emitting Diode
  • photoelectric performance characteristics such as low energy consumption, long life, good stability, fast response, and stable luminous wavelength. Therefore, it is widely used in lighting, home appliances, display screens, indicator lights and other fields.
  • flip-chip LED chips Compared with the traditional upright structure, flip-chip LED chips have more advantages in heat dissipation and luminous efficiency, so flip-chip LED chips are increasingly widely used.
  • Conventional flip-chip P and N contact materials can form good ohmic contact with GaN.
  • automotive-grade high-power chips have increasingly higher requirements for low voltage.
  • the contact material By adjusting the contact material, the voltage can only be slightly adjusted, and the voltage cannot be significantly reduced.
  • the adjustment of the structure during the voltage reduction process will also cause a loss in brightness, which cannot meet market demand.
  • the main purpose of the present invention is to provide a light-emitting element and a method for preparing the same, aiming to solve the technical problem in the prior art that the voltage cannot be significantly reduced and the adjustment of the structure during the voltage reduction process will cause a loss in brightness.
  • the present invention provides a light-emitting element, comprising a substrate and a light-emitting structure, a current spreading layer, a passivation layer, a reflective layer, a barrier layer, an insulating layer, and a pad sequentially grown on the substrate;
  • the pad includes two N-type pads and one P-type pad, the P-type pad is located between the two N-type pads, the area ratio of the N-type pad is greater than the area ratio of the P-type pad, and a plurality of N holes are evenly arranged on the end surface of each N-type pad to increase the current channel between the P electrode and the N electrode, so that the current between the P electrode and the N electrode is fully expanded, thereby reducing the voltage between the P electrode and the N electrode.
  • the plurality of N holes are arranged in a plurality of rows on the end surface of the N-type pad, with two adjacent N holes arranged in a plurality of rows.
  • the N holes in a row are arranged in a staggered manner so that the N holes are evenly distributed on the end surface of the N-type pad.
  • the area of the N-type pad is more than 10 times that of the P-type pad, so that a plurality of N holes can be excavated on the end surface of the N-type pad to increase the current channel between the P electrode and the N electrode.
  • the openings of the current spreading layer and the openings of the passivation layer are arranged in a staggered manner to improve brightness.
  • the reflective metal used to make the reflective layer includes Ag alloy and 2%-5% Pt component to improve brightness.
  • the present invention also provides a method for preparing a light-emitting element, comprising the following steps:
  • An N-type semiconductor layer, an active layer, and a P-type semiconductor layer are sequentially grown on the substrate to form an epitaxial layer;
  • the step of forming a passivation layer on the current spreading layer includes:
  • a SiO2 film layer is evaporated, and then a TiO2 film layer is evaporated on the SiO2 film layer;
  • the SiO 2 /TiO 2 stack is etched by ICP dry method until the bottom SiO 2 film layer is etched.
  • the bottommost SiO 2 film layer in the SiO 2 /TiO 2 stack is etched by BOE wet etching.
  • the step of manufacturing a reflective layer on the passivation layer includes:
  • a layer of reflective metal is plated on the passivation layer by a magnetron sputtering method or a vacuum evaporation coating process;
  • a Ti/Pt or TiW film layer is continuously deposited on the upper layer to cover the reflective metal.
  • the step of forming an insulating layer on the barrier layer includes:
  • the passivation film is deposited at 250°C-300°C using plasma enhanced vapor deposition
  • the passivation film layer is opened by yellow light photoresist exposure, development and etching.
  • depositing the N-type pad and the P-type pad comprises the following steps:
  • the pad is patterned.
  • the light-emitting element includes a substrate and a light-emitting structure, a current expansion layer, a passivation layer, a reflective layer, a barrier layer, an insulating layer, and a pad sequentially grown on the substrate; wherein the pad includes two N-type pads and one P-type pad, the P-type pad is located between the two N-type pads, the area ratio of the N-type pad is greater than the area ratio of the P-type pad, and a plurality of N holes are evenly arranged on the end surface of each N-type pad to increase the current channel between the P electrode and the N electrode, so that the current between the P electrode and the N electrode is fully expanded, thereby reducing the voltage between the P electrode and the N electrode.
  • the conventional symmetrical electrode structure design is changed, so that the current can be expanded more fully, thereby reducing the voltage between the PN electrodes.
  • the area of the N-type pad is much larger than the area of the P-type pad, which increases the area ratio of the N-type pad.
  • the area of the N-type pad occupies a larger proportion, the distribution of the N holes is wider, and the contact area of the N electrode is larger, so there will be more current channels between the P electrode and the N electrode, and the current expansion between the P electrode and the N electrode will be more sufficient, thereby reducing the voltage between the P electrode and the N electrode.
  • FIG1 is a schematic structural diagram of an embodiment of a light emitting element provided by the present invention.
  • FIG2 is a top view of the light emitting element in FIG1 ;
  • FIG3 is a schematic structural diagram of an N-type conductive region of the light emitting element in FIG1 ;
  • FIG4 is a schematic diagram of the structure of the current spreading layer of the light emitting element in FIG1 ;
  • FIG5 is a schematic diagram of the structure of the passivation layer of the light emitting element in FIG1 ;
  • FIG6 is a schematic diagram of the structure of the reflective layer of the light emitting element in FIG1 ;
  • FIG7 is a schematic diagram of the structure of the light emitting element barrier layer in FIG1 ;
  • FIG8 is a schematic structural diagram of an insulating layer of a light emitting element in FIG1 ;
  • FIG9 is a schematic structural diagram of the light emitting element pad in FIG1 ;
  • FIG. 10 is a schematic flow chart of an embodiment of a method for preparing a light-emitting element provided by the present invention.
  • Label name Label name 100 Light-emitting components 105 Barrier layer 101 Substrate 106 Insulation 102 Current spreading layer 107 Pads 103 Passivation layer 1071 N-type pad 104 Reflective layer 1072 P-type pad The The 1073 N hole
  • the directional indication is only used to explain the relative position relationship, movement status, etc. between the components in a certain specific posture. If the specific posture changes, the directional indication will also change accordingly.
  • the terms “installed”, “connected”, and “connected” should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components.
  • installed should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components.
  • the present invention provides a light-emitting element and a preparation method thereof, aiming to solve the above problems.
  • Fig. 1 is a schematic diagram of the structure of an embodiment of a light-emitting element 100 provided by the present invention.
  • the light-emitting element 100 includes a substrate 101, a light-emitting structure, a current spreading layer 102, a passivation layer 103, a reflective layer 104, a barrier layer 105, an insulating layer 106, and a pad 107.
  • the light-emitting structure, the current spreading layer 102, the passivation layer 103, the reflective layer 104, the barrier layer 105, the insulating layer 106, and the pad are sequentially grown on the substrate 101.
  • the substrate material of the semiconductor device is also called the substrate material, and the epitaxial layer is grown on the substrate material.
  • the substrate material There are many kinds of LED substrate materials.
  • a sapphire substrate is used, which has the advantages of good chemical stability, no absorption of visible light, and good light transmittance.
  • the light-emitting structure includes an N-type semiconductor layer, an active layer, and a P-type semiconductor layer formed sequentially on a sapphire substrate.
  • a buffer layer and a light-emitting structure are grown on the sapphire substrate by metal organic chemical vapor deposition technology.
  • the light-emitting structure includes an N-type semiconductor layer, an active layer, and a P-type semiconductor layer formed sequentially, which constitute the epitaxial layer of the chip.
  • the current spreading layer 102 is formed by depositing an ITO layer on the surface of the P-type semiconductor layer by a magnetron sputtering process, and is used to form a P-type ohmic contact after annealing.
  • the passivation layer 103 is a SiO 2 /TiO 2 stacked layer evaporated on the current spreading layer using a DBR evaporation device.
  • the reflective layer 104 is formed by depositing a reflective metal on the passivation layer by a magnetron sputtering method or a vacuum evaporation coating process.
  • the barrier layer 105 is a film layer plated on the reflective layer 104 by a vacuum evaporation coating method, and the barrier layer 105 is mainly composed of Au, and the remaining components include one or more of Cr/Pt/Ti/Ni/Sn elements.
  • the insulating layer 106 is a film layer deposited on the barrier layer using a plasma enhanced vapor deposition method.
  • the pad 107 includes two N-type pads 1071 and one P-type pad 1072, the two N-type pads 1071 are arranged on both sides, and the P-type pad 1072 is arranged in the middle.
  • the contact area of the N pad 1071 is increased, and the distribution of the N holes is wider, so there will be more current channels between the P electrode and the N electrode, and the current expansion between the P electrode and the N electrode will be more sufficient, thereby reducing the voltage between the P electrode and the N electrode.
  • the area ratio of the N-type pad 1071 is set to be more than 10 times that of the P-type pad 1072.
  • the area of the N-type pad 1071 is much larger than that of the P-type pad 1072, which increases the area ratio of the N-type pad 1071 and slightly reduces the area ratio of the P-side light-emitting area.
  • the larger the area ratio of the N-type pad 1071 the wider the distribution of the N holes 1073, and the larger the contact area of the N electrode. Larger, further reducing the voltage between the P electrode and the N electrode to meet more application scenarios.
  • the plurality of N holes 1073 are arranged in a plurality of rows on the end surface of the N-type pad 1071, and the N holes 1073 in two adjacent rows are staggered so that the N holes 1073 are evenly distributed on the end surface of the N-type pad 1071.
  • a plurality of N holes 1073 are provided on the end surface of the N-type pad 1071, and three adjacent N holes 1073 are arranged in an equilateral triangle. The N holes 1073 are evenly distributed, which can better optimize current conduction and reduce voltage compared with conventional non-uniform arrangement.
  • the openings of the current spreading layer 102 and the openings of the passivation layer 103 are arranged in a staggered manner.
  • the direct contact between the SiO2 / TiO2 stack and the P semiconductor layer can achieve the best ODR reflection effect, so the design of ITO patterned openings can not only ensure high-quality current spreading, but also increase the contact area between the passivation layer 103 and the P semiconductor layer.
  • the thickness of the SiO 2 /TiO 2 stack in the passivation layer 103 is The passivation layer 103 is a SiO 2 /TiO 2 stacked layer deposited on the current spreading layer using a DBR evaporation device.
  • the specific evaporation process of the SiO 2 /TiO 2 stacked layer is: firstly, a layer of SiO 2 film is evaporated on the current spreading layer, and then a layer of TiO 2 film is evaporated on the SiO 2 film.
  • the above evaporation process is repeated until a layer with a thickness of The SiO 2 /TiO 2 stacked layer grows to form a DBR structure, and at the same time forms an ODR structure with GaN and Ag, which further improves the reflectivity compared with the traditional ODR structure.
  • the reflective metal used to make the reflective layer 104 includes an Ag alloy and a 2%-5% Pt component.
  • the reflective metal of the reflective layer may also select Al/Rh as the reflective layer metal, but in this embodiment, it is preferred to select an Ag alloy component doped with 2%-5% Pt.
  • the advantage of this design is that it can reduce the migration of Ag; at the same time, it shortens the distance between the reflective layer and the edge of the Mesa, increases the area of the reflective layer, and improves the brightness.
  • the Ag reflective metal through the N hole 1073, the height difference of the film layer caused by the N hole 1073 is reduced, the eutectic void rate of the chip package is reduced, and the product reliability is improved.
  • the present invention also provides a method for preparing a light-emitting element.
  • FIG. 10 it is a flow chart of an embodiment of a method for preparing a light-emitting element of the present invention, and the method for preparing a light-emitting element comprises the following steps:
  • Step S10 growing an N-type semiconductor layer, an active layer, and a P-type semiconductor layer in sequence on the substrate 101 to form an epitaxial layer.
  • Step S20 etching isolation trenches between adjacent core particles so that each core particle is completely isolated on the epitaxial layer, thereby forming an independent unit.
  • Step S30 Opening a groove extending to the N-type semiconductor layer on the P-type semiconductor layer by inductively coupled plasma etching to form an N-type conductive region.
  • Step S40 forming a current spreading layer 102 on the P-type semiconductor layer.
  • Step S50 forming a passivation layer 103 on the current spreading layer 102 .
  • Step S60 forming a reflective layer 104 on the passivation layer 103 .
  • Step S70 forming a blocking layer 105 on the reflective layer 104 .
  • Step S80 forming an insulating layer 106 on the barrier layer 105 .
  • Step S90 depositing N-type pad 1071 and P-type pad 1072 .
  • a growth substrate 101 is provided, on which a buffer layer (not shown), an N-type semiconductor layer, an active layer, and a P-type semiconductor layer are sequentially grown.
  • the N-type semiconductor layer, the active layer, and the P-type semiconductor layer together constitute an epitaxial layer, i.e., a (light-emitting structure).
  • the growth substrate 101 can be a sapphire substrate, a GaN substrate, a silicon substrate, or a silicon carbide substrate.
  • the growth substrate 101 is a sapphire substrate, and the materials of the buffer layer, the N-type semiconductor layer, and the P-type semiconductor layer are all GaN materials.
  • the buffer layer, the N-type semiconductor layer 21, the active layer 22, and the P-type semiconductor layer 23 can all be formed by growth methods such as MOCVD (Metal Organic Chemical Vapor Deposition) and/or MBE (Molecular Beam Epitaxy).
  • step S20 the epitaxial layer structure 2 is deeply etched by an inductively coupled plasma etching process to form an isolation trench between adjacent light-emitting elements, so that each light-emitting element is completely isolated on the growth substrate 101 to form an independent light-emitting element unit.
  • the specific etching depth is determined according to the thickness of the epitaxial layer, and is generally between 6-7 ⁇ m. It should be noted that in this embodiment, a structure including a plurality of light-emitting elements is produced by step S10, and then deep etching is performed to completely isolate each light-emitting element on the growth substrate 101 to form an independent light-emitting element unit. In other embodiments of the present invention, a single light-emitting element structure can also be formed directly on the growth substrate 101 by step S10.
  • step S30 an inductively coupled plasma etching process is used to form a groove structure, and the etching depth is determined by the growth thickness of each semiconductor layer, generally 1-1.5 ⁇ m deep.
  • N-type conductive openings are arranged around the light-emitting element in step S30 to form an N-type conductive area.
  • an ITO layer is deposited on the surface of the P-type semiconductor layer 23 by a magnetron sputtering process, and the deposited thickness is
  • the current spreading layer 4 is deposited on the surface of the P-type semiconductor layer 23, and forms a P-type ohmic contact after annealing.
  • ITO is mainly composed of indium tin oxide, which is a semiconductor transparent conductive film. It can have the characteristics of low resistivity and high light transmittance at the same time, meeting the requirements of good conductivity and light transmittance; the function of ITO is to make the electrode and the epitaxial layer form a good ohmic contact, so that the current diffuses on the electrode surface and better passes into the electrode to reduce the voltage.
  • the Mg-H bond in the P-type gallium nitride layer is opened by annealing in an oxygen atmosphere, which plays a role in activating Mg and better forming an ohmic contact.
  • a passivation layer 103 is deposited on the current spreading layer 102 by using a DBR evaporation device.
  • the material of the passivation layer 103 is SiO 2 and TiO 2 , specifically a stacked deposition coating of SiO 2 /TiO 2.
  • the deposition temperature is 2000 °C and the deposition thickness is 2000 °C.
  • the reflective layer 104 is formed by depositing a reflective metal on the passivation layer by a magnetron sputtering method or a vacuum evaporation coating process.
  • the barrier layer is a film layer plated on the reflective layer using a vacuum evaporation coating method, and the barrier layer 105 is mainly composed of Au, and the remaining components include one or more of the Cr/Pt/Ti/Ni/Sn elements.
  • the insulating layer 106 is a film layer deposited on the barrier layer 105 using a plasma enhanced vapor deposition method.
  • an N-type pad 1071 and a P-type pad 1072 are deposited.
  • step S50 specifically includes the following steps:
  • Step S501 first evaporate a layer of SiO2 film, and then evaporate a layer of TiO2 film on the SiO2 film;
  • Step S502 Repeat the above evaporation process until a layer with a thickness of SiO 2 /TiO 2 stack;
  • Step S503 Use ICP dry etching to etch the SiO 2 /TiO 2 stack until the bottom TiO 2 film layer is etched.
  • Step S504 using BOE wet etching to etch the bottommost SiO 2 film layer in the SiO 2 /TiO 2 stack.
  • the yellow light uniform coating exposure and development process is used to open the pattern to be etched.
  • ICP dry etching and BOE wet etching are used to complete the pattern transfer of the passivation layer.
  • the reason why two methods are selected for etching pattern is that if only dry etching is used, the bottom of the passivation layer 103 is etched, and the plasma will damage the P GaN surface after SiO 2 is completely etched.
  • the SiO2 and TiO2 wet BOE etching rates are different, and there will be different corrosion rates of the two materials in the DBR, which will cause the film cross-section to be uneven, resulting in the presence of faults in the thickness of the metal plating, which will affect the current conduction of the chip and the reliability of the quality performance detection, resulting in leakage anomalies.
  • the reflectivity is improved by increasing the direct contact area between the passivation layer 103 and P GaN in the ODR structure.
  • step S60 specifically includes the following steps:
  • Step S601 a layer of reflective metal is plated on the passivation layer by using a magnetron sputtering method or a vacuum evaporation coating process.
  • Step S602 while coating the reflective metal, a Ti/Pt or TiW film layer is continuously deposited on the upper layer to cover the reflective metal.
  • an adhesion layer is first deposited, usually Ti or Ni is used, but since metal absorbs light, TCO material is preferred.
  • Ag/Al/Rh can be selected as the reflective layer metal, and the coating can be deposited by magnetron sputtering or vacuum evaporation coating process, with a deposition thickness of The reflective metal is plated and a Ti/Pt or TiW film is deposited on the upper layer to cover the reflective metal and inhibit the migration of the reflective metal.
  • an Ag alloy composition is selected and 2%-5% Pt composition is doped to reduce the migration of Ag; at the same time, the distance between the reflective layer and the edge of the Mesa is shortened, the area of the reflective layer is increased, and the brightness is improved.
  • step S80 specifically includes the following steps:
  • Step S801 depositing a layer with a thickness of Al metal reflective layer.
  • Step S802 depositing a passivation film layer on the Al metal reflective layer.
  • Step S803 opening holes in the passivation film layer by yellow light photoresist exposure, development and etching.
  • a plasma enhanced vapor deposition process is used to deposit a passivation film layer on the entire wafer surface.
  • the material of the passivation film layer is selected from any one or more stacks of silicon dioxide, silicon nitride, and aluminum oxide, and the silicon dioxide/silicon nitride, silicon dioxide/silicon nitride/aluminum oxide deposition coating is deposited at a deposition temperature of 250°C to 300°C and a deposition thickness of
  • the passivation film layer is silicon dioxide, and an independent light-emitting unit structure is formed by deep etching first, and then a silicon dioxide layer is formed on the entire surface of the wafer.
  • the insulating property of silicon dioxide is used to prevent leakage caused by direct exposure of the epitaxial layer material after product cutting.
  • the passivation film layer is opened by yellow light uniform coating exposure, development and etching, except for the passivation film opening area. The domain forms full coverage of the Al emission layer, further improving the brightness.
  • step S90 specifically includes the following steps:
  • Step S901 Patterning the pad by photolithography, exposure, and development
  • Step S902 using the Asher process to remove the negative resist base film
  • Step S903 After the source is washed with water, Cr/Pt/Ni/Pt/Ni/AuSn is deposited using an E-Beam device;
  • Step S904 using an alkaline stripping solution to remove the photoresist.
  • the thickness of AuSn is 3um-4um.

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Abstract

本发明提供了一种发光元件，涉及半导体技术领域，改变了常规的对称式电极结构设计，采用非对称式的电极结构以及大量的N孔，用以增加P电极和N电极之间的电流通道，降低P电极和N电极之间电压。发光元件的焊盘包括两个N型焊盘和一个P型焊盘，所述P型焊盘位于两个所述N型焊盘之间，所述N型焊盘的面积占比大于所述P型焊盘的面积占比，并且每一所述N型焊盘的端面上均匀的设有多个N孔。N型焊盘的面积占比更大，N孔的分布就更广，那么P电极和N电极之间的电流通道就会更多，P电极和N电极之间的电流扩展就会更充分，进而就能降低P电极和N电极之间电压。此外，本发明还提供一种制备发光元件的方法。

Description

一种发光元件及其制备方法 技术领域
本发明涉及半导体技术领域，尤其涉及一种发光元件及其制备方法。
背景技术
发光二极管(Light Emitting Diode)，简称LED，是一种半导体发光器件，具有能耗低、寿命长、稳定性好、响应快、发光波长稳定等光电性能特点，因而在照明、家电、显示屏、指示灯等领域有广泛的应用。
相对于传统的正装结构，倒装LED芯片在散热、发光效率等方面更具有优势，因此倒装LED芯片越来越被广泛的使用。常规的倒装芯片P、N接触材料与GaN可以形成良好的欧姆接触，但是，在实际应用中，车规级的大功率芯片对低电压要求越来越高，通过调整接触材料只能对电压进行微调整，无法大幅度降低电压，同时在降压的过程中结构的调整还会对亮度造成损失，无法满足市场的需求。
发明内容
本发明的主要目的是提供一种发光元件及其制备方法，旨在解决现有技术中，无法大幅度降低电压，同时在降压的过程中结构的调整会对亮度造成损失的技术问题。
为实现上述目的，本发明提供一种发光元件，包括衬底以及依次生长于所述衬底上的发光结构、电流扩展层、钝化层、反射层、阻挡层、绝缘层、焊盘；
其中，所述焊盘包括两个N型焊盘和一个P型焊盘，所述P型焊盘位于两个所述N型焊盘之间，所述N型焊盘的面积占比大于所述P型焊盘的面积占比，并且每一所述N型焊盘的端面上均匀的设有多个N孔，用以增加P电极和N电极之间的电流通道，使得P电极和N电极之间的电流扩展充分，进而降低P电极和N电极之间电压。
可选地，所述多个N孔在所述N型焊盘的端面上排成多列，相邻两 列的所述N孔之间呈交错设置，以使得所述N孔在所述N型焊盘的端面上均匀分布。
可选地，所述N型焊盘的面积占比是所述P型焊盘的10倍以上，以使得所述N型焊盘的端面上可开挖多个所述N孔，用以增加P电极和N电极之间的电流通道。
可选地，所述电流扩展层的开孔与所述钝化层的开孔呈交错设置，用以提高亮度。
可选地，用于制作所述反射层的反射金属的成分包括Ag合金，以及2％-5％的Pt成分，用以提高亮度。
此外，为实现上述目的，本发明还提出一种制备发光元件的方法，包括如下步骤：
在衬底上依次生长出N型半导体层、有源层、P型半导体层以形成外延层；
在相邻的芯粒间刻蚀出隔离沟道，以使各芯粒在所述外延层上完全隔断，进而形成独立单元；
在所述P型半导体层上通过电感耦合等离子体刻蚀开设延伸到所述N型半导体层的凹槽，以形成N型导电区域；
在所述P型半导体层上制作电流扩展层；
在所述电流扩展层上制作钝化层；
在所述钝化层上制作反射层；
在所述反射层上制作阻挡层；
在所述阻挡层上制作绝缘层；
沉积N型焊盘和P型焊盘。
可选地，在所述电流扩展层上制作钝化层的步骤包括：
先蒸镀一层SiO2膜层，再在所述SiO2膜层上蒸镀一层TiO2膜层；
重复上述蒸镀过程，直至形成厚度为的SiO2/TiO2叠层；
采用ICP干法刻蚀所述SiO2/TiO2叠层，直至刻蚀到最底层的所述SiO2膜层
采用BOE湿法刻蚀所述SiO2/TiO2叠层中最底层的所述SiO2膜层。
可选地，在所述钝化层上制作反射层的步骤包括：
采用磁控溅射法或者真空蒸发镀膜工艺在所述钝化层镀一层反射金属；
在镀膜所述反射金属的同时，上层继续沉积Ti/Pt或者TiW膜层，覆盖在所述反射金属上方。
可选地，在所述阻挡层上制作绝缘层的步骤包括：
使用等离子体增强型气相沉积法在250℃-300℃下沉积钝化膜层；
再在所述钝化膜层上沉积一层厚度为的Al金属反射层；
再在所述Al金属反射层的上方再沉积一层钝化膜层；
再通过黄光匀胶曝光显影刻蚀，将所述钝化膜层开孔。
可选地，沉积N型焊盘和P型焊盘包括如下步骤：
通过黄光工艺匀胶、曝光、显影，将焊盘图形化制作出来；
使用Asher工艺去除负胶底膜；
在片源甩水清洗后，使用E-Beam设备沉积Cr/Pt/Ni/Pt/Ni/AuSn；
使用碱性去胶液对去除光刻胶。
在本发明提供的技术方案中，发光元件包括衬底以及依次生长于所述衬底上的发光结构、电流扩展层、钝化层、反射层、阻挡层、绝缘层、焊盘；其中，所述焊盘包括两个N型焊盘和一个P型焊盘，所述P型焊盘位于两个所述N型焊盘之间，所述N型焊盘的面积占比大于所述P型焊盘的面积占比，并且每一所述N型焊盘的端面上均匀的设有多个N孔，用以增加P电极和N电极之间的电流通道，使得P电极和N电极之间的电流扩展充分，进而降低P电极和N电极之间电压。在本申请中，通过将P型焊盘设于两个N型焊盘之间，改变了常规的对称式电极结构设计，可以使电流扩展的更充分，进而降低了PN电极之间的电压。此外，N型焊盘的面积远大于P型焊盘的面积，提高了N型焊盘的面积占比。N型焊盘的面积占比更大，N孔的分布就更广，N电极的接触面积就更大，那么P电极和N电极之间的电流通道就会更多，P电极和N电极之间的电流扩展就会更充分，进而就能降低P电极和N电极之间电压。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图示出的结构获得其他的附图。
图1为本发明提供的发光元件的一实施例的结构示意图；
图2为图1中发光元件的俯视图；
图3为图1中发光元件N型导电区域的结构示意图；
图4为图1中发光元件电流扩展层的结构示意图；
图5为图1中发光元件钝化层的结构示意图；
图6为图1中发光元件反射层的结构示意图；
图7为图1中发光元件阻挡层的结构示意图；
图8为图1中发光元件绝缘层的结构示意图；
图9为图1中发光元件焊盘的结构示意图；
图10为本发明提供的制备发光元件的方法的一实施例的流程示意图
附图标号说明：
标号 名称 标号 名称
100 发光元件 105 阻挡层
101 衬底 106 绝缘层
102 电流扩展层 107 焊盘
103 钝化层 1071 N型焊盘
104 反射层 1072 P型焊盘
    1073 N孔
本发明目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本发明进一步详细说明。对本发明中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而 不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
以下，将参照附图来描述本发明的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本发明的范围。在下面的详细描述中，为便于解释，阐述了许多具体的细节以提供对本发明实施例的全面理解。然而，明显地，一个或多个实施例在没有这些具体细节的情况下也可以被实施。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本发明的概念。
在此使用的术语仅仅是为了描述具体实施例，而并非意在限制本发明。在此使用的术语“包括”、“包含”等表明了所述特征、步骤、操作和/或部件的存在，但是并不排除存在或添加一个或多个其他特征、步骤、操作或部件。
在此使用的所有术语(包括技术和科学术语)具有本领域技术人员通常所理解的含义，除非另外定义。应注意，这里使用的术语应解释为具有与本说明书的上下文相一致的含义，而不应以理想化或过于刻板的方式来解释。
在使用类似于“A、B和C等中至少一个”这样的表述的情况下，一般来说应该按照本领域技术人员通常理解该表述的含义来予以解释(例如，“具有A、B和C中至少一个的***”应包括但不限于单独具有A、单独具有B、单独具有C、具有A和B、具有A和C、具有B和C、和/或具有A、B、C的***等)。在使用类似于“A、B或C等中至少一个”这样的表述的情况下，一般来说应该按照本领域技术人员通常理解该表述的含义来予以解释(例如，“具有A、B或C中至少一个的***”应包括但不限于单独具有A、单独具有B、单独具有C、具有A和B、具有A和C、具有B和C、和/或具有A、B、C的***等)。
需要说明，若本发明实施例中有涉及方向性指示，则该方向性指示仅用于解释在某一特定姿态下各部件之间的相对位置关系、运动情况等，如果该特定姿态发生改变时，则该方向性指示也相应地随之改变。
另外，若本发明实施例中有涉及“第一”、“第二”等的描述，则该 “第一”、“第二”等的描述仅用于描述目的，而不能理解为指示或暗示其相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。另外，全文中出现的“和/或”的含义，包括三个并列的方案，以“A和/或B”为例，包括A方案、或B方案、或A和B同时满足的方案。还有就是，各个实施例之间的技术方案可以相互结合，但是必须是以本领域普通技术人员能够实现为基础，当技术方案的结合出现相互矛盾或无法实现时应当认为这种技术方案的结合不存在，也不在本发明要求的保护范围之内。
在本发明的描述中，需要说明的是，术语“上”、“下”、“顶”、“底”“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
在本发明的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本发明中的具体含义。
此外，在本发明的描述中，除非另有说明，“多个”、“多根”、“多组”的含义是两个或两个以上。
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
在实际应用中，车规级的大功率芯片对低电压要求越来越高，通过调整接触材料只能对电压进行微调整，无法大幅度降低电压，同时在降压的过程中结构条的调整会对亮度造成损失。鉴于此，本发明提供一种发光元件及其制备方法，旨在解决上述问题。
参见图1，图1为本发明提供的发光元件100一实施例的结构示意图。发光元件100包括衬底101、发光结构、电流扩展层102、钝化层103、反射层104、阻挡层105、绝缘层106、焊盘107。发光结构、电流扩展层102、钝化层103、反射层104、阻挡层105、绝缘层106、焊盘依次生长于衬底101上。
半导体器件的衬底材料也称为基片材料，外延层都是在衬底材料上生长获得的。LED衬底材料有多种，在本实施例中采用的是蓝宝石衬底，其优点是化学稳定性好，不吸收可见光，透光性好。
发光结构包括依次形成于蓝宝石衬底上的N型半导体层、有源层、P型半导体层。在蓝宝石衬底上通过金属有机化合物化学气相沉积技术(Metal Organic Chemical Vapor Deposition)生长出缓冲层和发光结构。发光结构包括依次形成的N型半导体层、有源层、P型半导体层，构成芯片的外延层。电流扩展层102是通过磁控溅射工艺，在P型半导体层的表面沉积ITO层而成的，并在退火后用以形成P型欧姆接触。钝化层103是使用DBR蒸镀设备在电流扩展层上蒸镀的SiO2/TiO2叠层。反射层104是通过磁控溅射法或者真空蒸发镀膜工艺在钝化层上沉积反射金属而生成的。阻挡层105是使用真空蒸发镀膜的方法在反射层104上镀的膜层，阻挡层105成分以Au为主，其余成分包含Cr/Pt/Ti/Ni/Sn元素中的一种或者几种。绝缘层106是使用等离子体增强型气相沉积法在阻挡层上沉积的膜层。
需要说明的是，在本实施例中，改变了当前常规的对称式电极结构设计，取而代之的是一种全新的非对称式电极结构设计。具体地，参见图2，在本实施例中，焊盘107包括两个N型焊盘1071和一个P型焊盘1072，两个N型焊盘1071设置在两侧，P型焊盘1072设置在中间。对比现有结构，增加了N焊盘1071接触面积，N孔的分布就更广，那么P电极和N电极之间的电流通道就会更多，P电极和N电极之间的电流扩展就会更充分，进而就能降低P电极和N电极之间电压。
此外，在本实施例中，将N型焊盘1071的面积占比设置成P型焊盘1072的10倍以上，N型焊盘1071的面积远大于P型焊盘1072的面积，提高了N型焊盘1071的面积占比，P面发光区占比小幅度降低。N型焊盘1071的面积占比更大，N孔1073的分布就更广，N电极的接触面积就 更大，进一步的降低P电极和N电极之间电压，满足更多应用场景。
进一步地，在本实施例中，所述多个N孔1073在所述N型焊盘1071的端面上排成多列，相邻两列的所述N孔1073之间呈交错设置，以使得所述N孔1073在所述N型焊盘1071的端面上均匀分布。N型焊盘1071的端面上设有多个N孔1073，并且相邻的三个所述N孔1073之间呈等边三角形排布。N孔1073呈现均匀分布设计，较常规非均匀性排布能够更好的优化电流传导，降低电压。
进一步地，参见图1，在本实施例中，所述电流扩展层102的开孔与所述钝化层103的开孔呈交错设置。SiO2/TiO2叠层与P半导体层直接接触可以使ODR反射达到最佳效果，因此设计ITO图形化开孔既保证优质的电流扩展，又可以增加钝化层103与P半导体层的接触面积。
进一步地，参见图5，在本实施例中，所述钝化层103中的SiO2/TiO2叠层厚度为钝化层103是使用DBR蒸镀设备在电流扩展层上蒸镀的SiO2/TiO2叠层，SiO2/TiO2叠层的具体蒸镀过程为：先电流扩展层上蒸镀一层SiO2膜层，再在所述SiO2膜层上蒸镀一层TiO2膜层，一直重复上述蒸镀过程，直至形成厚度为的SiO2/TiO2叠层为止。SiO2/TiO2叠层生长构成DBR结构，同时与GaN和Ag形成ODR结构，较传统ODR结构进一步提高反射率。
进一步地，参加图6，在本实施例中，用于制作所述反射层104的反射金属的成分包括Ag合金以及2％-5％的Pt成分。在其它实施例中，反射层的反射金属也可以选择Al/Rh等作为反射层金属，但是在本实施例中，优选选择Ag合金成分，掺杂2％-5％的Pt成分，这样设计的优点是能够减小Ag的迁移；同时缩短反射层距离Mesa边缘的距离，增加反射层面积，提高亮度。此外，通过N孔1073填充Ag反射金属，减少N孔1073造成的膜层高低差，降低芯片封装共晶空洞率，提高产品可靠性。
此外，为了实现上述发明目的，本发明还提供了一种制备发光元件的方法。参见图10，为本发明制备发光元件的方法一实施例的流程示意图，制备发光元件的方法包括如下步骤：
步骤S10：在衬底101上依次生长出N型半导体层、有源层、P型半导体层以形成外延层。
步骤S20：在相邻的芯粒间刻蚀出隔离沟道，以使各芯粒在所述外延层上完全隔断，进而形成独立单元。
步骤S30：在所述P型半导体层上通过电感耦合等离子体刻蚀开设延伸到所述N型半导体层的凹槽，以形成N型导电区域。
步骤S40：在所述P型半导体层上制作电流扩展层102。
步骤S50：在所述电流扩展层102上制作钝化层103。
步骤S60：在所述钝化层103上制作反射层104。
步骤S70：在所述反射层104上制作阻挡层105。
步骤S80：在所述阻挡层105上制作绝缘层106。
步骤S90：沉积N型焊盘1071和P型焊盘1072。
在本实施例中，提供一生长衬底101，在该生长衬底101上依次生长缓冲层(图中未示出)、N型半导体层、有源层、P型半导体层。N型半导体层、有源层、P型半导体层共同构成外延层，即(发光结构)。其中，生长衬底101可以为蓝宝石衬底、GaN衬底、硅衬底或碳化硅衬底等。在本实施例中，生长衬底101为蓝宝石衬底，缓冲层，N型半导体层和P型半导体层的材料均为GaN材料。缓冲层、N型半导体层21、有源层22和P型半导体层23均可以采用MOCVD(金属有机气相沉积，Metal Organic Chemical Vapor Deposition)和/或MBE(分子束外延，Molecular Beam Epitaxy)等生长方法形成。
在步骤S20中，采用电感耦合等离子体刻蚀工艺深度刻蚀外延层结构2，以在相邻发光元件间制作出隔离沟道，使得各个发光元件在生长衬底101上完全隔断，形成独立发光元件单元。具体刻蚀深度根据外延层厚度决定，一般在6-7μm之间。需要说明的是，在本实施例中，是通过步骤S10制作包含多个发光元件的结构，然后进行深刻蚀，使得各个发光元件在生长衬底101上完全隔断，形成独立发光元件单元。在本发明其他实施例中，也可以通过步骤S10直接在生长衬底101上形成单个发光元件结构。
结合图3所示，在步骤S30中，采用电感耦合等离子体刻蚀工艺刻蚀形成凹槽结构，刻蚀深度依据各半导体层生长厚度决定，一般在1-1.5μm深。本实施例通过步骤S30在发光元件四周分别排布N型导电开孔，以形成N型导电区域。
结合图4所示，在步骤S40中，采用磁控溅射工艺在所述P型半导体层23的表面沉积ITO层，沉积的厚度为电流扩展层4沉积在所述P型半导体层23的表面，退火后形成P型欧姆接触。ITO主要成分为氧化铟锡，是半导体透明导电膜，可同时具有低电阻率及高光穿透率的特性，符合了导电性及透光性良好的要求；ITO作用是使电极与外延层形成很好的欧姆接触，使电流在电极表面扩散，更好地通到电极里面，降低电压。同时通过退火在氧气氛围下将P型氮化镓层里面的Mg-H键打开，起到了活化Mg的作用，更好地形成欧姆接触。
结合图5所示，在步骤S50中，采用DBR蒸镀设备，在电流扩展层102上蒸镀一层钝化层103，钝化层103的材料为SiO2、TiO2，具体为SiO2/TiO2的叠层沉积镀膜，沉积温度为，沉积厚度
结合图6和图7所示，在步骤S60中，反射层104是通过磁控溅射法或者真空蒸发镀膜工艺在钝化层上沉积反射金属而生成的。在步骤S70中，阻挡层是使用真空蒸发镀膜的方法在反射层上镀的膜层，阻挡层105成分以Au为主，其余成分包含Cr/Pt/Ti/Ni/Sn元素中的一种或者几种。在步骤S80中，绝缘层106是使用等离子体增强型气相沉积法在阻挡层105上沉积的膜层。在步骤S90中，沉积N型焊盘1071和P型焊盘1072。
进一步地，在本实施例中，步骤S50具体包括如下步骤：
步骤S501：先蒸镀一层SiO2膜层，再在所述SiO2膜层上蒸镀一层TiO2膜层；
步骤S502：重复上述蒸镀过程，直至形成厚度为的SiO2/TiO2叠层；
步骤S503：采用ICP干法刻蚀所述SiO2/TiO2叠层，直至刻蚀到最底层的所述TiO2膜层
步骤S504：采用BOE湿法刻蚀所述SiO2/TiO2叠层中最底层的所述SiO2膜层。
在本实施例中，采用黄光匀胶曝光显影工艺开待刻蚀图形，针对两类膜层，分别使用ICP干法刻蚀和BOE湿法刻蚀完成钝化层的图形转移。刻蚀图形方法之所以选择两种方法，是由于如果只用干法刻蚀的情况下，刻蚀到钝化层103底部，SiO2刻蚀完全后等离子会对P GaN表面造成损 伤，造成芯片表面欧姆接触不良，电压升高；如果只是用湿法腐蚀，那SiO2和TiO2湿法BOE腐蚀速率不同，会存在DBR两种物质腐蚀速率不同，进而造成膜层截面参差不同，导致厚度金属镀膜存在断层，从而影响芯片的电流传导及品质的可靠性能检测，出现漏电异常。此外，还通过增加ODR结构中钝化层103与P GaN直接接触面积，提高反射率。
进一步地，在本实施例中，步骤S60具体包括如下步骤：
步骤S601：采用磁控溅射法或者真空蒸发镀膜工艺在所述钝化层镀一层反射金属。
步骤S602：在镀膜所述反射金属的同时，上层继续沉积Ti/Pt或者TiW膜层，覆盖在所述反射金属上方。
在本实施例中，先沉积一层粘附层，通常会使用Ti或者Ni，但是由于金属会吸光，所以优选TCO材料。此外，可以选择Ag/Al/Rh等作为反射层金属，镀膜可以通过磁控溅射法或者真空蒸发镀膜工艺，沉积厚度为的反射金属，镀膜反射金属的同时，上层继续沉积Ti/Pt或者TiW膜层，覆盖在反射金属上方，抑制反射金属的迁移，优选选择Ag合金成分，掺杂2％-5％的Pt成分，减小Ag的迁移；同时缩短反射层距离Mesa边缘的距离，增加反射层面积，提高亮度。
进一步地，在本实施例中，步骤S80具体包括如下步骤：
步骤S801：在所述阻挡层105上沉积一层厚度为的Al金属反射层。
步骤S802：在所述Al金属反射层上方沉积钝化膜层。
步骤S803：通过黄光匀胶曝光显影刻蚀，将所述钝化膜层开孔。
结合图8所示，在步骤S80中，采用等离子体增强型气相沉积工艺在整个晶圆表面沉积钝化膜层。在该步骤中，钝化膜层的材料选自二氧化硅、氮化硅、氧化铝中的任意一种或者多种叠层，二氧化硅/氮化硅、二氧化硅/氮化硅/氧化铝沉积镀膜，沉积温度为250℃～300℃，沉积厚度例如本实施例中钝化膜层为二氧化硅，通过先深度刻蚀形成独立发光单元结构，然后在晶圆整面制作二氧化硅层，利用二氧化硅的绝缘性，防止产品切割后外延层的材料直接暴露出来导致的漏电情况发生。此外，通过黄光匀胶曝光显影刻蚀，将钝化膜层开孔，除钝化膜层开孔区 域形成Al发射层的全覆盖，进一步提升亮度。
进一步地，参见图9，在本实施例中，步骤S90具体包括如下步骤：
步骤S901：通过黄光工艺匀胶、曝光、显影，将焊盘图形化制作出来；
步骤S902：使用Asher工艺去除负胶底膜；
步骤S903：在片源甩水清洗后，使用E-Beam设备沉积Cr/Pt/Ni/Pt/Ni/AuSn；
步骤S904：使用碱性去胶液对去除光刻胶。
在此，需要说明的是其中AuSn的厚度为3um-4um。
最后应说明的是：以上实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的精神和范围。以上所述的具体实施例，对本发明的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本发明的具体实施例而已，并不用于限制本发明，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (10)

  1. 一种发光元件，其特征在于，包括衬底(101)以及依次生长于所述衬底(101)上的发光结构、电流扩展层(102)、钝化层(103)、反射层(104)、阻挡层(105)、绝缘层(106)、焊盘(107)；
    其中，所述焊盘(107)包括两个N型焊盘(1071)和一个P型焊盘(1072)，所述P型焊盘(1072)位于两个所述N型焊盘(1071)之间，所述N型焊盘(1071)的面积占比大于所述P型焊盘(1072)的面积占比，并且每一所述N型焊盘(1071)的端面上均匀的设有多个N孔(1073)，用以增加P电极和N电极之间的电流通道，使得P电极和N电极之间的电流扩展充分，进而降低P电极和N电极之间电压。
  2. 如权利要求1所述的发光元件，其特征在于，所述多个N孔(1073)在所述N型焊盘(1071)的端面上排成多列，相邻两列的所述N孔(1073)之间呈交错设置，以使得所述N孔(1073)在所述N型焊盘(1071)的端面上均匀分布。
  3. 如权利要求1或2所述的发光元件，其特征在于，所述N型焊盘(1071)的面积占比是所述P型焊盘(1072)的10倍以上，以使得所述N型焊盘(1071)的端面上可开挖多个所述N孔(1073)，用以增加P电极和N电极之间的电流通道。
  4. 如权利要求3中任一项所述的发光元件，其特征在于，所述电流扩展层(102)的开孔与所述钝化层(103)的开孔呈交错设置，用以提高亮度。
  5. 如权利要求4中任一项所述的发光元件，其特征在于，用于制作所述反射层(104)的反射金属的成分包括Ag合金，以及2％-5％的Pt成分，用以提高亮度。
  6. 一种制备发光元件的方法，其特征在于，包括如下步骤：
    在衬底(101)上依次生长出N型半导体层、有源层、P型半导体层以形成外延层；
    在相邻的芯粒间刻蚀出隔离沟道，以使各芯粒在所述外延层上完全隔断，进而形成独立单元；
    在所述P型半导体层上通过电感耦合等离子体刻蚀开设延伸到所述N 型半导体层的凹槽，以形成N型导电区域；
    在所述P型半导体层上制作电流扩展层(102)；
    在所述电流扩展层(102)上制作钝化层(103)；
    在所述钝化层(103)上制作反射层(104)；
    在所述反射层(104)上制作阻挡层(105)；
    在所述阻挡层(105)上制作绝缘层(106)；
    沉积N型焊盘(1071)和P型焊盘(1072)。
  7. 如权利要求6所述的制备发光元件的方法，其特征在于，在所述电流扩展层(102)上制作钝化层(103)的步骤包括：
    先蒸镀一层SiO2膜层，再在所述SiO2膜层上蒸镀一层TiO2膜层；
    重复上述蒸镀过程，直至形成厚度为的SiO2/TiO2叠层；
    采用ICP干法刻蚀所述SiO2/TiO2叠层，直至刻蚀到最底层的所述SiO2膜层
    采用BOE湿法刻蚀所述SiO2/TiO2叠层中最底层的所述SiO2膜层。
  8. 如权利要求7所述的制备发光元件的方法，其特征在于，在所述钝化层(103)上制作反射层(104)的步骤包括：
    采用磁控溅射法或者真空蒸发镀膜工艺在所述钝化层(103)镀一层反射金属；
    在镀膜所述反射金属的同时，上层继续沉积Ti/Pt或者TiW膜层，覆盖在所述反射金属上方。
  9. 如权利要求8所述的制备发光元件的方法，其特征在于，在所述阻挡层(105)上制作绝缘层(106)的步骤包括：
    使用等离子体增强型气相沉积法在250℃-300℃下沉积钝化膜层；
    再在所述钝化膜层上沉积一层厚度为的Al金属反射层；
    再在所述Al金属反射层的上方再沉积一层钝化膜层；
    再通过黄光匀胶曝光显影刻蚀，将所述钝化膜层开孔。
  10. 如权利要求9所述的制备发光元件的方法，其特征在于，沉积N型焊盘(1071)和P型焊盘(1072)包括如下步骤：
    通过黄光工艺匀胶、曝光、显影，将焊盘图形化制作出来；
    使用Asher工艺去除负胶底膜；
    在片源甩水清洗后，使用E-Beam设备沉积Cr/Pt/Ni/Pt/Ni/AuSn；
    使用碱性去胶液对去除光刻胶。
PCT/CN2023/073196 2022-11-30 2023-01-19 一种发光元件及其制备方法 WO2024113477A1 (zh)

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