WO2024113225A1 - 像素电路、显示装置及驱动方法 - Google Patents

像素电路、显示装置及驱动方法 Download PDF

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Publication number
WO2024113225A1
WO2024113225A1 PCT/CN2022/135415 CN2022135415W WO2024113225A1 WO 2024113225 A1 WO2024113225 A1 WO 2024113225A1 CN 2022135415 W CN2022135415 W CN 2022135415W WO 2024113225 A1 WO2024113225 A1 WO 2024113225A1
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Prior art keywords
transistor
control signal
signal terminal
gate
coupled
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PCT/CN2022/135415
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English (en)
French (fr)
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郭永林
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to PCT/CN2022/135415 priority Critical patent/WO2024113225A1/zh
Publication of WO2024113225A1 publication Critical patent/WO2024113225A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a pixel circuit, a display device and a driving method.
  • Electroluminescent diodes such as organic light emitting diodes (OLED), quantum dot light emitting diodes (QLED), and micro light emitting diodes (Micro LED) have the advantages of self-luminescence and low energy consumption, and are one of the hot spots in the current research field of electroluminescent display devices.
  • pixel circuits are used in electroluminescent display devices to drive electroluminescent diodes to emit light.
  • a driving transistor coupled to the light emitting device and configured to generate a working current driving the light emitting device according to a data voltage
  • a first control circuit coupled to the gate of the driving transistor and configured to reduce the gate leakage of the driving transistor based on a signal at a leakage adjustment signal terminal;
  • the second control circuit is coupled to the driving transistor and the light-emitting device respectively, and is configured to reset the driving transistor and the light-emitting device, control the data voltage to be input into the gate of the driving transistor, and control the driving transistor to generate the working current to drive the light-emitting device to emit light.
  • the second control circuit includes: a first control subcircuit; the first control subcircuit is configured to provide a signal at a first initialization signal terminal to the light-emitting device in response to a signal at the first control signal terminal, and to connect the first power supply terminal to the first electrode of the driving transistor in response to a signal at the first light-emitting control signal terminal, and to connect the second electrode of the driving transistor to the light-emitting device in response to a signal at the second light-emitting control signal terminal, and to connect the gate of the driving transistor to the second electrode of the driving transistor in response to a signal at the third control signal terminal, and to provide the signal at the second initialization signal terminal to the gate of the driving transistor in response to a signal at the fourth control signal terminal.
  • the second control circuit further includes: the second control subcircuit is configured to provide a data voltage at the data signal terminal to the first node in response to a signal at the second control signal terminal; and to provide a signal at the second reference voltage signal terminal to the first node in response to a signal at the third control signal terminal.
  • the second control circuit further includes: a third control subcircuit; the third control subcircuit is configured to provide a signal at the first reference voltage signal terminal to the first electrode of the driving transistor in response to a signal at the first control signal terminal.
  • the effective level of the first control signal terminal appears before the effective level of the second control signal terminal, and the effective level of the first control signal terminal has an overlapping area with the effective level of the third control signal terminal.
  • the first control signal terminal and the third control signal terminal receive the same signal; in a display frame, the effective level of the first control signal terminal appears before the effective level of the second control signal terminal.
  • the effective level of the first light-emitting control signal terminal and the effective level of the third control signal terminal have an overlapping area
  • the effective level of the second control signal terminal appears after the effective level of the third control signal terminal
  • the effective level of the first control signal terminal appears after the effective level of the second control signal terminal.
  • the first control circuit includes: a first transistor and a second transistor;
  • the gate of the first transistor is coupled to the leakage regulating signal terminal, the first electrode of the first transistor is floating, and the second electrode of the first transistor is coupled to the gate of the driving transistor;
  • the gate of the second transistor is coupled to the leakage regulating signal terminal, the first electrode of the second transistor is floating, and the second electrode of the second transistor is coupled to the gate of the driving transistor.
  • the first control circuit includes: a voltage-stabilizing capacitor; a first electrode of the voltage-stabilizing capacitor is coupled to the gate of the driving transistor, and a second electrode of the voltage-stabilizing capacitor is coupled to the leakage adjustment signal terminal.
  • the first control circuit includes: a compensation transistor
  • the first electrode and the second electrode of the compensation transistor are coupled to the leakage adjustment signal terminal, and the gate of the compensation transistor is coupled to the gate of the driving transistor;
  • the gate of the compensation transistor is coupled to the leakage adjustment signal terminal, and the first electrode and the second electrode of the compensation transistor are coupled to the gate of the driving transistor.
  • the voltage of the signal at the leakage adjustment signal terminal is a first voltage
  • the voltage of the signal at the leakage adjustment signal terminal is a second voltage
  • the second voltage is not less than the first voltage.
  • the first voltage is the same;
  • the second voltage is greater than the third voltage; the third voltage is Vda-Vth; Vda represents the data voltage, and Vth represents the threshold voltage of the driving transistor.
  • the second voltage is the same in different display frames
  • the second voltage increases as the third voltage increases.
  • the third control subcircuit includes: a third transistor
  • a gate of the third transistor is coupled to the first control signal terminal, a first electrode of the third transistor is coupled to the first electrode of the driving transistor, and a second electrode of the third transistor is coupled to the first reference voltage signal terminal.
  • the second control subcircuit includes: a fourth transistor, a fifth transistor and a first capacitor;
  • the gate of the fourth transistor is coupled to the second control signal terminal, the first electrode of the fourth transistor is coupled to the data signal terminal, and the second electrode of the fourth transistor is coupled to the first node;
  • the gate of the fifth transistor is coupled to the third control signal terminal, the first electrode of the fifth transistor is coupled to the first node, and the second electrode of the fifth transistor is coupled to the second reference voltage signal terminal;
  • a first electrode of the first capacitor is coupled to the first power supply terminal, and a second electrode of the first capacitor is coupled to the first node.
  • the first control subcircuit includes: a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor and a second capacitor;
  • the gate of the sixth transistor is coupled to the first control signal terminal, the first electrode of the sixth transistor is coupled to the light emitting device, and the second electrode of the sixth transistor is coupled to the first initialization signal terminal;
  • the gate of the seventh transistor is coupled to the first light emitting control signal terminal, the first electrode of the seventh transistor is coupled to the first power supply terminal, and the second electrode of the seventh transistor is coupled to the first electrode of the driving transistor;
  • the gate of the eighth transistor is coupled to the second light emitting control signal terminal, the first electrode of the eighth transistor is coupled to the second electrode of the driving transistor, and the second electrode of the eighth transistor is coupled to the light emitting device;
  • the gate of the ninth transistor is coupled to the third control signal terminal, the first electrode of the ninth transistor is coupled to the gate of the driving transistor, and the second electrode of the ninth transistor is coupled to the second electrode of the driving transistor;
  • the gate of the tenth transistor is coupled to the fourth control signal terminal, the first electrode of the tenth transistor is coupled to the gate of the driving transistor, and the second electrode of the tenth transistor is coupled to the second initialization signal terminal;
  • a first electrode of the second capacitor is coupled to the first node, and a second electrode of the second capacitor is coupled to the gate of the driving transistor.
  • the embodiment of the present disclosure also provides a display device, including the above-mentioned pixel circuit.
  • the embodiment of the present disclosure also provides a driving method for the above pixel circuit, including:
  • the first control circuit reduces the gate leakage of the driving transistor based on the signal of the leakage adjustment signal terminal; the second control circuit controls the data voltage to be input into the gate of the driving transistor;
  • the first control circuit reduces the gate leakage of the driving transistor based on the signal of the leakage adjustment signal terminal; the second control circuit controls the driving transistor to generate the working current to drive the light-emitting device to emit light.
  • FIG1 is a schematic diagram of the structure of some pixel circuits provided by an embodiment of the present disclosure.
  • FIG2 is a schematic diagram of the structure of other pixel circuits provided by an embodiment of the present disclosure.
  • FIG3 is a schematic diagram of the structure of some other pixel circuits provided by an embodiment of the present disclosure.
  • FIG4a is a timing diagram of some signals provided by an embodiment of the present disclosure.
  • FIG4b is another signal timing diagram provided by an embodiment of the present disclosure.
  • FIG5 is a flow chart of some driving methods provided by embodiments of the present disclosure.
  • FIG6 is a schematic diagram of the structure of some other pixel circuits provided by an embodiment of the present disclosure.
  • FIG7 is a timing diagram of some further signals provided by an embodiment of the present disclosure.
  • FIG8 is a timing diagram of some further signals provided by an embodiment of the present disclosure.
  • FIG9 is a timing diagram of some further signals provided by an embodiment of the present disclosure.
  • FIG10 is a timing diagram of some further signals provided by an embodiment of the present disclosure.
  • FIG11 is a schematic diagram of the structure of some other pixel circuits provided by an embodiment of the present disclosure.
  • FIG. 12 is a schematic diagram of the structures of some further pixel circuits provided in an embodiment of the present disclosure.
  • the display device may include a display panel.
  • the display panel may include a substrate.
  • the substrate may include a display area and a non-display area (i.e., an area in the substrate except the display area).
  • the display area may include a plurality of pixel units arranged in an array.
  • each pixel unit includes sub-pixels of the same color or sub-pixels of multiple different colors.
  • the pixel unit may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, so that red, green, and blue can be mixed to achieve color display.
  • the pixel unit may also include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, so that red, green, blue, and white can be mixed to achieve color display.
  • the luminous color of the sub-pixel in the pixel unit can be designed and determined according to the actual application environment, and is not limited here. The following is an example of a pixel unit including a red sub-pixel, a green sub-pixel, and a blue sub-pixel.
  • each sub-pixel may include a pixel circuit
  • the pixel circuit may include a driving transistor and a light-emitting device to control the light-emitting device to emit light, so that the display panel can realize the function of displaying a picture.
  • the voltage of the gate of the driving transistor gradually changes, and the brightness of the display will also change accordingly.
  • the threshold voltage Vth of the driving transistor will drift, which will affect the generated driving current and affect the display problem.
  • the pixel circuit provided by the embodiment of the present disclosure includes: a light emitting device L, a driving transistor T0, a first control circuit 10 and a second control circuit 20;
  • the driving transistor T0 is coupled to the light emitting device L and is configured to generate a working current for driving the light emitting device L according to the data voltage;
  • the first control circuit 10 is coupled to the gate of the driving transistor T0 and is configured to reduce the gate leakage of the driving transistor T0 based on the signal of the leakage adjustment signal terminal VS;
  • the second control circuit 20 is coupled to the driving transistor T0 and the light emitting device L respectively, and is configured to reset the driving transistor T0 and the light emitting device L, control the data voltage to be input into the gate of the driving transistor T0, and control the driving transistor T0 to generate an operating current to drive the light emitting device L to emit light.
  • the pixel circuit provided by the embodiment of the present disclosure can reduce the gate leakage of the driving transistor based on the signal of the leakage adjustment signal terminal by setting a first control circuit coupled to the gate of the driving transistor, thereby improving the flicker problem during low grayscale display. And by setting a second control circuit, before driving the light-emitting device to emit light, the driving transistor and the light-emitting device are reset, the data voltage is controlled to be input to the gate of the driving transistor, and the driving transistor is controlled to generate an operating current, the light-emitting device is driven to emit light, and the hysteresis effect of the driving transistor is improved, thereby improving the flicker problem during high grayscale display.
  • the pixel circuit provided by the embodiment of the present disclosure can be applied to display panels driven by different refresh frequencies. Since the pixel circuit provided by the embodiment of the present disclosure can be compatible with improving the flicker problem when displaying high and low grayscales, when switching between different refresh frequencies, the flicker problem is improved, thereby improving the display effect of the product. In addition, in order to reduce power consumption, the pixel circuit provided by the embodiment of the present disclosure can be applied to the case of driving at a lower refresh frequency (for example, 1Hz, 30Hz, etc.). In addition, in order to improve the display effect, the pixel circuit provided by the embodiment of the present disclosure can be applied to the case of driving at a higher refresh frequency (for example, 60Hz, 90Hz, 120Hz, 240Hz, etc.).
  • the second control circuit 20 includes: a first control subcircuit 201 , a second control subcircuit 202 , and a third control subcircuit 203 ;
  • the first control subcircuit 201 is configured to provide the signal of the first initialization signal terminal VINIT1 to the light emitting device L in response to the signal of the first control signal terminal CS1, and to conduct the first power supply terminal VDD with the first electrode of the driving transistor T0 in response to the signal of the first light emitting control signal terminal EM1, and to conduct the second electrode of the driving transistor T0 with the light emitting device L in response to the signal of the second light emitting control signal terminal EM2, and to conduct the gate of the driving transistor T0 with the second electrode of the driving transistor T0 in response to the signal of the third control signal terminal CS3, and to provide the signal of the second initialization signal terminal VINIT2 to the gate of the driving transistor T0 in response to the signal of the fourth control signal terminal CS4;
  • the second control subcircuit 202 is configured to provide the data voltage Vda of the data signal terminal DA to the first node N1 in response to the signal of the second control signal terminal CS2; and provide the signal of the second reference voltage signal terminal VREF2 to the first node N1 in response to the signal of the third control signal terminal CS3;
  • the third control sub-circuit 203 is configured to provide a signal from the first reference voltage signal terminal VREF1 to the first electrode of the driving transistor T0 in response to a signal from the first control signal terminal CS1.
  • the first electrode of the light emitting device L may be coupled to the first control subcircuit 201, and the second electrode of the light emitting device L may be coupled to the second power supply terminal VSS. Furthermore, the first electrode of the light emitting device L may be its anode, and the second electrode may be its cathode. Exemplarily, the light emitting device L may be an electroluminescent diode.
  • the light emitting device L may include: at least one of a micro light emitting diode (Micro Light Emitting Diode, Micro LED), an organic electroluminescent diode (Organic Light Emitting Diode, OLED), and a quantum dot light emitting diode (Quantum Dot Light Emitting Diodes, QLED).
  • a micro light emitting diode Micro Light Emitting Diode, Micro LED
  • an organic electroluminescent diode Organic Light Emitting Diode, OLED
  • a quantum dot light emitting diode Quantantum Dot Light Emitting Diodes, QLED.
  • the specific structure of the light emitting device L can be designed and determined according to the actual application environment, and is not limited here.
  • the first power supply terminal VDD can be configured to load a constant first power supply voltage, and the first power supply voltage is generally a positive value.
  • the second power supply terminal VSS can load a constant second power supply voltage, and the second power supply voltage can generally be a ground voltage or a negative value.
  • the specific values of the first power supply voltage and the second power supply voltage can be designed and determined according to the actual application environment, and are not limited here.
  • the driving transistor T0 can be set as a P-type transistor; wherein the first electrode of the driving transistor T0 can be its source, the second electrode of the driving transistor T0 can be its drain, and when the driving transistor T0 is in a saturated state, the current flows from the source of the driving transistor T0 to its drain.
  • the driving transistor T0 can also be set as an N-type transistor, which is not limited here.
  • the first control circuit 10 includes: a first transistor T1 and a second transistor T2.
  • the gate of the first transistor T1 is coupled to the leakage adjustment signal terminal VS, the first electrode of the first transistor T1 is floating, and the second electrode of the first transistor T1 is coupled to the gate of the driving transistor T0.
  • the gate of the second transistor T2 is coupled to the leakage adjustment signal terminal VS, the first electrode of the second transistor T2 is floating, and the second electrode of the second transistor T2 is coupled to the gate of the driving transistor T0.
  • the leakage of the gate of the driving transistor T0 can be improved.
  • the first transistor T1 and the second transistor T2 may be configured as P-type transistors.
  • the first transistor and the second transistor may also be configured as N-type transistors, which is not limited here.
  • the voltage of the signal at the leakage adjustment signal terminal VS is the first voltage Vvs1
  • the voltage of the signal at the leakage adjustment signal terminal VS is the second voltage Vvs2.
  • the second voltage Vvs2 can be made equal to the first voltage Vvs1.
  • the voltage of the signal vs at the leakage adjustment signal terminal VS can be a fixed voltage in one display frame.
  • the voltage of the signal vs at the leakage adjustment signal terminal VS is the second voltage Vvs2.
  • the first voltage Vvs1 may be made the same, so that the first voltage Vvs1 does not need to be adjusted frequently, thereby reducing power consumption.
  • the second voltage Vvs2 can be made greater than the third voltage Vvs3.
  • the third voltage Vvs3 is Vda-Vth
  • Vda represents the data voltage
  • Vth represents the threshold voltage of the driving transistor.
  • Vda-Vth is approximately 0-1V
  • the second voltage Vvs2 can be set to 2V.
  • Vda can be a data voltage corresponding to a larger grayscale or a maximum grayscale.
  • the second voltage Vvs2 can be made the same, so that the second voltage Vvs2 does not need to be adjusted frequently, thereby reducing power consumption.
  • the voltage of the signal vs of the leakage adjustment signal terminal VS can be made a fixed voltage, so that the voltage of the signal vs of the leakage adjustment signal terminal VS does not need to be adjusted frequently, thereby reducing power consumption.
  • the second voltage Vvs2 can also be increased as the third voltage Vvs3 increases, so that the second voltage Vvs2 can be adjusted according to the third voltage Vvs3 to further reduce leakage.
  • the voltage of the signal vs at the leakage adjustment signal terminal VS can be an alternating voltage to further reduce leakage.
  • the voltage of the signal vs of the leakage adjustment signal terminal VS is the first voltage Vvs1
  • the voltage of the signal vs of the leakage adjustment signal terminal VS is the second voltage Vvs2.
  • the second voltage Vvs2 can be made greater than the first voltage Vvs1.
  • the voltage of the signal vs of the leakage adjustment signal terminal VS can be an alternating voltage in one display frame.
  • the voltage of the signal vs of the leakage adjustment signal terminal VS has the second voltage Vvs2 and the first voltage Vvs1.
  • the first voltage Vvs1 may be made the same, so that the first voltage Vvs1 does not need to be adjusted frequently, thereby reducing power consumption.
  • the second voltage Vvs2 can be made greater than the third voltage Vvs3.
  • the third voltage Vvs3 is Vda-Vth
  • Vda represents the data voltage
  • Vth represents the threshold voltage of the driving transistor.
  • Vda-Vth is approximately 0-1V
  • the second voltage Vvs2 can be set to 2V.
  • Vda can be a data voltage corresponding to a larger grayscale or a maximum grayscale.
  • the second voltage Vvs2 may be made the same, so that the second voltage Vvs2 does not need to be adjusted frequently, thereby reducing power consumption.
  • the second voltage Vvs2 may also be increased as the third voltage Vvs3 increases, so that the second voltage Vvs2 may be adjusted according to the third voltage Vvs3 to further reduce leakage.
  • the third control subcircuit 203 includes: a third transistor T3; the gate of the third transistor T3 is coupled to the first control signal terminal CS1, the first electrode of the third transistor T3 is coupled to the first electrode of the driving transistor T0, and the second electrode of the third transistor T3 is coupled to the first reference voltage signal terminal VREF1.
  • the third transistor T3 is turned on under the control of the effective level of the first control signal of the first control signal terminal CS1, and is turned off under the control of the ineffective level of the first control signal.
  • the third transistor T3 can be set as a P-type transistor, then the effective level of the first control signal can be a low level, and the ineffective level of the first control signal can be a high level.
  • the third transistor T3 can also be set as an N-type transistor, then the effective level of the first control signal can be a high level, and the ineffective level of the first control signal can be a low level.
  • the second control subcircuit 202 includes: a fourth transistor T4, a fifth transistor T5, and a first capacitor C1; wherein a gate of the fourth transistor T4 is coupled to the second control signal terminal CS2, a first electrode of the fourth transistor T4 is coupled to the data signal terminal DA, and a second electrode of the fourth transistor T4 is coupled to the first node N1;
  • a gate of the fifth transistor T5 is coupled to the third control signal terminal CS3, a first electrode of the fifth transistor T5 is coupled to the first node N1, and a second electrode of the fifth transistor T5 is coupled to the second reference voltage signal terminal VREF2;
  • a first electrode of the first capacitor C1 is coupled to the first power supply terminal VDD, and a second electrode of the first capacitor C1 is coupled to the first node N1.
  • the fourth transistor T4 is turned on under the control of the effective level of the second control signal of the second control signal terminal CS2, and is turned off under the control of the ineffective level of the second control signal.
  • the fourth transistor T4 can be set as a P-type transistor, then the effective level of the second control signal can be a low level, and the ineffective level of the second control signal can be a high level.
  • the fourth transistor T4 can also be set as an N-type transistor, then the effective level of the second control signal can be a high level, and the ineffective level of the second control signal can be a low level.
  • the fifth transistor T5 is turned on under the control of the effective level of the third control signal of the third control signal terminal CS3, and is turned off under the control of the ineffective level of the third control signal.
  • the fifth transistor T5 can be set as a P-type transistor, then the effective level of the third control signal can be a low level, and the ineffective level of the third control signal can be a high level.
  • the fifth transistor T5 can also be set as an N-type transistor, then the effective level of the third control signal can be a high level, and the ineffective level of the third control signal can be a low level.
  • the first control subcircuit 201 includes: a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, and a second capacitor C2; wherein the gate of the sixth transistor T6 is coupled to the first control signal terminal CS1, the first electrode of the sixth transistor T6 is coupled to the light emitting device L, and the second electrode of the sixth transistor T6 is coupled to the first initialization signal terminal VINIT1;
  • a gate of the seventh transistor T7 is coupled to the first light emitting control signal terminal EM1, a first electrode of the seventh transistor T7 is coupled to the first power supply terminal VDD, and a second electrode of the seventh transistor T7 is coupled to the first electrode of the driving transistor T0;
  • a gate of the eighth transistor T8 is coupled to the second light emitting control signal terminal EM2, a first electrode of the eighth transistor T8 is coupled to the second electrode of the driving transistor T0, and a second electrode of the eighth transistor T8 is coupled to the light emitting device L;
  • a gate of the ninth transistor T9 is coupled to the third control signal terminal CS3, a first electrode of the ninth transistor T9 is coupled to the gate of the driving transistor T0, and a second electrode of the ninth transistor T9 is coupled to the second electrode of the driving transistor T0;
  • a gate of the tenth transistor T10 is coupled to the fourth control signal terminal CS4, a first electrode of the tenth transistor T10 is coupled to the gate of the driving transistor T0, and a second electrode of the tenth transistor T10 is coupled to the second initialization signal terminal VINIT2;
  • a first electrode of the second capacitor C2 is coupled to the first node N1 , and a second electrode of the second capacitor C2 is coupled to the gate of the driving transistor T0 .
  • the sixth transistor T6 is turned on under the control of the effective level of the first control signal of the first control signal terminal CS1, and is turned off under the control of the ineffective level of the first control signal.
  • the sixth transistor T6 can be set as a P-type transistor, then the effective level of the first control signal can be a low level, and the ineffective level of the first control signal can be a high level.
  • the sixth transistor T6 can also be set as an N-type transistor, then the effective level of the first control signal can be a high level, and the ineffective level of the first control signal can be a low level.
  • the seventh transistor T7 is turned on under the control of the effective level of the first light-emitting control signal of the first light-emitting control signal terminal EM1, and is turned off under the control of the invalid level of the first light-emitting control signal.
  • the seventh transistor T7 can be set as a P-type transistor, then the effective level of the first light-emitting control signal can be a low level, and the invalid level of the first light-emitting control signal can be a high level.
  • the seventh transistor T7 can also be set as an N-type transistor, then the effective level of the first light-emitting control signal can be a high level, and the invalid level of the first light-emitting control signal can be a low level.
  • the eighth transistor T8 is turned on under the control of the effective level of the second light-emitting control signal of the second light-emitting control signal terminal EM2, and is turned off under the control of the ineffective level of the second light-emitting control signal.
  • the eighth transistor T8 can be set as a P-type transistor, then the effective level of the second light-emitting control signal can be a low level, and the ineffective level of the second light-emitting control signal can be a high level.
  • the eighth transistor T8 can also be set as an N-type transistor, then the effective level of the second light-emitting control signal can be a high level, and the ineffective level of the second light-emitting control signal can be a low level.
  • the ninth transistor T9 is turned on under the control of the effective level of the third control signal of the third control signal terminal CS3, and is turned off under the control of the ineffective level of the third control signal.
  • the ninth transistor T9 can be set as a P-type transistor, then the effective level of the third control signal can be a low level, and the ineffective level of the third control signal can be a high level.
  • the ninth transistor T9 can also be set as an N-type transistor, then the effective level of the third control signal can be a high level, and the ineffective level of the third control signal can be a low level.
  • the tenth transistor T10 is turned on under the control of the effective level of the fourth control signal of the fourth control signal terminal CS4, and is turned off under the control of the ineffective level of the fourth control signal.
  • the tenth transistor T10 can be set as a P-type transistor, then the effective level of the fourth control signal can be a low level, and the ineffective level of the fourth control signal can be a high level.
  • the tenth transistor T10 can also be set as an N-type transistor, then the effective level of the fourth control signal can be a high level, and the ineffective level of the fourth control signal can be a low level.
  • the first electrode of the transistor can be used as its source and the second electrode as its drain according to the type of transistor and the signal of its gate; or, conversely, the first electrode of the transistor can be used as its drain and the second electrode can be used as its source.
  • This can be designed and determined according to the actual application environment, and no specific distinction is made here.
  • FIG4a and FIG4b the signal timing diagram corresponding to the pixel circuit shown in FIG3 is shown in FIG4a and FIG4b.
  • em1 represents the first light-emitting control signal of the first light-emitting control signal terminal EM1
  • em2 represents the second light-emitting control signal of the second light-emitting control signal terminal EM2
  • cs1 represents the first control signal of the first control signal terminal CS1
  • cs2 represents the second control signal of the second control signal terminal CS2
  • cs3 represents the third control signal of the third control signal terminal CS3
  • cs4 represents the fourth control signal of the fourth control signal terminal CS4.
  • the first control signal terminal CS1, the second control signal CS2, the third control signal CS3 and the fourth control signal terminal CS4 can be set as different signal terminals.
  • the effective level (e.g., low level) of the first control signal cs1 of the first control signal terminal CS1 appears before the effective level (e.g., low level) of the second control signal cs2 of the second control signal terminal CS2, and the effective level (e.g., low level) of the first control signal cs1 of the first control signal terminal CS1 and the effective level (e.g., low level) of the third control signal cs3 of the third control signal terminal CS3 have an overlapping area.
  • the effective level (e.g., low level) of the fourth control signal cs4 of the fourth control signal terminal CS4 appears before the effective level (e.g., low level) of the first control signal cs1 of the first control signal terminal CS1.
  • the effective level (e.g., low level) of the first control signal cs1 of the first control signal terminal CS1 and the effective level (e.g., low level) of the third control signal cs3 of the third control signal terminal CS3 have an overlapping region. Then, the third transistor T3, the sixth transistor T6, the fifth transistor T5, and the ninth transistor T9 are all turned on during the time period of the overlapping region.
  • a gate driving circuit and a light emitting control circuit may be provided in a non-display area of the base substrate to drive each transistor in the pixel circuit.
  • three gate driving circuits (each gate driving circuit may include multiple cascaded shift register units) and one light-emitting control circuit (the light-emitting control circuit may include multiple cascaded shift register units) may be provided in the non-display area.
  • the first control signal cs1 of the first control signal terminal CS1 may be input by the first gate driving circuit of the three gate driving circuits.
  • the third control signal cs3 of the third control signal terminal CS3 may be input by the second gate driving circuit of the three gate driving circuits.
  • the second control signal cs2 of the second control signal terminal CS2 and the fourth control signal cs4 of the fourth control signal terminal CS4 may be input by the third gate driving circuit of the three gate driving circuits. Furthermore, the first light-emitting control signal em1 of the first light-emitting control signal terminal EM1 and the second light-emitting control signal em2 of the second light-emitting control signal terminal EM2 may be input by the light-emitting control circuit.
  • the first control signal cs1 may be a signal input by the nth shift register unit in the first gate driving circuit.
  • the third control signal cs3 may be a signal input by the nth shift register unit in the second gate driving circuit.
  • the fourth control signal cs4 may be a signal input by the n-3th shift register unit in the third gate driving circuit (such as Gate(n-3)), and the second control signal cs2 is a signal input by the nth shift register unit in the third gate driving circuit (such as Gate(n)).
  • the first light-emitting control signal em1 of the first light-emitting control signal terminal EM1 may be a signal input by the n-1th shift register unit in the light-emitting control circuit
  • the second light-emitting control signal em2 of the second light-emitting control signal terminal EM2 may be a signal input by the nth shift register unit in the light-emitting control circuit.
  • two gate driving circuits (each gate driving circuit may include multiple cascaded shift register units) and one light emitting control circuit (the light emitting control circuit may include multiple cascaded shift register units) may be provided in the non-display area.
  • one gate driving circuit may be saved, and the occupied space of the non-display area may be reduced.
  • the first light emitting control signal em1 of the first light emitting control signal terminal EM1 and the second light emitting control signal em2 of the second light emitting control signal terminal EM2 may adopt the light emitting control circuit.
  • the first control signal cs1 of the first control signal terminal CS1 can be input by the first gate driving circuit of the two gate driving circuits.
  • the second control signal cs2 of the second control signal terminal CS2, the third control signal cs3 of the third control signal terminal CS3, and the fourth control signal cs4 of the fourth control signal terminal CS4 can be input by the second gate driving circuit of the two gate driving circuits.
  • the first control signal cs1 to the fourth control signal cs4 received by the pixel circuit in the nth row of sub-pixels the first control signal cs1 can be a signal input by the nth stage shift register unit in the first gate driving circuit.
  • the fourth control signal cs4 may be a signal input by the n-3th shift register unit in the second gate driving circuit (such as Gate(n-3)), the third control signal cs3 may be a signal input by the n-2th shift register unit in the second gate driving circuit (such as Gate(n-2)), and the second control signal cs2 may be a signal input by the nth shift register unit in the second gate driving circuit (such as Gate(n)).
  • the first light-emitting control signal em1 of the first light-emitting control signal terminal EM1 may be a signal input by the n-1th shift register unit in the light-emitting control circuit
  • the second light-emitting control signal em2 of the second light-emitting control signal terminal EM2 may be a signal input by the nth shift register unit in the light-emitting control circuit.
  • the driving method of the pixel circuit may include the following steps:
  • the first control circuit reduces the gate leakage of the driving transistor based on the signal at the leakage adjustment signal terminal; the second control circuit controls the data voltage to be input into the gate of the driving transistor.
  • the first control circuit reduces the gate leakage of the driving transistor based on the signal at the leakage adjustment signal terminal; the second control circuit controls the driving transistor to generate an operating current to drive the light-emitting device to emit light.
  • em1 represents the first light control signal of the first light control signal terminal EM1
  • em2 represents the second light control signal of the second light control signal terminal EM2
  • cs1 represents the first control signal of the first control signal terminal CS1
  • cs2 represents the second control signal of the second control signal terminal CS2
  • cs3 represents the third control signal of the third control signal terminal CS3
  • cs4 represents the fourth control signal of the fourth control signal terminal CS4.
  • the seventh transistor T7 is turned off under the control of the high level of the first light-emitting control signal em1
  • the eighth transistor T8 is turned off under the control of the high level of the second light-emitting control signal em2
  • the third transistor T3 and the sixth transistor T6 are turned off under the control of the high level of the first control signal cs1
  • the tenth transistor T10 is turned on under the control of the low level of the fourth control signal cs4
  • the fourth transistor T4 is turned off under the control of the high level of the second control signal cs2
  • the fifth transistor T5 and the ninth transistor T9 are turned off under the control of the high level of the third control signal cs3.
  • the seventh transistor T7 is turned off under the control of the high level of the first light-emitting control signal em1
  • the eighth transistor T8 is turned off under the control of the high level of the second light-emitting control signal em2
  • the third transistor T3 and the sixth transistor T6 are turned on under the control of the low level of the first control signal cs1
  • the tenth transistor T10 is turned off under the control of the high level of the fourth control signal cs4
  • the fourth transistor T4 is turned off under the control of the high level of the second control signal cs2
  • the fifth transistor T5 and the ninth transistor T9 are turned on under the control of the low level of the third control signal cs3.
  • the turned-on third transistor T3 provides the signal of the first reference voltage signal terminal VREF1 to the first electrode of the driving transistor T0, and resets the first electrode of the driving transistor T0.
  • the turned-on sixth transistor T6 provides the signal of the first initialization signal terminal VINIT1 to the light-emitting device L, and resets the light-emitting device L.
  • the seventh transistor T7 is turned off under the control of the high level of the first light-emitting control signal em1
  • the eighth transistor T8 is turned off under the control of the high level of the second light-emitting control signal em2
  • the third transistor T3 and the sixth transistor T6 are turned off under the control of the high level of the first control signal cs1
  • the tenth transistor T10 is turned off under the control of the high level of the fourth control signal cs4
  • the fourth transistor T4 is turned on under the control of the low level of the second control signal cs2
  • the fifth transistor T5 and the ninth transistor T9 are turned off under the control of the high level of the third control signal cs3.
  • the turned-on fourth transistor T4 inputs the data voltage Vda of the data signal terminal DA to the first node N1, and VN1 changes from Vref2 to Vda.
  • VN2 changes from Vth+Vref1 to:
  • C2 represents the capacitance value of the second capacitor C2
  • Cgs_T10 represents the capacitance value of the tenth transistor T10
  • Cgs_T9 represents the capacitance value of the ninth transistor T9
  • Cgs_T0 represents the capacitance value of the driving transistor T0
  • Cgs_T1 represents the capacitance value of the first transistor T1
  • Cgs_T2 represents the capacitance value of the second transistor T2.
  • the gate leakage of the driving transistor T0 is reduced, and the gate voltage of the driving transistor T0 can be further kept stable.
  • the seventh transistor T7 is turned on under the control of the low level of the first light-emitting control signal em1
  • the eighth transistor T8 is turned off under the control of the high level of the second light-emitting control signal em2
  • the third transistor T3 and the sixth transistor T6 are turned off under the control of the high level of the first control signal cs1
  • the tenth transistor T10 is turned off under the control of the high level of the fourth control signal cs4
  • the fourth transistor T4 is turned off under the control of the high level of the second control signal cs2
  • the fifth transistor T5 and the ninth transistor T9 are turned off under the control of the high level of the third control signal cs3.
  • the turned-on seventh transistor T7 provides the signal of the first power supply terminal VDD to the first electrode of the driving transistor T0.
  • the gate leakage of the driving transistor T0 is reduced, and the gate voltage of the driving transistor T0 can be further kept stable.
  • the seventh transistor T7 is turned on under the control of the low level of the first light control signal em1
  • the eighth transistor T8 is turned on under the control of the low level of the second light control signal em2
  • the third transistor T3 and the sixth transistor T6 are turned off under the control of the high level of the first control signal cs1
  • the tenth transistor T10 is turned off under the control of the high level of the fourth control signal cs4
  • the fourth transistor T4 is turned off under the control of the high level of the second control signal cs2
  • the fifth transistor T5 and the ninth transistor T9 are turned off under the control of the high level of the third control signal cs3.
  • the turned-on seventh transistor T7 provides the signal of the first power supply terminal VDD to the first electrode of the driving transistor T0, so that the voltage of the first electrode of the driving transistor T0 is the first power supply voltage Vdd.
  • the turned-on eighth transistor T8 turns on the second electrode of the driving transistor T0 and the light emitting device L, so that the driving transistor T0 generates a driving current Ids for driving the light emitting device L to emit light, and controls the light emitting device L to emit light.
  • the driving transistor T0 generates a working current Ids for driving the light emitting device L to emit light, and Ids satisfies the following formula:
  • L represents the length of the channel of the driving transistor T0
  • W represents the width of the channel of the driving transistor T0
  • Cox represents the capacitance per unit area of the gate insulating layer of the driving transistor T0
  • ⁇ represents the mobility of the driving transistor T0
  • Vdd represents the voltage output by the first power supply terminal VDD.
  • the first control signal terminal CS1 and the third control signal terminal CS3 receive the same signal to reduce the number of signal terminals and the number of wirings.
  • the gate of the fifth transistor T5 and the gate of the ninth transistor T9 are both coupled to the first control signal terminal CS1.
  • the signal timing diagram corresponding to the pixel circuit shown in FIG6 is shown in FIG7.
  • em1 represents the first light-emitting control signal of the first light-emitting control signal terminal EM1
  • em2 represents the second light-emitting control signal of the second light-emitting control signal terminal EM2
  • cs1 represents the first control signal of the first control signal terminal CS1
  • cs2 represents the second control signal of the second control signal terminal CS2
  • cs4 represents the fourth control signal of the fourth control signal terminal CS4.
  • the first control signal terminal CS1, the second control signal terminal CS2, and the fourth control signal terminal CS4 can be set to different signal terminals.
  • the effective level (e.g., low level) of the first control signal cs1 of the first control signal terminal CS1 appears before the effective level (e.g., low level) of the second control signal cs2 of the second control signal terminal CS2.
  • the effective level (e.g., low level) of the fourth control signal cs4 of the fourth control signal terminal CS4 appears before the effective level (e.g., low level) of the first control signal cs1 of the first control signal terminal CS1.
  • a gate driving circuit and a light emitting control circuit may be provided in a non-display area of the base substrate to drive each transistor in the pixel circuit.
  • a gate driving circuit (the gate driving circuit may include multiple cascaded shift register units) and a light emitting control circuit (the light emitting control circuit may include multiple cascaded shift register units) may be provided in the non-display area.
  • the first control signal cs1 of the first control signal terminal CS1, the second control signal cs2 of the second control signal terminal CS2, and the fourth control signal cs4 of the fourth control signal terminal CS4 may be input by the gate driving circuit.
  • the gate driving circuit can be saved and the occupied space of the non-display area can be reduced.
  • the first light emitting control signal em1 of the first light emitting control signal terminal EM1 and the second light emitting control signal em2 of the second light emitting control signal terminal EM2 may adopt the light emitting control circuit.
  • the fourth control signal cs4 may be a signal input by the n-3th shift register unit in the gate drive circuit (such as Gate(n-3)), the first control signal cs1 is a signal input by the n-2th shift register unit in the gate drive circuit (such as Gate(n-2)), and the second control signal cs2 is a signal input by the nth shift register unit in the gate drive circuit (such as Gate(n)).
  • the first light-emitting control signal em1 of the first light-emitting control signal terminal EM1 may be a signal input by the n-1th shift register unit in the light-emitting control circuit
  • the second light-emitting control signal em2 of the second light-emitting control signal terminal EM2 may be a signal input by the nth shift register unit in the light-emitting control circuit.
  • two gate driving circuits (each gate driving circuit may include multiple cascaded shift register units) and one light-emitting control circuit (the light-emitting control circuit may include multiple cascaded shift register units) may be set in the non-display area and the first light-emitting control signal em1 of the first light-emitting control signal terminal EM1 and the second light-emitting control signal em2 of the second light-emitting control signal terminal EM2 may adopt the light-emitting control circuit.
  • the first control signal cs1 of the first control signal terminal CS1 can be input by the first gate drive circuit of the two gate drive circuits.
  • the second control signal cs2 of the second control signal terminal CS2 and the fourth control signal cs4 of the fourth control signal terminal CS4 can be input by the second gate drive circuit of the two gate drive circuits.
  • the first control signal cs1 can be a signal input by the nth stage shift register unit in the first gate drive circuit.
  • the fourth control signal cs4 can be a signal input by the n-3th stage shift register unit in the second gate drive circuit (such as Gate(n-3)), and the second control signal cs2 is a signal input by the nth stage shift register unit in the second gate drive circuit (such as Gate(n)).
  • the first light control signal em1 of the first light control signal terminal EM1 can be a signal input to the n-1th stage shift register unit in the light control circuit
  • the second light control signal em2 of the second light control signal terminal EM2 can be a signal input to the nth stage shift register unit in the light control circuit.
  • em1 represents the first light-emitting control signal of the first light-emitting control signal terminal EM1
  • em2 represents the second light-emitting control signal of the second light-emitting control signal terminal EM2
  • cs1 represents the first control signal of the first control signal terminal CS1
  • cs2 represents the second control signal of the second control signal terminal CS2
  • cs4 represents the fourth control signal of the fourth control signal terminal CS4.
  • the seventh transistor T7 is turned off under the control of the high level of the first light-emitting control signal em1
  • the eighth transistor T8 is turned off under the control of the high level of the second light-emitting control signal em2
  • the tenth transistor T10 is turned on under the control of the low level of the fourth control signal cs4
  • the fourth transistor T4 is turned off under the control of the high level of the second control signal cs2
  • the third transistor T3, the sixth transistor T6, the fifth transistor T5 and the ninth transistor T9 are turned off under the control of the high level of the first control signal cs1.
  • the seventh transistor T7 is turned off under the control of the high level of the first light-emitting control signal em1
  • the eighth transistor T8 is turned off under the control of the high level of the second light-emitting control signal em2
  • the tenth transistor T10 is turned off under the control of the high level of the fourth control signal cs4
  • the fourth transistor T4 is turned off under the control of the high level of the second control signal cs2
  • the third transistor T3, the sixth transistor T6, the fifth transistor T5 and the ninth transistor T9 are turned on under the control of the low level of the first control signal cs1.
  • the turned-on third transistor T3 provides the signal of the first reference voltage signal terminal VREF1 to the first electrode of the driving transistor T0, and resets the first electrode of the driving transistor T0.
  • the turned-on sixth transistor T6 provides the signal of the first initialization signal terminal VINIT1 to the light-emitting device L, and resets the light-emitting device L.
  • the seventh transistor T7 is turned off under the control of the high level of the first light-emitting control signal em1
  • the eighth transistor T8 is turned off under the control of the high level of the second light-emitting control signal em2
  • the tenth transistor T10 is turned off under the control of the high level of the fourth control signal cs4
  • the fourth transistor T4 is turned on under the control of the low level of the second control signal cs2
  • the third transistor T3, the sixth transistor T6, the fifth transistor T5 and the ninth transistor T9 are turned off under the control of the high level of the first control signal cs1.
  • the turned-on fourth transistor T4 inputs the data voltage Vda of the data signal terminal DA to the first node N1.
  • VN2 changes from Vth+Vref1 to:
  • the gate leakage of the driving transistor T0 is reduced, and the gate voltage of the driving transistor T0 can be further kept stable.
  • the seventh transistor T7 is turned on under the control of the low level of the first light-emitting control signal em1, the eighth transistor T8 is turned off under the control of the high level of the second light-emitting control signal em2, the tenth transistor T10 is turned off under the control of the high level of the fourth control signal cs4, the fourth transistor T4 is turned off under the control of the high level of the second control signal cs2, and the third transistor T3, the sixth transistor T6, the fifth transistor T5 and the ninth transistor T9 are turned off under the control of the high level of the first control signal cs1.
  • the turned-on seventh transistor T7 provides the signal of the first power supply terminal VDD to the first electrode of the driving transistor T0.
  • the gate leakage of the driving transistor T0 is reduced, and the gate voltage of the driving transistor T0 can be further kept stable.
  • the seventh transistor T7 is turned on under the control of the low level of the first light-emitting control signal em1
  • the eighth transistor T8 is turned on under the control of the low level of the second light-emitting control signal em2
  • the tenth transistor T10 is turned off under the control of the high level of the fourth control signal cs4
  • the fourth transistor T4 is turned off under the control of the high level of the second control signal cs2
  • the third transistor T3, the sixth transistor T6, the fifth transistor T5 and the ninth transistor T9 are turned off under the control of the high level of the first control signal cs1.
  • the turned-on seventh transistor T7 provides the signal of the first power supply terminal VDD to the first electrode of the driving transistor T0, so that the voltage of the first electrode of the driving transistor T0 is the first power supply voltage Vdd.
  • the turned-on seventh transistor T7 provides the signal of the first power supply terminal VDD to the first electrode of the driving transistor T0.
  • the turned-on eighth transistor T8 connects the second electrode of the driving transistor T0 to the light-emitting device L.
  • the driving transistor T0 generates a driving current Ids for driving the light-emitting device L to emit light, and controls the light-emitting device L to emit light.
  • the driving transistor T0 generates a working current Ids for driving the light-emitting device L to emit light, and Ids satisfies the following formula:
  • the gate leakage of the driving transistor T0 is reduced, and the gate voltage of the driving transistor T0 can be further kept stable.
  • the disclosed embodiment provides some signal timing diagrams of pixel circuits, as shown in Figure 8, which is a modification of the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.
  • the signal timing diagram corresponding to the pixel circuit shown in FIG3 may also be shown in FIG8.
  • em1 represents the first light-emitting control signal of the first light-emitting control signal terminal EM1
  • em2 represents the second light-emitting control signal of the second light-emitting control signal terminal EM2
  • cs1 represents the first control signal of the first control signal terminal CS1
  • cs2 represents the second control signal of the second control signal terminal CS2
  • cs3 represents the third control signal of the third control signal terminal CS3
  • cs4 represents the fourth control signal of the fourth control signal terminal CS4.
  • the first control signal terminal CS1, the second control signal CS2, the third control signal CS3, and the fourth control signal terminal CS4 may be set as different signal terminals.
  • the effective level (such as low level) of the first light-emitting control signal em1 of the first light-emitting control signal terminal EM1 and the effective level (such as low level) of the third control signal cs3 of the third control signal terminal CS3 have an overlapping area
  • the effective level (such as low level) of the second control signal cs2 of the second control signal terminal CS2 appears after the effective level (such as low level) of the third control signal cs3 of the third control signal terminal CS3
  • the effective level (such as low level) of the first control signal cs1 of the first control signal terminal CS1 appears after the effective level (such as low level) of the second control signal cs2 of the second control signal terminal CS2.
  • the voltage of the first power supply terminal can be compensated.
  • the effective level (such as a low level) of the first light-emitting control signal em1 of the first light-emitting control signal terminal EM1 and the effective level (such as a low level) of the third control signal cs3 of the third control signal terminal CS3 have an overlapping area, then the seventh transistor T7, the fifth transistor T5 and the ninth transistor T9 are all turned on within the time period of this overlapping area.
  • a gate driving circuit and a light emitting control circuit may be provided in a non-display area of the base substrate to drive each transistor in the pixel circuit.
  • three gate driving circuits (each gate driving circuit may include a plurality of cascaded shift register units) and two light-emitting control circuits (the light-emitting control circuit may include a plurality of cascaded shift register units) may be provided in the non-display area.
  • the first control signal cs1 of the first control signal terminal CS1 may be input by the first gate driving circuit of the three gate driving circuits.
  • the third control signal cs3 of the third control signal terminal CS3 may be input by the second gate driving circuit of the three gate driving circuits.
  • the second control signal cs2 of the second control signal terminal CS2 and the fourth control signal cs4 of the fourth control signal terminal CS4 may be input by the third gate driving circuit of the three gate driving circuits. Furthermore, the first light-emitting control signal em1 of the first light-emitting control signal terminal EM1 may be input by the first light-emitting control circuit of the two light-emitting control circuits. The second light-emitting control signal em2 of the second light-emitting control signal terminal EM2 may be input by the second light-emitting control circuit of the two light-emitting control circuits.
  • the first control signal cs1 may be a signal input by the nth shift register unit in the first gate driving circuit.
  • the third control signal cs3 may be a signal input by the nth shift register unit in the second gate driving circuit.
  • the fourth control signal cs4 may be a signal input by the n-3th shift register unit in the third gate driving circuit (such as Gate(n-3)), and the second control signal cs2 is a signal input by the nth shift register unit in the third gate driving circuit (such as Gate(n)).
  • the first light-emitting control signal em1 of the first light-emitting control signal terminal EM1 may be a signal input by the nth shift register unit in the first light-emitting control circuit.
  • the second light-emitting control signal em2 of the second light-emitting control signal terminal EM2 may be a signal input by the nth shift register unit in the second light-emitting control circuit.
  • em1 represents the first light-emitting control signal of the first light-emitting control signal terminal EM1
  • em2 represents the second light-emitting control signal of the second light-emitting control signal terminal EM2
  • cs1 represents the first control signal of the first control signal terminal CS1
  • cs2 represents the second control signal of the second control signal terminal CS2
  • cs3 represents the third control signal of the third control signal terminal CS3
  • cs4 represents the fourth control signal of the fourth control signal terminal CS4.
  • the seventh transistor T7 is turned off under the control of the high level of the first light-emitting control signal em1
  • the eighth transistor T8 is turned off under the control of the high level of the second light-emitting control signal em2
  • the third transistor T3 and the sixth transistor T6 are turned off under the control of the high level of the first control signal cs1
  • the tenth transistor T10 is turned on under the control of the low level of the fourth control signal cs4
  • the fourth transistor T4 is turned off under the control of the high level of the second control signal cs2
  • the fifth transistor T5 and the ninth transistor T9 are turned off under the control of the high level of the third control signal cs3.
  • the seventh transistor T7 is turned on under the control of the low level of the first light-emitting control signal em1
  • the eighth transistor T8 is turned off under the control of the high level of the second light-emitting control signal em2
  • the third transistor T3 and the sixth transistor T6 are turned off under the control of the high level of the first control signal cs1
  • the tenth transistor T10 is turned off under the control of the high level of the fourth control signal cs4
  • the fourth transistor T4 is turned off under the control of the high level of the second control signal cs2
  • the fifth transistor T5 and the ninth transistor T9 are turned on under the control of the low level of the third control signal cs3.
  • the turned-on seventh transistor T7 provides the signal of the first power supply terminal VDD to the first electrode of the driving transistor T0.
  • the seventh transistor T7 is turned off under the control of the high level of the first light-emitting control signal em1
  • the eighth transistor T8 is turned off under the control of the high level of the second light-emitting control signal em2
  • the third transistor T3 and the sixth transistor T6 are turned off under the control of the high level of the first control signal cs1
  • the tenth transistor T10 is turned off under the control of the high level of the fourth control signal cs4
  • the fourth transistor T4 is turned on under the control of the low level of the second control signal cs2
  • the fifth transistor T5 and the ninth transistor T9 are turned off under the control of the high level of the third control signal cs3.
  • the turned-on fourth transistor T4 inputs the data voltage Vda of the data signal terminal DA to the first node N1. Then VN1 changes from Vref1 to Vda, and VN2 will also change with the change of VN1, and VN1 changes from Vdd+Vth to Furthermore, due to the effect of the signal at the leakage regulating signal terminal VS, the gate leakage of the driving transistor T0 is reduced, and the gate voltage of the driving transistor T0 can be further kept stable.
  • the seventh transistor T7 is turned off under the control of the high level of the first light-emitting control signal em1
  • the eighth transistor T8 is turned off under the control of the high level of the second light-emitting control signal em2
  • the third transistor T3 and the sixth transistor T6 are turned on under the control of the low level of the first control signal cs1
  • the tenth transistor T10 is turned off under the control of the high level of the fourth control signal cs4
  • the fourth transistor T4 is turned on under the control of the low level of the second control signal cs2
  • the fifth transistor T5 and the ninth transistor T9 are turned off under the control of the high level of the third control signal cs3.
  • the turned-on third transistor T3 provides the signal of the first reference voltage signal terminal VREF1 to the first electrode of the driving transistor T0, and resets the first electrode of the driving transistor T0.
  • the turned-on sixth transistor T6 provides the signal of the first initialization signal terminal VINIT1 to the light-emitting device L, and resets the light-emitting device L.
  • the seventh transistor T7 is turned on under the control of the low level of the first light-emitting control signal em1
  • the eighth transistor T8 is turned on under the control of the low level of the second light-emitting control signal em2
  • the third transistor T3 and the sixth transistor T6 are turned off under the control of the high level of the first control signal cs1
  • the tenth transistor T10 is turned off under the control of the high level of the fourth control signal cs4
  • the fourth transistor T4 is turned off under the control of the high level of the second control signal cs2
  • the fifth transistor T5 and the ninth transistor T9 are turned off under the control of the high level of the third control signal cs3.
  • the turned-on seventh transistor T7 provides the signal of the first power supply terminal VDD to the first electrode of the driving transistor T0, so that the voltage of the first electrode of the driving transistor T0 is the first power supply voltage Vdd.
  • the turned-on seventh transistor T7 provides the signal of the first power supply terminal VDD to the first electrode of the driving transistor T0.
  • the turned-on eighth transistor T8 connects the second electrode of the driving transistor T0 to the light-emitting device L.
  • the driving transistor T0 generates a driving current Ids for driving the light-emitting device L to emit light, and controls the light-emitting device L to emit light.
  • the driving transistor T0 generates a working current Ids for driving the light emitting device L to emit light, and Ids satisfies the following formula:
  • the gate leakage of the driving transistor T0 is reduced, and the gate voltage of the driving transistor T0 can be further kept stable.
  • the voltage of the first power supply terminal can be compensated in this way.
  • the disclosed embodiment provides some signal timing diagrams of pixel circuits, as shown in Figure 9, which is a modification of the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.
  • the signal timing diagram corresponding to the pixel circuit shown in FIG3 may also be shown in FIG9.
  • em1 represents the first light-emitting control signal of the first light-emitting control signal terminal EM1
  • em2 represents the second light-emitting control signal of the second light-emitting control signal terminal EM2
  • cs1 represents the first control signal of the first control signal terminal CS1
  • cs2 represents the second control signal of the second control signal terminal CS2
  • cs3 represents the third control signal of the third control signal terminal CS3
  • cs4 represents the fourth control signal of the fourth control signal terminal CS4.
  • the first control signal terminal CS1, the second control signal CS2, the third control signal CS3, and the fourth control signal terminal CS4 may be set as different signal terminals.
  • the effective level (such as low level) of the first light-emitting control signal em1 of the first light-emitting control signal terminal EM1 and the effective level (such as low level) of the third control signal cs3 of the third control signal terminal CS3 have an overlapping area
  • the effective level (such as low level) of the second control signal cs2 of the second control signal terminal CS2 appears after the effective level (such as low level) of the third control signal cs3 of the third control signal terminal CS3
  • the effective level (such as low level) of the first control signal cs1 of the first control signal terminal CS1 appears after the effective level (such as low level) of the second control signal cs2 of the second control signal terminal CS2.
  • the voltage of the first power supply terminal can be compensated.
  • the effective level (such as a low level) of the first light-emitting control signal em1 of the first light-emitting control signal terminal EM1 and the effective level (such as a low level) of the third control signal cs3 of the third control signal terminal CS3 have an overlapping area, then the seventh transistor T7, the fifth transistor T5 and the ninth transistor T9 are all turned on within the time period of this overlapping area.
  • two gate driving circuits (each gate driving circuit may include a plurality of cascaded shift register units) and two light-emitting control circuits (the light-emitting control circuit may include a plurality of cascaded shift register units) may be provided in the non-display area.
  • the third control signal cs3 of the third control signal terminal CS3 can be input by the first gate driving circuit of the two gate driving circuits.
  • the first control signal cs1 of the first control signal terminal CS1, the second control signal cs2 of the second control signal terminal CS2, and the fourth control signal cs4 of the fourth control signal terminal CS4 can be input by the second gate driving circuit of the two gate driving circuits.
  • the first light-emitting control signal em1 of the first light-emitting control signal terminal EM1 can be input by the first light-emitting control circuit of the two light-emitting control circuits.
  • the second light-emitting control signal em2 of the second light-emitting control signal terminal EM2 can be input by the second light-emitting control circuit of the two light-emitting control circuits.
  • the third control signal cs3 may be a signal input by the nth shift register unit in the first gate driving circuit.
  • the fourth control signal cs4 may be a signal input by the n-3th shift register unit in the second gate driving circuit (such as Gate(n-3))
  • the second control signal cs2 may be a signal input by the nth shift register unit in the second gate driving circuit (such as Gate(n))
  • the first control signal cs1 may be a signal input by the n+2th shift register unit in the second gate driving circuit (such as Gate(n+2)).
  • the first light-emitting control signal em1 of the first light-emitting control signal terminal EM1 may be a signal input by the nth shift register unit in the first light-emitting control circuit.
  • the second light-emitting control signal em2 of the second light-emitting control signal terminal EM2 may be a signal input by the nth shift register unit in the second light-emitting control circuit.
  • the disclosed embodiment provides some signal timing diagrams of pixel circuits, as shown in Figure 10, which is a modification of the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.
  • the signal timing diagram corresponding to the pixel circuit shown in FIG3 may also be shown in FIG10.
  • em1 represents the first light-emitting control signal of the first light-emitting control signal terminal EM1
  • em2 represents the second light-emitting control signal of the second light-emitting control signal terminal EM2
  • cs1 represents the first control signal of the first control signal terminal CS1
  • cs2 represents the second control signal of the second control signal terminal CS2
  • cs3 represents the third control signal of the third control signal terminal CS3
  • cs4 represents the fourth control signal of the fourth control signal terminal CS4.
  • the first control signal terminal CS1, the second control signal CS2, the third control signal CS3, and the fourth control signal terminal CS4 may be set as different signal terminals.
  • the effective level (such as low level) of the first light-emitting control signal em1 of the first light-emitting control signal terminal EM1 and the effective level (such as low level) of the third control signal cs3 of the third control signal terminal CS3 have an overlapping area
  • the effective level (such as low level) of the second control signal cs2 of the second control signal terminal CS2 appears after the effective level (such as low level) of the third control signal cs3 of the third control signal terminal CS3
  • the effective level (such as low level) of the first control signal cs1 of the first control signal terminal CS1 appears after the effective level (such as low level) of the second control signal cs2 of the second control signal terminal CS2.
  • the voltage of the first power supply terminal can be compensated.
  • the effective level (such as a low level) of the first light-emitting control signal em1 of the first light-emitting control signal terminal EM1 and the effective level (such as a low level) of the third control signal cs3 of the third control signal terminal CS3 have an overlapping area, then the seventh transistor T7, the fifth transistor T5 and the ninth transistor T9 are all turned on within the time period of this overlapping area.
  • one gate driving circuit (each gate driving circuit may include multiple cascaded shift register units) and two light-emitting control circuits (the light-emitting control circuit may include multiple cascaded shift register units) may be provided in the non-display area.
  • This can save the number of gate driving circuits and reduce the occupied space.
  • the first control signal cs1 of the first control signal terminal CS1, the second control signal cs2 of the second control signal terminal CS2, the third control signal cs3 of the third control signal terminal CS3, and the fourth control signal cs4 of the fourth control signal terminal CS4 can be input by the gate driving circuit.
  • first light-emitting control signal em1 of the first light-emitting control signal terminal EM1 can be input by the first of the two light-emitting control circuits.
  • the second light-emitting control signal em2 of the second light-emitting control signal terminal EM2 can be input by the second of the two light-emitting control circuits.
  • the pixel circuits in the nth row of sub-pixels receive the first control signal cs1 to the fourth control signal cs4.
  • the fourth control signal cs4 may be a signal input to the n-3th shift register unit in the gate drive circuit (such as Gate(n-3)), the third control signal cs3 may be a signal input to the n-2th shift register unit in the gate drive circuit (such as Gate(n-2)), the second control signal cs2 may be a signal input to the nth shift register unit in the gate drive circuit (such as Gate(n)), and the first control signal cs1 may be a signal input to the n+2th shift register unit in the gate drive circuit (such as Gate(n+2)).
  • the first light-emitting control signal em1 of the first light-emitting control signal terminal EM1 may be a signal input to the nth shift register unit in the first light-emitting control circuit.
  • the second light-emitting control signal em2 of the second light-emitting control signal terminal EM2 may be a signal input to the nth shift register unit in the second light-emitting control circuit.
  • the first control circuit 10 may also include: a voltage stabilizing capacitor CFT, wherein a first electrode of the voltage stabilizing capacitor CFT is coupled to the gate of the driving transistor T0, and a second electrode of the voltage stabilizing capacitor CFT is coupled to the leakage adjustment signal terminal VS.
  • a voltage stabilizing capacitor CFT wherein a first electrode of the voltage stabilizing capacitor CFT is coupled to the gate of the driving transistor T0, and a second electrode of the voltage stabilizing capacitor CFT is coupled to the leakage adjustment signal terminal VS.
  • the implementation of the signal at the leakage adjustment signal terminal VS may be set with reference to the above description, which will not be elaborated herein.
  • the signal timing diagram corresponding to the pixel circuit shown in Figure 11 may be shown in Figure 4a or Figures 7 to 10.
  • the driving process of the pixel circuit provided by the embodiment of the present disclosure may refer to the above description and will not be repeated here.
  • the disclosed embodiment provides some pixel circuits, as shown in Figure 12, which are modified from the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.
  • the first control circuit 10 may also include: a compensation transistor MFT, wherein the first electrode and the second electrode of the compensation transistor MFT are coupled to the leakage adjustment signal terminal VS, and the gate of the compensation transistor MFT is coupled to the gate of the driving transistor T0.
  • a compensation transistor MFT wherein the first electrode and the second electrode of the compensation transistor MFT are coupled to the leakage adjustment signal terminal VS, and the gate of the compensation transistor MFT is coupled to the gate of the driving transistor T0.
  • the gate of the compensation transistor may be coupled to the leakage adjustment signal terminal, and the first electrode and the second electrode of the compensation transistor may be coupled to the gate of the driving transistor, which is not limited here.
  • the implementation of the signal at the leakage adjustment signal terminal VS may be set with reference to the above description, which will not be elaborated herein.
  • the signal timing diagram corresponding to the pixel circuit shown in Figure 12 may be shown in Figure 4a or Figures 7 to 10.
  • the driving process of the pixel circuit provided by the embodiment of the present disclosure may refer to the above description and will not be repeated here.
  • the embodiment of the present disclosure also provides a display device, including the above pixel circuit provided by the embodiment of the present disclosure.
  • the principle of solving the problem by the display device is similar to that of the above pixel circuit, so the implementation of the display device can refer to the implementation of the above pixel circuit, and the repeated parts will not be repeated here.
  • the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.
  • Other essential components of the display device should be understood by ordinary technicians in the field, and will not be elaborated here, nor should they be used as limitations to the present disclosure.

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Abstract

本公开实施例提供的像素电路、显示装置及驱动方法，其中，像素电路，包括：发光器件；驱动晶体管，与发光器件耦接，被配置为根据数据电压产生驱动发光器件的工作电流；第一控制电路，与驱动晶体管的栅极耦接，被配置为基于漏电调节信号端的信号，降低驱动晶体管的栅极漏电；第二控制电路，分别与驱动晶体管和发光器件耦接，被配置为对驱动晶体管与发光器件进行复位，控制数据电压输入驱动晶体管的栅极以及控制驱动晶体管产生工作电流，驱动发光器件发光。

Description

像素电路、显示装置及驱动方法 技术领域
本公开涉及显示技术领域，特别涉及像素电路、显示装置及驱动方法。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)、量子点发光二极管(Quantum Dot Light Emitting Diodes，QLED)、微型发光二极管(Micro Light Emitting Diode，Micro LED)等电致发光二极管具有自发光、低能耗等优点，是当今电致发光显示装置应用研究领域的热点之一。一般电致发光显示装置中采用像素电路来驱动电致发光二极管发光。
发明内容
本公开实施例提供的像素电路，包括：
发光器件；
驱动晶体管，与所述发光器件耦接，被配置为根据数据电压产生驱动所述发光器件的工作电流；
第一控制电路，与所述驱动晶体管的栅极耦接，被配置为基于漏电调节信号端的信号，降低所述驱动晶体管的栅极漏电；
第二控制电路，分别与所述驱动晶体管和所述发光器件耦接，被配置为对所述驱动晶体管与所述发光器件进行复位，控制所述数据电压输入所述驱动晶体管的栅极以及控制所述驱动晶体管产生所述工作电流，驱动所述发光器件发光。
在一些可能的实施方式中，所述第二控制电路包括：第一控制子电路；所述第一控制子电路被配置为响应于所述第一控制信号端的信号，将第一初始化信号端的信号提供给所述发光器件，以及响应于第一发光控制信号端的信号，将第一电源端与所述驱动晶体管的第一极导通，以及响应于第二发光 控制信号端的信号，将所述驱动晶体管的第二极与所述发光器件导通，以及响应于所述第三控制信号端的信号，将所述驱动晶体管的栅极与所述驱动晶体管的第二极导通，以及响应于第四控制信号端的信号，将第二初始化信号端的信号提供给所述驱动晶体管的栅极。
在一些可能的实施方式中，所述第二控制电路还包括：所述第二控制子电路被配置为响应于第二控制信号端的信号，将数据信号端的数据电压提供给第一节点；以及响应于第三控制信号端的信号，将第二参考电压信号端的信号提供给所述第一节点。
在一些可能的实施方式中，所述第二控制电路还包括：第三控制子电路；所述第三控制子电路被配置为响应于第一控制信号端的信号，将第一参考电压信号端的信号提供给所述驱动晶体管的第一极。
在一些可能的实施方式中，在一个显示帧中，所述第一控制信号端的有效电平在所述第二控制信号端的有效电平之前出现，所述第一控制信号端的有效电平与所述第三控制信号端的有效电平具有交叠区域。
在一些可能的实施方式中，所述第一控制信号端与所述第三控制信号端接收同一信号；在一个显示帧中，所述第一控制信号端的有效电平在所述第二控制信号端的有效电平之前出现。
在一些可能的实施方式中，在一个显示帧中，所述第一发光控制信号端的有效电平与所述第三控制信号端的有效电平具有交叠区域，所述第二控制信号端的有效电平在所述第三控制信号端的有效电平之后出现，所述第一控制信号端的有效电平在所述第二控制信号端的有效电平之后出现。
在一些可能的实施方式中，所述第一控制电路包括：第一晶体管和第二晶体管；
所述第一晶体管的栅极与所述漏电调节信号端耦接，所述第一晶体管的第一极浮接，所述第一晶体管的第二极与所述驱动晶体管的栅极耦接；
所述第二晶体管的栅极与所述漏电调节信号端耦接，所述第二晶体管的第一极浮接，所述第二晶体管的第二极与所述驱动晶体管的栅极耦接。
在一些可能的实施方式中，所述第一控制电路包括：稳压电容；所述稳压电容的第一电极与所述驱动晶体管的栅极耦接，所述稳压电容的第二电极与所述漏电调节信号端耦接。
在一些可能的实施方式中，所述第一控制电路包括：补偿晶体管；
所述补偿晶体管的第一极和第二极与所述漏电调节信号端耦接，所述补偿晶体管的栅极与所述驱动晶体管的栅极耦接；
或者，所述补偿晶体管的栅极与所述漏电调节信号端耦接，所述补偿晶体管的第一极和第二极与所述驱动晶体管的栅极耦接。
在一些可能的实施方式中，在同一个显示帧中，在对所述驱动晶体管的栅极进行复位时，所述漏电调节信号端的信号的电压为第一电压，在所述数据电压输入所述驱动晶体管的栅极时，所述漏电调节信号端的信号的电压为第二电压；
所述第二电压不小于所述第一电压。
在一些可能的实施方式中，在不同显示帧中，所述第一电压相同；
在不同显示帧中，所述第二电压大于第三电压；所述第三电压为Vda-Vth；Vda代表所述数据电压，Vth代表所述驱动晶体管的阈值电压。
在一些可能的实施方式中，在不同显示帧中，所述第二电压相同；
或者，在不同显示帧中，所述第二电压随着所述第三电压的增加而增加。
在一些可能的实施方式中，所述第三控制子电路包括：第三晶体管；
所述第三晶体管的栅极与所述第一控制信号端耦接，所述第三晶体管的第一极与所述驱动晶体管的第一极耦接，所述第三晶体管的第二极与所述第一参考电压信号端耦接。
在一些可能的实施方式中，所述第二控制子电路包括：第四晶体管、第五晶体管以及第一电容；
所述第四晶体管的栅极与所述第二控制信号端耦接，所述第四晶体管的第一极与所述数据信号端耦接，所述第四晶体管的第二极与所述第一节点耦接；
所述第五晶体管的栅极与所述第三控制信号端耦接，所述第五晶体管的第一极与所述第一节点耦接，所述第五晶体管的第二极与所述第二参考电压信号端耦接；
所述第一电容的第一电极与所述第一电源端耦接，所述第一电容的第二电极与所述第一节点耦接。
在一些可能的实施方式中，所述第一控制子电路包括：第六晶体管、第七晶体管、第八晶体管、第九晶体管、第十晶体管以及第二电容；
所述第六晶体管的栅极与所述第一控制信号端耦接，所述第六晶体管的第一极与所述发光器件耦接，所述第六晶体管的第二极与所述第一初始化信号端耦接；
所述第七晶体管的栅极与所述第一发光控制信号端耦接，所述第七晶体管的第一极与所述第一电源端耦接，所述第七晶体管的第二极与所述驱动晶体管的第一极耦接；
所述第八晶体管的栅极与所述第二发光控制信号端耦接，所述第八晶体管的第一极与所述驱动晶体管的第二极耦接，所述第八晶体管的第二极与所述发光器件耦接；
所述第九晶体管的栅极与所述第三控制信号端耦接，所述第九晶体管的第一极与所述驱动晶体管的栅极耦接，所述第九晶体管的第二极与所述驱动晶体管的第二极耦接；
所述第十晶体管的栅极与所述第四控制信号端耦接，所述第十晶体管的第一极与所述驱动晶体管的栅极耦接，所述第十晶体管的第二极与所述第二初始化信号端耦接；
所述第二电容的第一电极与所述第一节点耦接，所述第二电容的第二电极与所述驱动晶体管的栅极耦接。
本公开实施例还提供了显示装置，包括上述的像素电路。
本公开实施例还提供了用于上述的像素电路的驱动方法，包括：
数据写入阶段，所述第一控制电路基于所述漏电调节信号端的信号，降 低所述驱动晶体管的栅极漏电；所述第二控制电路控制所述数据电压输入所述驱动晶体管的栅极；
发光阶段，所述第一控制电路基于所述漏电调节信号端的信号，降低所述驱动晶体管的栅极漏电；所述第二控制电路控制所述驱动晶体管产生所述工作电流，驱动所述发光器件发光。
附图说明
图1为本公开实施例提供的一些像素电路的结构示意图；
图2为本公开实施例提供的另一些像素电路的结构示意图；
图3为本公开实施例提供的又一些像素电路的结构示意图；
图4a为本公开实施例提供的一些信号时序图；
图4b为本公开实施例提供的另一些信号时序图；
图5为本公开实施例提供的一些驱动方法的流程图；
图6为本公开实施例提供的又一些像素电路的结构示意图；
图7为本公开实施例提供的又一些信号时序图；
图8为本公开实施例提供的又一些信号时序图；
图9为本公开实施例提供的又一些信号时序图；
图10为本公开实施例提供的又一些信号时序图；
图11为本公开实施例提供的又一些像素电路的结构示意图；
图12为本公开实施例提供的又一些像素电路的结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所 获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本发明内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
在本公开一些实施例中，本公开实施例提供的显示装置可以包括显示面板。显示面板可以包括衬底基板。其中，衬底基板可以包括显示区域和非显示区域(即衬底基板中除显示区域之外的区域)。其中，显示区域可以包括多个阵列排布的像素单元。示例性的，每个像素单元包括同一种颜色的子像素或多种不同颜色的子像素。例如，像素单元可以包括红色子像素，绿色子像素以及蓝色子像素，这样可以通过红绿蓝进行混色，以实现彩色显示。或者，像素单元也可以包括红色子像素，绿色子像素、蓝色子像素以及白色子像素，这样可以通过红绿蓝白进行混色，以实现彩色显示。当然，在实际应用中，像素单元中的子像素的发光颜色可以根据实际应用环境来设计确定，在此不作限定。下面以像素单元包括红色子像素，绿色子像素以及蓝色子像素为例进行说明。
在本公开一些实施例中，每一个子像素中可以包括像素电路，像素电路可以包括驱动晶体管和发光器件，以控制发光器件发光，从而使显示面板实现画面显示的功能。但是在低频驱动情况下，由于驱动晶体管的栅极存在漏电和迟滞问题，在较长工作时间后，导致驱动晶体管的栅极的电压逐渐变化，从而显示的亮度也会随之变化。当不同驱动频率切换时，会出现低灰阶闪烁 的问题。并且，由于工艺、老化等原因会造成驱动晶体管的阈值电压Vth漂移，对产生的驱动电流造成影响，影响显示的问题。
本公开实施例提供的像素电路，如图1所示，包括：发光器件L、驱动晶体管T0、第一控制电路10以及第二控制电路20；
其中，驱动晶体管T0与发光器件L耦接，被配置为根据数据电压产生驱动发光器件L的工作电流；
第一控制电路10与驱动晶体管T0的栅极耦接，被配置为基于漏电调节信号端VS的信号，降低驱动晶体管T0的栅极漏电；
第二控制电路20分别与驱动晶体管T0和发光器件L耦接，被配置为对驱动晶体管T0与发光器件L进行复位，控制数据电压输入驱动晶体管T0的栅极以及控制驱动晶体管T0产生工作电流，驱动发光器件L发光。
本公开实施例提供的像素电路，通过设置与驱动晶体管的栅极耦接的第一控制电路，可以基于漏电调节信号端的信号，降低驱动晶体管的栅极漏电，从而实现改善低灰阶显示时的闪烁(Flicker)问题。以及通过设置第二控制电路，在驱动发光器件发光之前，对驱动晶体管和发光器件进行复位，控制数据电压输入驱动晶体管的栅极以及控制驱动晶体管产生工作电流，驱动发光器件发光，改善驱动晶体管的迟滞效应，从而实现改善高灰阶显示时的闪烁(Flicker)问题。
本公开实施例提供的像素电路可以应用于不同刷新频率驱动的显示面板中。由于本公开实施例提供的像素电路可以兼容改善高低灰阶显示时的闪烁(Flicker)问题，在不同刷新频率切换时，改善出现的闪烁等的问题，提高产品的显示效果。并且，为了降低功耗，本公开实施例提供的像素电路可以应用于较低刷新频率(例如，1Hz、30Hz等)驱动的情况下。以及，为了提高显示效果，本公开实施例提供的像素电路可以应用于较高刷新频率(例如，60Hz、90Hz、120Hz、240Hz等)驱动的情况下。
在本公开一些实施例中，如图1与图2所示，第二控制电路20包括：第一控制子电路201、第二控制子电路202以及第三控制子电路203；
第一控制子电路201被配置为响应于第一控制信号端CS1的信号，将第一初始化信号端VINIT1的信号提供给发光器件L，以及响应于第一发光控制信号端EM1的信号，将第一电源端VDD与驱动晶体管T0的第一极导通，以及响应于第二发光控制信号端EM2的信号，将驱动晶体管T0的第二极与发光器件L导通，以及响应于第三控制信号端CS3的信号，将驱动晶体管T0的栅极与驱动晶体管T0的第二极导通，以及响应于第四控制信号端CS4的信号，将第二初始化信号端VINIT2的信号提供给驱动晶体管T0的栅极；
第二控制子电路202被配置为响应于第二控制信号端CS2的信号，将数据信号端DA的数据电压Vda提供给第一节点N1；以及响应于第三控制信号端CS3的信号，将第二参考电压信号端VREF2的信号提供给第一节点N1；
第三控制子电路203被配置为响应于第一控制信号端CS1的信号，将第一参考电压信号端VREF1的信号提供给驱动晶体管T0的第一极。
在本公开一些实施例中，如图2所示，发光器件L的第一电极可以与第一控制子电路201耦接，发光器件L的第二电极可以与第二电源端VSS耦接。并且，发光器件L的第一电极可以为其阳极，第二电极为其阴极。示例性地，发光器件L可以为电致发光二极管。例如，发光器件L可以包括：微型发光二极管(Micro Light Emitting Diode，Micro LED)、有机电致发光二极管(Organic Light Emitting Diode，OLED)以及量子点发光二极管(Quantum Dot Light Emitting Diodes，QLED)中的至少一种。在实际应用中，可以根据实际应用环境来设计确定发光器件L的具体结构，在此不作限定。
在本公开一些实施例中，第一电源端VDD可以被配置为加载恒定的第一电源电压，并且第一电源电压一般为正值。以及，第二电源端VSS可以加载恒定的第二电源电压，并且第二电源电压一般可以为接地电压或为负值。在实际应用中，第一电源电压和第二电源电压的具体数值可以根据实际应用环境来设计确定，在此不作限定。
在本公开一些实施例中，如图1和图2所示，驱动晶体管T0可以设置为P型晶体管；其中，驱动晶体管T0的第一极可以为其源极，驱动晶体管T0 的第二极可以为其漏极，并且该驱动晶体管T0处于饱和状态时，电流由驱动晶体管T0的源极流向其漏极。当然，驱动晶体管T0也可以设置为N型晶体管，在此不作限定。
在本公开一些实施例中，如图3所示，第一控制电路10包括：第一晶体管T1和第二晶体管T2。其中，第一晶体管T1的栅极与漏电调节信号端VS耦接，第一晶体管T1的第一极浮接，第一晶体管T1的第二极与驱动晶体管T0的栅极耦接。第二晶体管T2的栅极与漏电调节信号端VS耦接，第二晶体管T2的第一极浮接，第二晶体管T2的第二极与驱动晶体管T0的栅极耦接。这样通过设置第一晶体管T1和第二晶体管T2，并使第一晶体管T1和第二晶体管T2均与漏电调节信号端VS连接，在漏电调节信号端VS加载电压时，可以改善驱动晶体管T0的栅极的漏电。
示例性地，第一晶体管T1和第二晶体管T2可以设置为P型晶体管。当然，在实际应用中，第一晶体管和第二晶体管也可以设置为N型晶体管，在此不作限定。
在一些示例中，在同一个显示帧中，在对驱动晶体管T0的栅极进行复位时，漏电调节信号端VS的信号的电压为第一电压Vvs1，在数据电压Vda输入驱动晶体管T0的栅极时，漏电调节信号端VS的信号的电压为第二电压Vvs2。可以使第二电压Vvs2等于第一电压Vvs1。这样可以使漏电调节信号端VS的信号vs的电压在一个显示帧中是固定电压。例如，如图4a所示，漏电调节信号端VS的信号vs的电压为第二电压Vvs2。
示例性地，在不同显示帧中，可以使第一电压Vvs1相同，从而可以不用频繁的调整第一电压Vvs1，降低功耗。
示例性地，在不同显示帧中，可以使第二电压Vvs2大于第三电压Vvs3。其中，第三电压Vvs3为Vda-Vth，Vda代表所数据电压，Vth代表驱动晶体管的阈值电压。例如，Vda-Vth大约为0～1V，则第二电压Vvs2可以设置为2V。可选地，Vda可为较大灰阶或最大灰阶对应的数据电压。
示例性地，在不同显示帧中，可以使第二电压Vvs2相同，从而可以不用 频繁的调整第二电压Vvs2，降低功耗。基于此，在不同显示帧中，可以使漏电调节信号端VS的信号vs的电压为固定电压，从而可以不用频繁的调整漏电调节信号端VS的信号vs的电压，降低功耗。
示例性地，在不同显示帧中，也可以使第二电压Vvs2随着第三电压Vvs3的增加而增加，从而可以随着第三电压Vvs3来调整第二电压Vvs2，进一步降低漏电。基于此，在不同显示帧中，可以使漏电调节信号端VS的信号vs的电压为交变电压，进一步降低漏电。
在另一些示例中，示例性地，在同一个显示帧中，在对驱动晶体管T0的栅极进行复位时，漏电调节信号端VS的信号vs的电压为第一电压Vvs1，在数据电压输入驱动晶体管T0的栅极时，漏电调节信号端VS的信号vs的电压为第二电压Vvs2。可以使第二电压Vvs2大于第一电压Vvs1。这样可以使漏电调节信号端VS的信号vs的电压在一个显示帧中是交变电压。例如，如图4b所示，漏电调节信号端VS的信号vs的电压具有第二电压Vvs2和第一电压Vvs1。
示例性地，在不同显示帧中，可以使第一电压Vvs1相同，从而可以不用频繁的调整第一电压Vvs1，降低功耗。
示例性地，在不同显示帧中，可以使第二电压Vvs2大于第三电压Vvs3。其中，第三电压Vvs3为Vda-Vth，Vda代表所数据电压，Vth代表驱动晶体管的阈值电压。例如，Vda-Vth大约为0～1V，则第二电压Vvs2可以设置为2V。可选地，Vda可为较大灰阶或最大灰阶对应的数据电压。
示例性，在不同显示帧中，可以使第二电压Vvs2相同，从而可以不用频繁的调整第二电压Vvs2，降低功耗。
示例性地，在不同显示帧中，也可以使第二电压Vvs2随着第三电压Vvs3的增加而增加，从而可以随着第三电压Vvs3来调整第二电压Vvs2，进一步降低漏电。
在本公开一些实施例中，如图3所示，第三控制子电路203包括：第三晶体管T3；第三晶体管T3的栅极与第一控制信号端CS1耦接，第三晶体管 T3的第一极与驱动晶体管T0的第一极耦接，第三晶体管T3的第二极与第一参考电压信号端VREF1耦接。
示例性地，第三晶体管T3在第一控制信号端CS1的第一控制信号的有效电平的控制下导通，在第一控制信号的无效电平的控制下截止。可选地，第三晶体管T3可以设置为P型晶体管，则第一控制信号的有效电平可以为低电平，第一控制信号的无效电平可以为高电平。或者，第三晶体管T3也可以设置为N型晶体管，则第一控制信号的有效电平可以为高电平，第一控制信号的无效电平可以为低电平。
在本公开一些实施例中，如图3所示，第二控制子电路202包括：第四晶体管T4、第五晶体管T5以及第一电容C1；其中，第四晶体管T4的栅极与第二控制信号端CS2耦接，第四晶体管T4的第一极与数据信号端DA耦接，第四晶体管T4的第二极与第一节点N1耦接；
第五晶体管T5的栅极与第三控制信号端CS3耦接，第五晶体管T5的第一极与第一节点N1耦接，第五晶体管T5的第二极与第二参考电压信号端VREF2耦接；
第一电容C1的第一电极与第一电源端VDD耦接，第一电容C1的第二电极与第一节点N1耦接。
示例性地，第四晶体管T4在第二控制信号端CS2的第二控制信号的有效电平的控制下导通，在第二控制信号的无效电平的控制下截止。可选地，第四晶体管T4可以设置为P型晶体管，则第二控制信号的有效电平可以为低电平，第二控制信号的无效电平可以为高电平。或者，第四晶体管T4也可以设置为N型晶体管，则第二控制信号的有效电平可以为高电平，第二控制信号的无效电平可以为低电平。
示例性地，第五晶体管T5在第三控制信号端CS3的第三控制信号的有效电平的控制下导通，在第三控制信号的无效电平的控制下截止。可选地，第五晶体管T5可以设置为P型晶体管，则第三控制信号的有效电平可以为低电平，第三控制信号的无效电平可以为高电平。或者，第五晶体管T5也可以设 置为N型晶体管，则第三控制信号的有效电平可以为高电平，第三控制信号的无效电平可以为低电平。
在本公开一些实施例中，如图3所示，第一控制子电路201包括：第六晶体管T6、第七晶体管T7、第八晶体管T8、第九晶体管T9、第十晶体管T10以及第二电容C2；其中，第六晶体管T6的栅极与第一控制信号端CS1耦接，第六晶体管T6的第一极与发光器件L耦接，第六晶体管T6的第二极与第一初始化信号端VINIT1耦接；
第七晶体管T7的栅极与第一发光控制信号端EM1耦接，第七晶体管T7的第一极与第一电源端VDD耦接，第七晶体管T7的第二极与驱动晶体管T0的第一极耦接；
第八晶体管T8的栅极与第二发光控制信号端EM2耦接，第八晶体管T8的第一极与驱动晶体管T0的第二极耦接，第八晶体管T8的第二极与发光器件L耦接；
第九晶体管T9的栅极与第三控制信号端CS3耦接，第九晶体管T9的第一极与驱动晶体管T0的栅极耦接，第九晶体管T9的第二极与驱动晶体管T0的第二极耦接；
第十晶体管T10的栅极与第四控制信号端CS4耦接，第十晶体管T10的第一极与驱动晶体管T0的栅极耦接，第十晶体管T10的第二极与第二初始化信号端VINIT2耦接；
第二电容C2的第一电极与第一节点N1耦接，第二电容C2的第二电极与驱动晶体管T0的栅极耦接。
示例性地，第六晶体管T6在第一控制信号端CS1的第一控制信号的有效电平的控制下导通，在第一控制信号的无效电平的控制下截止。可选地，第六晶体管T6可以设置为P型晶体管，则第一控制信号的有效电平可以为低电平，第一控制信号的无效电平可以为高电平。或者，第六晶体管T6也可以设置为N型晶体管，则第一控制信号的有效电平可以为高电平，第一控制信号的无效电平可以为低电平。
示例性地，第七晶体管T7在第一发光控制信号端EM1的第一发光控制信号的有效电平的控制下导通，在第一发光控制信号的无效电平的控制下截止。可选地，第七晶体管T7可以设置为P型晶体管，则第一发光控制信号的有效电平可以为低电平，第一发光控制信号的无效电平可以为高电平。或者，第七晶体管T7也可以设置为N型晶体管，则第一发光控制信号的有效电平可以为高电平，第一发光控制信号的无效电平可以为低电平。
示例性地，第八晶体管T8在第二发光控制信号端EM2的第二发光控制信号的有效电平的控制下导通，在第二发光控制信号的无效电平的控制下截止。可选地，第八晶体管T8可以设置为P型晶体管，则第二发光控制信号的有效电平可以为低电平，第二发光控制信号的无效电平可以为高电平。或者，第八晶体管T8也可以设置为N型晶体管，则第二发光控制信号的有效电平可以为高电平，第二发光控制信号的无效电平可以为低电平。
示例性地，第九晶体管T9在第三控制信号端CS3的第三控制信号的有效电平的控制下导通，在第三控制信号的无效电平的控制下截止。可选地，第九晶体管T9可以设置为P型晶体管，则第三控制信号的有效电平可以为低电平，第三控制信号的无效电平可以为高电平。或者，第九晶体管T9也可以设置为N型晶体管，则第三控制信号的有效电平可以为高电平，第三控制信号的无效电平可以为低电平。
示例性地，第十晶体管T10在第四控制信号端CS4的第四控制信号的有效电平的控制下导通，在第四控制信号的无效电平的控制下截止。可选地，第十晶体管T10可以设置为P型晶体管，则第四控制信号的有效电平可以为低电平，第四控制信号的无效电平可以为高电平。或者，第十晶体管T10也可以设置为N型晶体管，则第四控制信号的有效电平可以为高电平，第四控制信号的无效电平可以为低电平。
在具体实施中，可以根据晶体管的类型以及其栅极的信号，将晶体管的第一极作为其源极，第二极作为其漏极；或者，反之，将晶体管的第一极作为其漏极，第二极作为其源极，这可以根据实际应用环境来设计确定，具体 在此不做具体区分。
以上仅是举例说明本公开实施例提供的像素电路中的各电路的具体结构，在具体实施时，上述电路的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，这些均在本公开的保护范围之内，具体在此不作限定。
下面以上述各晶体管为P型为例进行说明。示例性地，图3所示的像素电路对应的信号时序图，如图4a与图4b所示。其中，em1代表第一发光控制信号端EM1的第一发光控制信号，em2代表第二发光控制信号端EM2的第二发光控制信号，cs1代表第一控制信号端CS1的第一控制信号，cs2代表第二控制信号端CS2的第二控制信号，cs3代表第三控制信号端CS3的第三控制信号，cs4代表第四控制信号端CS4的第四控制信号。示例性地，第一控制信号cs1、第二控制信号cs2、第三控制信号cs3以及第四控制信号端cs4中的任意两个不相同，则第一控制信号端CS1、第二控制信号端CS2、第三控制信号端CS3以及第四控制信号端CS4可以设置为不同的信号端。
示例性地，如图4a与图4b所示，在一个显示帧中，第一控制信号端CS1的第一控制信号cs1的有效电平(如低电平)在第二控制信号端CS2的第二控制信号cs2的有效电平(如低电平)之前出现，第一控制信号端CS1的第一控制信号cs1的有效电平(如低电平)与第三控制信号端CS3的第三控制信号cs3的有效电平(如低电平)具有交叠区域。并且，第四控制信号端CS4的第四控制信号cs4的有效电平(如低电平)在第一控制信号端CS1的第一控制信号cs1的有效电平(如低电平)之前出现。
示例性地，第一控制信号端CS1的第一控制信号cs1的有效电平(如低电平)与第三控制信号端CS3的第三控制信号cs3的有效电平(如低电平)具有交叠区域。则，第三晶体管T3、第六晶体管T6、第五晶体管T5以及第九晶体管T9均在此交叠区域的时间段内导通。
示例性地，可以在衬底基板的非显示区域中设置栅极驱动电路和发光控制电路，以实现对像素电路中的各晶体管的驱动。
在一些示例中，结合图3与图4a以及图4b，可以在非显示区域中设置3个栅极驱动电路(每个栅极驱动电路可包括多个级联的移位寄存器单元)和1个发光控制电路(发光控制电路可包括多个级联的移位寄存器单元)。其中，第一控制信号端CS1的第一控制信号cs1可以采用这3个栅极驱动电路中的第1个栅极驱动电路输入。第三控制信号端CS3的第三控制信号cs3可以采用这3个栅极驱动电路中的第2个栅极驱动电路输入。第二控制信号端CS2的第二控制信号cs2和第四控制信号端CS4的第四控制信号cs4可以采用这3个栅极驱动电路中的第3个栅极驱动电路输入。并且，第一发光控制信号端EM1的第一发光控制信号em1和第二发光控制信号端EM2的第二发光控制信号em2可以采用该发光控制电路。
示例性地，对于第n行子像素中的像素电路接收到的第一控制信号cs1至第四控制信号cs4，第1控制信号cs1可为第1个栅极驱动电路中的第n级移位寄存器单元输入的信号。第3控制信号cs3可为第2个栅极驱动电路中的第n级移位寄存器单元输入的信号。以及，第四控制信号cs4可为第3个栅极驱动电路中的第n-3级移位寄存器单元输入的信号(如Gate(n-3))，且第二控制信号cs2为第3个栅极驱动电路中的第n级移位寄存器单元输入的信号(如Gate(n))。以及，第一发光控制信号端EM1的第一发光控制信号em1可为发光控制电路中的第n-1级移位寄存器单元输入的信号，第二发光控制信号端EM2的第二发光控制信号em2可为发光控制电路中的第n级移位寄存器单元输入的信号。
在另一些示例中，结合图3与图4a以及图4b，可以在非显示区域中设置2个栅极驱动电路(每个栅极驱动电路可包括多个级联的移位寄存器单元)和1个发光控制电路(发光控制电路可包括多个级联的移位寄存器单元)。这样可以节省一个栅极驱动电路，降低非显示区的占用空间。并且，第一发光控制信号端EM1的第一发光控制信号em1和第二发光控制信号端EM2的第二发光控制信号em2可以采用该发光控制电路。
示例性地，第一控制信号端CS1的第一控制信号cs1可以采用这2个栅 极驱动电路中的第1个栅极驱动电路输入。第二控制信号端CS2的第二控制信号cs2、第三控制信号端CS3的第三控制信号cs3以及第四控制信号端CS4的第四控制信号cs4可以采用这2个栅极驱动电路中的第2个栅极驱动电路输入。示例性地，对于第n行子像素中的像素电路接收到的第一控制信号cs1至第四控制信号cs4，第1控制信号cs1可为第1个栅极驱动电路中的第n级移位寄存器单元输入的信号。以及，第四控制信号cs4可为第2个栅极驱动电路中的第n-3级移位寄存器单元输入的信号(如Gate(n-3))，第3控制信号cs3可为第2个栅极驱动电路中的第n-2级移位寄存器单元输入的信号(如Gate(n-2))，第二控制信号cs2为第2个栅极驱动电路中的第n级移位寄存器单元输入的信号(如Gate(n))。以及，第一发光控制信号端EM1的第一发光控制信号em1可为发光控制电路中的第n-1级移位寄存器单元输入的信号，第二发光控制信号端EM2的第二发光控制信号em2可为发光控制电路中的第n级移位寄存器单元输入的信号。
如图5所示，本公开实施例提供的像素电路的驱动方法，可以包括如下步骤：
S100、数据写入阶段，第一控制电路基于漏电调节信号端的信号，降低驱动晶体管的栅极漏电；第二控制电路控制数据电压输入驱动晶体管的栅极。
S200、发光阶段，第一控制电路基于漏电调节信号端的信号，降低驱动晶体管的栅极漏电；第二控制电路控制驱动晶体管产生工作电流，驱动发光器件发光。
下面以图3所示的像素电路的结构为例，结合图4a所示的信号时序图，对本公开实施例提供的像素电路在一个显示帧内的工作过程作以描述。其中，em1代表第一发光控制信号端EM1的第一发光控制信号，em2代表第二发光控制信号端EM2的第二发光控制信号，cs1代表第一控制信号端CS1的第一控制信号，cs2代表第二控制信号端CS2的第二控制信号，cs3代表第三控制信号端CS3的第三控制信号，cs4代表第四控制信号端CS4的第四控制信号。
在第一阶段F1中，第七晶体管T7在第一发光控制信号em1的高电平的 控制下截止，第八晶体管T8在第二发光控制信号em2的高电平的控制下截止，第三晶体管T3和第六晶体管T6在第一控制信号cs1的高电平的控制下截止，第十晶体管T10在第四控制信号cs4的低电平的控制下导通，第四晶体管T4在第二控制信号cs2的高电平的控制下截止，第五晶体管T5和第九晶体管T9在第三控制信号cs3的高电平的控制下截止。导通的第十晶体管T10将第二初始化信号端VINIT2的信号提供给驱动晶体管T0的栅极(即第二节点N2)，对驱动晶体管T0的栅极进行复位。则，VN2＝Vinit2，其中，VN2代表第二节点N2的电压，Vinit2代表第二初始化信号端VINIT2输出的电压。
在第二阶段F2中，第七晶体管T7在第一发光控制信号em1的高电平的控制下截止，第八晶体管T8在第二发光控制信号em2的高电平的控制下截止，第三晶体管T3和第六晶体管T6在第一控制信号cs1的低电平的控制下导通，第十晶体管T10在第四控制信号cs4的高电平的控制下截止，第四晶体管T4在第二控制信号cs2的高电平的控制下截止，第五晶体管T5和第九晶体管T9在第三控制信号cs3的低电平的控制下导通。导通的第三晶体管T3将第一参考电压信号端VREF1的信号提供给驱动晶体管T0的第一极，对驱动晶体管T0的第一极进行复位。导通的第六晶体管T6将第一初始化信号端VINIT1的信号提供给发光器件L，对发光器件L进行复位。导通的第五晶体管T5将第二参考电压信号端VREF2的信号提供给第一节点N1。则，VN1＝Vref2，其中，VN1代表第一节点N1的电压，Vref2代表第二参考电压信号端VREF2输出的电压。导通的第九晶体管T9将驱动晶体管T0的栅极与第二极导通，则VN2＝Vth+Vref1，其中，Vth代表驱动晶体管T0的阈值电压，Vref1代表第一参考电压信号端VREF1输出的电压。
在第三阶段F3中，第七晶体管T7在第一发光控制信号em1的高电平的控制下截止，第八晶体管T8在第二发光控制信号em2的高电平的控制下截止，第三晶体管T3和第六晶体管T6在第一控制信号cs1的高电平的控制下截止，第十晶体管T10在第四控制信号cs4的高电平的控制下截止，第四晶体管T4在第二控制信号cs2的低电平的控制下导通，第五晶体管T5和第九晶体管T9 在第三控制信号cs3的高电平的控制下截止。导通的第四晶体管T4将数据信号端DA的数据电压Vda输入到第一节点N1，则VN1由Vref2变化为Vda。VN2由Vth+Vref1变化为：
Figure PCTCN2022135415-appb-000001
其中，C 2代表第二电容C2的电容值，Cgs_T10代表第十晶体管T10的电容值，Cgs_T9代表第九晶体管T9的电容值，Cgs_T0代表驱动晶体管T0的电容值，Cgs_T1代表第一晶体管T1的电容值，Cgs_T2代表第二晶体管T2的电容值。并且，由于漏电调节信号端VS的信号的作用，降低驱动晶体管T0的栅极漏电，可以进一步保持驱动晶体管T0的栅极电压的稳定。
在第四阶段F4中，第七晶体管T7在第一发光控制信号em1的低电平的控制下导通，第八晶体管T8在第二发光控制信号em2的高电平的控制下截止，第三晶体管T3和第六晶体管T6在第一控制信号cs1的高电平的控制下截止，第十晶体管T10在第四控制信号cs4的高电平的控制下截止，第四晶体管T4在第二控制信号cs2的高电平的控制下截止，第五晶体管T5和第九晶体管T9在第三控制信号cs3的高电平的控制下截止。导通的第七晶体管T7将第一电源端VDD的信号提供给驱动晶体管T0的第一极。并且，由于漏电调节信号端VS的信号的作用，降低驱动晶体管T0的栅极漏电，可以进一步保持驱动晶体管T0的栅极电压的稳定。
在第五阶段F5中，第七晶体管T7在第一发光控制信号em1的低电平的控制下导通，第八晶体管T8在第二发光控制信号em2的低电平的控制下导通，第三晶体管T3和第六晶体管T6在第一控制信号cs1的高电平的控制下截止，第十晶体管T10在第四控制信号cs4的高电平的控制下截止，第四晶体管T4在第二控制信号cs2的高电平的控制下截止，第五晶体管T5和第九晶体管T9在第三控制信号cs3的高电平的控制下截止。导通的第七晶体管T7将第一电源端VDD的信号提供给驱动晶体管T0的第一极，以使驱动晶体管T0的第一极的电压为第一电源电压Vdd。导通的第八晶体管T8将驱动晶体管T0的第 二极与发光器件L导通，使驱动晶体管T0产生驱动发光器件L发光的驱动电流Ids，控制发光器件L发光。驱动晶体管T0产生驱动发光器件L发光的工作电流为Ids，并且，Ids满足如下公式：
Figure PCTCN2022135415-appb-000002
其中，
Figure PCTCN2022135415-appb-000003
L代表驱动晶体管T0的沟道的长度，W代表驱动晶体管T0的沟道的宽度，C ox代表驱动晶体管T0的栅绝缘层单位面积电容，μ代表驱动晶体管T0的迁移率，Vdd代表第一电源端VDD输出的电压。并且，由于漏电调节信号端VS的信号的作用，降低驱动晶体管T0的栅极漏电，可以进一步保持驱动晶体管T0的栅极电压的稳定。
本公开实施例提供了另一些像素电路，如图6所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其大致相同之处在此不作赘述。
在本公开的一些实施例中，如图6所示，第一控制信号端CS1与第三控制信号端CS3接收同一信号，以降低信号端的数量，降低走线的数量。示例性的，第五晶体管T5的栅极和第九晶体管T9的栅极都与第一控制信号端CS1耦接。
在本公开的一些实施例中，图6所示的像素电路对应的信号时序图，如图7所示。其中，em1代表第一发光控制信号端EM1的第一发光控制信号，em2代表第二发光控制信号端EM2的第二发光控制信号，cs1代表第一控制信号端CS1的第一控制信号，cs2代表第二控制信号端CS2的第二控制信号，cs4代表第四控制信号端CS4的第四控制信号。示例性地，第一控制信号cs1、第二控制信号cs2以及第四控制信号端cs4中的任意两个不相同，则第一控制信号端CS1、第二控制信号端CS2以及第四控制信号端CS4可以设置为不同的信号端。
示例性地，在一个显示帧中，第一控制信号端CS1的第一控制信号cs1的有效电平(如低电平)在第二控制信号端CS2的第二控制信号cs2的有效 电平(如低电平)之前出现。并且，第四控制信号端CS4的第四控制信号cs4的有效电平(如低电平)在第一控制信号端CS1的第一控制信号cs1的有效电平(如低电平)之前出现。
示例性地，可以在衬底基板的非显示区域中设置栅极驱动电路和发光控制电路，以实现对像素电路中的各晶体管的驱动。
在一些示例中，结合图6与图7，可以在非显示区域中设置1个栅极驱动电路(栅极驱动电路可包括多个级联的移位寄存器单元)和1个发光控制电路(发光控制电路可包括多个级联的移位寄存器单元)。其中，第一控制信号端CS1的第一控制信号cs1、第二控制信号端CS2的第二控制信号cs2和第四控制信号端CS4的第四控制信号cs4可以采用该栅极驱动电路输入。这样可以节省栅极驱动电路，降低非显示区的占用空间。并且，第一发光控制信号端EM1的第一发光控制信号em1和第二发光控制信号端EM2的第二发光控制信号em2可以采用该发光控制电路。
示例性地，对于第n行子像素中的像素电路接收到的第一控制信号cs1至第四控制信号cs4，第四控制信号cs4可为该栅极驱动电路中的第n-3级移位寄存器单元输入的信号(如Gate(n-3))，第一控制信号cs1为该栅极驱动电路中的第n-2级移位寄存器单元输入的信号(如Gate(n-2))，且第二控制信号cs2为该栅极驱动电路中的第n级移位寄存器单元输入的信号(如Gate(n))。以及，第一发光控制信号端EM1的第一发光控制信号em1可为发光控制电路中的第n-1级移位寄存器单元输入的信号，第二发光控制信号端EM2的第二发光控制信号em2可为发光控制电路中的第n级移位寄存器单元输入的信号。
在另一些示例中，结合图6与图7，可以在非显示区域中设置2个栅极驱动电路(每个栅极驱动电路可包括多个级联的移位寄存器单元)和1个发光控制电路(发光控制电路可包括多个级联的移位寄存器单元)并且，第一发光控制信号端EM1的第一发光控制信号em1和第二发光控制信号端EM2的第二发光控制信号em2可以采用该发光控制电路。
示例性地，第一控制信号端CS1的第一控制信号cs1可以采用这2个栅极驱动电路中的第1个栅极驱动电路输入。第二控制信号端CS2的第二控制信号cs2以及第四控制信号端CS4的第四控制信号cs4可以采用这2个栅极驱动电路中的第2个栅极驱动电路输入。示例性地，对于第n行子像素中的像素电路接收到的第一控制信号cs1至第四控制信号cs4，第1控制信号cs1可为第1个栅极驱动电路中的第n级移位寄存器单元输入的信号。以及，第四控制信号cs4可为第2个栅极驱动电路中的第n-3级移位寄存器单元输入的信号(如Gate(n-3))，第二控制信号cs2为第2个栅极驱动电路中的第n级移位寄存器单元输入的信号(如Gate(n))。以及，第一发光控制信号端EM1的第一发光控制信号em1可为发光控制电路中的第n-1级移位寄存器单元输入的信号，第二发光控制信号端EM2的第二发光控制信号em2可为发光控制电路中的第n级移位寄存器单元输入的信号。
下面以图6所示的像素电路的结构为例，结合图7所示的信号时序图，对本公开实施例提供的像素电路在一个显示帧内的工作过程作以描述。其中，em1代表第一发光控制信号端EM1的第一发光控制信号，em2代表第二发光控制信号端EM2的第二发光控制信号，cs1代表第一控制信号端CS1的第一控制信号，cs2代表第二控制信号端CS2的第二控制信号，cs4代表第四控制信号端CS4的第四控制信号。
在第一阶段F1中，第七晶体管T7在第一发光控制信号em1的高电平的控制下截止，第八晶体管T8在第二发光控制信号em2的高电平的控制下截止，第十晶体管T10在第四控制信号cs4的低电平的控制下导通，第四晶体管T4在第二控制信号cs2的高电平的控制下截止，第三晶体管T3、第六晶体管T6、第五晶体管T5以及第九晶体管T9在第一控制信号cs1的高电平的控制下截止。导通的第十晶体管T10将第二初始化信号端VINIT2的信号提供给驱动晶体管T0的栅极，对驱动晶体管T0的栅极进行复位。则，VN2＝Vinit2。
在第二阶段F2中，第七晶体管T7在第一发光控制信号em1的高电平的控制下截止，第八晶体管T8在第二发光控制信号em2的高电平的控制下截止， 第十晶体管T10在第四控制信号cs4的高电平的控制下截止，第四晶体管T4在第二控制信号cs2的高电平的控制下截止，第三晶体管T3、第六晶体管T6、第五晶体管T5以及第九晶体管T9在第一控制信号cs1的低电平的控制下导通。导通的第三晶体管T3将第一参考电压信号端VREF1的信号提供给驱动晶体管T0的第一极，对驱动晶体管T0的第一极进行复位。导通的第六晶体管T6将第一初始化信号端VINIT1的信号提供给发光器件L，对发光器件L进行复位。导通的第五晶体管T5将第二参考电压信号端VREF2的信号提供给第一节点N1。则，VN1＝Vref2。导通的第九晶体管T9将驱动晶体管T0的栅极与第二极导通，则VN2＝Vth+Vref1。
在第三阶段F3中，第七晶体管T7在第一发光控制信号em1的高电平的控制下截止，第八晶体管T8在第二发光控制信号em2的高电平的控制下截止，第十晶体管T10在第四控制信号cs4的高电平的控制下截止，第四晶体管T4在第二控制信号cs2的低电平的控制下导通，第三晶体管T3、第六晶体管T6、第五晶体管T5以及第九晶体管T9在第一控制信号cs1的高电平的控制下截止。导通的第四晶体管T4将数据信号端DA的数据电压Vda输入到第一节点N1。则VN2由Vth+Vref1变化为：
Figure PCTCN2022135415-appb-000004
并且，由于漏电调节信号端VS的信号的作用，降低驱动晶体管T0的栅极漏电，可以进一步保持驱动晶体管T0的栅极电压的稳定。
在第四阶段F4中，第七晶体管T7在第一发光控制信号em1的低电平的控制下导通，第八晶体管T8在第二发光控制信号em2的高电平的控制下截止，第十晶体管T10在第四控制信号cs4的高电平的控制下截止，第四晶体管T4在第二控制信号cs2的高电平的控制下截止，第三晶体管T3、第六晶体管T6、第五晶体管T5以及第九晶体管T9在第一控制信号cs1的高电平的控制下截止。导通的第七晶体管T7将第一电源端VDD的信号提供给驱动晶体管T0的第一极。并且，由于漏电调节信号端VS的信号的作用，降低驱动晶体管 T0的栅极漏电，可以进一步保持驱动晶体管T0的栅极电压的稳定。
在第五阶段F5中，第七晶体管T7在第一发光控制信号em1的低电平的控制下导通，第八晶体管T8在第二发光控制信号em2的低电平的控制下导通，第十晶体管T10在第四控制信号cs4的高电平的控制下截止，第四晶体管T4在第二控制信号cs2的高电平的控制下截止，第三晶体管T3、第六晶体管T6、第五晶体管T5以及第九晶体管T9在第一控制信号cs1的高电平的控制下截止。导通的第七晶体管T7将第一电源端VDD的信号提供给驱动晶体管T0的第一极，以使驱动晶体管T0的第一极的电压为第一电源电压Vdd。导通的第七晶体管T7将第一电源端VDD的信号提供给驱动晶体管T0的第一极。导通的第八晶体管T8将驱动晶体管T0的第二极与发光器件L导通。使驱动晶体管T0产生驱动发光器件L发光的驱动电流Ids，控制发光器件L发光。驱动晶体管T0产生驱动发光器件L发光的工作电流为Ids，Ids满足如下公式：
Figure PCTCN2022135415-appb-000005
并且，由于漏电调节信号端VS的信号的作用，降低驱动晶体管T0的栅极漏电，可以进一步保持驱动晶体管T0的栅极电压的稳定。
本公开实施例提供了又一些像素电路的信号时序图，如图8所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其大致相同之处在此不作赘述。
示例性地，图3所示的像素电路对应的信号时序图，也可以如图8所示。其中，em1代表第一发光控制信号端EM1的第一发光控制信号，em2代表第二发光控制信号端EM2的第二发光控制信号，cs1代表第一控制信号端CS1的第一控制信号，cs2代表第二控制信号端CS2的第二控制信号，cs3代表第三控制信号端CS3的第三控制信号，cs4代表第四控制信号端CS4的第四控制信号。示例性地，第一控制信号cs1、第二控制信号cs2、第三控制信号cs3以及第四控制信号端cs4中的任意两个不相同，则第一控制信号端CS1、第二控制信号端CS2、第三控制信号端CS3以及第四控制信号端CS4可以设置为 不同的信号端。
示例性地，如图8所示，在一个显示帧中，第一发光控制信号端EM1的第一发光控制信号em1的有效电平(如低电平)与第三控制信号端CS3的第三控制信号cs3的有效电平(如低电平)具有交叠区域，第二控制信号端CS2的第二控制信号cs2的有效电平(如低电平)在第三控制信号端CS3的第三控制信号cs3的有效电平(如低电平)之后出现，第一控制信号端CS1的第一控制信号cs1的有效电平(如低电平)在第二控制信号端CS2的第二控制信号cs2的有效电平(如低电平)之后出现。这样可以实现对第一电源端的电压进行补偿。
示例性的，第一发光控制信号端EM1的第一发光控制信号em1的有效电平(如低电平)与第三控制信号端CS3的第三控制信号cs3的有效电平(如低电平)具有交叠区域，则，第七晶体管T7、第五晶体管T5以及第九晶体管T9均在此交叠区域的时间段内导通。
示例性地，可以在衬底基板的非显示区域中设置栅极驱动电路和发光控制电路，以实现对像素电路中的各晶体管的驱动。
在一些示例中，结合图3与图8，可以在非显示区域中设置3个栅极驱动电路(每个栅极驱动电路可包括多个级联的移位寄存器单元)和2个发光控制电路(发光控制电路可包括多个级联的移位寄存器单元)。其中，第一控制信号端CS1的第一控制信号cs1可以采用这3个栅极驱动电路中的第1个栅极驱动电路输入。第三控制信号端CS3的第三控制信号cs3可以采用这3个栅极驱动电路中的第2个栅极驱动电路输入。第二控制信号端CS2的第二控制信号cs2和第四控制信号端CS4的第四控制信号cs4可以采用这3个栅极驱动电路中的第3个栅极驱动电路输入。并且，第一发光控制信号端EM1的第一发光控制信号em1可以采用这2个发光控制电路中的第1个发光控制电路输入。第二发光控制信号端EM2的第二发光控制信号em2可以采用这2个发光控制电路中的第2个发光控制电路输入。
示例性地，对于第n行子像素中的像素电路接收到的第一控制信号cs1 至第四控制信号cs4，第1控制信号cs1可为第1个栅极驱动电路中的第n级移位寄存器单元输入的信号。第3控制信号cs3可为第2个栅极驱动电路中的第n级移位寄存器单元输入的信号。以及，第四控制信号cs4可为第3个栅极驱动电路中的第n-3级移位寄存器单元输入的信号(如Gate(n-3))，且第二控制信号cs2为第3个栅极驱动电路中的第n级移位寄存器单元输入的信号(如Gate(n))。以及，第一发光控制信号端EM1的第一发光控制信号em1可为第1发光控制电路中的第n级移位寄存器单元输入的信号。以及，第二发光控制信号端EM2的第二发光控制信号em2可为第2个发光控制电路中的第n级移位寄存器单元输入的信号。
下面以图3所示的像素电路的结构为例，结合图8所示的信号时序图，对本公开实施例提供的像素电路在一个显示帧内的工作过程作以描述。其中，em1代表第一发光控制信号端EM1的第一发光控制信号，em2代表第二发光控制信号端EM2的第二发光控制信号，cs1代表第一控制信号端CS1的第一控制信号，cs2代表第二控制信号端CS2的第二控制信号，cs3代表第三控制信号端CS3的第三控制信号，cs4代表第四控制信号端CS4的第四控制信号。
在第一阶段F1中，第七晶体管T7在第一发光控制信号em1的高电平的控制下截止，第八晶体管T8在第二发光控制信号em2的高电平的控制下截止，第三晶体管T3和第六晶体管T6在第一控制信号cs1的高电平的控制下截止，第十晶体管T10在第四控制信号cs4的低电平的控制下导通，第四晶体管T4在第二控制信号cs2的高电平的控制下截止，第五晶体管T5和第九晶体管T9在第三控制信号cs3的高电平的控制下截止。导通的第十晶体管T10将第二初始化信号端VINIT2的信号提供给驱动晶体管T0的栅极，对驱动晶体管T0的栅极进行复位。则，VN2＝Vinit2。
在第二阶段F2中，第七晶体管T7在第一发光控制信号em1的低电平的控制下导通，第八晶体管T8在第二发光控制信号em2的高电平的控制下截止，第三晶体管T3和第六晶体管T6在第一控制信号cs1的高电平的控制下截止，第十晶体管T10在第四控制信号cs4的高电平的控制下截止，第四晶体管T4 在第二控制信号cs2的高电平的控制下截止，第五晶体管T5和第九晶体管T9在第三控制信号cs3的低电平的控制下导通。导通的第七晶体管T7将第一电源端VDD的信号提供给驱动晶体管T0的第一极。导通的第五晶体管T5将第二参考电压信号端VREF2的信号提供给第一节点N1。则，VN1＝Vref2。导通的第九晶体管T9将驱动晶体管T0的栅极与第二极导通，则VN2＝Vth+Vdd。
在第三阶段F3中，第七晶体管T7在第一发光控制信号em1的高电平的控制下截止，第八晶体管T8在第二发光控制信号em2的高电平的控制下截止，第三晶体管T3和第六晶体管T6在第一控制信号cs1的高电平的控制下截止，第十晶体管T10在第四控制信号cs4的高电平的控制下截止，第四晶体管T4在第二控制信号cs2的低电平的控制下导通，第五晶体管T5和第九晶体管T9在第三控制信号cs3的高电平的控制下截止。导通的第四晶体管T4将数据信号端DA的数据电压Vda输入到第一节点N1。则VN1由Vref1变化为Vda，而VN2也会随着VN1的变化而变化，VN1由Vdd+Vth变化为
Figure PCTCN2022135415-appb-000006
Figure PCTCN2022135415-appb-000007
并且，由于漏电调节信号端VS的信号的作用，降低驱动晶体管T0的栅极漏电，可以进一步保持驱动晶体管T0的栅极电压的稳定。
在第四阶段F4中，第七晶体管T7在第一发光控制信号em1的高电平的控制下截止，第八晶体管T8在第二发光控制信号em2的高电平的控制下截止，第三晶体管T3和第六晶体管T6在第一控制信号cs1的低电平的控制下导通，第十晶体管T10在第四控制信号cs4的高电平的控制下截止，第四晶体管T4在第二控制信号cs2的低电平的控制下导通，第五晶体管T5和第九晶体管T9在第三控制信号cs3的高电平的控制下截止。导通的第三晶体管T3将第一参考电压信号端VREF1的信号提供给驱动晶体管T0的第一极，对驱动晶体管T0的第一极进行复位。导通的第六晶体管T6将第一初始化信号端VINIT1的信号提供给发光器件L，对发光器件L进行复位。
在第五阶段F5中，第七晶体管T7在第一发光控制信号em1的低电平的 控制下导通，第八晶体管T8在第二发光控制信号em2的低电平的控制下导通，第三晶体管T3和第六晶体管T6在第一控制信号cs1的高电平的控制下截止，第十晶体管T10在第四控制信号cs4的高电平的控制下截止，第四晶体管T4在第二控制信号cs2的高电平的控制下截止，第五晶体管T5和第九晶体管T9在第三控制信号cs3的高电平的控制下截止。导通的第七晶体管T7将第一电源端VDD的信号提供给驱动晶体管T0的第一极，以使驱动晶体管T0的第一极的电压为第一电源电压Vdd。导通的第七晶体管T7将第一电源端VDD的信号提供给驱动晶体管T0的第一极。导通的第八晶体管T8将驱动晶体管T0的第二极与发光器件L导通。使驱动晶体管T0产生驱动发光器件L发光的驱动电流Ids，控制发光器件L发光。驱动晶体管T0产生驱动发光器件L发光的工作电流为Ids，则Ids满足如下公式：
Figure PCTCN2022135415-appb-000008
并且，由于漏电调节信号端VS的信号的作用，降低驱动晶体管T0的栅极漏电，可以进一步保持驱动晶体管T0的栅极电压的稳定。以及，这样可以实现对第一电源端的电压进行补偿。
本公开实施例提供了又一些像素电路的信号时序图，如图9所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其大致相同之处在此不作赘述。
示例性地，图3所示的像素电路对应的信号时序图，也可以如图9所示。其中，em1代表第一发光控制信号端EM1的第一发光控制信号，em2代表第二发光控制信号端EM2的第二发光控制信号，cs1代表第一控制信号端CS1的第一控制信号，cs2代表第二控制信号端CS2的第二控制信号，cs3代表第三控制信号端CS3的第三控制信号，cs4代表第四控制信号端CS4的第四控制信号。示例性地，第一控制信号cs1、第二控制信号cs2、第三控制信号cs3以及第四控制信号端cs4中的任意两个不相同，则第一控制信号端CS1、第二控制信号端CS2、第三控制信号端CS3以及第四控制信号端CS4可以设置为 不同的信号端。
示例性地，如图9所示，在一个显示帧中，第一发光控制信号端EM1的第一发光控制信号em1的有效电平(如低电平)与第三控制信号端CS3的第三控制信号cs3的有效电平(如低电平)具有交叠区域，第二控制信号端CS2的第二控制信号cs2的有效电平(如低电平)在第三控制信号端CS3的第三控制信号cs3的有效电平(如低电平)之后出现，第一控制信号端CS1的第一控制信号cs1的有效电平(如低电平)在第二控制信号端CS2的第二控制信号cs2的有效电平(如低电平)之后出现。这样可以实现对第一电源端的电压进行补偿。
示例性的，第一发光控制信号端EM1的第一发光控制信号em1的有效电平(如低电平)与第三控制信号端CS3的第三控制信号cs3的有效电平(如低电平)具有交叠区域，则，第七晶体管T7、第五晶体管T5以及第九晶体管T9均在此交叠区域的时间段内导通。
在一些示例中，结合图3与图9，可以在非显示区域中设置2个栅极驱动电路(每个栅极驱动电路可包括多个级联的移位寄存器单元)和2个发光控制电路(发光控制电路可包括多个级联的移位寄存器单元)。这样可以节省栅极驱动电路的数量，降低占用空间。其中，第三控制信号端CS3的第三控制信号cs3可以采用这2个栅极驱动电路中的第1个栅极驱动电路输入。第一控制信号端CS1的第一控制信号cs1、第二控制信号端CS2的第二控制信号cs2和第四控制信号端CS4的第四控制信号cs4可以采用这2个栅极驱动电路中的第2个栅极驱动电路输入。并且，第一发光控制信号端EM1的第一发光控制信号em1可以采用这2个发光控制电路中的第1个发光控制电路输入。第二发光控制信号端EM2的第二发光控制信号em2可以采用这2个发光控制电路中的第2个发光控制电路输入。
示例性地，对于第n行子像素中的像素电路接收到的第一控制信号cs1至第四控制信号cs4，第3控制信号cs3可为第1个栅极驱动电路中的第n级移位寄存器单元输入的信号。以及，第四控制信号cs4可为第2个栅极驱动电 路中的第n-3级移位寄存器单元输入的信号(如Gate(n-3))，且第二控制信号cs2为第2个栅极驱动电路中的第n级移位寄存器单元输入的信号(如Gate(n))，且第一控制信号cs1为第2个栅极驱动电路中的第n+2级移位寄存器单元输入的信号(如Gate(n+2))。以及，第一发光控制信号端EM1的第一发光控制信号em1可为第1发光控制电路中的第n级移位寄存器单元输入的信号。以及，第二发光控制信号端EM2的第二发光控制信号em2可为第2个发光控制电路中的第n级移位寄存器单元输入的信号。
并且，图3所示的像素电路结合图9所示的信号时序图的工作过程可以参照上述描述，在此不作赘述。
本公开实施例提供了又一些像素电路的信号时序图，如图10所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其大致相同之处在此不作赘述。
示例性地，图3所示的像素电路对应的信号时序图，也可以如图10所示。其中，em1代表第一发光控制信号端EM1的第一发光控制信号，em2代表第二发光控制信号端EM2的第二发光控制信号，cs1代表第一控制信号端CS1的第一控制信号，cs2代表第二控制信号端CS2的第二控制信号，cs3代表第三控制信号端CS3的第三控制信号，cs4代表第四控制信号端CS4的第四控制信号。示例性地，第一控制信号cs1、第二控制信号cs2、第三控制信号cs3以及第四控制信号端cs4中的任意两个不相同，则第一控制信号端CS1、第二控制信号端CS2、第三控制信号端CS3以及第四控制信号端CS4可以设置为不同的信号端。
示例性地，如图10所示，在一个显示帧中，第一发光控制信号端EM1的第一发光控制信号em1的有效电平(如低电平)与第三控制信号端CS3的第三控制信号cs3的有效电平(如低电平)具有交叠区域，第二控制信号端CS2的第二控制信号cs2的有效电平(如低电平)在第三控制信号端CS3的第三控制信号cs3的有效电平(如低电平)之后出现，第一控制信号端CS1的第一控制信号cs1的有效电平(如低电平)在第二控制信号端CS2的第二 控制信号cs2的有效电平(如低电平)之后出现。这样可以实现对第一电源端的电压进行补偿。
示例性的，第一发光控制信号端EM1的第一发光控制信号em1的有效电平(如低电平)与第三控制信号端CS3的第三控制信号cs3的有效电平(如低电平)具有交叠区域，则，第七晶体管T7、第五晶体管T5以及第九晶体管T9均在此交叠区域的时间段内导通。
在一些示例中，结合图3与图10，可以在非显示区域中设置1个栅极驱动电路(每个栅极驱动电路可包括多个级联的移位寄存器单元)和2个发光控制电路(发光控制电路可包括多个级联的移位寄存器单元)。这样可以节省栅极驱动电路的数量，降低占用空间。其中，第一控制信号端CS1的第一控制信号cs1、第二控制信号端CS2的第二控制信号cs2、第三控制信号端CS3的第三控制信号cs3以及第四控制信号端CS4的第四控制信号cs4可以采用该栅极驱动电路输入。并且，第一发光控制信号端EM1的第一发光控制信号em1可以采用这2个发光控制电路中的第1个发光控制电路输入。第二发光控制信号端EM2的第二发光控制信号em2可以采用这2个发光控制电路中的第2个发光控制电路输入。
示例性地，对于第n行子像素中的像素电路接收到的第一控制信号cs1至第四控制信号cs4。
第四控制信号cs4可为该栅极驱动电路中的第n-3级移位寄存器单元输入的信号(如Gate(n-3))，第3控制信号cs3可为该栅极驱动电路中的第n-2级移位寄存器单元输入的信号(如Gate(n-2))，第二控制信号cs2为该栅极驱动电路中的第n级移位寄存器单元输入的信号(如Gate(n))，第一控制信号cs1为该栅极驱动电路中的第n+2级移位寄存器单元输入的信号(如Gate(n+2))。以及，第一发光控制信号端EM1的第一发光控制信号em1可为第1发光控制电路中的第n级移位寄存器单元输入的信号。以及，第二发光控制信号端EM2的第二发光控制信号em2可为第2个发光控制电路中的第n级移位寄存器单元输入的信号。
并且，图3所示的像素电路结合图10所示的信号时序图的工作过程可以参照上述描述，在此不作赘述。
本公开实施例提供了又一些像素电路，如图11所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其大致相同之处在此不作赘述。
本公开一些实施例中，如图11所示，第一控制电路10也可以包括：稳压电容CFT，其中，稳压电容CFT的第一电极与驱动晶体管T0的栅极耦接，稳压电容CFT的第二电极与漏电调节信号端VS耦接。这样，通过稳压电容CFT，可以基于漏电调节信号端VS的信号，降低驱动晶体管T0的栅极漏电，从而实现改善低灰阶显示时的闪烁(Flicker)问题。
示例性地，漏电调节信号端VS的信号的实施方式可以参照上述描述进行设置，在此不作赘述。
图11所示的像素电路对应的信号时序图，可以如图4a或图7至图10所示。并且，本公开实施例提供的像素电路的驱动过程，可以参照上述描述，在此不作赘述。
本公开实施例提供了又一些像素电路，如图12所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其大致相同之处在此不作赘述。
本公开一些实施例中，如图12所示，第一控制电路10也可以包括：补偿晶体管MFT，其中，补偿晶体管MFT的第一极和第二极与漏电调节信号端VS耦接，补偿晶体管MFT的栅极与驱动晶体管T0的栅极耦接。这样，通过设置单个晶体管，可以基于漏电调节信号端VS的信号，降低驱动晶体管T0的栅极漏电，从而实现改善低灰阶显示时的闪烁(Flicker)问题。
示例性地，也可以使补偿晶体管的栅极与漏电调节信号端耦接，补偿晶体管的第一极和第二极与驱动晶体管的栅极耦接，在此不作限定。
示例性地，漏电调节信号端VS的信号的实施方式可以参照上述描述进行设置，在此不作赘述。
图12所示的像素电路对应的信号时序图，可以如图4a或图7至图10所示。并且，本公开实施例提供的像素电路的驱动过程，可以参照上述描述，在此不作赘述。
本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述像素电路。该显示装置解决问题的原理与前述像素电路相似，因此该显示装置的实施可以参见前述像素电路的实施，重复之处在此不再赘述。
需要说明的是，在具体实施时，在本公开实施例中，显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
尽管已描述了本公开的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本公开范围的所有变更和修改。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (18)

  1. 一种像素电路，包括：
    发光器件；
    驱动晶体管，与所述发光器件耦接，被配置为根据数据电压产生驱动所述发光器件的工作电流；
    第一控制电路，与所述驱动晶体管的栅极耦接，被配置为基于漏电调节信号端的信号，降低所述驱动晶体管的栅极漏电；
    第二控制电路，分别与所述驱动晶体管和所述发光器件耦接，被配置为对所述驱动晶体管与所述发光器件进行复位，控制所述数据电压输入所述驱动晶体管的栅极以及控制所述驱动晶体管产生所述工作电流，驱动所述发光器件发光。
  2. 如权利要求1所述的像素电路，其中，所述第二控制电路包括：第一控制子电路；
    所述第一控制子电路被配置为响应于所述第一控制信号端的信号，将第一初始化信号端的信号提供给所述发光器件，以及响应于第一发光控制信号端的信号，将第一电源端与所述驱动晶体管的第一极导通，以及响应于第二发光控制信号端的信号，将所述驱动晶体管的第二极与所述发光器件导通，以及响应于所述第三控制信号端的信号，将所述驱动晶体管的栅极与所述驱动晶体管的第二极导通，以及响应于第四控制信号端的信号，将第二初始化信号端的信号提供给所述驱动晶体管的栅极。
  3. 如权利要求2所述的像素电路，其中，所述第二控制电路还包括：
    所述第二控制子电路被配置为响应于第二控制信号端的信号，将数据信号端的数据电压提供给第一节点；以及响应于第三控制信号端的信号，将第二参考电压信号端的信号提供给所述第一节点。
  4. 如权利要求2或3所述的像素电路，其中，所述第二控制电路还包括：第三控制子电路；
    所述第三控制子电路被配置为响应于第一控制信号端的信号，将第一参考电压信号端的信号提供给所述驱动晶体管的第一极。
  5. 如权利要求1-4任一项所述的像素电路，其中，在一个显示帧中，所述第一控制信号端的有效电平在所述第二控制信号端的有效电平之前出现，所述第一控制信号端的有效电平与所述第三控制信号端的有效电平具有交叠区域。
  6. 如权利要求1-4任一项所述的像素电路，其中，所述第一控制信号端与所述第三控制信号端接收同一信号；
    在一个显示帧中，所述第一控制信号端的有效电平在所述第二控制信号端的有效电平之前出现。
  7. 如权利要求1-4任一项所述的像素电路，其中，在一个显示帧中，所述第一发光控制信号端的有效电平与所述第三控制信号端的有效电平具有交叠区域，所述第二控制信号端的有效电平在所述第三控制信号端的有效电平之后出现，所述第一控制信号端的有效电平在所述第二控制信号端的有效电平之后出现。
  8. 如权利要求1所述的像素电路，其中，所述第一控制电路包括：第一晶体管和第二晶体管；
    所述第一晶体管的栅极与所述漏电调节信号端耦接，所述第一晶体管的第一极浮接，所述第一晶体管的第二极与所述驱动晶体管的栅极耦接；
    所述第二晶体管的栅极与所述漏电调节信号端耦接，所述第二晶体管的第一极浮接，所述第二晶体管的第二极与所述驱动晶体管的栅极耦接。
  9. 如权利要求1所述的像素电路，其中，所述第一控制电路包括：稳压电容；
    所述稳压电容的第一电极与所述驱动晶体管的栅极耦接，所述稳压电容的第二电极与所述漏电调节信号端耦接。
  10. 如权利要求1所述的像素电路，其中，所述第一控制电路包括：补偿晶体管；
    所述补偿晶体管的第一极和第二极与所述漏电调节信号端耦接，所述补偿晶体管的栅极与所述驱动晶体管的栅极耦接；
    或者，所述补偿晶体管的栅极与所述漏电调节信号端耦接，所述补偿晶体管的第一极和第二极与所述驱动晶体管的栅极耦接。
  11. 如权利要求1-10任一项所述的像素电路，其中，在同一个显示帧中，在对所述驱动晶体管的栅极进行复位时，所述漏电调节信号端的信号的电压为第一电压，在所述数据电压输入所述驱动晶体管的栅极时，所述漏电调节信号端的信号的电压为第二电压；
    所述第二电压不小于所述第一电压。
  12. 如权利要求11所述的像素电路，其中，在不同显示帧中，所述第一电压相同；
    在不同显示帧中，所述第二电压大于第三电压；所述第三电压为Vda-Vth；Vda代表所述数据电压，Vth代表所述驱动晶体管的阈值电压。
  13. 如权利要求12所述的像素电路，其中，在不同显示帧中，所述第二电压相同；
    或者，在不同显示帧中，所述第二电压随着所述第三电压的增加而增加。
  14. 如权利要求4所述的像素电路，其中，所述第三控制子电路包括：第三晶体管；
    所述第三晶体管的栅极与所述第一控制信号端耦接，所述第三晶体管的第一极与所述驱动晶体管的第一极耦接，所述第三晶体管的第二极与所述第一参考电压信号端耦接。
  15. 如权利要求3所述的像素电路，其中，所述第二控制子电路包括：第四晶体管、第五晶体管以及第一电容；
    所述第四晶体管的栅极与所述第二控制信号端耦接，所述第四晶体管的第一极与所述数据信号端耦接，所述第四晶体管的第二极与所述第一节点耦接；
    所述第五晶体管的栅极与所述第三控制信号端耦接，所述第五晶体管的 第一极与所述第一节点耦接，所述第五晶体管的第二极与所述第二参考电压信号端耦接；
    所述第一电容的第一电极与所述第一电源端耦接，所述第一电容的第二电极与所述第一节点耦接。
  16. 如权利要求2-4任一项所述的像素电路，其中，所述第一控制子电路包括：第六晶体管、第七晶体管、第八晶体管、第九晶体管、第十晶体管以及第二电容；
    所述第六晶体管的栅极与所述第一控制信号端耦接，所述第六晶体管的第一极与所述发光器件耦接，所述第六晶体管的第二极与所述第一初始化信号端耦接；
    所述第七晶体管的栅极与所述第一发光控制信号端耦接，所述第七晶体管的第一极与所述第一电源端耦接，所述第七晶体管的第二极与所述驱动晶体管的第一极耦接；
    所述第八晶体管的栅极与所述第二发光控制信号端耦接，所述第八晶体管的第一极与所述驱动晶体管的第二极耦接，所述第八晶体管的第二极与所述发光器件耦接；
    所述第九晶体管的栅极与所述第三控制信号端耦接，所述第九晶体管的第一极与所述驱动晶体管的栅极耦接，所述第九晶体管的第二极与所述驱动晶体管的第二极耦接；
    所述第十晶体管的栅极与所述第四控制信号端耦接，所述第十晶体管的第一极与所述驱动晶体管的栅极耦接，所述第十晶体管的第二极与所述第二初始化信号端耦接；
    所述第二电容的第一电极与所述第一节点耦接，所述第二电容的第二电极与所述驱动晶体管的栅极耦接。
  17. 一种显示装置，包括如权利要求1-16任一项所述的像素电路。
  18. 一种用于如权利要求1-16任一项所述的像素电路的驱动方法，包括：
    数据写入阶段，所述第一控制电路基于所述漏电调节信号端的信号，降 低所述驱动晶体管的栅极漏电；所述第二控制电路控制所述数据电压输入所述驱动晶体管的栅极；
    发光阶段，所述第一控制电路基于所述漏电调节信号端的信号，降低所述驱动晶体管的栅极漏电；所述第二控制电路控制所述驱动晶体管产生所述工作电流，驱动所述发光器件发光。
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