WO2019019622A1 - 像素电路及其驱动方法、显示面板和显示装置 - Google Patents

像素电路及其驱动方法、显示面板和显示装置 Download PDF

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Publication number
WO2019019622A1
WO2019019622A1 PCT/CN2018/077011 CN2018077011W WO2019019622A1 WO 2019019622 A1 WO2019019622 A1 WO 2019019622A1 CN 2018077011 W CN2018077011 W CN 2018077011W WO 2019019622 A1 WO2019019622 A1 WO 2019019622A1
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WIPO (PCT)
Prior art keywords
circuit
control
driving
pixel
node
Prior art date
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PCT/CN2018/077011
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English (en)
French (fr)
Inventor
林奕呈
徐攀
张保侠
李全虎
王玲
盖翠丽
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to JP2018545204A priority Critical patent/JP7113750B2/ja
Priority to EP18755388.8A priority patent/EP3660825A4/en
Priority to KR1020187026426A priority patent/KR20190025812A/ko
Priority to US16/078,840 priority patent/US20210210013A1/en
Publication of WO2019019622A1 publication Critical patent/WO2019019622A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2230/00—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/043—Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • Embodiments of the present disclosure relate to a pixel circuit and a method of driving the same, a display panel, and a display device.
  • OLED Organic Light Emitting Diode
  • LCD liquid crystal display
  • OLED display has low energy consumption, low production cost, self-illumination, wide viewing angle and The response speed is fast.
  • LCDs that use a stable voltage to control brightness
  • OLEDs are driven by current and require a constant current to control their illumination. Due to process process and device aging, etc., the threshold voltage Vth of the driving transistor in the pixel circuit may be non-uniform, which causes a difference in current flowing through each OLED to cause uneven display brightness, thereby affecting the display of the entire image. effect.
  • the current flowing through each OLED is related to the source of the driving transistor, that is, the power supply voltage, due to the voltage drop (IR Drop), the current difference in different regions may also occur, thereby causing uneven brightness of the OLEDs in different regions.
  • At least one embodiment of the present disclosure provides a pixel circuit including: a data writing circuit, a compensation control circuit, a storage circuit, an illumination control circuit, and a driving circuit.
  • the data writing circuit is respectively connected to the first control signal end, the data signal end and the first node; the data writing circuit is configured to provide the signal of the data signal end to the control of the first control signal end to The first node.
  • the storage circuit is respectively connected to the first node, the control end of the driving circuit, and the second end of the driving circuit; the storage circuit is configured to maintain the first node and the control end of the driving circuit A voltage difference between the two, and maintaining a voltage difference between the first node and the second end of the drive circuit.
  • the compensation control circuit is respectively connected to a second control signal end, a control end of the drive circuit, and a first end of the drive circuit; the compensation control circuit is configured to enable the control under the control of the second control signal end
  • the control terminal of the driving circuit is electrically connected to the first end of the driving circuit.
  • the illuminating control circuit is respectively connected to the illuminating control signal end, the first power end, and the first end of the driving circuit; the illuminating control circuit is configured to: at the first power end under the control of the illuminating control signal end A signal is provided to the drive circuit.
  • the driving circuit is respectively connected to the compensation control circuit, the illumination control circuit and the storage circuit; the drive circuit is configured to output a drive current.
  • the storage circuit includes a first storage circuit and a second storage circuit.
  • the first storage circuit is respectively connected to the first node and a control end of the driving circuit; the first storage circuit is configured to maintain a voltage difference between the first node and a control end of the driving circuit .
  • the second storage circuit is respectively connected to the first node and the second end of the driving circuit; the second storage circuit is configured to maintain a voltage difference between the first node and the second end of the driving circuit.
  • a pixel circuit provided by an embodiment of the present disclosure further includes a light emitting element.
  • a first pole of the light emitting element is connected to the second end of the driving circuit and the storage circuit, and a second pole of the light emitting element is connected to a second power terminal; the light emitting component is used in the driving circuit The light is emitted by the output drive current.
  • the driving circuit includes a driving transistor.
  • a gate of the driving transistor is connected as a control end of the driving circuit to the memory circuit and the compensation control circuit, a first pole of the driving transistor is used as a first end of the driving circuit, and the compensation control
  • the circuit and the illumination control circuit are connected, and a second pole of the drive transistor is connected to the storage circuit as a second end of the drive circuit.
  • the first storage circuit includes a first capacitor.
  • the first end of the first capacitor is connected to the first node, and the second end of the first capacitor is connected to the control end of the driving circuit.
  • the second storage circuit includes a second capacitor.
  • the first end of the second capacitor is connected to the first node, and the second end of the second capacitor is connected to the second end of the driving circuit.
  • a capacitance value of the first capacitor is greater than a capacitance value of the second capacitor.
  • the data writing circuit includes a first switching transistor. a gate of the first switching transistor is connected to the first control signal end, a first pole of the first switching transistor is connected to the data signal end, and a second pole of the first switching transistor is The first node is connected.
  • the compensation control circuit includes a second switching transistor. a gate of the second switching transistor is connected to the second control signal end, a first pole of the second switching transistor is connected to a control end of the driving circuit, and a second pole of the second switching transistor is The first end of the driving circuit is connected.
  • the light emission control circuit includes a third switching transistor. a gate of the third switching transistor is connected to the light emission control signal end, a first pole of the third switching transistor is connected to the first power terminal, and a second pole of the third switching transistor is The first end of the drive circuit is connected.
  • the driving transistor is an N-type transistor.
  • the switching transistor is a P-type transistor or an N-type transistor.
  • At least one embodiment of the present disclosure also provides a display panel including a plurality of pixel units distributed in an array, each of the pixel units including any of the pixel circuits provided in an embodiment of the present disclosure.
  • At least one embodiment of the present disclosure also provides a display device including a display panel as provided by an embodiment of the present disclosure.
  • a display device further includes a plurality of first control signal lines, a plurality of second control signal lines, a plurality of light emission control signal lines, and a plurality of data signal lines.
  • the first control signal line of each row is connected to the first control signal end in the row of pixel circuits; the second control signal line of each row and the second control signal end of the row of pixel circuits.
  • the light-emitting control signal lines of each row are connected to the light-emission control signal terminals of the pixel circuits of the row; the data signal lines of each column are connected to the data signal terminals of the pixel circuits of the column.
  • At least one embodiment of the present disclosure also provides a driving method of a pixel circuit, including: a reset and compensation phase, a data writing phase, and an illumination phase.
  • the compensation control circuit turns on the control end of the driving circuit and the first end of the driving circuit under the control of the second control signal end;
  • the data writing phase the a data writing circuit supplies a signal of the data signal end to the first node under control of the first control signal end;
  • the storage circuit maintains control of the first node and the driving circuit a voltage difference between the terminals, and maintaining a voltage difference between the first node and the second end of the driving circuit;
  • the lighting control circuit provides the signal of the first power terminal to the control of the lighting control signal end to The driving circuit;
  • the driving circuit outputs a driving current.
  • 1 is a schematic diagram of a pixel circuit
  • FIG. 2 is a schematic diagram of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of another pixel circuit according to an embodiment of the present disclosure.
  • FIG. 4 is a circuit diagram of a specific implementation example of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 5 is a circuit timing diagram of a driving method according to an embodiment of the present disclosure.
  • FIG. 6 is a simulation diagram of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic flowchart diagram of a driving method of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of a display device according to an embodiment of the present disclosure.
  • the transistors used in the embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other switching device having the same characteristics.
  • a thin film transistor is taken as an example for description.
  • the source and drain of the transistor used here may be structurally symmetrical, so that the source and the drain may be structurally indistinguishable.
  • the embodiment of the present disclosure in order to distinguish the two poles of the transistor except the gate, one of the first poles and the other pole are directly described.
  • the switching transistor employed in the embodiments of the present disclosure may include any one of a P-type switching transistor and an N-type switching transistor, wherein the P-type switching transistor is turned on when the gate is at a low level, and is turned off when the gate is at a high level.
  • the N-type switching transistor is turned on when the gate is at a high level and turned off when the gate is at a low level.
  • the pixel circuit is composed of a driving transistor M0, a switching transistor M, and a storage capacitor Cs.
  • the scan line Scan selects a certain row, the scan line Scan inputs a low level signal, the P-type switch transistor M is turned on, and the voltage on the data line Data is written to the storage capacitor Cs; when the line scan ends, the scan line Scan input
  • the signal changes to a high level, the P-type switching transistor M is turned off, and the gate voltage stored by the storage capacitor Cs causes the driving transistor M0 to generate a current to drive the OLED, ensuring that the OLED continues to emit light within one frame.
  • the threshold voltage Vth of the driving transistor M0 may drift due to process process and device aging, etc., and since the current is related to the power supply voltage, Due to the voltage drop (IR Drop), the source voltage Vs of the driving transistor is also different, so that the current flowing through each OLED changes due to the variation of the threshold voltage Vth of the driving transistor and the source voltage of the driving transistor, thereby Causes uneven brightness of the image.
  • At least one embodiment of the present disclosure provides a pixel circuit including a data write circuit, a compensation control circuit, a first storage circuit, a second storage circuit, an illumination control circuit, and a drive circuit. At least one embodiment of the present disclosure also provides a driving method, a display panel, and a display device corresponding to the pixel circuit.
  • the pixel circuit, the display panel, the display device and the driving method provided by the embodiments of the present disclosure can make the current output by the driving circuit in the pixel circuit only related to the data voltage and the reference voltage of the data signal end, and is independent of the threshold voltage of the driving circuit.
  • the influence of the threshold voltage of the driving circuit on the current output by the driving circuit can be avoided, so that the current outputted by the driving circuit is kept stable, and the uniformity of the brightness of the display screen of the display device including the pixel circuit can be improved.
  • At least one embodiment of the present disclosure provides a pixel circuit including, as shown in FIG. 2, a data writing circuit 1, a storage circuit 2, a compensation control circuit 4, an illumination control circuit 5, and a drive circuit 6.
  • the data writing circuit 1 is respectively connected to the first control signal terminal G1, the data signal terminal Data and the first node A; the data writing circuit 1 is configured to provide the signal of the data signal terminal Data under the control of the first control signal terminal G1.
  • the signal of the data signal terminal Data is a data voltage that controls the degree of brightness of the pixel.
  • the memory circuit 2 is connected to the first node A, the control terminal 60 of the drive circuit 6, and the second terminal 62 of the drive circuit 6, respectively.
  • the memory circuit 2 is for maintaining a voltage difference between the first node A and the control terminal 60 of the drive circuit 6, and maintaining a voltage difference between the first node A and the second terminal 62 of the drive circuit 6.
  • the compensation control circuit 4 is respectively connected to the second control signal terminal G2, the control terminal 60 of the driving circuit 6, and the first terminal 61 of the driving circuit 6, and the compensation control circuit 4 is configured to drive the driving circuit under the control of the second control signal terminal G2.
  • the control terminal 60 of 6 is electrically connected to the first terminal 61 of the drive circuit 6.
  • the illuminating control circuit 5 is respectively connected to the illuminating control signal terminal EM, the first power terminal VDD and the first end 61 of the driving circuit 6.
  • the illuminating control circuit 5 is configured to turn the first power terminal VDD under the control of the illuminating control signal terminal EM.
  • the signal is provided to the drive circuit 6, for example to the first end 61 of the drive circuit 6.
  • the drive circuit 6 is connected to the compensation control circuit 4, the illumination control circuit 5, and the storage circuit 2, respectively, and the drive circuit 6 is for outputting a drive current.
  • the drive circuit 6 outputs the drive current from the second terminal 62, for example, the drive current can be used to drive the light emitting element to emit light.
  • the pixel circuit provided by the embodiment of the present disclosure includes a data writing circuit, a compensation control circuit, a storage circuit, an illumination control circuit, and a driving circuit.
  • the data writing circuit is configured to provide a signal of the data signal end to the first node under the control of the first control signal end;
  • the storage circuit is configured to maintain a voltage difference between the first node and the control end of the driving circuit, and maintain the first node a voltage difference from the second end of the driving circuit;
  • the compensation control circuit is configured to make the control end of the driving circuit and the first end of the driving circuit conductive under the control of the second control signal end; and the lighting control circuit is used for controlling the light emitting control signal end
  • the signal of the first power terminal is supplied to the driving circuit, and the driving circuit is used for outputting the driving current.
  • the current outputted by the driving circuit in the pixel circuit can be related only to the data voltage and the reference voltage of the data signal end, and is independent of the threshold voltage of the driving circuit and the voltage of the second power terminal, thereby avoiding The threshold voltage of the driving transistor and the influence of the voltage drop on the current outputted by the driving circuit stabilize the current outputted by the driving circuit, thereby improving the uniformity of the brightness of the display screen of the display device including the pixel circuit.
  • the storage circuit 2 may include a first storage circuit 21 and a second storage circuit 22,
  • the first storage circuit 21 is connected to the first node A and the control terminal 60 of the drive circuit 6, respectively, and the first storage circuit 21 is for maintaining a voltage difference between the first node A and the control terminal 60 of the drive circuit 6.
  • the second storage circuit 22 is connected to the first node A and the second end 62 of the drive circuit 6, respectively, and the second storage circuit 22 is for maintaining the voltage difference between the first node A and the second end 62 of the drive circuit 6.
  • the pixel circuit may further include a light emitting element LE.
  • the first pole of the light-emitting element LE is connected to the second end 62 of the drive circuit 6 and the second storage circuit 3, and the second pole of the light-emitting element LE is connected to the second power supply terminal VSS.
  • the light-emitting element LE is used to emit light by the driving current output from the drive circuit 6.
  • the light-emitting element LE realizes light emission under the action of a current when the drive circuit is in a saturated state.
  • the light-emitting element LE may be an organic light-emitting diode (OLED).
  • OLED organic light-emitting diode
  • the embodiments of the present disclosure include, but are not limited to, the following embodiments are described by using an OLED as an example, and details are not described herein.
  • the anode of the OLED may be connected to the second end 62 of the driving circuit 6, and the cathode of the OLED may be connected to the second power supply terminal VSS.
  • the OLED may be of various types, such as a top emission, a bottom emission, or the like, and may emit red light, green light, blue light, or white light, etc., which is not limited by the embodiments of the present disclosure.
  • the OLED also has a threshold voltage, and emits light when the voltage across the OLED is greater than or equal to the threshold voltage.
  • the voltage of the first power terminal VDD is a high level voltage
  • the voltage of the second power terminal VSS is grounded or a low level voltage
  • the pixel circuit shown in FIG. 3 can be embodied as the pixel circuit structure shown in FIG.
  • the pixel circuit includes a driving transistor M0, a first switching transistor M1, a second switching transistor M2, a third switching transistor M3, a first capacitor C1, a second capacitor C2, and a light emitting element OLED.
  • the transistors in the pixel circuit are all described by taking an N-type transistor as an example.
  • the drive circuit 6 can be implemented as the drive transistor M0.
  • the gate of the driving transistor M0 is connected as the control terminal 60 of the driving circuit 6 to the first storage circuit 21 and the compensation control circuit 4, and the first electrode of the driving transistor M0 serves as the first terminal 61 and the compensation control circuit 4 of the driving circuit 6 and emits light.
  • the control circuit 5 is connected, and the second electrode of the driving transistor M0 is connected as the second terminal 62 of the driving circuit 6 and the second storage circuit 22.
  • the first storage circuit 21 can be implemented as a first capacitor C1.
  • the first end of the first capacitor C1 is connected to the first node A, and the second end of the first capacitor C1 is connected to the control end of the driving circuit 6.
  • the driving circuit 6 is implemented as the driving transistor M0
  • the second end of the first capacitor C1 may be connected to the gate of the driving transistor M0.
  • the first capacitor C1 is charged under the common control of the signal of the first node A and the signal of the gate of the driving transistor M0; and the signal and the driving transistor at the first node A Discharging is performed under the common control of the signal of the gate of M0; and when the gate of the driving transistor M0 is in the floating state, the voltage difference between the gates of the first node A and the driving transistor M0 is kept stable to drive the transistor
  • the threshold voltage Vth of M0 and the data voltage input to the data signal terminal Data are stored on the gate of the driving transistor M0.
  • the above is only a specific structure of the first storage circuit 21 in the pixel circuit.
  • the specific structure of the first storage circuit 21 is not limited to the above-mentioned structure provided by the embodiment of the present disclosure, and may be known to those skilled in the art. Other structures are not limited here.
  • the second storage circuit 22 can be implemented as a second capacitor C2.
  • the first end of the second capacitor C2 is connected to the first node A, and the second end of the second capacitor C2 is connected to the second end of the driving circuit 6.
  • the driving circuit 6 is implemented as the driving transistor M0
  • the second end of the second capacitor C2 may be connected to the second electrode of the driving transistor M0.
  • the second end of the second capacitor C2 can also be connected to the anode of the light-emitting element OLED.
  • the second capacitor C2 is charged under the common control of the signal of the first node A and the signal of the second pole of the driving transistor M0, and the signal and driving at the first node A are performed. Discharging under the common control of the signal of the second pole of the transistor M0; and maintaining the voltage difference between the first node A and the second pole of the driving transistor M0 stable when the light emitting element OLED is in the light emitting state, to ensure the output of the driving transistor M0 Stable drive current.
  • the above is only a specific structure of the second storage circuit 22 in the pixel circuit.
  • the specific structure of the second storage circuit 22 is not limited to the above-mentioned structure provided by the embodiment of the present disclosure, and may be known to those skilled in the art. Other structures are not limited here.
  • the capacitance value of the first capacitor C1 is relatively large. In order to reduce the space occupied area, the capacitance value of the second capacitor C2 is relatively small. Therefore, in the pixel circuit provided by one embodiment of the present disclosure, the capacitance value of the first capacitor C1 may be greater than the capacitance value of the second capacitor C2.
  • the data writing circuit 1 can be implemented as the first switching transistor M1.
  • the gate of the first switching transistor M1 is connected to the first control signal terminal G1
  • the first pole of the first switching transistor M1 is connected to the data signal terminal Data
  • the second pole of the first switching transistor M1 is connected to the first node A.
  • the signal of the data signal terminal Data may be supplied to the first node A.
  • the above is only a specific structure of the data writing circuit 1 in the pixel circuit.
  • the specific structure of the data writing circuit 1 is not limited to the above-mentioned structure provided by the embodiment of the present disclosure, and may be known to those skilled in the art. Other structures are not limited here.
  • the compensation control circuit 4 can be implemented as a second switching transistor M2.
  • the gate of the second switching transistor M2 is connected to the second control signal terminal G2, the first pole of the second switching transistor M2 is connected to the control terminal of the driving circuit 6, and the second pole of the second switching transistor M2 is connected to the driving circuit 6. Connected at one end.
  • the driving circuit 6 is implemented as the driving transistor M0
  • the first electrode of the second switching transistor M2 may be connected to the gate of the driving transistor M0
  • the second electrode of the second switching transistor M2 may be coupled to the first electrode of the driving transistor M0. connection.
  • the second switching transistor M2 can conduct the gate of the driving transistor M0 and the first electrode of the driving transistor M0 under the control of the second control signal terminal G2 to control The drive transistor M0 is in a diode connected state.
  • the above is only a specific structure of the compensation control circuit 4 in the pixel circuit.
  • the specific structure of the compensation control circuit 4 is not limited to the above-mentioned structure provided by the embodiments of the present disclosure, and may be other known to those skilled in the art. Structure, not limited here.
  • the illumination control circuit 5 can be implemented as a third switching transistor M3.
  • the gate of the third switching transistor M3 is connected to the light-emitting control signal terminal EM, the first pole of the third switching transistor M3 is connected to the first power terminal VDD, and the second pole of the third switching transistor M3 is connected to the first terminal of the driving circuit.
  • the driving circuit 6 is implemented as the driving transistor M0, the second electrode of the third switching transistor M3 may be connected to the first electrode of the driving transistor M0.
  • the third switching transistor M3 can supply the voltage of the first power terminal VDD to the first pole of the driving transistor M0 under the control of the light emission control signal terminal EM, and the driving transistor The driving current of the second pole output of M0 is output to, for example, the light emitting element OLED to drive its light emission.
  • the above is only a specific structure of the illuminating control circuit 5 in the pixel circuit.
  • the specific structure of the illuminating control circuit 5 is not limited to the above-mentioned structure provided by the embodiments of the present disclosure, and may be other known to those skilled in the art. Structure, not limited here.
  • the driving transistor M0 is an N-type transistor.
  • the first switching transistor M1, the second switching transistor M2, and the third switching transistor M3 may be in addition to the N-type transistor as shown in FIG. P-type transistors may be used or P-type transistors and N-type transistors may be mixed, as long as the port polarities of the selected types of transistors are simultaneously connected in accordance with the port polarity of the corresponding transistor in the embodiment of the present disclosure.
  • the driving transistor M0 and all of the switching transistors M1-M3 are N-type transistors.
  • the N-type switching transistor is turned on under a high potential and turned off under a low potential.
  • the driving transistor M0 is an N-type transistor, and all switching transistors are N-type transistors, and the corresponding timing chart is as shown in FIG. 5. Specifically, the three stages of the reset and compensation phase T1, the data writing phase T2, and the lighting phase T3 in the timing chart shown in FIG. 5 are selected for description.
  • the first switching transistor M1, the second switching transistor M2, and the driving transistor M0 are both in an on state, and the third switching transistor M3 is in an off state.
  • the turned-on second switching transistor M2 can turn on the gate of the driving transistor M0 and its first electrode, so that the driving transistor M0 is in a diode-connected state, and thus the voltage of the gate and source of the driving transistor M0 is released through the light-emitting element OLED. , that is, the reset of the pixel circuit is realized.
  • the first switching transistor M1 and the driving transistor M0 are both in an on state, and the second switching transistor M2 and the third switching transistor M3 are both in an off state.
  • the voltage written by the data signal terminal Data is Vdata, that is, the turned-on first switching transistor M1 supplies the voltage Vdata of the data signal terminal Data to the first node A, so the voltage V A of the first node A is One stage of Vref becomes Vdata.
  • the third switching transistor M3 and the driving transistor M0 are both in an on state, and the first switching transistor M1 and the second switching transistor M2 are in an off state.
  • the voltage change at the second end of the second capacitor C2 is coupled to the first node of the second capacitor C2, that is, the first node A, so the voltage of the first node A becomes V.
  • A Vdata + Voled-Voled0.
  • the first pole voltage of the driving transistor M0 is the voltage V DD of the first power terminal VDD, and the driving transistor M0 is in a saturated state. According to the saturation state current characteristic, the operating current I flowing through the driving transistor M0 for driving the light emitting element OLED to emit light is known. OLED satisfies the formula:
  • I OLED K(Vgs–Vth) 2
  • K is a structural parameter, and this value is relatively stable in the same structure and can be counted as a constant. It can be seen that the operating current I OLED of the light emitting element OLED can be unaffected by the threshold voltage Vth of the driving transistor M0, and is independent of the voltage V SS of the second power supply terminal VSS, and only the data voltage Vdata and the reference of the data signal terminal Data.
  • the voltage Vref is related to the influence of the threshold voltage Vth drift of the driving transistor M0 and the voltage drop (IR Drop) on the operating current I OLED of the light emitting element OLED due to the process process and long-time operation.
  • the I OLED is also independent of the threshold voltage Voled0 and the operating voltage Voled of the OLED, and the difference in current due to aging of the OLED can be avoided, thereby improving the unevenness of the panel display.
  • the pixel circuit provided by the embodiment of the present disclosure can compensate the threshold voltage Vth of the driving transistor M0 by using only 4 transistors and 2 capacitors, and the structure is relatively simple.
  • the present disclosure also performs simulation simulation on the pixel circuit provided by the above embodiment in three stages, and the simulation result is shown in FIG. 6.
  • the current flows through the operating current I OLED of the light-emitting element OLED at a time of 1.2447 ms.
  • the pixel circuit provided in the disclosure, the light emitting element OLED operating current I OLED can be the threshold voltage Vth of the transistor M0 is not driven.
  • the embodiment of the present disclosure further provides a driving method, which can be used in any of the pixel circuits provided by the embodiments of the present disclosure.
  • the driving method includes the following operational steps.
  • Step S701 In the reset and compensation phase, the compensation control circuit turns on the control end of the driving circuit and the first end of the driving circuit under the control of the second control signal end;
  • Step S702 In the data writing phase, the data writing circuit provides the signal of the data signal end to the first node under the control of the first control signal end;
  • Step S703 In the light emitting phase, the storage circuit maintains a voltage difference between the first node and the control end of the driving circuit, and maintains a voltage difference between the first node and the second end of the driving circuit; the light emitting control circuit is under the control of the light emitting control signal end The signal of the first power terminal is supplied to the driving circuit; the driving circuit outputs the driving current.
  • the driving method of the pixel circuit may enable the operating current of the driving transistor in the pixel circuit to drive the light emitting element to emit light only related to the data voltage and the reference voltage of the data signal end, and the threshold voltage of the driving transistor and the second
  • the voltage at the power supply terminal is independent, and the influence of the threshold voltage of the driving transistor and the voltage drop on the current outputted by the driving transistor can be avoided, so that the current outputted by the driving transistor is kept stable, thereby improving the uniform brightness of the display screen of the display device including the pixel circuit. Sex.
  • Embodiments of the present disclosure also provide a display panel including a plurality of pixel units distributed in an array, each pixel unit including any of the pixel circuits as provided by embodiments of the present disclosure.
  • the principle of the problem of the display panel is similar to that of the foregoing pixel circuit. Therefore, the implementation of the display panel can be referred to the implementation of the pixel circuit described above, and the repeated description is omitted.
  • the display panel may be an organic electroluminescence display panel.
  • Embodiments of the present disclosure also provide a display device including a display panel provided by an embodiment of the present disclosure.
  • the display device 1 includes: a plurality of pixel units 40 distributed in an array, a plurality of first control signal lines, a plurality of second control signal lines, a plurality of light emission control signal lines, and a plurality of pieces of data.
  • Signal line It should be noted that only a part of the pixel unit 40, the first control signal line, the second control signal line, the light emission control signal line, and the data signal line are shown in FIG.
  • S1 N represents the first control signal line of the Nth row
  • S1 N+1 represents the first control signal line of the N+1th row
  • S2 N represents the second control signal line of the Nth row
  • S2 N+1 represents The second control signal line of the N+1th row
  • E N represents the light emission control signal line of the Nth row
  • E N+1 represents the light emission control signal line of the (N+1)th row
  • D M represents the data signal line of the Mth column
  • D M+1 represents the data signal line of the M+1th column.
  • N and M are, for example, integers greater than zero.
  • each of the pixel units 40 may include any of the pixel circuits 10 provided in the above embodiments, including, for example, the pixel circuits shown in FIG.
  • the first control signal line of each row is connected to the first control signal end of the pixel circuit of the row; the second control signal line of each row is connected with the second control signal end of the pixel circuit of the row; the illumination of each row
  • the control signal line is connected to the light emission control signal end of the pixel circuit of the row; the data signal line of each column is connected to the data signal end of the pixel circuit of the column.
  • the display device 1 shown in FIG. 8 may further include a plurality of first power lines and a plurality of second power lines to respectively provide V DD and V SS (not shown).
  • the display device 1 may further include a scan driving circuit 20 and a data driving circuit 30.
  • the data driving circuit 30 may be connected to a plurality of data signal lines (D M , D M+1 , etc.) to provide a data voltage Vdata.
  • the scan driving circuit 20 may be connected to a plurality of first control signal lines (S1 N , S1 N+1 , etc.), a plurality of second control signal lines (S2 N , S2 N+1 , etc.), and a plurality of light emission control signal lines. (E N , E N+1 , etc.) to provide a control signal.
  • the scan driving circuit 20 and the data driving circuit 30 may be implemented as a semiconductor chip.
  • the display device 1 may also include other components such as a timing controller, a signal decoding circuit, a voltage conversion circuit, etc., which may be, for example, conventional conventional components, and will not be described in detail herein.
  • the display device 1 provided by the embodiment of the present disclosure may be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • Other indispensable components of the display device are understood by those skilled in the art, and are not described herein, nor should they be construed as limiting the invention.

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Abstract

一种像素电路及其驱动方法、显示面板和显示装置。该像素电路包括：数据写入电路(1)、补偿控制电路(4)、存储电路(2)、发光控制电路(5)和驱动电路(6)。本公开的像素电路中的驱动电路(6)输出的电流仅与数据信号端(Data)的数据电压和参考电压有关，而与驱动电路(6)的阈值电压以及第二电源端(VSS)的电压无关，可以避免驱动电路(6)的阈值电压以及压降对驱动电路(6)输出的电流的影响，从而使驱动电路(6)输出的电流保持稳定，进而可以提高包括该像素电路的显示装置的显示画面亮度的均匀性。

Description

像素电路及其驱动方法、显示面板和显示装置
本申请要求于2017年7月27日递交的中国专利申请第201710624591.3号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开实施例涉及一种像素电路及其驱动方法、显示面板和显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)是平板显示器研究领域的热点之一，与液晶显示器(Liquid Crystal Display，LCD)相比，OLED显示器具有低能耗、生产成本低、自发光、宽视角及响应速度快等优点。与LCD利用稳定的电压控制亮度不同，OLED采用电流驱动，需要稳定的电流来控制其发光。由于工艺制程和器件老化等原因，会使像素电路中的驱动晶体管的阈值电压Vth存在不均匀性，这样就导致流过每个OLED的电流存在差异导致显示亮度不均，从而影响整个图像的显示效果。并且由于流过每个OLED的电流与驱动晶体管的源极即电源电压相关，由于压降(IR Drop)原因，也会造成不同区域的电流差异，进而造成不同区域的OLED出现亮度不均匀现象。
发明内容
本公开至少一实施例提供一种像素电路，包括：数据写入电路、补偿控制电路、存储电路、发光控制电路和驱动电路。所述数据写入电路分别与第一控制信号端、数据信号端以及第一节点连接；所述数据写入电路用于在所述第一控制信号端的控制下将所述数据信号端的信号提供至所述第一节点。所述存储电路分别与所述第一节点、所述驱动电路的控制端以及所述驱动电路的第二端连接；所述存储电路用于保持所述第一节点与所述驱动电路的控制端之间的电压差，以及保持所述第一节点与所述驱动电路 的第二端的电压差。所述补偿控制电路分别与第二控制信号端、所述驱动电路的控制端以及所述驱动电路的第一端连接；所述补偿控制电路用于在所述第二控制信号端的控制下使所述驱动电路的控制端与所述驱动电路的第一端导通。所述发光控制电路分别与发光控制信号端、第一电源端以及所述驱动电路的第一端连接；所述发光控制电路用于在所述发光控制信号端的控制下将所述第一电源端的信号提供至所述驱动电路。所述驱动电路分别与所述补偿控制电路、所述发光控制电路以及存储电路连接；所述驱动电路用于输出驱动电流。
例如，在本公开一实施例提供的像素电路中，所述存储电路包括第一存储电路和第二存储电路。所述第一存储电路分别与所述第一节点以及所述驱动电路的控制端连接；所述第一存储电路用于保持所述第一节点与所述驱动电路的控制端之间的电压差。所述第二存储电路分别与所述第一节点以及所述驱动电路的第二端连接；所述第二存储电路用于保持所述第一节点与所述驱动电路的第二端的电压差。
例如，本公开一实施例提供的像素电路还包括发光元件。所述发光元件的第一极和所述驱动电路的第二端以及所述存储电路连接，所述发光元件的第二极和第二电源端连接；所述发光元件用于在所述驱动电路输出的驱动电流的作用下进行发光。
例如，在本公开一实施例提供的像素电路中，所述驱动电路包括驱动晶体管。所述驱动晶体管的栅极作为所述驱动电路的控制端和所述存储电路以及所述补偿控制电路连接，所述驱动晶体管的第一极作为所述驱动电路的第一端和所述补偿控制电路以及所述发光控制电路连接，所述驱动晶体管的第二极作为所述驱动电路的第二端和所述存储电路连接。
例如，在本公开一实施例提供的像素电路中，所述第一存储电路包括第一电容。所述第一电容的第一端与所述第一节点连接，所述第一电容的第二端与所述驱动电路的控制端连接。
例如，在本公开一实施例提供的像素电路中，所述第二存储电路包括第二电容。所述第二电容的第一端与所述第一节点连接，所述第二电容的第二端与所述驱动电路的第二端连接。
例如，在本公开一实施例提供的像素电路中，所述第一电容的电容值大于所述第二电容的电容值。
例如，在本公开一实施例提供的像素电路中，所述数据写入电路包括第一开关晶体管。所述第一开关晶体管的栅极与所述第一控制信号端连接，所述第一开关晶体管的第一极与所述数据信号端连接，所述第一开关晶体管的第二极与所述第一节点连接。
例如，在本公开一实施例提供的像素电路中，所述补偿控制电路包括第二开关晶体管。所述第二开关晶体管的栅极与所述第二控制信号端连接，所述第二开关晶体管的第一极与所述驱动电路的控制端连接，所述第二开关晶体管的第二极与所述驱动电路的第一端连接。
例如，在本公开一实施例提供的像素电路中，所述发光控制电路包括第三开关晶体管。所述第三开关晶体管的栅极与所述发光控制信号端连接，所述第三开关晶体管的第一极与所述第一电源端连接，所述第三开关晶体管的第二极与所述驱动电路的第一端连接。
例如，在本公开一实施例提供的像素电路中，所述驱动晶体管为N型晶体管。
例如，在本公开一实施例提供的像素电路中，所述开关晶体管为P型晶体管或N型晶体管。
本公开至少一实施例还提供一种显示面板，包括呈阵列分布的多个像素单元，每个所述像素单元包括如本公开的实施例提供的任一像素电路。
本公开至少一实施例还提供一种显示装置，包括如本公开的实施例提供的显示面板。
例如，本公开一实施例提供的显示装置还包括多条第一控制信号线、多条第二控制信号线、多条发光控制信号线和多条数据信号线。每一行的所述第一控制信号线和本行像素电路中的所述第一控制信号端连接；每一行的所述第二控制信号线和本行像素电路中的所述第二控制信号端连接；每一行的所述发光控制信号线和本行像素电路中的所述发光控制信号端连接；每一列的数据信号线和本列像素电路中的所述数据信号端连接。
本公开至少一实施例还提供一种像素电路的驱动方法，包括：重置与补偿阶段、数据写入阶段和发光阶段。在重置与补偿阶段，所述补偿控制电路在所述第二控制信号端的控制下将所述驱动电路的控制端与所述驱动电路的第一端导通；在数据写入阶段，所述数据写入电路在所述第一控制信号端的控制下将所述数据信号端的信号提供至所述第一节点；在发光阶 段，所述存储电路保持所述第一节点与所述驱动电路的控制端之间的电压差，以及保持所述第一节点与所述驱动电路的第二端的电压差；所述发光控制电路在所述发光控制信号端的控制下将所述第一电源端的信号提供至所述驱动电路；所述驱动电路输出驱动电流。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种像素电路的示意图；
图2为本公开一实施例提供的一种像素电路的示意图；
图3为本公开一实施例提供的另一种像素电路的示意图；
图4为本公开一实施例提供的一种像素电路的具体实现示例的电路图；
图5为本公开一实施例提供的驱动方法的电路时序图；
图6为本公开一实施例提供的一种像素电路的仿真模拟图；
图7为本公开一实施例提供的一种像素电路的驱动方法的流程示意图；以及
图8为本公开一实施例提供的一种显示装置的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者 物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。此外，本公开实施例所采用的开关晶体管可以包括P型开关晶体管和N型开关晶体管中的任一种，其中，P型开关晶体管在栅极为低电平时导通，在栅极为高电平时截止，N型开关晶体管在栅极为高电平时导通，在栅极为低电平时截止。
在一种像素电路中，如图1所示，该像素电路由一个驱动晶体管M0，一个开关晶体管M和一个存储电容Cs组成。当扫描线Scan选择某一行时，扫描线Scan输入低电平信号，P型的开关晶体管M导通，数据线Data上的电压写入存储电容Cs；当该行扫描结束后，扫描线Scan输入的信号变为高电平，P型的开关晶体管M关断，存储电容Cs存储的栅极电压使驱动晶体管M0产生电流来驱动OLED，保证OLED在一帧内持续发光。其中，驱动晶体管M0的饱和电流公式为I OLED＝K(Vsg-Vth) 2，由于工艺制程和器件老化等原因，驱动晶体管M0的阈值电压Vth可能会发生漂移，并且由于电流与电源电压相关，由于压降(IR Drop)原因，驱动晶体管的源极电压Vs也会不同，这样就导致流过每个OLED的电流因驱动晶体管的阈值电压Vth和驱动晶体管的源极电压的变化而变化，从而导致图像亮度不均匀。
本公开至少一实施例提供一种像素电路，其包括数据写入电路、补偿控制电路、第一存储电路、第二存储电路、发光控制电路和驱动电路。本公开至少一实施例还提供对应于该像素电路的驱动方法、显示面板以及显示装置。
本公开的实施例提供的像素电路、显示面板、显示装置以及驱动方法， 可以使像素电路中的驱动电路输出的电流仅与数据信号端的数据电压和参考电压有关，而与驱动电路的阈值电压无关，可以避免驱动电路的阈值电压对驱动电路输出的电流的影响，从而使驱动电路输出的电流保持稳定，进而可以提高包括该像素电路的显示装置的显示画面亮度的均匀性。
下面结合附图对本公开的实施例进行详细说明。
本公开的至少一个实施例提供一种像素电路，如图2所示，该像素电路包括：数据写入电路1、存储电路2、补偿控制电路4、发光控制电路5和驱动电路6。
数据写入电路1分别与第一控制信号端G1、数据信号端Data以及第一节点A连接；数据写入电路1用于在第一控制信号端G1的控制下将数据信号端Data的信号提供至第一节点A，例如数据信号端Data的信号为控制像素明暗程度的数据电压。
存储电路2分别与第一节点A、驱动电路6的控制端60以及驱动电路6的第二端62连接。存储电路2用于保持第一节点A与驱动电路6的控制端60之间的电压差，以及保持第一节点A与驱动电路6的第二端62的电压差。
补偿控制电路4分别与第二控制信号端G2、驱动电路6的控制端60以及驱动电路6的第一端61连接，补偿控制电路4用于在第二控制信号端G2的控制下使驱动电路6的控制端60与驱动电路6的第一端61导通。
发光控制电路5分别与发光控制信号端EM、第一电源端VDD以及驱动电路6的第一端61连接，发光控制电路5用于在发光控制信号端EM的控制下将第一电源端VDD的信号提供至驱动电路6，例如提供至驱动电路6的第一端61。
驱动电路6分别与补偿控制电路4、发光控制电路5以及存储电路2连接，驱动电路6用于输出驱动电流。例如，驱动电路6由第二端62输出该驱动电流，例如该驱动电流可以用于驱动发光元件进行发光。
本公开的实施例提供的像素电路，包括数据写入电路、补偿控制电路、存储电路、发光控制电路和驱动电路。数据写入电路用于在第一控制信号端的控制下将数据信号端的信号提供至第一节点；存储电路用于保持第一节点与驱动电路的控制端之间的电压差，以及保持第一节点与驱动电路的第二端的电压差；补偿控制电路用于在第二控制信号端的控制下使驱动电 路的控制端与驱动电路的第一端导通；发光控制电路用于在发光控制信号端的控制下将第一电源端的信号提供至驱动电路；驱动电路用于输出驱动电流。因此通过上述五个电路的相互配合，可以使像素电路中的驱动电路输出的电流仅与数据信号端的数据电压和参考电压有关，而与驱动电路的阈值电压以及第二电源端的电压无关，可以避免驱动晶体管的阈值电压以及压降对驱动电路输出的电流的影响，从而使驱动电路输出的电流保持稳定，进而可以提高包括该像素电路的显示装置的显示画面亮度的均匀性。
例如，在本公开的一个实施例中，如图2所示，存储电路2可以包括第一存储电路21和第二存储电路22，
第一存储电路21分别与第一节点A以及驱动电路6的控制端60连接，第一存储电路21用于保持第一节点A与驱动电路6的控制端60之间的电压差。
第二存储电路22分别与第一节点A以及驱动电路6的第二端62连接，第二存储电路22用于保持第一节点A与驱动电路6的第二端62的电压差。
例如，在本公开的一个实施例中，如图3所示，像素电路还可以包括发光元件LE。发光元件LE的第一极和驱动电路6的第二端62以及第二存储电路3连接，发光元件LE的第二极和第二电源端VSS连接。发光元件LE用于在驱动电路6输出的驱动电流的作用下进行发光。例如，发光元件LE在驱动电路处于饱和状态时的电流的作用下实现发光。
例如，发光元件LE可以采用有机发光二极管(OLED)，本公开的实施例包括但不限于此，以下各实施例均以OLED为例进行说明，不再赘述。例如，在发光元件LE采用OLED的情形下，该OLED的阳极可以与驱动电路6的第二端62连接，该OLED的阴极可以与第二电源端VSS连接。需要说明的是，该OLED可以为各种类型，例如顶发射、底发射等，可以发红光、绿光、蓝光或白光等，本公开的实施例对此不作限制。另外，OLED也具有阈值电压，在OLED两端的电压大于或等于阈值电压时进行发光。
需要说明的是，在本公开的实施例提供的像素电路中，第一电源端VDD的电压为高电平电压，第二电源端VSS的电压接地或为低电平电压，以下各实施例与此相同，不再赘述。
例如，图3中所示的像素电路可以具体实现为图4所示的像素电路结构。如图4所示，该像素电路包括驱动晶体管M0、第一开关晶体管M1、 第二开关晶体管M2、第三开关晶体管M3、第一电容C1、第二电容C2和发光元件OLED。该像素电路中的晶体管均以N型晶体管为例进行说明。
例如，如图4所示，更详细地，驱动电路6可以实现为驱动晶体管M0。驱动晶体管M0的栅极作为驱动电路6的控制端60和第一存储电路21以及补偿控制电路4连接，驱动晶体管M0的第一极作为驱动电路6的第一端61和补偿控制电路4以及发光控制电路5连接，驱动晶体管M0的第二极作为驱动电路6的第二端62和第二存储电路22连接。
第一存储电路21可以实现为第一电容C1。第一电容C1的第一端与第一节点A连接，第一电容C1的第二端与驱动电路6的控制端连接。例如，在驱动电路6实现为驱动晶体管M0时，第一电容C1的第二端可以和驱动晶体管M0的栅极连接。
在本公开的实施例提供的像素电路中，第一电容C1在第一节点A的信号和驱动晶体管M0的栅极的信号的共同控制下进行充电；并在第一节点A的信号和驱动晶体管M0的栅极的信号的共同控制下进行放电；以及在驱动晶体管M0的栅极处于浮接状态时，保持第一节点A和驱动晶体管M0的栅极之间的电压差稳定，以将驱动晶体管M0的阈值电压Vth和数据信号端Data输入的数据电压存储于驱动晶体管M0的栅极上。
以上仅是举例说明像素电路中第一存储电路21的具体结构，在具体实施时，第一存储电路21的具体结构不限于本公开的实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不做限定。
例如，如图4所示，第二存储电路22可以实现为第二电容C2。第二电容C2的第一端与第一节点A连接，第二电容C2的第二端与驱动电路6的第二端连接。例如，在驱动电路6实现为驱动晶体管M0时，第二电容C2的第二端可以和驱动晶体管M0的第二极连接。例如，第二电容C2的第二端还可以和发光元件OLED的阳极连接。
在本公开的实施例提供的像素电路中，第二电容C2在第一节点A的信号与驱动晶体管M0的第二极的信号的共同控制下进行充电，并在第一节点A的信号和驱动晶体管M0的第二极的信号的共同控制下进行放电；以及在发光元件OLED处于发光状态时保持第一节点A与驱动晶体管M0的第二极之间的电压差稳定，以保证驱动晶体管M0输出稳定的驱动电流。
以上仅是举例说明像素电路中第二存储电路22的具体结构，在具体 实施时，第二存储电路22的具体结构不限于本公开的实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不做限定。
在本公开的实施例提供的像素电路中，由于第一电容C1要长时间保持驱动晶体管M0的栅极与第一节点A之间的电压差稳定，以保证流向发光元件OLED的电流恒定，因此第一电容C1的电容值相对较大。而为了减小空间占用面积，第二电容C2的电容值相对较小。因此，在本公开的一个实施例提供的像素电路中，第一电容C1的电容值可以大于第二电容C2的电容值。
例如，如图4所示，数据写入电路1可以实现为第一开关晶体管M1。第一开关晶体管M1的栅极与第一控制信号端G1连接，第一开关晶体管M1的第一极与数据信号端Data连接，第一开关晶体管M1的第二极与第一节点A连接。
在本公开的实施例提供的像素电路中，例如第一开关晶体管M1在第一控制信号端G1的控制下处于导通状态时，可以将数据信号端Data的信号提供至第一节点A。
以上仅是举例说明像素电路中数据写入电路1的具体结构，在具体实施时，数据写入电路1的具体结构不限于本公开的实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不做限定。
例如，如图4所示，补偿控制电路4可以实现为第二开关晶体管M2。第二开关晶体管M2的栅极与第二控制信号端G2连接，第二开关晶体管M2的第一极与驱动电路6的控制端连接，第二开关晶体管M2的第二极与驱动电路6的第一端连接。例如，在驱动电路6实现为驱动晶体管M0时，第二开关晶体管M2的第一极可以与驱动晶体管M0的栅极连接，第二开关晶体管M2的第二极可以与驱动晶体管M0的第一极连接。
在本公开的实施例提供的像素电路中，例如第二开关晶体管M2可以在第二控制信号端G2的控制下，将驱动晶体管M0的栅极与驱动晶体管M0的第一极导通，以控制驱动晶体管M0处于二极管连接状态。
以上仅是举例说明像素电路中补偿控制电路4的具体结构，在具体实施时，补偿控制电路4的具体结构不限于本公开的实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不做限定。
例如，如图4所示，发光控制电路5可以实现为第三开关晶体管M3。 第三开关晶体管M3的栅极与发光控制信号端EM连接，第三开关晶体管M3的第一极与第一电源端VDD连接，第三开关晶体管M3的第二极与驱动电路的第一端连接。例如，在驱动电路6实现为驱动晶体管M0时，第三开关晶体管M3的第二极可以与驱动晶体管M0的第一极连接。
在本公开的实施例提供的像素电路中，例如第三开关晶体管M3在发光控制信号端EM的控制下，可以将第一电源端VDD的电压提供至驱动晶体管M0的第一极，将驱动晶体管M0的第二极输出的驱动电流输出至例如发光元件OLED以驱动其发光。
以上仅是举例说明像素电路中发光控制电路5的具体结构，在具体实施时，发光控制电路5的具体结构不限于本公开的实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不做限定。
例如，在本公开的实施例提供的像素电路中，驱动晶体管M0为N型晶体管。需要说明的是，在本公开的实施例提供的像素电路中，第一开关晶体管M1、第二开关晶体管M2以及第三开关晶体管M3除了可以采用如图4中所示的N型晶体管外，还可以都采用P型晶体管或者可以混合采用P型晶体管和N型晶体管，只需同时将选定类型的晶体管的端口极性按照本公开的实施例中的相应晶体管的端口极性相应连接即可。
较佳地，在具体实施时，在本公开的实施例提供的像素电路中，如图4所示，驱动晶体管M0和所有开关晶体管M1-M3均为N型晶体管。
在具体实施时，在本公开的实施例提供的像素电路中，N型开关晶体管在高电位作用下导通，在低电位作用下截止。
下面以图4所示的像素电路为例，结合图5所示的电路时序图对本公开的实施例提供的像素电路的工作原理进行描述。需要说明的是，在以下描述中以1表示高电位，0表示低电位。1和0是逻辑电位，其仅是为了更好的解释本公开的实施例提供的像素电路的工作原理，而不是施加在各开关晶体管的栅极上的电位。
如图4所示，驱动晶体管M0为N型晶体管，所有开关晶体管均为N型晶体管，对应的时序图如图5所示。具体地，选取如图5所示的时序图中的重置与补偿阶段T1、数据写入阶段T2以及发光阶段T3三个阶段进行描述。
在重置与补偿阶段T1，G1＝1，G2＝1，EM＝0。
第一开关晶体管M1、第二开关晶体管M2和驱动晶体管M0均处于导通状态，第三开关晶体管M3处于截止状态。此阶段数据信号端Data的电压为参考电压Vref，从而导通的第一开关晶体管M1将数据信号端Data的参考电压Vref提供至第一节点A，因此第一节点A的电压V A＝Vref，即实现了第一节点A的电压的重置。导通的第二开关晶体管M2可以将驱动晶体管M0的栅极与其第一极导通，使驱动晶体管M0处于二极管连接状态，因此驱动晶体管M0的栅极和源极的电压通过发光元件OLED被释放，即实现了像素电路的重置。发光元件OLED的阳极的电压即驱动晶体管M0的源极的电压Vs为第二电源端VSS的电压V SS和发光元件OLED的阈值电压Voled0之和，即Vs＝V SS+Voled0。由于驱动晶体管M0在该阶段处于二极管连接状态，所以驱动晶体管M0的栅极的电压Vg为驱动晶体管M0的源极的电压加上驱动晶体管M0的阈值电压Vth，即Vg＝V SS+Voled0+Vth，从而可以实现将驱动晶体管M0的阈值电压Vth写入驱动晶体管M0的栅极。
在数据写入阶段T2，G1＝1，G2＝0，EM＝0。第一开关晶体管M1和驱动晶体管M0均处于导通状态，第二开关晶体管M2和第三开关晶体管M3均处于截止状态。例如在此阶段数据信号端Data写入的电压为Vdata，即导通的第一开关晶体管M1将数据信号端Data的电压Vdata提供至第一节点A，因此第一节点A的电压V A由上一阶段的Vref变为Vdata。由于第一电容C1的耦合作用，驱动晶体管M0的栅极的电压Vg变为Vg＝V SS+Voled0+Vth+Vdata-Vref。
在发光阶段T3，G1＝0，G2＝0，EM＝1。第三开关晶体管M3和驱动晶体管M0均处于导通状态，第一开关晶体管M1和第二开关晶体管M2处于截止状态。发光元件OLED开始发光，发光元件OLED的阳极的电压为V SS+Voled，即驱动晶体管M0的源极的电压Vs＝V SS+Voled，Voled为发光器件OLED发光时的电压。在此阶段中，由于第二电容C2的耦合作用，第二电容C2第二端的电压变化会耦合至第二电容C2的第一端即第一节点A，所以第一节点A的电压变为V A＝Vdata+Voled-Voled0。同时又由于第一电容C1的耦合作用，驱动晶体管M0的栅极的电压变为Vg＝V SS+Voled0+Vth+Vdata-Vref+Voled-Voled0＝V SS+Voled+Vth+Vdata-Vref。驱动晶体管M0的第一极电压为第一电源端VDD的电压V DD，驱动晶体 管M0处于饱和状态，根据饱和状态电流特性可知，流过驱动晶体管M0且用于驱动发光元件OLED发光的工作电流I OLED满足公式：
I OLED＝K(Vgs–Vth) 2
＝K(V SS+Voled+Vth+Vdata-Vref-V SS-Voled–Vth) 2
＝K(Vdata-Vref) 2；
其中K为结构参数，相同结构中此数值相对稳定，可以算作常量。从而可以看出发光元件OLED的工作电流I OLED可以不受驱动晶体管M0的阈值电压Vth的影响，且和第二电源端VSS的电压V SS无关，仅与数据信号端Data的数据电压Vdata和参考电压Vref有关，解决了由于工艺制程以及长时间的操作造成的驱动晶体管M0的阈值电压Vth漂移以及压降(IR Drop)对发光元件OLED的工作电流I OLED造成的影响。同时I OLED还和发光元件OLED的阈值电压Voled0和工作电压Voled无关，可以避免由于OLED的老化带来的电流差异，从而改善了面板显示的不均匀性。并且本公开的实施例提供的像素电路仅采用了4个晶体管和2个电容就可以实现对驱动晶体管M0的阈值电压Vth进行补偿，结构比较简单。
并且，当驱动晶体管M0的阈值电压Vth取不同值时，本公开还对上述实施例提供的像素电路在三个阶段进行了仿真模拟，仿真结果如图6所示。当驱动晶体管M0的阈值电压Vth分别为Vth＝1和Vth＝2时，由图6的仿真结果可以看出，流过发光元件OLED的驱动电流基本上是重合的，取图中T3阶段任一时刻如1.2447ms时刻时流过发光元件OLED的工作电流I OLED，当驱动晶体管M0的阈值电压Vth＝1时，I OLED1＝4.842uA；当驱动晶体管M0的阈值电压Vth＝2时，I OLED2＝4.8416uA；I OLED1与I OLED2近似相等，因此可以验证在本公开的实施例提供的像素电路中，发光元件OLED的工作电流I OLED可以不受驱动晶体管M0的阈值电压Vth的影响。
本公开的实施例还提供一种驱动方法，该驱动方法可以用于本公开的实施例提供的任一种像素电路，例如如图7所示，该驱动方法包括如下操作步骤。
步骤S701：在重置与补偿阶段，补偿控制电路在第二控制信号端的控制下将驱动电路的控制端与驱动电路的第一端导通；
步骤S702：在数据写入阶段，数据写入电路在第一控制信号端的控制下将数据信号端的信号提供至第一节点；以及
步骤S703：在发光阶段，存储电路保持第一节点与驱动电路的控制端之间的电压差，以及保持第一节点与驱动电路的第二端的电压差；发光控制电路在发光控制信号端的控制下将第一电源端的信号提供至驱动电路；驱动电路输出驱动电流。
需要说明的是，本公开的实施例提供的像素电路的驱动方法的详细描述可以参考关于像素电路的工作原理的相应描述，这里不再赘述。
本公开的实施例提供的像素电路的驱动方法，可以使像素电路中的驱动晶体管驱动发光元件发光的工作电流仅与数据信号端的数据电压和参考电压有关，而与驱动晶体管的阈值电压以及第二电源端的电压无关，可以避免驱动晶体管的阈值电压以及压降对驱动晶体管输出的电流的影响，从而使驱动晶体管输出的电流保持稳定，进而可以提高包括该像素电路的显示装置的显示画面亮度的均匀性。
本公开的实施例还提供一种显示面板，该显示面板包括呈阵列分布的多个像素单元，每个像素单元包括如本公开的实施例提供的任一像素电路。该显示面板解决问题的原理与前述的像素电路相似，因此该显示面板的实施可以参见上述像素电路的实施，重复之处不再赘述。
在具体实施时，在本公开的实施例提供的显示面板中，显示面板可以为有机电致发光显示面板。
本公开的实施例还提供一种显示装置，该显示装置包括本公开的实施例提供的显示面板。
例如，如图8所示，该显示装置1包括：呈阵列分布的多个像素单元40，多条第一控制信号线、多条第二控制信号线、多条发光控制信号线和多条数据信号线。需要说明的是，在图8中仅示出了部分的像素单元40、第一控制信号线、第二控制信号线、发光控制信号线和数据信号线。例如，S1 N表示第N行的第一控制信号线，S1 N+1表示第N+1行的第一控制信号线，S2 N表示第N行的第二控制信号线，S2 N+1表示第N+1行的第二控制信号线，E N表示第N行的发光控制信号线，E N+1表示第N+1行的发光控制信号线，D M表示第M列的数据信号线，D M+1表示第M+1列的数据信号线。这里，N与M例如为大于0的整数。
例如，每个像素单元40可以包括上述实施例中提供的任一像素电路10，例如包括图4中所示的像素电路。
例如，每一行的第一控制信号线和本行像素电路中的第一控制信号端连接；每一行的第二控制信号线和本行像素电路中的第二控制信号端连接；每一行的发光控制信号线和本行像素电路中的发光控制信号端连接；每一列的数据信号线和本列像素电路中的数据信号端连接。
需要说明的是，图8所示的显示装置1还可以包括多条第一电源线和多条第二电源线以分别提供V DD和V SS(图中未示出)。
例如，如图8所示，该显示装置1还可以包括扫描驱动电路20和数据驱动电路30。
例如，数据驱动电路30可以与多条数据信号线(D M、D M+1等)连接，以提供数据电压Vdata。例如，扫描驱动电路20可以与多条第一控制信号线(S1 N、S1 N+1等)、多条第二控制信号线(S2 N、S2 N+1等)和多条发光控制信号线(E N、E N+1等)以提供控制信号。
例如，扫描驱动电路20和数据驱动电路30可以实现为半导体芯片。该显示装置1还可以包括其他部件，例如时序控制器、信号解码电路、电压转换电路等，这些部件例如可以采用已有的常规部件，这里不再详述。
例如，本公开的实施例提供的显示装置1可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本发明的限制。该显示装置的实施可以参见上述像素电路的实施例，重复之处不再赘述。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (16)

  1. 一种像素电路，包括：数据写入电路、补偿控制电路、存储电路、发光控制电路和驱动电路；其中，
    所述数据写入电路分别与第一控制信号端、数据信号端以及第一节点连接；所述数据写入电路用于在所述第一控制信号端的控制下将所述数据信号端的信号提供至所述第一节点；
    所述存储电路分别与所述第一节点、所述驱动电路的控制端以及所述驱动电路的第二端连接；所述存储电路用于保持所述第一节点与所述驱动电路的控制端之间的电压差，以及保持所述第一节点与所述驱动电路的第二端的电压差；
    所述补偿控制电路分别与第二控制信号端、所述驱动电路的控制端以及所述驱动电路的第一端连接；所述补偿控制电路用于在所述第二控制信号端的控制下使所述驱动电路的控制端与所述驱动电路的第一端导通；
    所述发光控制电路分别与发光控制信号端、第一电源端以及所述驱动电路的第一端连接；所述发光控制电路用于在所述发光控制信号端的控制下将所述第一电源端的信号提供至所述驱动电路；
    所述驱动电路分别与所述补偿控制电路、所述发光控制电路以及所述存储电路连接；所述驱动电路用于输出驱动电流。
  2. 如权利要求1所述的像素电路，其中，所述存储电路包括第一存储电路和第二存储电路，
    所述第一存储电路分别与所述第一节点以及所述驱动电路的控制端连接；所述第一存储电路用于保持所述第一节点与所述驱动电路的控制端之间的电压差；
    所述第二存储电路分别与所述第一节点以及所述驱动电路的第二端连接；所述第二存储电路用于保持所述第一节点与所述驱动电路的第二端的电压差。
  3. 如权利要求1所述的像素电路，还包括发光元件，其中，
    所述发光元件的第一极和所述驱动电路的第二端以及所述存储电路连接，所述发光元件的第二极和第二电源端连接；所述发光元件用于在所述驱动电路输出的驱动电流的作用下进行发光。
  4. 如权利要求1所述的像素电路，其中，所述驱动电路包括驱动晶体管，
    所述驱动晶体管的栅极作为所述驱动电路的控制端和所述存储电路以及所述补偿控制电路连接，所述驱动晶体管的第一极作为所述驱动电路的第一端和所述补偿控制电路以及所述发光控制电路连接，所述驱动晶体管的第二极作为所述驱动电路的第二端和所述存储电路连接。
  5. 如权利要求2所述的像素电路，其中，所述第一存储电路包括第一电容，
    所述第一电容的第一端与所述第一节点连接，所述第一电容的第二端与所述驱动电路的控制端连接。
  6. 如权利要求5所述的像素电路，其中，所述第二存储电路包括第二电容，
    所述第二电容的第一端与所述第一节点连接，所述第二电容的第二端与所述驱动电路的第二端连接。
  7. 如权利要求6所述的像素电路，其中，所述第一电容的电容值大于所述第二电容的电容值。
  8. 如权利要求1所述的像素电路，其中，所述数据写入电路包括第一开关晶体管，
    所述第一开关晶体管的栅极与所述第一控制信号端连接，所述第一开关晶体管的第一极与所述数据信号端连接，所述第一开关晶体管的第二极与所述第一节点连接。
  9. 如权利要求1所述的像素电路，其中，所述补偿控制电路包括第二开关晶体管，
    所述第二开关晶体管的栅极与所述第二控制信号端连接，所述第二开关晶体管的第一极与所述驱动电路的控制端连接，所述第二开关晶体管的第二极与所述驱动电路的第一端连接。
  10. 如权利要求1所述的像素电路，其中，所述发光控制电路包括第三开关晶体管，
    所述第三开关晶体管的栅极与所述发光控制信号端连接，所述第三开关晶体管的第一极与所述第一电源端连接，所述第三开关晶体管的第二极与所述驱动电路的第一端连接。
  11. 如权利要求4所述的像素电路，其中，所述驱动晶体管为N型晶体管。
  12. 如权利要求8-10任一项所述的像素电路，其中，所述开关晶体管为P型晶体管或N型晶体管。
  13. 一种显示面板，包括呈阵列分布的多个像素单元，其中，每个所述像素单元包括如权利1-12任一项所述的像素电路。
  14. 一种显示装置，包括如权利要求13所述的显示面板。
  15. 如权利要求14所述的显示装置，还包括：多条第一控制信号线、多条第二控制信号线、多条发光控制信号线和多条数据信号线；其中，
    每一行的所述第一控制信号线和本行像素电路中的所述第一控制信号端连接；每一行的所述第二控制信号线和本行像素电路中的所述第二控制信号端连接；每一行的所述发光控制信号线和本行像素电路中的所述发光控制信号端连接；每一列的数据信号线和本列像素电路中的所述数据信号端连接。
  16. 一种如权利要求1-12任一项所述的像素电路的驱动方法，包括：重置与补偿阶段、数据写入阶段和发光阶段；其中，
    在重置与补偿阶段，所述补偿控制电路在所述第二控制信号端的控制下将所述驱动电路的控制端与所述驱动电路的第一端导通；
    在数据写入阶段，所述数据写入电路在所述第一控制信号端的控制下将所述数据信号端的信号提供至所述第一节点；
    在发光阶段，所述存储电路保持所述第一节点与所述驱动电路的控制端之间的电压差，以及保持所述第一节点与所述驱动电路的第二端的电压差；所述发光控制电路在所述发光控制信号端的控制下将所述第一电源端的信号提供至所述驱动电路；所述驱动电路输出驱动电流。
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KR20190025812A (ko) 2019-03-12
JP2020528154A (ja) 2020-09-17

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