WO2024093288A1 - 芯片、芯片堆叠结构、芯片封装结构以及电子设备 - Google Patents

芯片、芯片堆叠结构、芯片封装结构以及电子设备 Download PDF

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Publication number
WO2024093288A1
WO2024093288A1 PCT/CN2023/103154 CN2023103154W WO2024093288A1 WO 2024093288 A1 WO2024093288 A1 WO 2024093288A1 CN 2023103154 W CN2023103154 W CN 2023103154W WO 2024093288 A1 WO2024093288 A1 WO 2024093288A1
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Prior art keywords
chip
dielectric layer
wafer
isolation ring
metal
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PCT/CN2023/103154
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English (en)
French (fr)
Inventor
董金文
朱继锋
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华为技术有限公司
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Publication of WO2024093288A1 publication Critical patent/WO2024093288A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers

Definitions

  • the present application relates to the field of semiconductor technology, and in particular to a chip, a chip stacking structure, a chip packaging structure and an electronic device.
  • one of the 3D stacking packaging technologies is to use through silicon vias (TSV) to construct a chip stacking structure, which includes two or more vertically stacked chips. Any two chips in the two or more vertically stacked chips can be electrically connected through silicon vias.
  • TSV through silicon vias
  • the silicon via can be set in the first chip, and the second chip is electrically connected to the silicon via. Then, the signal can be transmitted between the first chip and the second chip through the silicon via.
  • Embodiments of the present application provide a chip, a chip stacking structure, a chip packaging structure, and an electronic device.
  • the vias in the chip such as through silicon vias (TSV), generate smaller parasitic capacitance when passing an AC signal, thereby improving the signal transmission performance of the chip.
  • TSV through silicon vias
  • a chip including a wafer; a via is provided in the wafer, a metal line is provided in the via, and a first dielectric layer is provided between the metal line and the wafer; the wafer also includes a first isolation ring surrounding the via, and the dielectric constant of the first isolation ring is less than the dielectric constant of the material of the first dielectric layer.
  • the metal line in the via, the wafer and the first dielectric layer will constitute a capacitor C1, wherein one electrode of the capacitor C1 is the metal line in the via, the other electrode of the capacitor C1 is the wafer, and the dielectric material between the two electrodes of the capacitor C1 is the first dielectric layer.
  • the first isolation ring and the wafers on both sides of the first isolation ring will also constitute a capacitor C2, wherein one electrode of the capacitor C2 is the wafer on one side of the first isolation ring, and the other electrode of the capacitor C2 is the wafer on the other side of the first isolation ring.
  • the capacitor C2 The dielectric material between the two electrodes is a first isolation ring, wherein, since the dielectric constant of the first isolation ring is smaller than the dielectric constant of the material of the first dielectric layer, the capacitance value of capacitor C2 will be smaller than the capacitance value of capacitor C1.
  • the first isolation ring includes an air gap.
  • the dielectric constant of the air gap is lower, thereby further reducing the capacitance value of the capacitor C2, further reducing the parasitic capacitance between the via and the electronic components arranged in the wafer in the chip, thereby improving the signal transmission performance of the chip.
  • the wafer also includes a second isolation ring surrounding the first isolation ring, and the dielectric constant of the second isolation ring is smaller than the dielectric constant of the material of the first dielectric layer.
  • the second isolation ring surrounds the first isolation ring
  • the second isolation ring and the wafers on both sides of the second isolation ring will also form a capacitor C3, wherein one electrode of capacitor C3 is the wafer on one side of the second isolation ring, the other electrode of capacitor C3 is the wafer on the other side of the second isolation ring, and the dielectric material between the two electrodes of capacitor C3 is the second isolation ring, wherein, since the dielectric constant of the second isolation ring is smaller than the dielectric constant of the material of the first dielectric layer, the capacitance value of capacitor C3 will be smaller than the capacitance value of capacitor C1, then, when the signal is transmitted through the via, it is equivalent to the via and the dielectric constant between the via and the wafer.
  • Capacitors C1, C2 and C3 are connected in series between the electronic components in the chip. The equivalent capacitance after the series connection will be reduced again, so that the parasitic capacitance between the via and the electronic components in the chip is also reduced again, so that the signal transmission performance of the chip is higher.
  • the second isolation ring includes an air gap.
  • the dielectric constant of the air gap is lower, thereby further reducing the capacitance value of the capacitor C3, further reducing the parasitic capacitance between the via and the electronic components arranged in the wafer in the chip, thereby improving the signal transmission performance of the chip.
  • the distance between the first isolation ring and the via hole is greater than or equal to 0.5 microns.
  • a ring width of the first isolation ring is greater than or equal to 0.1 micrometer and less than or equal to 1 micrometer.
  • a diameter of the first via hole is greater than or equal to 1 micron.
  • the material of the metal circuit includes copper or tungsten.
  • the chip further includes a second dielectric layer, which is disposed on one side of the wafer, and the metal line is electrically connected to the metal wiring in the second dielectric layer.
  • a chip stacking structure in a second aspect, includes a plurality of stacked chips, wherein the plurality of stacked chips include the chip as described in any one of the above-mentioned first aspect.
  • the plurality of stacked chips include a first chip and a second chip; the first chip and the second chip both include a second dielectric layer disposed on one side of the wafer; in the plurality of stacked chips, the wafer of the first chip is disposed between the second dielectric layer of the first chip and the second dielectric layer of the second chip, and the second dielectric layer of the first chip is disposed between the wafer of the first chip and the wafer of the second chip; one end of the metal line of the first chip is electrically connected to the metal wiring in the second dielectric layer of the first chip, and the other end of the metal line of the first chip is electrically connected to the metal wiring in the second dielectric layer of the second chip.
  • one or more metal wirings are disposed in the second dielectric layer of the first chip, and the metal wirings in the second dielectric layer of the first chip are electrically connected to the electronic components disposed in the wafer of the first chip to form a circuit structure, then the active surface of the first chip is located on the side of the second dielectric layer of the first chip away from the wafer of the first chip; one or more metal wirings are disposed in the second dielectric layer of the second chip, and the metal wirings in the second dielectric layer of the second chip are electrically connected to the electronic components disposed in the wafer of the second chip to form a circuit structure, then the active surface of the second chip is located on the side of the second dielectric layer of the second chip away from the wafer of the second chip.
  • the wafer of the first chip is arranged between the second dielectric layer of the first chip and the second dielectric layer of the second chip, and the second dielectric layer of the first chip is arranged between the wafer of the first chip and the wafer of the second chip, so the active surface of the second chip is bonded to the passive surface of the first chip, and this bonding method is also called face-to-back bonding.
  • one end of the metal line of the first chip is electrically connected to the metal wiring in the second dielectric layer of the first chip, and the other end of the metal line of the first chip is electrically connected to the metal wiring in the second dielectric layer of the second chip, so the signal received by the active surface of the first chip can be transmitted to the active surface of the second chip through the metal wiring of the second dielectric layer of the first chip and the metal line in the via of the first chip, and then transmitted to the electronic components arranged in the wafer of the second chip through the metal wiring of the second dielectric layer of the second chip; or the signal received by the active surface of the second chip can be transmitted to the active surface of the first chip through the metal wiring of the second dielectric layer of the second chip and the metal line in the via of the first chip, and then transmitted to the electronic components arranged in the wafer of the first chip through the metal wiring of the second dielectric layer of the first chip.
  • signal communication between the second chip and the first chip is electrically connected to the metal wiring in the second dielectric layer of the first chip, and
  • the plurality of stacked chips include a first chip and a second chip; the first chip and the second chip both include a second dielectric layer disposed on one side of a wafer; in the plurality of stacked chips, the second dielectric layer of the second chip and the second dielectric layer of the first chip are disposed between the wafer of the first chip and the wafer of the second chip; one end of the metal line of the first chip is electrically connected to the metal wiring in the second dielectric layer of the first chip, and the metal wiring in the second dielectric layer of the first chip is electrically connected to the metal wiring in the second dielectric layer of the second chip.
  • one or more metal wirings are disposed in the second dielectric layer of the first chip, and the metal wirings in the second dielectric layer of the first chip are electrically connected to the electronic components disposed in the wafer of the first chip to form a circuit structure, then the active surface of the first chip is located on the side of the second dielectric layer of the first chip away from the wafer of the first chip; one or more metal wirings are disposed in the second dielectric layer of the second chip, and the metal wirings in the second dielectric layer of the second chip are electrically connected to the electronic components disposed in the wafer of the second chip to form a circuit structure, then the active surface of the second chip is located on the side of the second dielectric layer of the second chip away from the wafer of the second chip.
  • the second dielectric layer of the second chip and the second dielectric layer of the first chip are arranged between the wafer of the first chip and the wafer of the second chip, so that the active surface of the second chip is bonded to the active surface of the first chip, and this bonding method is also called face-to-face bonding.
  • one end of the metal line of the first chip is electrically connected to the metal wiring in the second dielectric layer of the first chip, and the metal wiring in the second dielectric layer of the first chip is electrically connected to the metal wiring in the second dielectric layer of the second chip.
  • the first chip and the second chip are connected by metal wiring, so the signal received by the active surface of the first chip can be transmitted to the active surface of the second chip through the metal wiring of the second dielectric layer of the first chip, and then transmitted to the electronic components set in the wafer of the second chip through the metal wiring of the second dielectric layer of the second chip; or, the signal received by the active surface of the second chip can be transmitted to the active surface of the first chip through the metal wiring of the second dielectric layer of the second chip, and then transmitted to the electronic components set in the wafer of the first chip through the metal wiring of the second dielectric layer of the first chip, which means that the second chip and the first chip can achieve signal intercommunication.
  • the signal when some signals are transmitted to the active surface of the first chip through the passive surface of the first chip, the signal is transmitted to the active surface of the first chip through the metal line in the via of the first chip, and then transmitted to the electronic components set in the wafer of the first chip through the metal wiring in the second dielectric layer of the first chip. Since the first chip and the second chip can achieve signal intercommunication, the signal transmitted to the active surface of the first chip through the passive surface of the first chip can also be transmitted to the active surface of the second chip.
  • the plurality of stacked chips include a first chip and a second chip; the first chip and the second chip both include a second dielectric layer disposed on one side of the wafer; in the plurality of stacked chips, the wafer of the second chip and the wafer of the first chip are disposed between the second dielectric layer of the first chip and the second dielectric layer of the second chip; one end of the metal line of the first chip is electrically connected to the metal wiring in the second dielectric layer of the first chip, one end of the metal line of the second chip is electrically connected to the metal wiring in the second dielectric layer of the second chip, and the other end of the metal line of the first chip is electrically connected to the other end of the metal line of the second chip.
  • one or more metal wirings are disposed in the second dielectric layer of the first chip, and the metal wirings in the second dielectric layer of the first chip are electrically connected to the electronic components disposed in the wafer of the first chip to form a circuit structure, then the active surface of the first chip is located on the side of the second dielectric layer of the first chip away from the wafer of the first chip; one or more metal wirings are disposed in the second dielectric layer of the second chip, and the metal wirings in the second dielectric layer of the second chip are electrically connected to the electronic components disposed in the wafer of the second chip to form a circuit structure, then the active surface of the second chip is located on the side of the second dielectric layer of the second chip away from the wafer of the second chip.
  • the wafer of the second chip and the wafer of the first chip are arranged between the second dielectric layer of the first chip and the second dielectric layer of the second chip, so that the passive surface of the second chip is bonded to the passive surface of the first chip, and this bonding method is also called back-to-back bonding.
  • one end of the metal circuit of the first chip is electrically connected to the metal wiring in the second dielectric layer of the first chip
  • one end of the metal circuit of the second chip is electrically connected to the metal wiring in the second dielectric layer of the second chip
  • the other end of the metal circuit of the first chip is electrically connected to the other end of the metal circuit of the second chip.
  • the signal received by the active surface of the first chip can be transmitted to the active surface of the second chip through the metal wiring of the second dielectric layer of the first chip, the metal circuit in the via of the first chip, and the metal circuit in the via of the second chip, and then transmitted to the electronic components arranged in the wafer of the second chip through the metal wiring of the second dielectric layer of the second chip; or, the signal received by the active surface of the second chip can be transmitted to the active surface of the first chip through the metal wiring of the second dielectric layer of the second chip, the metal circuit in the via of the second chip, and the metal circuit in the via of the first chip, and then transmitted to the circuit structure formed by the electronic components arranged in the wafer of the first chip through the metal wiring of the second dielectric layer of the first chip, which means that by setting the metal circuit in the via of the first chip and the metal circuit in the via of the second chip, signal communication between the second chip and the first chip can be achieved.
  • a chip packaging structure comprising a packaging substrate and a chip stacking structure as described in any one of the second aspects above; the chip stacking structure is electrically connected to the packaging substrate.
  • an electronic device comprising a printed circuit board and the chip packaging structure as described in the second aspect above; the packaging substrate in the chip packaging structure is electrically connected to the printed circuit board.
  • a chip manufacturing method comprising: forming a via in a wafer, forming a metal circuit and a first dielectric layer in the via, wherein the first dielectric layer is located between the metal circuit and the wafer; forming a first isolation ring, wherein the first isolation surrounds the via, and the dielectric constant of the first isolation ring is smaller than the dielectric constant of the material of the first dielectric layer.
  • the technical effects brought about by any possible implementation method of the third and fourth aspects can refer to the technical effects brought about by different implementation methods of the second and first aspects mentioned above
  • the technical effects brought about by the fifth aspect can refer to the technical effects brought about by different implementation methods of the first aspect mentioned above, which will not be repeated here.
  • FIG1 is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application.
  • FIG2 is a schematic diagram of a chip packaging structure provided in an embodiment of the present application.
  • FIG3 is a schematic diagram of a chip stacking structure provided in an embodiment of the present application.
  • FIG4 is a schematic diagram of the structure of a chip provided in an embodiment of the present application.
  • FIG5 is a schematic diagram of the structure of a chip provided by another embodiment of the present application.
  • FIG6 is a schematic diagram of the structure of a chip provided in yet another embodiment of the present application.
  • FIG7 is a schematic diagram of the structure of a chip provided in yet another embodiment of the present application.
  • FIG8 is a schematic structural diagram of a chip stacking structure provided by another embodiment of the present application.
  • FIG9 is a schematic structural diagram of a chip stacking structure provided in yet another embodiment of the present application.
  • FIG10 is a schematic structural diagram of a chip stacking structure provided in yet another embodiment of the present application.
  • FIG11 is a flow chart of a chip manufacturing method provided in an embodiment of the present application.
  • FIG12 is a first schematic diagram of the structure of a chip in a chip manufacturing method provided in another embodiment of the present application.
  • FIG13 is a second schematic diagram of the structure of a chip in a chip manufacturing method provided in another embodiment of the present application.
  • FIG14 is a third schematic diagram of the structure of a chip in a chip manufacturing method provided in another embodiment of the present application.
  • FIG15 is a fourth schematic diagram of the structure of a chip in a chip manufacturing method provided in another embodiment of the present application.
  • FIG16 is a fifth structural diagram of a chip in a chip manufacturing method provided in another embodiment of the present application.
  • FIG17 is a first schematic diagram of the structure of a chip in a chip manufacturing method provided in yet another embodiment of the present application.
  • FIG18 is a second schematic diagram of the structure of a chip in a chip manufacturing method provided in yet another embodiment of the present application.
  • FIG19 is a third schematic diagram of the structure of a chip in a chip manufacturing method provided in yet another embodiment of the present application.
  • FIG20 is a fourth schematic diagram of the structure of a chip in a chip manufacturing method provided in yet another embodiment of the present application.
  • FIG21 is a schematic diagram of the structure of a chip in a chip manufacturing method provided in yet another embodiment of the present application.
  • FIG22 is a second schematic diagram of the structure of a chip in a chip manufacturing method provided in yet another embodiment of the present application.
  • FIG23 is a third schematic diagram of the structure of a chip in a chip manufacturing method provided in yet another embodiment of the present application.
  • FIG24 is a fourth schematic diagram of the structure of a chip in a chip manufacturing method provided in yet another embodiment of the present application.
  • FIG25 is a fifth structural diagram of a chip in a chip manufacturing method provided in yet another embodiment of the present application.
  • FIG. 26 is a sixth schematic diagram of the structure of a chip in a chip manufacturing method provided in yet another embodiment of the present application.
  • At least one of the following (individuals) refers to any combination of these items, including any combination of single items (individuals) or plural items (individuals).
  • at least one of a, b or c (individuals) may represent: a, b, c, a and b, a and c, b and c or a, b and c, wherein a, b and c may be single or multiple.
  • the words “first”, “second” and the like do not limit the quantity and order.
  • directional terms such as “upper” and “lower” are defined relative to the orientation of the components in the drawings. It should be understood that these directional terms are relative concepts. They are used for relative description and clarification, and they may change accordingly according to changes in the orientation of the components in the drawings.
  • words such as “exemplary” or “for example” are used to indicate examples, illustrations or descriptions. Any embodiment or design described as “exemplary” or “for example” in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as “exemplary” or “for example” is intended to present related concepts in a specific way.
  • the embodiments of the present application provide an electronic device.
  • the electronic device may include a mobile phone, a tablet computer (pad), a television, a smart wearable product (e.g., a smart watch, a smart bracelet), a virtual reality (VR) device, an augmented reality (AR) device, etc.
  • a smart wearable product e.g., a smart watch, a smart bracelet
  • VR virtual reality
  • AR augmented reality
  • the embodiments of the present application do not impose any special restrictions on the specific forms of the above electronic devices.
  • an embodiment of the present application provides a schematic diagram of the structure of the above-mentioned electronic device, wherein the above-mentioned electronic device 10 includes a printed circuit board (PCB) 12 and a chip packaging structure 11, and the chip packaging structure 11 is electrically connected to the PCB 12, so that the chip packaging structure 11 can be connected to other chips or other modules on the PCB 12. Interconnection.
  • an electrical connection structure c1 is further provided between the chip package structure 11 and the PCB 12 , and the electrical connection structure c1 may be a ball grid array (BGA), wherein the chip package structure 11 is specifically electrically connected to the PCB 12 via the electrical connection structure c1 .
  • BGA ball grid array
  • FIG. 2 shows a chip packaging structure 11, which includes a packaging substrate 30 and a chip stacking structure 20 constructed based on a three-dimensional (3D) stacking packaging technology.
  • the chip packaging structure 11 is electrically connected to a PCB 12, specifically, the packaging substrate 30 in the chip packaging structure 11 is electrically connected to the PCB 12, wherein the chip stacking structure 20 includes two or more vertically stacked chips, wherein the chip stacking structure 20 is electrically connected to the packaging substrate 30.
  • 3D three-dimensional
  • an electrical connection structure c2 is further provided between the chip stacking structure 20 and the packaging substrate 30, and the electrical connection structure c2 may be a micro bump (uBump) or a controlled collapse chip connection solder joint (C4 for short), and the chip stacking structure 20 is specifically electrically connected to the packaging substrate 30 through the electrical connection structure c2.
  • the electrical connection structure c2 may be a micro bump (uBump) or a controlled collapse chip connection solder joint (C4 for short), and the chip stacking structure 20 is specifically electrically connected to the packaging substrate 30 through the electrical connection structure c2.
  • an embodiment of the present application provides a cross-sectional view of a chip stacking structure 20.
  • the chip stacking structure 20 includes a plurality of stacked chips, wherein the plurality of stacked chips include a chip 21 and a chip 22.
  • the chip 22 is disposed above the chip 21.
  • the chip 21 includes a wafer 210 and a dielectric layer 211 disposed on one side of the wafer 210. Specifically, the dielectric layer 211 is disposed below the wafer 210.
  • the chip 22 includes a wafer 220 and a dielectric layer 221 disposed on one side of the wafer 220.
  • the dielectric layer 221 is disposed below the wafer 220.
  • the wafer 210 is disposed between the dielectric layer 211 and the dielectric layer 221, and the dielectric layer 221 is disposed between the wafer 210 and the wafer 220.
  • the chip 210 is also provided with a through silicon via (TSV) 213, and the through silicon via 213 is provided with a metal circuit 214 and a dielectric layer 215 arranged between the metal circuit 214 and the chip 210.
  • TSV through silicon via
  • One end of the metal circuit 214 is electrically connected to the metal wiring 212 in the dielectric layer 211 of the chip 21, and the other end of the metal circuit 214 is electrically connected to the metal wiring 222 in the dielectric layer 221 of the chip 22.
  • the chip 21 is used as an example for explanation.
  • Some electronic components are usually arranged in the wafer 210 in the chip 21.
  • an electronic component EC is shown in FIG. 3, wherein the electronic components arranged in the wafer 210 include capacitors, resistors, diodes, bipolar junction transistors (BJT), metal-oxide-semiconductor field effect transistors (MOSFET), etc.
  • the electronic components arranged in the wafer 210 include capacitors, resistors, diodes, bipolar junction transistors (BJT), metal-oxide-semiconductor field effect transistors (MOSFET), etc.
  • one or more metal wirings are often arranged in the dielectric layer 211 arranged on one side of the wafer 210.
  • the one or more metal wirings are electrically connected with the electronic components arranged in the wafer 210 in the chip 21 to form a circuit structure.
  • the active surface of the chip 21 is the side of the dielectric layer 211 of the chip 21 away from the wafer 210, and the passive surface of the chip 21 is the side of the wafer 210 of the chip 21 away from the dielectric layer 211.
  • the dielectric layer 211 of the chip 21 and the one or more metal wirings arranged in the dielectric layer 211 are also referred to as a redistribution layer (RDL).
  • the metal wiring 212 in the dielectric layer 211 is electrically connected to the electronic components arranged in the wafer 210 in the chip 21, and the dielectric layer 211 is located below the wafer 210, then the active surface of the chip 21 is located below the dielectric layer 211, and the passive surface of the chip 21 is located above the wafer 210; since the metal wiring in the dielectric layer 221 is electrically connected to the electronic components arranged in the wafer 220 in the chip 22, and the dielectric layer 221 is located below the wafer 220, then the active surface of the chip 22 is located below the dielectric layer 211, and the passive surface of the chip 22 is located above the wafer 210.
  • the wafer 210 is arranged between the dielectric layer 211 and the dielectric layer 221, and the dielectric layer 221 is arranged between the wafer 210 and the wafer 220, therefore, the active surface of the chip 22 is bonded to the passive surface of the chip 21, and this bonding method is also called face-to-back bonding.
  • a through silicon via 213 penetrating the wafer 210 is also provided in the wafer 210, and one end of the metal line 214 in the through silicon via 213 is electrically connected to the metal wiring 212 in the dielectric layer 211 of the chip 21, and the other end of the metal line 214 in the through silicon via 213 is electrically connected to the metal wiring 222 in the dielectric layer 221 of the chip 22, the signal received by the active surface of the chip 21 can be transmitted to the active surface of the chip 22 through the metal wiring 212 and the metal line 214 in the through silicon via 213, and then transmitted to the electronic components arranged in the wafer 220 of the chip 22 through the metal wiring 222 in the dielectric layer 221 of the chip 22; or, the signal received by the active surface of the chip 22 can be transmitted to the active surface of the chip 21 through the metal wiring 222 and the metal line 214 in the through silicon via 213, and then transmitted to the circuit structure formed by the electronic components arranged in the wafer 210 of the chip 21 through the metal wiring 212 in the
  • the chip stacking structure 20 shown in FIG. 3 when the metal line 214 in the through silicon via 213 passes the signal, the chip When the chip 21 can realize signal communication with the chip 22, since a dielectric layer 215 is also provided between the metal line 214 and the wafer 210, the wafer 210, the metal line 214 and the dielectric layer 215 will form a capacitor C, one electrode of the capacitor C is the metal line 214, the other electrode of the capacitor C is the wafer 210, and the dielectric material of the capacitor C is the dielectric layer 215.
  • the existence of the capacitor C causes a large parasitic capacitance to be generated between the metal line 214 in the through silicon via 213 and the electronic component EC provided in the wafer 210 of the chip 21, and the parasitic capacitance will affect the normal operation of the electronic component EC, wherein the parasitic capacitance will increase the resistance capacitance delay (RC delay) of the chip 21, thereby affecting the signal transmission performance of the chip 21.
  • RC delay resistance capacitance delay
  • an embodiment of the present application provides a chip, as shown in FIG4 , when an AC signal passes through the via hole in the chip 21, the parasitic capacitance generated between the metal line in the via hole and the electronic components arranged in the wafer of the chip 21 is small, thereby improving the signal transmission performance of the chip 21.
  • FIG4 (a) is a top view of the chip 21
  • FIG4 (b) is a cross-sectional view of the chip 21 along AA' shown in FIG4 (a).
  • the chip 21 shown in FIG4 includes a wafer 210.
  • the chip 21 also includes a dielectric layer 211 disposed on one side of the wafer 210, wherein one or more metal wirings are disposed in the dielectric layer 211, and only one metal wiring 212 is shown in FIG4.
  • the metal wirings in the dielectric layer 211 are electrically connected to the electronic components disposed in the wafer 210 of the chip 21 to form a circuit structure.
  • the active surface of the chip 21 is the side of the dielectric layer 211 of the chip 21 away from the wafer 210, and the passive surface of the chip 21 is the side of the wafer 210 of the chip 21 away from the dielectric layer 211.
  • the dielectric layer 211 is located below the wafer 210, so the active surface of the chip 21 is located below the dielectric layer 211.
  • a via 213 is provided in the wafer 210, a metal line 214 is provided in the via 213, and a dielectric layer 215 is provided between the metal line 214 and the wafer 210.
  • the metal line 214 in the via 213 is electrically connected to the metal wiring 212 in the dielectric layer 211, and the via 213 passes through the wafer 210.
  • the via 213 shown in Figure 4 may not pass through the chip 210.
  • one end of the metal line 214 in the via 213 may be electrically connected to the metal wiring 212 in the dielectric layer 211, and the other end of the metal line 214 in the via 213 may be electrically connected to the electronic component provided in the chip 210.
  • the material of the metal line 214 includes copper and tungsten, and the material of the metal line 214 is a conductive material. Only when the material of the metal line 214 is a conductive material, the signal can be transmitted through the metal line 214 in the via 213.
  • the via 213 is usually set to a cylindrical shape, and the diameter of the cylindrical via 213 is greater than or equal to 1 micron.
  • the via 213 can also be set to a prism shape, and the bottom surface of the via 213 set to a prism shape can be an arbitrary polygon, and the side length of the arbitrary polygon can be greater than or equal to 1 micron.
  • the bottom surface of the metal line 214 in the via 213 is circular. In other embodiments, the bottom surface of the metal line 214 in the via 213 is annular.
  • the via 213 is also generally referred to as a through silicon via.
  • the material of the wafer 210 may also include: gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), indium phosphide (InP), and the embodiments of the present application do not limit the material of the wafer 210.
  • the dielectric layer 215 is generally made of insulating material. In some embodiments, the material of the dielectric layer 215 includes silicon dioxide, silicon nitride, etc. When the metal line 214 in the via 213 passes a signal, the dielectric layer 215 can insulate the metal line 214 from the wafer 210.
  • the wafer 210 further includes an isolation ring 216 surrounding the via hole 213, and the dielectric constant of the isolation ring 216 is less than the dielectric constant of the material of the dielectric layer 215.
  • the bottom surface of the isolation ring 216 is annular, for example, a circular ring or a polygonal ring, and the isolation ring 216 surrounds the via hole 213, and the isolation ring 216 does not contact the via hole 213.
  • the isolation ring 216 surrounds the via 213, and the isolation ring 216 also passes through the wafer 210, wherein the wafer 210 can be separated into a wafer region 210a and a wafer region 210b by providing the isolation ring 216, wherein the via 213 is provided in the wafer region 210a, and the electronic components are provided in the wafer region 210b.
  • FIG. 4 takes the electronic component EC as an example for explanation, wherein the electronic component EC can be separated from the via 213 by providing the isolation ring 216.
  • the distance between the isolation ring 216 and the via 213 is greater than or equal to 0.5 microns, and the ring width of the bottom surface of the isolation ring 216 is greater than or equal to 0.1 microns and less than or equal to 1 micron. That is, the width of the wafer region 210a between the isolation ring 216 and the via 213 is small enough to ensure that there is no electronic component EC in the wafer region 210a, and to minimize the waste of the effective area of the wafer.
  • the wafer 210 when the wafer 210 includes two or more vias 213, the wafer also includes a plurality of isolation rings, one isolation ring surrounding one via 213. In other embodiments, when the wafer 210 includes two or more vias 213, the wafer may include one or more isolation rings, one isolation ring surrounding two or more vias 213.
  • the material of the dielectric layer 215 is silicon dioxide or silicon nitride, wherein the dielectric constant of silicon dioxide is approximately equal to 3.9.
  • the dielectric constant of the isolation ring 216 is less than the dielectric constant of the material of the dielectric layer 215, wherein the isolation ring 216 can be made of one or more of the following materials: SiLK, carbon-doped silicon oxide, hydrogen silses quioxane (HSQ), methyl silses quioxane (MSQ) and Nanoglass.
  • SiLK is a low dielectric constant material, which is currently widely used in chip production.
  • SiLK is a polymer material with a dielectric constant of 2.6; the dielectric constant of carbon-doped silicon oxide is about 2.4 to 2.7; the dielectric constant of HSQ can reach 2.9; MSQ is a silicon-based polymer material with a dielectric constant of 2.2; the dielectric constant of Nanoglass can reach 1.3.
  • the metal line 214 in the via hole 213, the wafer 210 and the dielectric layer 215 will constitute a capacitor C1, wherein one electrode of the capacitor C1 is the metal line 214 in the via hole 213, the other electrode of the capacitor C1 is the wafer 210, specifically the wafer region 210a, and the dielectric material between the two electrodes of the capacitor C1 is the dielectric layer 215.
  • the isolation ring 216 surrounds the via hole 213, the isolation ring 216 and the wafer 210 on both sides of the isolation ring 216 will also constitute a capacitor C2, wherein one electrode of the capacitor C2 is the wafer 210 on one side of the isolation ring 216, specifically the wafer region 210a, and the other electrode of the capacitor C2 is the wafer 210 on the other side of the isolation ring 216.
  • the dielectric material between the two electrodes of the capacitor C2 is the isolation ring 216, wherein, since the dielectric constant of the isolation ring 216 is smaller than the dielectric constant of the material of the dielectric layer 215, the capacitance value of the capacitor C2 will be smaller than the capacitance value of the capacitor C1.
  • the parasitic capacitance between the metal line 214 of the via 213 and the electronic component EC arranged in the wafer 210 of the chip 21 can be reduced, thereby improving the signal transmission performance of the chip 21.
  • the isolation ring 216 also includes an air gap 217, wherein, exemplarily, when making the isolation ring, an isolation ring groove is first etched out by an etching process, and the isolation ring material is deposited in the groove of the isolation ring by chemical vapor deposition (chemical vapor deposition, CVD). Since the bottom surface of the isolation ring 216 is a circular ring, the ring width of the circular ring is greater than or equal to 0.1 microns and less than or equal to 1 micron. Therefore, the ring width of the isolation ring groove is greater than or equal to 0.1 microns and less than or equal to 1 micron.
  • the isolation ring material When the isolation ring material is deposited by chemical vapor deposition in the isolation ring groove of such a size, the deposited isolation ring material will adhere to the bottom and side walls of the isolation ring groove, and the opening of the isolation ring groove will be sealed first, so the isolation ring 216 formed will include an air gap 217.
  • the dielectric constant of the air in the air gap 217 is 1, so the capacitance value of the capacitor C2 will be smaller, further reducing the parasitic capacitance between the metal line 214 in the via 213 and the electronic components EC provided in the wafer 210 of the chip 21 .
  • the isolation ring 216 can also be made of silicon dioxide or silicon nitride. Since the isolation ring 216 made of silicon dioxide or silicon nitride has the air gap 217, the dielectric constant of the isolation ring 216 is also lower than that of silicon dioxide or silicon nitride.
  • the material of dielectric layer 211 includes silicon dioxide and silicon nitride.
  • the material of dielectric layer 215 includes silicon dioxide and nitride.
  • the material of dielectric layer 211 may be the same as the material of dielectric layer 215, or the material of dielectric layer 211 may be different from the material of dielectric layer 215, which is not limited in the embodiments of the present application.
  • the material of the isolation ring 216 , the material of the dielectric layer 215 , and the material of the dielectric layer 211 may all be the same silicon dioxide, which is not limited in the embodiments of the present application.
  • the wafer 210 further includes: an isolation ring 218 surrounding the isolation ring 216, and the dielectric constant of the isolation ring 218 is less than the dielectric constant of the material of the dielectric layer 215.
  • the isolation ring 216 surrounds the via 213, and the isolation ring 216 also passes through the wafer 210, and the isolation ring 218 surrounds the isolation ring 216, and the isolation ring 218 also passes through the wafer 210, wherein, by providing the isolation ring 216 and the isolation ring 218, the electronic component EC can be separated from the via 213.
  • the dielectric layer 215 is made of silicon dioxide, and the dielectric constant of silicon dioxide is approximately equal to 3.9.
  • the dielectric constant of the isolation ring 218 is less than the dielectric constant of the material of the dielectric layer 215, wherein the isolation ring 218 can be made of one or more of the following materials: SiLK, carbon-doped silicon oxide, hydrogen silses quioxane (HSQ), methyl silses quioxane (MSQ) and Nanoglass.
  • the isolation ring 218 surrounds the isolation ring 216, the isolation ring 218 and the wafers 210 on both sides of the isolation ring 218 will also form a capacitor C3, wherein one electrode of the capacitor C3 is the wafer 210 on one side of the isolation ring 218, and the other electrode of the capacitor C3 is the wafer 210 on the other side of the isolation ring 218.
  • the dielectric material between the two electrodes of the capacitor C3 is the isolation ring 218. Since the dielectric constant of the isolation ring 218 is less than the dielectric constant of the material of the dielectric layer 215, the capacitance of the capacitor C3 is The value will be smaller than the capacitance value of capacitor C1.
  • the isolation ring 218 also includes an air gap 219, wherein, exemplarily, when manufacturing the isolation ring, an isolation ring groove is first etched out by an etching process, and the isolation ring material is deposited in the groove of the isolation ring by chemical vapor deposition (chemical vapor deposition, CVD). Since the bottom surface of the isolation ring 218 is a circular ring, the ring width of the circular ring is greater than or equal to 0.1 microns and less than or equal to 1 micron. Therefore, the ring width of the isolation ring groove is greater than or equal to 0.1 microns and less than or equal to 1 micron.
  • the isolation ring material When the isolation ring material is deposited by chemical vapor deposition in the isolation ring groove of such a size, the deposited isolation ring material will adhere to the bottom and side walls of the isolation ring groove, and the opening of the isolation ring groove will be sealed first, so the isolation ring 218 formed will include an air gap 219.
  • the dielectric constant of the air in the air gap 219 is 1, so the capacitance value of the capacitor C3 will be smaller, further reducing the equivalent capacitance between the metal line 214 in the via 213 and the electronic component EC provided in the wafer 210 of the chip 21 .
  • the isolation ring 218 can also be made of silicon dioxide or silicon nitride. Since the isolation ring 218 made of silicon dioxide or silicon nitride has an air gap 219, the dielectric constant of the isolation ring 218 is also lower than that of silicon dioxide or silicon nitride.
  • an embodiment of the present application further provides a chip stacking structure, which may be, for example, the chip stacking structure 20 shown in FIG. 3 , wherein the chip stacking structure 20 includes a plurality of stacked chips, and the plurality of stacked chips include the chip 21 shown in any one of FIGS. 4 to 7 .
  • the chip 21 in the chip stacking structure 20 shown in FIG. 3 may be replaced by the chip 21 shown in any one of FIGS. 4 to 7 .
  • the multiple stacked chips include chip 21 and chip 22; chip 21 includes a dielectric layer 211 arranged on one side of a wafer 210; chip 22 includes a dielectric layer 221 arranged on one side of a wafer 220; among the multiple stacked chips, the wafer 210 of chip 21 is arranged between the dielectric layer 211 of chip 21 and the dielectric layer 221 of chip 22, and the dielectric layer 211 of chip 21 is arranged between the wafer 210 of chip 21 and the wafer 220 of chip 22; one end of the metal line 214 of chip 21 is electrically connected to the metal wiring 212 in the dielectric layer 211 of chip 21, and the other end of the metal line 214 of chip 21 is electrically connected to the metal wiring 222 in the dielectric layer 221 of chip 22.
  • the chip stacking structure 20 shown in FIG. 8 can be specifically applied to high bandwidth memory (HBM), or to dynamic random access memory (DRAM), or to complementary metal oxide semiconductor (CMOS) image sensor (CIS), or to NAND flash memory (NAND Flash), etc., and the embodiments of the present application are not limited to this.
  • HBM high bandwidth memory
  • DRAM dynamic random access memory
  • CMOS complementary metal oxide semiconductor
  • CIS complementary metal oxide semiconductor image sensor
  • NAND Flash NAND flash memory
  • the chip 21 shown in FIG. 8 is illustrated by taking the chip 21 shown in FIG. 5 as an example.
  • the chip 21 in the chip stacking structure 20 shown in FIG. 8 may also be the chip 21 shown in FIG. 4 or FIG. 6 or FIG. 7 , and the embodiments of the present application are not limited to this.
  • the chip 22 in the chip stacking structure 20 shown in FIG. 8 may also be the chip 21 shown in any one of FIG. 4 to FIG. 7 , and the embodiments of the present application are not limited to this.
  • one or more metal wirings are provided in the dielectric layer 211, and only one metal wiring 212 is shown in FIG. 8 .
  • the metal wiring in the dielectric layer 211 is electrically connected to the electronic components provided in the wafer 210 in the chip 21 to form a circuit structure. Then, when the dielectric layer 211 is located below the wafer 210, the active surface of the chip 21 is located below the dielectric layer 211; one or more metal wirings are provided in the dielectric layer 221, and only one metal wiring 212 is shown in FIG.
  • the metal wiring 222, the metal wiring in the dielectric layer 221 and the electronic components arranged in the wafer 210 in the chip 22 are electrically connected to form a circuit structure. Then, when the dielectric layer 221 is located below the wafer 220, the active surface of the chip 22 is located below the dielectric layer 221. In addition, the wafer 210 of the chip 21 is arranged between the dielectric layer 211 of the chip 21 and the dielectric layer 221 of the chip 22, and the dielectric layer 211 of the chip 21 is arranged between the wafer 210 of the chip 21 and the wafer 220 of the chip 22. Therefore, the active surface of the chip 22 is bonded to the passive surface of the chip 21. This bonding method is also called face-to-back bonding.
  • one end of the metal line 214 in the via 213 is electrically connected to the metal wiring 212 in the dielectric layer 211 in the chip 21, and the other end of the metal line 214 in the via 213 is electrically connected to the metal wiring 222 in the dielectric layer 221 in the chip 22, so the signal received by the active surface of the chip 21 can be transmitted to the active surface of the chip 22 through the metal wiring 212 and the metal line 214 in the via 213, and then transmitted to the electronic components set in the wafer 220 of the chip 22 through the metal wiring 222 in the dielectric layer 221 of the chip 22; or, the signal received by the active surface of the chip 22 can be transmitted to the active surface of the chip 21 through the metal wiring 222 and the metal line 214 in the via 213, and then transmitted to the electronic components set in the wafer 210 of the chip 21 through the metal wiring 212 in the dielectric layer 211 of the chip 21.
  • signal communication between the chip 21 and the chip 22 can be
  • a dielectric layer 100 is often disposed between the active surface of chip 22 and the passive surface of chip 21.
  • Dielectric layer 100 serves as a bonding layer of a fusion bonding process to achieve a fixed connection between chip 22 and chip 21, wherein the metal line 214 in the via 213 passes through the dielectric layer 100 and is electrically connected to the metal wiring 222.
  • a dielectric layer may be provided on the passive surface of the chip 21, and the dielectric layer is used to protect the wafer 210 on the passive surface of the chip 21. Then, when the active surface of the chip 22 is bonded face-to-back with the passive surface of the chip 21, the metal line 214 in the via 213 penetrates the dielectric layer provided on the passive surface of the chip 21 and is electrically connected to the metal wiring 222.
  • metal wiring may also be provided in the dielectric layer, and the metal line 214 in the via 213 may be electrically connected to the metal wiring in the dielectric layer, or may not be electrically connected to the metal wiring in the dielectric layer, and the embodiments of the present application are not limited thereto.
  • the chip 21 in the chip stacking structure 20 shown in FIG8 may be a crystal grain (also referred to as a particle or a bare chip) (die), or a chip wafer; the chip 22 in the chip stacking structure 20 may be a crystal grain (also referred to as a particle or a bare chip) (die), or a chip wafer.
  • a chip wafer may be formed, and the chip wafer may be cut to obtain a bare chip (die).
  • the chip 21 may be a die, and the chip 22 may be a die, and such a structure may be referred to as die-to-die bonding (D2D bonding); or, as shown in FIG8 , the chip 21 may be a chip wafer, and the chip 22 may be a chip wafer, and such a structure may be referred to as wafer-to-wafer bonding (W2W bonding); or, as shown in FIG8 , the chip 21 may be a chip wafer, and the chip 22 may be a die, and such a structure may be referred to as die-to-wafer bonding (D2W bonding).
  • D2D bonding die-to-die bonding
  • W2W bonding wafer-to-wafer bonding
  • D2W bonding die-to-wafer bonding
  • the plurality of stacked chips include a chip 21 and a chip 22;
  • the chip 21 includes a dielectric layer 211 disposed on one side of a wafer 210;
  • the chip 22 includes a dielectric layer 221 disposed on one side of a wafer 220; in the plurality of stacked chips, the dielectric layer 221 of the chip 22 and the dielectric layer 211 of the chip 21 are disposed between the wafer 210 of the chip 21 and the wafer 220 of the chip 22; one end of the metal line 214 of the chip 21 is electrically connected to the metal wiring 212 in the dielectric layer 211 of the chip 21, and the metal wiring 212 in the dielectric layer 211 of the chip 21 is electrically connected to the metal wiring 222 in the dielectric layer 221 of the chip 22.
  • the chip 21 shown in FIG. 9 is illustrated by taking the chip 21 shown in FIG. 5 as an example.
  • the chip 21 in the chip stacking structure 20 shown in FIG. 9 may also be the chip 21 shown in FIG. 4 , 6 , or 7 , and the embodiments of the present application are not limited to this.
  • the chip 22 in the chip stacking structure 20 shown in FIG. 9 may also be the chip 21 shown in any one of FIG. 4 to FIG. 7 , and the embodiments of the present application are not limited to this.
  • one or more metal wirings are provided in the dielectric layer 211, and only one metal wiring 212 is shown in FIG. 9 .
  • the metal wirings in the dielectric layer 211 are electrically connected to the electronic components provided in the wafer 210 in the chip 21 to form a circuit structure. Then, when the dielectric layer 211 is located above the wafer 210, the active surface of the chip 21 is located above the dielectric layer 211; one or more metal wirings are provided in the dielectric layer 221, and only one metal wiring 222 is shown in FIG. 9 .
  • the metal wirings 222 in the dielectric layer 221 are electrically connected to the electronic components provided in the wafer 220 in the chip 22 to form a circuit structure. Then, when the dielectric layer 221 is located below the wafer 220, the active surface of the chip 22 Located below the dielectric layer 221. In addition, the dielectric layer 221 of the chip 22 and the dielectric layer 211 of the chip 21 are disposed between the wafer 210 of the chip 21 and the wafer 220 of the chip 22, so that the active surface of the chip 22 is bonded to the active surface of the chip 21, and this bonding method is also called face-to-face bonding.
  • one end of the metal line 214 in the via 213 is electrically connected to the metal wiring 212 in the dielectric layer 211, and the metal wiring 212 in the dielectric layer 211 is electrically connected to the metal wiring 222 in the dielectric layer 221, so the signal received by the active surface of the chip 21 can be transmitted to the active surface of the chip 22 through the metal wiring 212, and then transmitted to the electronic components set in the wafer 220 of the chip 22 through the metal wiring 222 in the dielectric layer 221 of the chip 22, or the signal received by the active surface of the chip 22 can be transmitted to the active surface of the chip 21 through the metal wiring 222, and then transmitted to the circuit structure formed by the electronic components set in the wafer 210 of the chip 21 through the metal wiring 212 in the dielectric layer 211 of the chip 21.
  • signal communication can be achieved between the chip 21 and the chip 22.
  • the signal when some signals are transmitted from the passive surface of chip 21 to the active surface of chip 21, the signal is transmitted to the active surface of chip 21 through the metal line 214 in the via 213, and then transmitted to the electronic components arranged in the wafer 210 of chip 21 through the metal wiring 212 in the dielectric layer 211 of chip 21. Since signal communication can be achieved between chip 21 and chip 22, the signal transmitted from the passive surface of chip 21 to the active surface of chip 21 can also be transmitted to the active surface of chip 22.
  • a dielectric layer 100 is often disposed between the active surface of chip 22 and the active surface of chip 21.
  • Dielectric layer 100 serves as a bonding layer of a fusion bonding process to achieve a fixed connection between chip 22 and chip 21, wherein metal wiring 212 in dielectric layer 211 and metal wiring 222 in dielectric layer 221 are electrically connected through dielectric layer 100.
  • the plurality of stacked chips include a chip 21a and a chip 21b;
  • the chip 21a includes a dielectric layer 211 disposed on one side of a wafer 210;
  • the chip 22b includes a dielectric layer 211 disposed on one side of the wafer 210;
  • the wafer 220 of the chip 22 and the wafer 210 of the chip 21 are disposed between the dielectric layer 211 of the chip 21 and the dielectric layer 221 of the chip 22;
  • one end of the metal line 214 of the chip 21a is electrically connected to the metal wiring 212 in the dielectric layer 211 of the chip 21a, one end of the metal line 214 of the chip 21b is electrically connected to the metal wiring 212 in the dielectric layer 211 of the chip 21b, and the other end of the metal line 214 of the chip 21a is electrically connected to the other end of the metal line 214 of the chip
  • the chip 21a shown in FIG. 10 is described by taking the chip 21 shown in FIG. 5 as an example.
  • the chip 21a in the chip stacking structure 20 shown in FIG. 10 may also be the chip 21 shown in FIG. 4, FIG. 6, or FIG. 7, and the embodiments of the present application do not limit this.
  • the chip 21b shown in FIG. 10 is described by taking the chip 21 shown in FIG. 5 as an example.
  • the chip 21b in the chip stacking structure 20 shown in FIG. 10 may also be the chip 21 shown in FIG. 4, FIG. 6, or FIG. 7, and the embodiments of the present application do not limit this.
  • one or more metal wirings are arranged in the dielectric layer 211 of the chip 21a, and only one metal wiring 212 is shown in FIG. 10 .
  • the metal wiring 212 in the dielectric layer 211 of the chip 21a is electrically connected to the electronic components arranged in the wafer 210 in the chip 21a to form a circuit structure.
  • the metal wiring 212 in the dielectric layer 211 of the chip 21a is electrically connected to the electronic components arranged in the wafer 210 in the chip 21a to form a circuit structure.
  • the active surface is located below the dielectric layer 211 of the chip 21a; one or more metal wirings are arranged in the dielectric layer 221 of the chip 21b, and only one metal wiring 212 is shown in FIG10.
  • the metal wirings in the dielectric layer 211 of the chip 21b are electrically connected to the electronic components arranged in the wafer 210 of the chip 21b to form a circuit structure. Then, when the dielectric layer 211 of the chip 21b is located above the wafer 210 of the chip 21b, the active surface of the chip 21b is located above the dielectric layer 211 of the chip 21b.
  • the wafer 220 of the chip 22 and the wafer 210 of the chip 21 are arranged between the dielectric layer 211 of the chip 21 and the dielectric layer 221 of the chip 22. Therefore, the passive surface of the chip 21b is bonded to the passive surface of the chip 21a.
  • This bonding method is also called back-to-back bonding.
  • one end of the metal line 214 of the chip 21a is electrically connected to the metal wiring 212 in the dielectric layer 211 of the chip 21a
  • one end of the metal line 214 of the chip 21b is electrically connected to the metal wiring 212 in the dielectric layer 211 of the chip 21b
  • the other end of the metal line 214 of the chip 21a is electrically connected to the other end of the metal line 214 of the chip 21b. Therefore, the signal received by the active surface of the chip 21a can be transmitted to the chip 21 through the metal wiring 212 of the chip 21a, the metal line 214 in the via 213 of the chip 21a, and the metal line 214 in the via 213 of the chip 21b.
  • the signal intercommunication between the chip 21a and the chip 21b can be achieved through the metal line 214 in the via 213 of the chip 21a and the metal line 214 in the via 213 of the chip 21b.
  • a dielectric layer 100 is often provided between the passive surface of chip 21b and the passive surface of chip 21a.
  • Dielectric layer 100 is used as a bonding layer of a fusion bonding process to achieve a fixed connection between chip 21b and chip 21a.
  • the metal line 214 in the via 213 of chip 21b passes through the dielectric layer 100 and is electrically connected to the metal line 214 in the via 213 of chip 21a, and/or, the metal line 214 in the via 213 of chip 21a passes through the dielectric layer 100 and is electrically connected to the metal line 214 in the via 213 of chip 21b.
  • the chip stacking structure 20 may include more stacked chips, wherein two adjacent chips in the more stacked chips may be bonded face-to-back, face-to-face, or back-to-back, and the embodiments of the present application are not limited to this.
  • an embodiment of the present application provides a method for manufacturing a chip, including:
  • a dielectric layer 211 may be formed on one side of the wafer 210, and one or more metal wirings may be formed in the dielectric layer 211.
  • FIG. 12 shows only one metal wiring 212, wherein the metal wiring in the dielectric layer 211 is electrically connected to the electronic components disposed in the wafer 210 of the chip 21 to form a circuit structure.
  • the active surface of the chip 21 is the side of the dielectric layer 211 of the chip 21 away from the wafer 210
  • the passive surface of the chip 21 is the side of the wafer 210 of the chip 21 away from the dielectric layer 211.
  • the active surface of the chip 21 may be used as the working surface to form vias in the wafer 210 of the chip 21; in other embodiments, the passive surface of the chip 21 may be used as the working surface to form vias in the wafer 210 of the chip 21.
  • the bonding methods that can be selected between the chip 21 and the chip adjacent to the chip 21 include face-to-back bonding, face-to-face bonding, or back-to-back bonding.
  • the bonding method between the chip 21 and the chip adjacent to the chip 21 After the bonding method between the chip 21 and the chip adjacent to the chip 21 is selected, it can be determined whether the active surface of the chip 21 is used as the working surface to form vias in the wafer 210 of the chip 21, or the passive surface of the chip 21 is used as the working surface to form vias in the wafer 210 of the chip 21.
  • the embodiments of the present application do not limit this.
  • vias may be first made on the chip 21, and then the bonding method between the chip 21 and the chip adjacent to the chip 21 may be determined, and then the bonding step between the chip 21 and the chip adjacent to the chip 21 may be performed.
  • FIG. 12 shows that a via is formed in the wafer 210 of the chip 21 with the passive surface of the chip 21 as the working surface.
  • the substrate portion of the wafer 210 of the chip 21 exposed on the passive surface of the chip 21 needs to be thinned to the required thickness to facilitate subsequent operations.
  • a dielectric layer 61 needs to be deposited on the passive surface of the chip 21 to protect the substrate of the wafer 210 exposed on the passive surface of the chip 21 to avoid electrically connecting the wafer 210 to the metal circuit when the material of the metal circuit is subsequently deposited, or to avoid etching through the electronic components arranged in the wafer 210 when etching the isolation ring groove or the via groove, causing the electronic components to fail.
  • a photoresist 62 covering the passive surface of the chip 21 is made.
  • the photoresist 62 can be a positive photoresist or a negative photoresist.
  • a photoresist 62 covering the dielectric layer 61 on the passive surface of the chip 21 needs to be made.
  • the photoresist 62 is photolithographically processed to form a via opening 63 , wherein the via opening 63 is specifically circular.
  • the chip 21 is etched through the via opening 63 shown in FIG12 , and the dielectric layer 61, the wafer 210 of the chip 21 and part of the dielectric layer 211 need to be etched to form the via 213 shown in FIG13 , wherein the via 213 is in contact with the metal wiring 212.
  • a two-step etching process is often performed when forming the via 213, wherein the etching stop layer of the first etching process is the dielectric layer 211, and the etching stop layer of the second etching process is the metal wiring 212, and the etched via 213 is in contact with the metal wiring 212 through the two-step etching process.
  • etching usually uses an isotropic etching method, and in the second etching process, it is particularly necessary to ensure that the thickness of the dielectric layer 211 less than the dielectric layer 61 is greater than the thickness of the dielectric layer 211 above the metal wiring 212, so as to avoid the etching process from affecting the electronic components in the wafer 210.
  • the formed via 213 is generally cylindrical, and the diameter of the cylindrical via 213 is greater than or equal to 1 micron.
  • the via opening can be set to a polygon, and the formed via 213 can be a prism.
  • the embodiment of the present application does not limit the shape of the via 213.
  • a dielectric layer material is deposited in the via hole 213 shown in FIG. 13 by chemical vapor deposition (CVD), wherein the dielectric layer material includes silicon dioxide, silicon nitride, etc., and then a dielectric layer is formed on the sidewall of the via hole 213.
  • a dielectric layer 215 (that is, the first dielectric layer mentioned above) is formed.
  • a material for a metal circuit is deposited in the via hole 213 formed with the dielectric layer 215 to form a metal circuit 214 in the via hole 213. That is, the dielectric layer 215 is located between the metal circuit 214 and the wafer 210.
  • a material for a metal circuit is deposited in the via hole 213 formed with the dielectric layer 215 shown in FIG. 14 to form the metal circuit 214.
  • the material for the metal circuit includes metal materials such as copper and tungsten.
  • the bottom surface of the metal circuit 214 in the via hole 213 is circular. In other embodiments, the bottom surface of the metal circuit 214 in the via hole 213 is annular. The embodiments of the present application do not limit the shape of the metal circuit 214.
  • a dielectric layer material is deposited on the surface of the metal line 214 to protect the metal on the surface of the metal line 214.
  • a metal connection process may be performed later to enable the metal line 214 to be electrically connected to other metal wirings.
  • a photoresist 65 covering the passive surface of the chip 21 is again made on the passive surface of the chip 21.
  • the photoresist 65 can be a positive photoresist or a negative photoresist.
  • a photoresist 65 covering the dielectric layer 61 on the passive surface of the chip 21 needs to be made.
  • the photoresist 65 is subjected to photolithography to form an isolation ring window 66 , wherein the isolation ring window 66 is specifically in the shape of a circular ring.
  • the chip 21 is etched through the isolation ring opening 66 shown in Fig. 15, and the dielectric layer 61 and the wafer 210 need to be etched through to form the isolation ring groove 67 shown in Fig. 16.
  • the etching stop layer of the etching process is the dielectric layer 211.
  • isolation ring material is deposited in the isolation ring trench 67 shown in Fig. 16 to form an isolation ring 216 (ie, the first isolation ring mentioned above).
  • the width of the isolation ring trench is greater than or equal to 0.1 micrometers and less than or equal to 1 micrometer.
  • one or more of the following materials may be deposited in the isolation ring groove 67 shown in FIG. 16 to prepare the isolation ring 216: SiLK, carbon-doped silicon oxide, hydrogen silses quioxane (HSQ), methyl silses quioxane (MSQ) and Nanoglass.
  • SiLK silicon-doped silicon oxide
  • HSQ hydrogen silses quioxane
  • MSQ methyl silses quioxane
  • Nanoglass nanoglass.
  • silicon dioxide or silicon nitride may be deposited in the isolation ring groove 67 shown in FIG. 16 to prepare the isolation ring 216, and the ring width of the isolation ring groove 67 is greater than or equal to 0.1 micron and less than or equal to 1 micron.
  • the isolation ring groove 67 When silicon dioxide or silicon nitride is deposited in the isolation ring groove 67 of such a size by chemical vapor deposition, the deposited silicon dioxide or silicon nitride will be attached to the bottom and sidewall of the isolation ring groove 67, and the opening of the isolation ring groove 67 will be sealed first, so that the isolation ring 216 formed will include an air gap 217.
  • an isolation ring 218 surrounding the isolation ring 216 may be further manufactured, for example, to form the chip 21 as shown in FIG. 6 , which is not limited in the embodiments of the present application.
  • a second chip including vias can be manufactured, and then the second chip is bonded to the chip 21 to form the chip stacking structure 20 shown in FIG10.
  • a second chip not including vias is manufactured, and then the second chip is bonded to the chip 21 to form the chip stacking structure 20 shown in FIG8 or FIG9.
  • the specific steps of bonding the two chips refer to the existing chip bonding technology, such as setting a dielectric layer between the two chips as a bonding layer for the fusion bonding process, etc., and the embodiments of the present application are not limited to this.
  • the chip stacking structure includes a plurality of stacked chips, wherein two adjacent chips in the plurality of stacked chips may be bonded face-to-back, face-to-face, or back-to-back, and the embodiments of the present application are not limited to this.
  • the step of making vias may be performed before making electronic components disposed in the wafer of the chip 21, or when making electronic components disposed in the wafer of the chip 21, or after making electronic components disposed in the wafer of the chip 21.
  • the embodiments of the present application are not limited to this.
  • the via hole is first made, and then the isolation ring is made.
  • the metal line 214 in the via hole 213 and the dielectric layer 215 between the wafer 210 and the isolation ring 216 can also be made at the same time.
  • a dielectric layer 211 may be formed on one side of a wafer 210, and one or more metal wirings may be formed in the dielectric layer 211.
  • FIG. 17 shows only one metal wiring 212, wherein the metal wiring in the dielectric layer 211 is electrically connected to the electronic components disposed in the wafer of the chip to form a circuit structure.
  • the active surface of the chip 21 is the side of the dielectric layer 211 away from the wafer 210, and the passive surface of the chip 21 is the side of the wafer 210 away from the dielectric layer 211.
  • FIG. 17 shows that the passive surface of the chip 21 is used as the working surface to form a via hole in the wafer 210 of the chip 21 .
  • the substrate portion of the wafer 210 of the chip 21 exposed on the passive surface of the chip 21 needs to be thinned to the required thickness to facilitate subsequent operations.
  • a dielectric layer 71 needs to be deposited on the passive surface of the chip 21 to protect the substrate of the wafer 210 exposed on the passive surface of the chip 21 to avoid electrically connecting the wafer 210 to the metal circuit when subsequently depositing the material of the metal circuit, or to avoid etching through the electronic components arranged in the wafer 210 when etching the isolation ring groove or the via groove, causing the electronic components to fail.
  • a photoresist 72 covering the passive surface of the chip 21 is made.
  • the photoresist 72 can be a positive photoresist or a negative photoresist.
  • a photoresist 72 covering the dielectric layer 71 on the passive surface of the chip 21 needs to be made.
  • the photoresist 72 is photolithographically processed to form a via window 73 and an isolation ring window 74 , wherein the via window 73 is specifically circular, and the isolation ring window 74 is specifically annular, and the isolation ring window 74 surrounds the via window 73 .
  • the chip 21 is etched through the via opening 73 shown in FIG17 , and the dielectric layer 71 and the wafer 210 of the chip 21 need to be etched to form the via groove 75 shown in FIG18 , wherein the via groove 75 does not contact the metal wiring 212.
  • the chip 21 is etched through the isolation ring opening 74 shown in FIG17 , and the dielectric layer 71 and the wafer 210 of the chip 21 need to be etched to form the isolation ring groove 76 shown in FIG18 .
  • the etching stop layer of the etching process is the dielectric layer 211.
  • silicon dioxide or silicon nitride is deposited in the via groove 75 and the isolation ring groove 76 shown in FIG. 18 by chemical vapor deposition, and then a dielectric layer 215 is formed on the side wall of the via groove 75, and an isolation ring 216 is formed in the isolation ring groove 76, wherein the ring width of the isolation ring groove is greater than or equal to 0.1 microns and less than or equal to 1 micron, and the diameter of the fabricated via groove is greater than or equal to 1 micron. Based on the size difference between the via groove and the isolation ring groove, the same step of chemical vapor deposition can make the isolation ring 216 formed include an air gap 217.
  • etching is performed in the via trench 75 of the dielectric layer 215 formed on the sidewall shown in FIG. 19 , and the etching stop layer this time is the metal wiring 212 , forming a metal line trench 77 , wherein the metal line trench 77 is in contact with the metal wiring 212 .
  • the metal line material is deposited in the metal line trench 77 shown in Fig. 20 to form the metal line 214, thereby forming the chip 21 shown in Fig. 5.
  • the metal line material includes metal materials such as copper and tungsten.
  • a dielectric layer material is deposited on the surface of the metal line 214 to protect the metal on the surface of the metal line 214.
  • a metal connection process may be performed later to enable the metal line 214 to be electrically connected to other metal wirings.
  • the isolation ring may be manufactured first, and then the via hole may be manufactured.
  • a dielectric layer 211 may be formed on one side of the wafer 210, and one or more metal wirings may be formed in the dielectric layer 211.
  • FIG. 21 shows only one metal wiring 212, wherein the metal wiring in the dielectric layer 211 is electrically connected to the electronic components disposed in the wafer of the chip to form a circuit structure.
  • the active surface of the chip 21 is the side of the dielectric layer 211 away from the wafer 210, and the passive surface of the chip 21 is the side of the wafer 210 away from the dielectric layer 211.
  • the passive surface of the chip 21 is used as the working surface, and via holes and isolation rings are formed in the wafer 210 of the chip 21.
  • the substrate portion of the wafer 210 of the chip 21 exposed on the passive surface of the chip 21 needs to be thinned to the required thickness to facilitate subsequent operations.
  • a dielectric layer 81 needs to be deposited on the passive surface of the chip 21 to protect the substrate of the wafer 210 exposed on the passive surface of the chip 21 to avoid the wafer 210 being electrically connected to the metal circuit when the material of the metal circuit is subsequently deposited, or to avoid etching through the electronic components set in the wafer 210 when etching the isolation ring groove or the via groove, causing the electronic components to fail.
  • the dielectric layer 61, the dielectric layer 71, and the dielectric layer 81 are the same material layers formed in different manufacturing steps.
  • a photoresist 82 covering the passive surface of the chip 21 is made.
  • the photoresist 82 can be a positive photoresist or a negative photoresist.
  • a photoresist 82 covering the dielectric layer 81 on the passive surface of the chip 21 needs to be made.
  • the photoresist 82 is photolithographically processed to form an isolation ring window 83 , wherein the isolation ring window 83 is specifically in the shape of a circular ring.
  • the chip 21 is etched through the isolation ring opening 83 shown in FIG. 21. It is necessary to etch through the dielectric layer 81 and the wafer 210 to form the isolation ring groove 84 shown in FIG. 22.
  • the etching process The etching stop layer of the process is the dielectric layer 211.
  • an isolation ring material is deposited in the isolation ring groove 84 shown in FIG. 22 by chemical vapor deposition to form an isolation ring 216 .
  • isolation ring 216 shown in FIG. 4 when forming the structure of the isolation ring 216 shown in FIG. 4 , one or more of the following materials may be deposited in the isolation ring groove 84 shown in FIG. 22 to prepare the isolation ring 216: SiLK, carbon-doped silicon oxide, hydrogen silses quioxane (HSQ), methyl silses quioxane (MSQ) and Nanoglass.
  • SiLK silicon-doped silicon oxide
  • HSQ hydrogen silses quioxane
  • MSQ methyl silses quioxane
  • Nanoglass Nanoglass.
  • silicon dioxide or silicon nitride may be deposited in the isolation ring groove 84 shown in FIG. 22 , and the ring width of the isolation ring groove 84 is greater than or equal to 0.1 micrometers and less than or equal to 1 micrometer.
  • the isolation ring 216 formed will include an air gap 217.
  • the isolation ring 216 shown in FIG. 23 includes an air gap 217.
  • a photoresist 85 covering the passive surface of the chip 21 is formed on the passive surface of the chip 21.
  • the photoresist 85 may be a positive photoresist or a negative photoresist.
  • a photoresist 85 covering the dielectric layer 81 on the passive surface of the chip 21 needs to be formed.
  • the photoresist 85 is subjected to photolithography to form a via opening 86 , wherein the via opening 86 is specifically circular.
  • the chip 21 is etched through the via opening 86 shown in FIG. 24 , and the dielectric layer 81 and the wafer 210 need to be etched to form a via groove 87 shown in FIG. 25 , wherein the via groove 87 does not contact the metal wiring 212 .
  • a dielectric layer material is deposited in the via groove 87 shown in FIG. 25 by chemical vapor deposition, wherein the dielectric layer material includes silicon dioxide, silicon nitride, etc., thereby forming a dielectric layer 215 (that is, the first dielectric layer mentioned above) on the sidewall of the via groove 87 .
  • etching is performed in the via trench 87 with the dielectric layer 215 formed on the sidewall, and the etching stop layer this time is the metal wiring 212 , forming a metal line trench 88 , wherein the metal line trench 88 is in contact with the metal wiring 212 .
  • the metal line material is deposited in the metal line trench 88 shown in Fig. 26 to form the metal line 214, thereby forming the chip 21 shown in Fig. 5.
  • the metal line material includes metal materials such as copper and tungsten.
  • a dielectric layer material is deposited on the surface of the metal line 214 to protect the metal on the surface of the metal line 214.
  • a metal connection process may be performed later to enable the metal line 214 to be electrically connected to other metal wirings.

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Abstract

提供了一种芯片、芯片堆叠结构、芯片封装结构以及电子设备，涉及半导体技术领域，芯片中的过孔，例如可以是硅通孔(through silicon via，TSV)在通过交流信号时，产生的寄生电容较小，进而使得芯片的信号传输性能提高。芯片（21）包括晶片（210）；晶片（210）中设置有过孔（213），过孔（213）中设置有金属线路（214），在金属线路（214）和晶片（210）之间设置有第一介质层（215），晶片（210）中还包括环绕过孔（213）的第一隔离环（216），第一隔离环（216）的介电常数小于第一介质层（215）的材料的介电常数。

Description

芯片、芯片堆叠结构、芯片封装结构以及电子设备
本申请要求于2022年10月31日提交国家知识产权局、申请号为202211345283.4、申请名称为“芯片、芯片堆叠结构、芯片封装结构以及电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体技术领域，尤其是涉及一种芯片、芯片堆叠结构、芯片封装结构以及电子设备。
背景技术
目前，电子设备向着尺寸更小、功能更强的趋势发展，电子设备的尺寸取决于电子设备中的芯片的尺寸。近年来，芯片的平面尺寸已经缩减到极限，三维(three dimensional，3D)堆叠封装技术为芯片的尺寸缩减提供了新的解决方案。其中，3D堆叠封装技术之一是使用硅通孔(through silicon via，TSV)构造芯片堆叠结构，该芯片堆叠结构中包括两个或多个垂直堆叠的芯片，该两个或多个垂直堆叠的芯片中的任意两个芯片之间可以通过硅通孔电连接，例如可以将硅通孔设置于第一芯片中，第二芯片与硅通孔电连接，那么信号通过硅通孔可以在第一芯片与第二芯片之间传输。
但是，当硅通孔中通过交流信号时，硅通孔与第一芯片中设置的其他电子元器件之间会产生较大的寄生电容，寄生电容将使得第一芯片的电阻电容延迟(resistance capacitance delay，RC delay)增加，进而降低第一芯片的信号传输性能。
发明内容
本申请的实施例提供了一种芯片、芯片堆叠结构、芯片封装结构以及电子设备，该芯片中的过孔，例如可以是硅通孔(through silicon via，TSV)在通过交流信号时，产生的寄生电容较小，进而使得该芯片的信号传输性能提高。
第一方面，提供了一种芯片，包括晶片；晶片中设置有过孔，过孔中设置有金属线路，在金属线路和晶片之间设置有第一介质层；晶片中还包括环绕过孔的第一隔离环，第一隔离环的介电常数小于第一介质层的材料的介电常数。在该芯片中，过孔通过信号使得芯片与其他芯片实现信号互通时，由于过孔中的金属线路与晶片之间设置有第一介质层，因此过孔中的金属线路、晶片以及第一介质层将构成一个电容器C1，其中，电容器C1的一个电极为过孔中的金属线路，电容器C1的另一个电极为晶片，电容器C1两个电极之间的介电材料为第一介质层,另外，由于第一隔离环环绕过孔，因此，第一隔离环、以及第一隔离环两侧的晶片也将构成一个电容器C2，其中，电容器C2的一个电极为第一隔离环一侧的晶片，电容器C2的另一个电极为第一隔离环另一侧的晶片，电容器C2两个电极之间的介电材料为第一隔离环，其中，由于第一隔离环的介电常数小于第一介质层的材料的介电常数小，因此，电容器C2的电容值将小于电容器C1的电容值小，那么，在信号通过过孔传输时，相当于在过孔与芯片中的晶片中设置的电子元器件之间串联了电容器C1与电容器C2，该串联后的等效电容为C，C＝(C1*C2)/(C1+C2)，即1/C＝(1/C1)+(1/C2)，可见，在串联电容器C1与电容器C2以后，可以使得过孔与芯片中的晶片中设置的电子元器件之间的寄生电容减小，进而使得该芯片的信号传输性能提高。
可选的，第一隔离环中包括空气隙。在该可选方案中，在第一隔离环中包括空气隙时，空气隙的介电常数更低，进而使得电容器C2的电容值进一步降低，使得过孔与芯片中的晶片中设置的电子元器件之间的寄生电容也进一步降低，进而使得该芯片的信号传输性能提高。
可选的，晶片中还包括环绕第一个隔离环的第二隔离环，第二隔离环的介电常数小于第一介质层的材料的介电常数。在该可选方式中，由于第二隔离环环绕第一隔离环，因此，第二隔离环、以及第二隔离环两侧的晶片也将构成一个电容器C3，其中，电容器C3的一个电极为第二隔离环一侧的晶片，电容器C3的另一个电极为第二隔离环另一侧的晶片，电容器C3两个电极之间的介电材料为第二隔离环，其中，由于第二隔离环的介电常数小于第一介质层的材料的介电常数，因此，电容器C3的电容值将会小于电容器C1的电容值，那么，在信号通过过孔传输时，相当于在过孔与 芯片中的晶片中设置的电子元器件之间串联了电容器C1、电容器C2与电容器C3，该串联后的等效电容将再次减小，使得过孔与芯片中的晶片中设置的电子元器件之间的寄生电容也再次降低，以使得该芯片的信号传输性能更高。
可选的，第二隔离环中包括空气隙。在该可选方案中，在第二隔离环中包括空气隙时，空气隙的介电常数更低，进而使得电容器C3的电容值进一步降低，使得过孔与芯片中的晶片中设置的电子元器件之间的寄生电容也进一步降低，进而使得该芯片的信号传输性能提高。
可选的，第一隔离环与过孔之间的距离大于等于0.5微米。
可选的，第一隔离环的环宽大于等于0.1微米，小于等于1微米。
可选的，第一过孔的直径大于等于1微米。
可选的，金属线路的材料包括铜、钨。
可选的，芯片还包括第二介质层，第二介质层设置于晶片的一侧，金属线路与第二介质层中的金属布线电连接。
第二方面，提供了一种芯片堆叠结构，芯片堆叠结构中包括多个堆叠设置的芯片，多个堆叠设置的芯片中包括如上述第一方面任一项所述的芯片。
可选的，多个堆叠设置的芯片包括第一芯片和第二芯片；第一芯片和第二芯片均包括设置于晶片一侧的第二介质层；在多个堆叠设置的芯片中，第一芯片的晶片设置于第一芯片的第二介质层与第二芯片的第二介质层之间，且，第一芯片的第二介质层设置于第一芯片的晶片与第二芯片的晶片之间；第一芯片的金属线路的一端与第一芯片的第二介质层中的金属布线电连接，第一芯片的金属线路的另一端与第二芯片的第二介质层中的金属布线电连接。在该可选方式中，第一芯片的第二介质层中设置有一个或多个金属布线，第一芯片的第二介质层中的金属布线与第一芯片中的晶片中设置的电子元器件电连接形成电路结构，那么，第一芯片的有源面位于第一芯片的第二介质层远离第一芯片的晶片的一面；第二芯片的第二介质层中设置有一个或多个金属布线，第二芯片的第二介质层中的金属布线与第二芯片中的晶片中设置的电子元器件电连接形成电路结构，那么，第二芯片的有源面位于第二芯片的第二介质层远离第二芯片的晶片的一面。另外，第一芯片的晶片设置于第一芯片的第二介质层与第二芯片的第二介质层之间，且，第一芯片的第二介质层设置于第一芯片的晶片与第二芯片的晶片之间，因此，第二芯片的有源面与第一芯片的无源面键合，该键合方式也被称为face-to-back键合。其中，第一芯片的金属线路的一端与第一芯片的第二介质层中的金属布线电连接，第一芯片的金属线路的另一端与第二芯片的第二介质层中的金属布线电连接，因此第一芯片的有源面接收的信号可以通过第一芯片的第二介质层的金属布线、第一芯片的过孔中的金属线路传输至第二芯片的有源面，进而通过第二芯片的第二介质层的金属布线传输至第二芯片的晶片中设置的电子元器件中；或者，第二芯片的有源面接收的信号可以通过第二芯片的第二介质层的金属布线、第一芯片的过孔中的金属线路传输至第一芯片的有源面，进而通过第一芯片的第二介质层的金属布线传输至第一芯片的晶片中设置的电子元器件中。也就表示，通过设置第一芯片的过孔中的金属线路，可以使得第二芯片与第一芯片之间实现信号互通。
可选的，多个堆叠设置的芯片包括第一芯片和第二芯片；第一芯片和第二芯片均包括设置于晶片一侧的第二介质层；在多个堆叠设置的芯片中，第二芯片的第二介质层以及第一芯片的第二介质层设置于第一芯片的晶片与第二芯片的晶片之间；第一芯片的金属线路的一端与第一芯片的第二介质层中的金属布线电连接，第一芯片的第二介质层中的金属布线与第二芯片的第二介质层中的金属布线电连接。在该可选方式中，第一芯片的第二介质层中设置有一个或多个金属布线，第一芯片的第二介质层中的金属布线与第一芯片中的晶片中设置的电子元器件电连接形成电路结构，那么，第一芯片的有源面位于第一芯片的第二介质层远离第一芯片的晶片的一面；第二芯片的第二介质层中设置有一个或多个金属布线，第二芯片的第二介质层中的金属布线与第二芯片中的晶片中设置的电子元器件电连接形成电路结构，那么，第二芯片的有源面位于第二芯片的第二介质层远离第二芯片的晶片的一面。另外，第二芯片的第二介质层以及第一芯片的第二介质层设置于第一芯片的晶片与第二芯片的晶片之间，因此，第二芯片的有源面与第一芯片的有源面键合，该键合方式也被称为face-to-face键合。其中，第一芯片的金属线路的一端与第一芯片的第二介质层中的金属布线电连接，第一芯片的第二介质层中的金属布线与第二芯片的第二介质层中的金 属布线电连接，因此第一芯片的有源面接收的信号可以通过第一芯片的第二介质层的金属布线传输至第二芯片的有源面，进而通过第二芯片的第二介质层的金属布线传输至第二芯片的晶片中设置的电子元器件中；或者，第二芯片的有源面接收的信号可以通过第二芯片的第二介质层的金属布线传输至第一芯片的有源面，进而通过第一芯片的第二介质层的金属布线传输至第一芯片的晶片中设置的电子元器件中，也就表示，第二芯片与第一芯片之间可以实现信号互通。其中，在一些信号是通过第一芯片的无源面传输至第一芯片的有源面时，该信号通过第一芯片的过孔中的金属线路传输至第一芯片的有源面，进而通过第一芯片的第二介质层中的金属布线传输至第一芯片的晶片中设置的电子元器件中，由于第一芯片与第二芯片之间可以实现信号互通，因此通过第一芯片的无源面传输至第一芯片的有源面的信号也可以传输至第二芯片的有源面。
可选的，多个堆叠设置的芯片包括第一芯片和第二芯片；第一芯片和第二芯片均包括设置于晶片一侧的第二介质层；在多个堆叠设置的芯片中，第二芯片的晶片以及第一芯片的晶片设置于第一芯片的第二介质层与第二芯片的第二介质层之间；第一芯片的金属线路的一端与第一芯片的第二介质层中的金属布线电连接，第二芯片的金属线路的一端与第二芯片的第二介质层中的金属布线电连接，第一芯片的金属线路的另一端与第二芯片的金属线路的另一端电连接。在该可选方式中，第一芯片的第二介质层中设置有一个或多个金属布线，第一芯片的第二介质层中的金属布线与第一芯片中的晶片中设置的电子元器件电连接形成电路结构，那么，第一芯片的有源面位于第一芯片的第二介质层远离第一芯片的晶片的一面；第二芯片的第二介质层中设置有一个或多个金属布线，第二芯片的第二介质层中的金属布线与第二芯片中的晶片中设置的电子元器件电连接形成电路结构，那么，第二芯片的有源面位于第二芯片的第二介质层远离第二芯片的晶片的一面。另外，第二芯片的晶片以及第一芯片的晶片设置于第一芯片的第二介质层与第二芯片的第二介质层之间，因此，第二芯片的无源面与第一芯片的无源面键合，该键合方式也被称为back-to-back键合。其中，第一芯片的金属线路的一端与第一芯片的第二介质层中的金属布线电连接，第二芯片的金属线路的一端与第二芯片的第二介质层中的金属布线电连接，第一芯片的金属线路的另一端与第二芯片的金属线路的另一端电连接，因此第一芯片的有源面接收的信号可以通过第一芯片的第二介质层的金属布线、第一芯片的过孔中的金属线路、第二芯片的过孔中的金属线路传输至第二芯片的有源面，进而通过第二芯片的第二介质层的金属布线传输至第二芯片的晶片中设置的电子元器件中；或者，第二芯片的有源面接收的信号可以通过第二芯片的第二介质层的金属布线、第二芯片的过孔中的金属线路、第一芯片的过孔中的金属线路传输至第一芯片的有源面，进而通过第一芯片的第二介质层的金属布线传输至第一芯片的晶片中设置的电子元器件形成的电路结构中，也就表示，通过设置第一芯片的过孔中的金属线路以及第二芯片的过孔中的金属线路，可以使得第二芯片与第一芯片之间实现信号互通。
第三方面，提供了一种芯片封装结构，包括封装基板以及如上述第二方面任一项所述的芯片堆叠结构；芯片堆叠结构与封装基板电连接。
第四方面，提供了一种电子设备，包括印刷电路板以及如上述第二方面所述的芯片封装结构；芯片封装结构中的封装基板与印刷电路板电连接。
第五方面，提供了一种芯片的制作方法，包括：在晶片中形成过孔，在过孔中形成金属线路和第一介质层，其中，第一介质层位于金属线路与晶片之间；形成第一隔离环，其中第一隔离环绕过孔，第一隔离环的介电常数小于第一介质层的材料的介电常数。
其中，第三方面以及第四方面中任一种可能实现方式中所带来的技术效果可参见上述第二方面以及第一方面不同的实现方式所带来的技术效果，第五方面中所带来的技术效果可参见上述第一方面不同的实现方式所带来的技术效果，此处不再赘述。
附图说明
图1是本申请的实施例提供的电子设备的结构示意图；
图2是本申请的实施例提供的芯片封装结构的结构示意图；
图3是本申请的实施例提供的芯片堆叠结构的结构示意图；
图4是本申请的实施例提供的芯片的结构示意图；
图5是本申请的另一实施例提供的芯片的结构示意图；
图6是本申请的又一实施例提供的芯片的结构示意图；
图7是本申请的再一实施例提供的芯片的结构示意图；
图8是本申请的另一实施例提供的芯片堆叠结构的结构示意图；
图9是本申请的又一实施例提供的芯片堆叠结构的结构示意图；
图10是本申请的再一实施例提供的芯片堆叠结构的结构示意图；
图11是本申请的实施例提供的芯片的制作方法的流程图；
图12是本申请的另一实施例提供的芯片的制作方法中的芯片的结构示意图一；
图13是本申请的另一实施例提供的芯片的制作方法中的芯片的结构示意图二；
图14是本申请的另一实施例提供的芯片的制作方法中的芯片的结构示意图三；
图15是本申请的另一实施例提供的芯片的制作方法中的芯片的结构示意图四；
图16是本申请的另一实施例提供的芯片的制作方法中的芯片的结构示意图五；
图17是本申请的又一实施例提供的芯片的制作方法中的芯片的结构示意图一；
图18是本申请的又一实施例提供的芯片的制作方法中的芯片的结构示意图二；
图19是本申请的又一实施例提供的芯片的制作方法中的芯片的结构示意图三；
图20是本申请的又一实施例提供的芯片的制作方法中的芯片的结构示意图四；
图21是本申请的再一实施例提供的芯片的制作方法中的芯片的结构示意图一；
图22是本申请的再一实施例提供的芯片的制作方法中的芯片的结构示意图二；
图23是本申请的再一实施例提供的芯片的制作方法中的芯片的结构示意图三；
图24是本申请的再一实施例提供的芯片的制作方法中的芯片的结构示意图四；
图25是本申请的再一实施例提供的芯片的制作方法中的芯片的结构示意图五；
图26是本申请的再一实施例提供的芯片的制作方法中的芯片的结构示意图六。
具体实施方式
下面将结合本申请的实施例中的附图，对本申请的实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。
除非另有定义，否则本文所用的所有科技术语都具有与本领域普通技术人员公知的含义相同的含义。在本申请的实施例中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b或c中的至少一项(个)，可以表示：a，b，c，a和b，a和c，b和c或a、b和c，其中a、b和c可以是单个，也可以是多个。另外，在本申请的实施例中，“第一”、“第二”等字样并不对数量和次序进行限定。
此外，本申请的实施例中，“上”、“下”等方位术语是相对于附图中的部件示意置放的方位来定义的，应当理解到，这些方向性术语是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中部件所放置的方位的变化而相应地发生变化。
本申请的实施例中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请的实施例中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其他实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
下面将结合附图，对本申请的实施例中的技术方案进行描述。
本申请的实施例提供一种电子设备。该电子设备可以包括手机(mobile phone)、平板电脑(pad)、电视、智能穿戴产品(例如，智能手表、智能手环)、虚拟现实(vitual reality，VR)设备、增强现实(augmented reality，AR)设备等，本申请实施例对上述电子设备的具体形式不做特殊限制。
示例性的，参照图1所示，本申请的实施例提供了上述电子设备的结构示意图，其中，上述电子设备10包括印制电路板(printed circuit board，PCB)12和芯片封装结构11，芯片封装结构11与PCB12电连接，因此，芯片封装结构11能够与PCB12上的其他芯片或者其他模块实现 互连。示例性的，参照图1所示，芯片封装结构11与PCB12之间还设置有电连接结构c1，该电连接结构c1可以是球阵列(ball grid array，BGA)，其中，芯片封装结构11具体是通过电连接结构c1与PCB12电连接。
参照图2所示，其中，图2所示的是一种芯片封装结构11，该芯片封装结构11包括封装基板30和基于三维(three dimensional，3D)堆叠封装技术构造的芯片堆叠结构20，芯片封装结构11与PCB12电连接，具体是芯片封装结构11中的封装基板30与PCB12电连接，其中，该芯片堆叠结构20中包括两个或多个垂直堆叠的芯片，其中，芯片堆叠结构20与封装基板30电连接。示例性的，参照图2所示，芯片堆叠结构20与封装基板30之间还设置有电连接结构c2，该电连接结构c2可以是微凸点(micro bump，uBump)，也可以是可控塌陷芯片连接焊点(controlled collapse chip connection，简称C4)，芯片堆叠结构20具体是通过电连接结构c2与封装基板30电连接。
示例性的，参照图3所示，本申请的实施例提供了一种的芯片堆叠结构20的剖面图，参照图3所示，该芯片堆叠结构20包括多个堆叠设置的芯片，多个堆叠设置的芯片中包括芯片21以及芯片22，按照图3所示的芯片堆叠结构20的摆放位置，芯片22设置于芯片21上方，芯片21中包括晶片210以及设置于晶片210的一侧的介质层211，具体的，介质层211设置于晶片210的下方。芯片22中包括晶片220以及设置于晶片220的一侧的介质层221，具体的，介质层221设置于晶片220的下方，晶片210设置于介质层211与介质层221之间，且，介质层221设置于晶片210与晶片220之间。其中，晶片210中还设置有硅通孔(through silicon via，TSV)213，硅通孔213中设置有金属线路214以及设置于金属线路214与晶片210之间的介质层215，金属线路214的一端与芯片21的介质层211中的金属布线212电连接，金属线路214的另一端与芯片22的介质层221中的金属布线222电连接。
示例性的，以芯片21为例进行说明，芯片21中的晶片210中通常会设置一些电子元器件，例如在图3中示出了一个电子元器件EC，其中，晶片210中设置的电子元器件包括电容、电阻、二极管(diode)、三极管(bipolar junction transistor，BJT)、金属-氧化物半导体场效应晶体管(metal-oxide-semiconductor field effect transistor,MOSFET)等。其中，晶片210的一侧设置的介质层211中，往往会设置有一个或多个金属布线，该一个或多个金属布线与芯片21中的晶片210中设置的电子元器件电连接形成电路结构，通常，芯片21的有源面为芯片21的介质层211远离晶片210的一面，芯片21的无源面为芯片21的晶片210远离介质层211的一面。在一些实施例中，芯片21的介质层211以及设置于介质层211中的一个或多个金属布线也被称为重布线层(redistribution layer，RDL)。
示例性的，参照图3所示，按照图3所示的芯片堆叠结构20的摆放位置，其中，介质层211中的金属布线212与芯片21中的晶片210中设置的电子元器件电连接，且介质层211位于晶片210的下方，那么芯片21的有源面位于介质层211的下面，芯片21的无源面位于晶片210的上面；由于介质层221中的金属布线与芯片22中的晶片220中设置的电子元器件电连接，且介质层221位于晶片220的下方，那么芯片22的有源面位于介质层211的下面，芯片22的无源面位于晶片210的上面。另外，晶片210设置于介质层211与介质层221之间，且，介质层221设置于晶片210与晶片220之间，因此，芯片22的有源面与芯片21的无源面键合，该键合方式也被称为face-to-back键合。由于在晶片210中还设置有贯穿晶片210的硅通孔213，且硅通孔213中的金属线路214的一端与芯片21的介质层211中的金属布线212电连接，硅通孔213中的金属线路214的另一端与芯片22的介质层221中的金属布线222电连接，因此芯片21的有源面接收的信号可以通过金属布线212、硅通孔213中的金属线路214传输至芯片22的有源面，进而通过芯片22的介质层221中的金属布线222传输至芯片22的晶片220中设置的电子元器件中，或者，芯片22的有源面接收的信号可以通过金属布线222、硅通孔213中的金属线路214传输至芯片21的有源面，进而通过芯片21的介质层211中的金属布线212传输至芯片21的晶片210中设置的电子元器件形成的电路结构中。也就表示，通过设置硅通孔213中的金属线路214，使得芯片21可以与芯片22之间实现信号互通。
其中，在图3所示的芯片堆叠结构20中，当硅通孔213中的金属线路214通过信号使得芯片 21可以与芯片22之间实现信号互通时，由于金属线路214与晶片210之间还设置有介质层215，因此，晶片210、金属线路214以及介质层215，会构成一个电容器C，该电容器C的一个电极为金属线路214，该电容器C的另一个电极为晶片210，该电容器C的介电材料为介质层215。该电容器C的存在使得硅通孔213中的金属线路214与芯片21的晶片210中设置的电子元器件EC之间产生较大的寄生电容，该寄生电容会对电子元器件EC的正常工作造成影响，其中，寄生电容将使得芯片21的电阻电容延迟(resistance capacitance delay，RC delay)增加，进而影响芯片21的信号传输性能。
因此，本申请的实施例提供了一种芯片，参照图4所示，该芯片21中的过孔在通过交流信号时，过孔中的金属线路与芯片21的晶片中设置的电子元器件之间产生的寄生电容较小，进而使得该芯片21的信号传输性能提高。其中，图4中的(a)为芯片21的俯视图，图4中的(b)为芯片21沿图4中的(a)所示的AA’的剖面图。
在图4所示的芯片21中，包括晶片210。示例性的，芯片21还包括设置于晶片210的一侧的介质层211，其中，介质层211中设置有一个或多个金属布线，图4中仅示出一个金属布线212，介质层211中的金属布线与芯片21的晶片210中设置的电子元器件电连接形成电路结构，芯片21的有源面为芯片21的介质层211远离晶片210的一面，芯片21的无源面为芯片21的晶片210远离介质层211的一面。具体的，按照图4所示的芯片21的摆放位置，介质层211位于晶片210的下方，因此芯片21的有源面位于介质层211的下面。
晶片210中设置有过孔213，过孔213中设置有金属线路214，金属线路214与晶片210之间设置有介质层215。示例性的，参照图4所示，过孔213中的金属线路214与介质层211中的金属布线212电连接，过孔213贯穿晶片210，在此情况下，当图4所示的芯片21与图3所示的芯片22按照face-to-back键合方式键合时，过孔213中的金属线路214的一端与介质层211中的金属布线212电连接，过孔213中的金属线路214的另一端与介质层221中的金属布线222电连接。在另一些实施例中，图4所示的过孔213可以不贯穿晶片210，示例性的，在晶片210中设置有一个电子元器件时，可以是过孔213中的金属线路214的一端与介质层211中的金属布线212电连接，过孔213中的金属线路214的另一端与设置于晶片210中的电子元器件电连接。
示例性的，金属线路214的材料包括铜、钨，金属线路214的材料是导电材料，只有在金属线路214的材料为导电材料时，信号才能通过过孔213中的金属线路214传输。其中，过孔213通常会设置为圆柱形，该圆柱形的过孔213的直径大于等于1微米。在另一些实施例中，过孔213还可以设置为棱柱形，设置为棱柱形的过孔213的底面可以是任意多边形，该任意多边形的边长可以大于等于1微米。在一些实施例中，过孔213中的金属线路214的底面为圆形。在另一些实施例中，过孔213中的金属线路214的底面为环形。
示例性的，当晶片210的材料包括硅时，过孔213通常也被称为硅通孔。在另一些实施例中，晶片210的材料还可以包括：氮化镓(GaN)、碳化硅(SiC)、砷化镓(GaAs)、磷化铟(InP)，本申请的实施例对晶片210的材料不做限定。示例性的，介质层215通常使用绝缘材料，在一些实施例中，介质层215的材料包括二氧化硅、氮化硅等，在过孔213中的金属线路214通过信号时，介质层215可以使得金属线路214与晶片210之间绝缘。
晶片210中还包括环绕过孔213的隔离环216，隔离环216的介电常数小于介质层215的材料的介电常数。示例性的，参照图4所示，隔离环216的底面为环形，例如可以是圆环形或者多边环形，隔离环216环绕过孔213，并且，隔离环216与过孔213不接触。
示例性的，参照图4所示，当过孔213贯穿晶片210时，隔离环216环绕过孔213，并且，隔离环216也贯穿晶片210，其中，通过设置隔离环216，可以将晶片210分隔为晶片区域210a与晶片区域210b，其中，晶片区域210a中设置有过孔213，晶片区域210b中设置有电子元器件，示例性的，图4中以电子元器件EC为例进行说明，其中，通过设置隔离环216，可以将电子元器件EC与过孔213分隔开。在一些实施例中，隔离环216与过孔213之间的距离大于等于0.5微米，隔离环216的底面的环宽大于等于0.1微米，小于等于1微米。即晶片区域210a在隔离环216与过孔213之间的宽度足够小时，可以确保晶片区域210a中不具有电子元器件EC，并且尽量减少对晶片的有效面积的浪费。
在一些实施例中，当晶片210包括两个或两个以上的过孔213时，那么晶片中也包括多个隔离环，一个隔离环环绕一个过孔213。在另一些实施例中，当晶片210包括两个或两个以上的过孔213时，那么晶片中可以包括一个或多个隔离环，其中，一个隔离环环绕两个或两个以上的过孔213。
在一些实施例中，介质层215的材料为二氧化硅或氮化硅，其中二氧化硅的介电常数约等于3.9。隔离环216的介电常数小于介质层215的材料的介电常数，其中隔离环216可以采用以下一种或多种材料制备：SiLK、碳掺杂氧化硅、hydrogen silses quioxane(HSQ)、methyl silses quioxane(MSQ)和Nanoglass。其中，SiLK是一种低介电常数材料，目前广泛用于芯片生产中，SiLK是一种高分子材料，介电常数为2.6；碳掺杂氧化硅的介电常数约为2.4至2.7；HSQ的介电常数可以达到2.9；MSQ是一种硅基高分子材料，介电常数可以达到2.2；Nanoglass的介电常数可以达到1.3。
其中，在图4所示的芯片21中的过孔通过交流信号时，由于过孔213中的金属线路214与晶片210之间设置有介质层215，因此过孔213中的金属线路214、晶片210以及介质层215将构成一个电容器C1，其中，电容器C1的一个电极为过孔213中的金属线路214，电容器C1的另一个电极为晶片210，具体是晶片区域210a，电容器C1两个电极之间的介电材料为介质层215,另外，由于隔离环216环绕过孔213，因此，隔离环216、以及隔离环216两侧的晶片210也将构成一个电容器C2，其中，电容器C2的一个电极为隔离环216一侧的晶片210，具体是晶片区域210a，电容器C2的另一个电极为隔离环216另一侧的晶片210，具体是晶片区域210b，电容器C2两个电极之间的介电材料为隔离环216，其中，由于隔离环216的介电常数小于介质层215的材料的介电常数，因此，电容器C2的电容值将小于电容器C1的电容值小，那么，在信号通过过孔213传输时，相当于在过孔213的金属线路214与芯片21的晶片210中设置的电子元器件EC之间串联了电容器C1与电容器C2，该串联后的等效电容为C，C＝(C1*C2)/(C1+C2)，即1/C＝(1/C1)+(1/C2)，可见，在串联电容器C1与电容器C2以后，可以使得过孔213的金属线路214与芯片21的晶片210中设置的电子元器件EC之间的寄生电容减小，进而使得该芯片21的信号传输性能提高。
参照图5所示，基于图4所示的芯片21的基础上，图5所示的芯片21中，隔离环216中还包括空气隙217，其中，示例性的，当制作隔离环时，先通过刻蚀工艺刻蚀出隔离环沟槽，在隔离环中沟槽中通过化学气相沉积(chemical vapor deposition，CVD)的方式沉积隔离环材料，由于隔离环216的底面为圆环形，该圆环的环宽大于等于0.1微米，小于等于1微米，因此，隔离环沟槽的环宽大于等于0.1微米，小于等于1微米，在这样的尺寸大小的隔离环沟槽中通过化学气相沉积的方式沉积隔离环材料时，会使得沉积的隔离环材料附着于隔离环沟槽的底部以及侧壁，且在隔离环沟槽的开口处会先封口，因此形成的隔离环216中会包括空气隙217。其中，空气隙217中的空气的介电常数为1，因此，该电容器C2的电容值将会更小，进一步降低过孔213中的金属线路214与芯片21的晶片210中设置的电子元器件EC之间的寄生电容。
在隔离环216中还包括空气隙217时，隔离环216也可以采用二氧化硅或氮化硅制备。由于采用二氧化硅或氮化硅制备的隔离环216中形成有空气隙217，因此隔离环216的介电常数也会低于二氧化硅或氮化硅的介电常数。
示例性的，介质层211的材料包括二氧化硅、氮化硅。介质层215的材料包括二氧化硅、氮化。其中，介质层211的材料可以与介质层215的材料相同，或者，介质层211的材料也可以与介质层215的材料不同，本申请的实施例对此不做限定。
在另一些实施例中，隔离环216的材料、介质层215的材料、介质层211的材料可以都相同使用二氧化硅，本申请的实施例对此不做限定。
示例性的，参照图6所示，在图5所示的芯片21的基础上，在图6所示的芯片21中，晶片210还包括：环绕隔离环216的隔离环218，隔离环218的介电常数小于介质层215的材料的介电常数。示例性的，参照图6所示，当过孔213贯穿晶片210时，隔离环216环绕过孔213，并且，隔离环216也贯穿晶片210，隔离环218环绕隔离环216，并且，隔离环218也贯穿晶片210，其中，通过设置隔离环216以及隔离环218，可以将电子元器件EC与过孔213分隔开。
在一些实施例中，介质层215的材料为二氧化硅，二氧化硅的介电常数约等于3.9。隔离环218的介电常数小于介质层215的材料的介电常数，其中隔离环218可以采用以下一种或多种材料制备：SiLK、碳掺杂氧化硅、hydrogen silses quioxane(HSQ)、methyl silses quioxane(MSQ)和Nanoglass。
其中，由于隔离环218环绕隔离环216，因此，隔离环218、以及隔离环218两侧的晶片210也将构成一个电容器C3，其中，电容器C3的一个电极为隔离环218一侧的晶片210，电容器C3的另一个电极为隔离环218另一侧的晶片210，电容器C3两个电极之间的介电材料为隔离环218，其中，由于隔离环218的介电常数小于介质层215的材料的介电常数因此，电容器C3的电容值将小于电容器C1的电容值，那么，在信号通过过孔213中的金属线路214传输时，相当于在过孔213的金属线路214与芯片21的晶片210中设置的电子元器件EC之间串联了电容器C1、电容器C2与电容器C3，该串联后的等效电容将再次减小，使得过孔213的金属线路214与芯片21中的晶片210中设置的电子元器件EC之间的寄生电容减小，以使得该芯片21的信号传输性能更高。
参照图7所示，基于图6所示的芯片21的基础上，图7所示的芯片21中，隔离环218中还包括空气隙219，其中，示例性的，当制作隔离环时，先通过刻蚀工艺刻蚀出隔离环沟槽，在隔离环中沟槽中通过化学气相沉积(chemical vapor deposition，CVD)的方式沉积隔离环材料，由于隔离环218的底面为圆环形，该圆环的环宽大于等于0.1微米，小于等于1微米，因此，隔离环沟槽的环宽大于等于0.1微米，小于等于1微米，在这样的尺寸大小的隔离环沟槽中通过化学气相沉积的方式沉积隔离环材料时，会使得沉积的隔离环材料附着于隔离环沟槽的底部以及侧壁，且在隔离环沟槽的开口处会先封口，因此形成的隔离环218中会包括空气隙219。其中，空气隙219中的空气的介电常数为1，因此，该电容器C3的电容值将会更小，进一步降低过孔213中的金属线路214与芯片21的晶片210中设置的电子元器件EC之间的等效电容。
在隔离环218中还包括空气隙219时，隔离环218也可以采用二氧化硅或氮化硅制备。由于采用二氧化硅或氮化硅制备的隔离环218中形成有空气隙219，因此隔离环218的介电常数也会低于二氧化硅或氮化硅的介电常数。
示例性的，本申请的实施例还提供了一种芯片堆叠结构，例如可以是图3所示的芯片堆叠结构20，其中，芯片堆叠结构20中包括多个堆叠设置的芯片，多个堆叠设置的芯片中包括图4-图7任一幅图中所示的芯片21，例如可以将图3所示的芯片堆叠结构20中的芯片21替换为图4-图7任一幅图中所示的芯片21。
示例性的，参照图8所示的芯片堆叠结构20，其中，图8所示的芯片堆叠结构20中，多个堆叠设置的芯片包括芯片21和芯片22；芯片21包括设置于晶片210一侧的介质层211；芯片22包括设置于晶片220一侧的介质层221；在多个堆叠设置的芯片中，芯片21的晶片210设置于芯片21的介质层211与芯片22的介质层221之间，且，芯片21的介质层211设置于芯片21的晶片210与芯片22的晶片220之间；芯片21的金属线路214的一端与芯片21的介质层211中的金属布线212电连接，芯片21的金属线路214的另一端与芯片22的介质层221中的金属布线222电连接。
示例性的，将图8所示的芯片堆叠结构20具体可以应用于高带宽存储器(high bandwidth memory，HBM)，或者应用于动态随机访问存储器(dynamic random access memory，DRAM)，或者应用于互补金属氧化物半导体(complementary metal oxide semiconductor，CMOS)图像传感器(CMOSimage sensor，CIS)，或者应用于NAND闪存(NANDFlash)等，本申请的实施例对此不做限定。
示例性的，图8所示的芯片21以图5所示的芯片21为例进行说明，当然图8所示的芯片堆叠结构20中的芯片21也可以是图4或图6或图7所示的芯片21，本申请的实施例对此不做限定。
在另一些实施例中，图8所示的芯片堆叠结构20中的芯片22也可以是图4-图7任一幅图中所示的芯片21，本申请的实施例对此不做限定。
示例性的，参照图8所示，按照图8所示的芯片堆叠结构20的摆放位置，其中，介质层211中设置有一个或多个金属布线，图8中仅示出一个金属布线212，介质层211中的金属布线与芯片21中的晶片210中设置的电子元器件电连接形成电路结构，那么，在介质层211位于晶片210的下方时，芯片21的有源面位于介质层211的下方；介质层221中设置有一个或多个金属布线，图8中仅示出一个 金属布线222，介质层221中的金属布线与芯片22中的晶片210中设置的电子元器件电连接形成电路结构，那么，在介质层221位于晶片220的下方时，芯片22的有源面位于介质层221的下方。另外，芯片21的晶片210设置于芯片21的介质层211与芯片22的介质层221之间，且，芯片21的介质层211设置于芯片21的晶片210与芯片22的晶片220之间，因此，芯片22的有源面与芯片21的无源面键合，该键合方式也被称为face-to-back键合。其中，过孔213中的金属线路214的一端与芯片21中的介质层中211中的金属布线212电连接，过孔213中的金属线路214的另一端与芯片22中的介质层中221中的金属布线222电连接，因此芯片21的有源面接收的信号可以通过金属布线212、过孔213中的金属线路214传输至芯片22的有源面，进而通过芯片22的介质层221中的金属布线222传输至芯片22的晶片220中设置的电子元器件中；或者，芯片22的有源面接收的信号可以通过金属布线222、过孔213中的金属线路214传输至芯片21的有源面，进而通过芯片21的介质层211中的金属布线212传输至芯片21的晶片210中设置的电子元器件中。也就表示，通过设置过孔213中的金属线路214，可以使得芯片21与芯片22之间实现信号互通。
示例性的，参照图8所示，在一些实施例中，为了使得芯片22与芯片21之间face-to-back键合，往往还会在芯片22的有源面与芯片21的无源面之间设置介电层100，介电层100作为熔融键合(fusion bonding)工艺的键合层，用于实现芯片22与芯片21的固定连接，其中，过孔213中的金属线路214贯穿介电层100与金属布线222电连接。
示例性的，在另一些实施例中，芯片21的无源面上也可以设置有介质层，该介质层用于保护芯片21的无源面上的晶片210，那么在芯片22的有源面与芯片21的无源面face-to-back键合时，过孔213中的金属线路214贯穿芯片21的无源面上设置的介质层与金属布线222电连接。在另一些实施例中，当芯片21的无源面上设置有介质层时，该介质层中也可以设置有金属布线，过孔213中的金属线路214可以与该介质层中的金属布线电连接，也可以不与该介质层中的金属布线电连接，本申请的实施例对此不做限定。
示例性的，图8所示的芯片堆叠结构20中的芯片21可以是晶粒(也可以称为颗粒或裸芯片)(die)，也可以是芯片晶圆；芯片堆叠结构20中的芯片22可以是晶粒(也可以称为颗粒或裸芯片)(die)，也可以是芯片晶圆。示例性的，在晶圆(wafer)上生长外延层后，可以形成芯片晶圆，对芯片晶圆进行切割后得到裸芯片(die)。参照图8所示，芯片21可以为晶粒，芯片22也可以为晶粒，这样的结构可以称为晶粒与晶粒键合(die-to-die bonding，D2D bonding)；或者，参照图8所示，芯片21可以为芯片晶圆，芯片22可以为芯片晶圆，这样的结构可以称为晶圆与晶圆键合(wafer-to-wafer bonding，W2W bonding)；或者，参照图8所示，芯片21可以为芯片晶圆，芯片22可以为晶粒，这样的结构可以称为晶粒与晶圆键合(die-to-wafer bonding，D2W bonding)。本申请的实施例对此不做限定。
在另一些实施例中，参照图9所示，其中，图9所示的芯片堆叠结构20中，多个堆叠设置的芯片包括芯片21和芯片22；芯片21包括设置于晶片210一侧的介质层211；芯片22包括设置于晶片220一侧的介质层221；在多个堆叠设置的芯片中，芯片22的介质层221以及芯片21的介质层211设置于芯片21的晶片210与芯片22的晶片220之间；芯片21的金属线路214的一端与芯片21的介质层211中的金属布线212电连接，芯片21的介质层211中的金属布线212与芯片22的介质层221中的金属布线222电连接。
示例性的，图9所示的芯片21以图5所示的芯片21为例进行说明，当然图9所示的芯片堆叠结构20中的芯片21也可以是图4或图6或图7所示的芯片21，本申请的实施例对此不做限定。
在另一些实施例中，图9所示的芯片堆叠结构20中的芯片22也可以是图4-图7任一幅图中所示的芯片21，本申请的实施例对此不做限定。
示例性的，参照图9所示，按照图9所示的芯片堆叠结构20的摆放位置，其中，介质层211中设置有一个或多个金属布线，图9中仅示出一个金属布线212，介质层211中的金属布线与芯片21中的晶片210中设置的电子元器件电连接形成电路结构，那么，在介质层211位于晶片210的上方时，芯片21的有源面位于介质层211的上面；介质层221中设置有一个或多个金属布线，图9中仅示出一个金属布线222，介质层221中的金属布线222与芯片22中的晶片220中设置的电子元器件电连接形成电路结构，那么，在介质层221位于晶片220的下方时，芯片22的有源面 位于介质层221的下方。另外，芯片22的介质层221以及芯片21的介质层211设置于芯片21的晶片210与芯片22的晶片220之间，因此，芯片22的有源面与芯片21的有源面键合，该键合方式也被称为face-to-face键合。其中，过孔213中的金属线路214的一端与介质层211中的金属布线212电连接，介质层211中的金属布线212与介质层221中的金属布线222电连接，因此芯片21的有源面接收的信号可以通过金属布线212传输至芯片22的有源面，进而通过芯片22的介质层221中的金属布线222传输至芯片22的晶片220中设置的电子元器件中，或者，芯片22的有源面接收的信号可以通过金属布线222传输至芯片21的有源面，进而通过芯片21的介质层211中的金属布线212传输至芯片21的晶片210中设置的电子元器件形成的电路结构中。也就表示，芯片21与芯片22之间可以实现信号互通。其中，在一些信号是通过芯片21的无源面传输至芯片21的有源面时，该信号通过过孔213中的金属线路214传输至芯片21的有源面，进而通过芯片21的介质层211中的金属布线212传输至芯片21的晶片210中设置的电子元器件中，由于芯片21与芯片22之间可以实现信号互通，因此通过芯片21的无源面传输至芯片21的有源面的信号也可以传输至芯片22的有源面。
示例性的，参照图9所示，在一些实施例中，为了使得芯片22与芯片21之间face-to-face键合，往往还会在芯片22的有源面与芯片21的有源面之间设置介电层100，介电层100作为熔融键合(fusion bonding)工艺的键合层，用于实现芯片22与芯片21的固定连接，其中，介质层211中的金属布线212与介质层221中的金属布线222通过介电层100电连接。
在另一些实施例中，参照图10所示，其中，图10所示的芯片堆叠结构20中，多个堆叠设置的芯片包括芯片21a和芯片21b；芯片21a包括设置于晶片210一侧的介质层211；芯片22b包括设置于晶片210一侧的介质层211；在多个堆叠设置的芯片中，芯片22的晶片220以及芯片21的晶片210设置于芯片21的介质层211与芯片22的介质层221之间；芯片21a的金属线路214的一端与芯片21a的介质层211中的金属布线212电连接，芯片21b的金属线路214的一端与芯片21b的介质层211中的金属布线212电连接,芯片21a的金属线路214的另一端与芯片21b的金属线路214的另一端电连接。
示例性的，图10所示的芯片21a以图5所示的芯片21为例进行说明，当然图10所示的芯片堆叠结构20中的芯片21a也可以是图4或图6或图7所示的芯片21，本申请的实施例对此不做限定。图10所示的芯片21b以图5所示的芯片21为例进行说明，当然图10所示的芯片堆叠结构20中的芯片21b也可以是图4或图6或图7所示的芯片21，本申请的实施例对此不做限定。
示例性的，参照图10所示，按照图10所示的芯片堆叠结构20的摆放位置，其中，芯片21a的介质层211中设置有一个或多个金属布线，图10中仅示出一个金属布线212，芯片21a的介质层211中的金属布线212与芯片21a中的晶片210中设置的电子元器件电连接形成电路结构，那么，在芯片21a的介质层211位于芯片21a的晶片210的下方时，芯片21a的有源面位于芯片21a的介质层211的下面；芯片21b的介质层221中设置有一个或多个金属布线，图10中仅示出一个金属布线212，芯片21b的介质层211中的金属布线与芯片21b的晶片210中设置的电子元器件电连接形成电路结构，那么，在芯片21b的介质层211位于芯片21b的晶片210的上方时，芯片21b的有源面位于芯片21b的介质层211的上方。另外，芯片22的晶片220以及芯片21的晶片210设置于芯片21的介质层211与芯片22的介质层221之间，因此，芯片21b的无源面与芯片21a的无源面键合，该键合方式也被称为back-to-back键合。其中，芯片21a的金属线路214的一端与芯片21a的介质层211中的金属布线212电连接，芯片21b的金属线路214的一端与芯片21b的介质层211中的金属布线212电连接,芯片21a的金属线路214的另一端与芯片21b的金属线路214的另一端电连接，因此芯片21a的有源面接收的信号可以通过芯片21a的金属布线212、芯片21a的过孔213中的金属线路214、芯片21b的过孔213中的金属线路214传输至芯片21b的有源面，进而通过芯片21b的介质层211中的金属布线212传输至芯片21b的晶片210中设置的电子元器件形成的电路结构中，或者，芯片21b的有源面接收的信号可以通过芯片21b的金属布线212、芯片21b的过孔213中的金属线路214、芯片21a的过孔213中的金属线路214传输至芯片21a的有源面，进而通过芯片21a的介质层211中的金属布线212传输至芯片21a的晶片210中设置的电子元器件形成的电路结构中。也就表示，通过芯片21a的过孔213中的金属线路214与芯片21b的过孔213中的金属线路214，可以使得芯片21a与芯片21b之间实现信号互通。
示例性的，参照图10所示，在一些实施例中，为了使得芯片21a与芯片21b之间back-to-back键合，往往还会在芯片21b的无源面与芯片21a的无源面之间设置介电层100，介电层100作为熔融键合(fusion bonding)工艺的键合层，用于实现芯片21b与芯片21a的固定连接。其中，芯片21b的过孔213中的金属线路214贯穿介电层100与芯片21a的过孔213中的金属线路214电连接，和/或，芯片21a的过孔213中的金属线路214贯穿介电层100与芯片21b的过孔213中的金属线路214电连接。
示例性的，在图8至图10任一幅图所示的芯片堆叠结构20中，芯片堆叠结构20可以包括更多个堆叠设置的芯片，其中，更多个堆叠设置的芯片中的相邻两个芯片之间可以是face-to-back键合，也可以是face-to-face键合，还可以是back-to-back键合，本申请的实施例对此不做限定。
示例性的，参照图11所示，本申请的实施例提供了一种芯片的制作方法，包括：
S101、在晶片中形成过孔。
示例性的，参照图12所示，可以先在晶片210的一侧形成介质层211，在介质层211中形成一个或多个金属布线，图12仅示出一个金属布线212，其中，介质层211中的金属布线与芯片21的晶片210中设置的电子元器件电连接形成电路结构。具体的，芯片21的有源面为芯片21的介质层211远离晶片210的一面，芯片21的无源面为芯片21的晶片210远离介质层211的一面。
示例性的，在一些实施例中，可以是以芯片21的有源面为工作面，在芯片21的晶片210中形成过孔；在另一些实施例中，也可以是以芯片21的无源面为工作面，在芯片21的晶片210中形成过孔。其中，在明确芯片21与其他芯片堆叠时，芯片21与和芯片21相邻的芯片之间可以选择的键合方式有face-to-back键合、face-to-face键合或者back-to-back键合，在选定芯片21与和芯片21相邻的芯片之间的键合方式以后，即可确定是以芯片21的有源面为工作面，在芯片21的晶片210中形成过孔，还是以芯片21的无源面为工作面，在芯片21的晶片210中形成过孔。本申请的实施例对此不做限定。
在另一些实施例中，也可以先在芯片21上制作过孔，随后再确定芯片21与和芯片21相邻的芯片之间的键合方式，再进行芯片21与和芯片21相邻的芯片之间的键合步骤。示例性的，参照图12所示，其中，图12所示的是以芯片21的无源面为工作面，在芯片21的晶片210中形成过孔。
示例性的，在形成过孔时，首先需要将芯片21的无源面上暴露的芯片21的晶片210的衬底部分减薄到需求的厚度，便于后续的操作，其次，需要在芯片21的无源面上沉积介质层61，以保护芯片21的无源面上暴露的晶片210的衬底，避免后续沉积金属线路的材料时，将晶片210与金属线路电连接，或者，避免在刻蚀隔离环沟槽或过孔沟槽时，将晶片210中设置的电子元器件刻蚀穿，造成电子元器件失效。
再次，在芯片21的无源面上，制作覆盖芯片21的无源面的光刻胶62，该光刻胶62可以是正性光刻胶或负性光刻胶。具体的，在芯片21的无源面上沉积有介质层61时，就需要制作覆盖芯片21的无源面上的介质层61的光刻胶62。
随后，对光刻胶62进行光刻，形成过孔开窗63，其中，过孔开窗63具体为圆形。
如图13所示，通过图12所示过孔开窗63对芯片21进行刻蚀(etch)，需要刻蚀穿介质层61、芯片21的晶片210以及部分介质层211，形成图13所示的过孔213，其中，过孔213与金属布线212接触。在一些实施例中，形成过孔213时往往会进行两步刻蚀工艺，第一步刻蚀工艺的刻蚀停止层为介质层211，第二步刻蚀工艺的刻蚀停止层为金属布线212，通过两步刻蚀工艺使得刻蚀出的过孔213与金属布线212接触。示例性的，刻蚀通常会采样各向同性的刻时方式，在第二步刻蚀工艺中，尤其要保障小于介质层61的厚度大于金属布线212上方的介质层211的厚度，依次避免刻蚀工艺对晶片210中的电子元器件造成影响。
示例性的，因为过孔开窗为圆形，因此形成的过孔213通常为圆柱形，且该圆柱形的过孔213的直径大于等于1微米。在另一些实施例中，可以将过孔开窗设置为多边形，那么形成的过孔213将可以为棱柱形，本申请的实施例对过孔213的形状不做限定。
S102、在过孔中形成金属线路和第一介质层。
示例性的，在图13所示的过孔213中通过化学气相沉积的方式(chemical vapor deposition，CVD)沉积介质层材料，其中，介质层材料包括二氧化硅、氮化硅等，进而在过孔213的侧壁上形 成介质层215(也就是上述的第一介质层)。
随后，在形成有介质层215的过孔213中沉积金属线路的材料，形成过孔213中的金属线路214，也就是说，介质层215位于金属线路214与晶片210之间。如图14所示，在图14所示的形成有介质层215的过孔213中沉积金属线路的材料形成金属线路214，示例性的，金属线路的材料包括铜、钨等金属材料。在一些实施例中，过孔213中的金属线路214的的底面为圆形。在另一些实施例中，过孔213中的金属线路214的底面为圆环形。本申请的实施例对金属线路214的形状不做限定。
示例性的，在另一些实施例中，在形成金属线路214以后，还会在金属线路214的表面沉积介质层材料，以保护金属线路214表面的金属。后续还有可能再进行金属连接工艺，以使得金属线路214与其他的金属布线可以实现电连接。
S103、形成第一隔离环，其中第一隔离环绕过孔，第一隔离环的介电常数小于第一介质层的材料的介电常数。
示例性的，参照图15所示，以芯片21的无源面为工作面，在芯片21的无源面上再次制作覆盖芯片21的无源面的光刻胶65，该光刻胶65可以是正性光刻胶或负性光刻胶。具体的，在芯片21的无源面上沉积有介质层61时，就需要制作覆盖芯片21的无源面上的介质层61的光刻胶65。
随后，对光刻胶65进行光刻，形成隔离环开窗66，其中，隔离环开窗66具体为圆环形。
如图16所示，通过图15所示隔离环开窗66对芯片21进行刻蚀(etch)，需要刻蚀穿介质层61以及晶片210，形成图16所示的隔离环沟槽67。在刻蚀形成隔离环沟槽67时，刻蚀工艺的刻蚀停止层为介质层211。
在图16所示的隔离环沟槽67中沉积隔离环材料形成隔离环216(也就是上述的第一隔离环)。示例性的，隔离环沟槽的环宽大于等于0.1微米小于等于1微米。
示例性的，在形成图4所示的隔离环216的结构时，可以在图16所示的隔离环沟槽67中沉积以下一种或多种材料制备隔离环216：SiLK、碳掺杂氧化硅、hydrogen silses quioxane(HSQ)、methyl silses quioxane(MSQ)和Nanoglass。在形成图5所示的隔离环216的结构时，可以在图16所示的隔离环沟槽67中沉积二氧化硅或氮化硅制备隔离环216，并且，隔离环沟槽67的环宽为大于等于0.1微米，小于等于1微米，在这样的尺寸大小的隔离环沟槽67中通过化学气相沉积的方式沉积二氧化硅或氮化硅时，会使得沉积的二氧化硅或氮化硅附着于隔离环沟槽67的底部以及侧壁，且在隔离环沟槽67的开口处会先封口，因此形成的隔离环216中会包括空气隙217。
在一些实施例中，还可以再制作一个环绕隔离环216的隔离环218，例如形成如图6所示的芯片21，本申请的实施例对此不做限定。
示例性的，在另一些实施例中，可以通过选择步骤S101至步骤S103，制作出包含过孔的第二芯片，然后将第二芯片与芯片21键合，形成图10所示的芯片堆叠结构20。或者，制作出不包含过孔的第二芯片，然后将第二芯片与芯片21键合，形成图8或图9所示的芯片堆叠结构20。其中，两个芯片键合的具体步骤参照现有的芯片键合技术，例如在两个芯片之间设置介电层作为熔融键合工艺的键合层等，本申请的实施例对此不做限定。
示例性的，在芯片堆叠结构包括更多个堆叠设置的芯片，其中，更多个堆叠设置的芯片中的相邻两个芯片之间可以是face-to-back键合，也可以是face-to-face键合，还可以是back-to-back键合，本申请的实施例对此不做限定。
示例性的，制作过孔的步骤可以在制作芯片21的晶片中设置的电子元器件之前进行，或者，在制作芯片21的晶片中设置的电子元器件时进行，或者，制作完芯片21的晶片中设置的电子元器件之后进行。本申请的实施例对此不做限定。
其中，上述的芯片21的制造方法中，是先制作过孔，再制作隔离环。在另一些实施例中，参照图17至图20所示，芯片21的制造方法中，也可以是同时制作过孔213中的金属线路214与晶片210之间的介质层215以及隔离环216。
示例性的，参照图17所示，可以先在晶片210的一侧形成介质层211，在介质层211中形成一个或多个金属布线，图17仅示出一个金属布线212，其中，介质层211中的金属布线与芯片的晶片中设置的电子元器件电连接形成电路结构。芯片21的有源面为介质层211远离晶片210的一面，芯片21的无源面为晶片210远离介质层211的一面。
其中，图17所示的是以芯片21的无源面为工作面，在芯片21的晶片210中形成过孔。
示例性的，在形成过孔时，首先需要将芯片21的无源面上暴露的芯片21的晶片210的衬底部分减薄到需求的厚度，便于后续的操作，其次，需要在芯片21的无源面上沉积介质层71，以保护芯片21的无源面上暴露的晶片210的衬底，避免后续沉积金属线路的材料时，将晶片210与金属线路电连接，或者，避免在刻蚀隔离环沟槽或过孔沟槽时，将晶片210中设置的电子元器件刻蚀穿，造成电子元器件失效。
再次，在芯片21的无源面上，制作覆盖芯片21的无源面的光刻胶72，该光刻胶72可以是正性光刻胶或负性光刻胶。具体的，在芯片21的无源面上沉积有介质层71时，就需要制作覆盖芯片21的无源面上的介质层71的光刻胶72。
随后，对光刻胶72进行光刻，形成过孔开窗73以及隔离环开窗74，其中，过孔开窗73具体为圆形，隔离环开窗74具体为圆环形，隔离环开窗74环绕过孔开窗73。
如图18所示，通过图17所示过孔开窗73对芯片21进行刻蚀(etch)，需要刻蚀穿介质层71以及芯片21的晶片210，形成图18所示的过孔沟槽75，其中，过孔沟槽75与金属布线212不接触。如图18所示，通过图17所示隔离环开窗74对芯片21进行刻蚀(etch)，需要刻蚀穿介质层71以及芯片21的晶片210，形成图18所示的隔离环沟槽76。示例性的，在刻蚀形成过孔沟槽75以及隔离环沟槽76时，刻蚀工艺的刻蚀停止层为介质层211。
示例性的，参照图19所示，在图18所示的过孔沟槽75以及隔离环沟槽76中通过化学气相沉积的方式沉积二氧化硅或氮化硅等，进而在过孔沟槽75的侧壁上形成介质层215，在隔离环沟槽76中形成隔离环216，其中，隔离环沟槽的环宽大于等于0.1微米小于等于1微米，制作的过孔沟槽的直径大于等于1微米，基于过孔沟槽与隔离环沟槽的尺寸差，同一步化学气相沉积可以使得形成的隔离环216中包括空气隙217。
参照图20所示，在图19所示的侧壁上形成介质层215的过孔沟槽75中进行刻蚀，此次的刻蚀停止层为金属布线212，形成金属线路沟槽77，其中，金属线路沟槽77与金属布线212接触。
在图20所示的金属线路沟槽77中沉积金属线路材料形成金属线路214，即可形成图5所示的芯片21。示例性的，金属线路材料包括铜、钨等金属材料。
示例性的，在另一些实施例中，在形成金属线路214后，还会在金属线路214的表面沉积介质层材料，以保护金属线路214表面的金属。后续还有可能再进行金属连接工艺，以使得金属线路214与其他的金属布线可以实现电连接。
在另一些实施例中，参照图21至图26所示，芯片21的制造方法中，也可以是先制作隔离环，再制作过孔。
示例性的，可以先在晶片210的一侧形成介质层211，在介质层211中形成一个或多个金属布线，图21仅示出一个金属布线212，其中，介质层211中的金属布线与芯片的晶片中设置的电子元器件电连接形成电路结构。芯片21的有源面为介质层211远离晶片210的一面，芯片21的无源面为晶片210远离介质层211的一面。
其中，图21所示的是以芯片21的无源面为工作面，在芯片21的晶片210中形成过孔以及隔离环。
示例性的，在形成过孔以及隔离环时，首先需要将芯片21的无源面上暴露的芯片21的晶片210的衬底部分减薄到需求的厚度，便于后续的操作，其次，需要在芯片21的无源面上沉积介质层81，以保护芯片21的无源面上暴露的晶片210的衬底，避免后续沉积金属线路的材料时，将晶片210与金属线路电连接，或者，避免在刻蚀隔离环沟槽或过孔沟槽时，将晶片210中设置的电子元器件刻蚀穿，造成电子元器件失效。示例性的，在上述步骤中，介质层61、介质层71以及介质层81为不同的制作步骤下形成的相同的材料层。
再次，在芯片21的无源面上，制作覆盖芯片21的无源面的光刻胶82，该光刻胶82可以是正性光刻胶或负性光刻胶。具体的，在芯片21的无源面上沉积有介质层81时，就需要制作覆盖芯片21的无源面上的介质层81的光刻胶82。
随后，对光刻胶82进行光刻，形成隔离环开窗83，其中，隔离环开窗83具体为圆环形。
如图22所示，通过图21所示的隔离环开窗83对芯片21进行刻蚀(etch)，需要刻蚀穿介质层81以及晶片210，形成图22所示的隔离环沟槽84。示例性的，在刻蚀形成隔离环沟槽84时，刻蚀工 艺的刻蚀停止层为介质层211。
示例性的，参照图23所示，在图22所示的隔离环沟槽84中通过化学气相沉积的方式沉积隔离环材料，形成隔离环216。
示例性的，在形成图4所示的隔离环216的结构时，可以在图22所示的隔离环沟槽84中沉积以下一种或多种材料制备隔离环216：SiLK、碳掺杂氧化硅、hydrogen silses quioxane(HSQ)、methyl silses quioxane(MSQ)和Nanoglass。在形成图5所示的隔离环216的结构时，可以在图22所示的隔离环沟槽84中沉积二氧化硅或氮化硅，并且，隔离环沟槽84的环宽为大于等于0.1微米，小于等于1微米，在这样的尺寸大小的隔离环沟槽84中通过化学气相沉积的方式沉积二氧化硅或氮化硅时，会使得沉积的二氧化硅或氮化硅附着于隔离环沟槽84的底部以及侧壁，且在隔离环沟槽的开口处会先封口，因此形成的隔离环216中会包括空气隙217。其中，图23所示的隔离环216中包括空气隙217。
示例性的，参照图24所示，在芯片21的无源面上，制作覆盖芯片21的无源面的光刻胶85，该光刻胶85可以是正性光刻胶或负性光刻胶。具体的，在芯片21的无源面上沉积有介质层81时，就需要制作覆盖芯片21的无源面上的介质层81的光刻胶85。
随后，对光刻胶85进行光刻，形成过孔开窗86，其中，过孔开窗86具体为圆形。
如图25所示，通过图24所示过孔开窗86对芯片21进行刻蚀(etch)，需要刻蚀穿介质层81以及晶片210，形成图25所示的过孔沟槽87，其中，过孔沟槽87与金属布线212不接触。
示例性的，参照图26所示，在图25所示的过孔沟槽87中通过化学气相沉积的方式沉积介质层材料，其中，介质层材料包括二氧化硅、氮化硅等，进而在过孔沟槽87的侧壁上形成介质层215(也就是上述的第一介质层)。
参照图26所示，侧壁上形成介质层215的过孔沟槽87中进行刻蚀，此次的刻蚀停止层为金属布线212，形成金属线路沟槽88，其中，金属线路沟槽88与金属布线212接触。
在图26所示的金属线路沟槽88中沉积金属线路的材料形成金属线路214，即可形成图5所示的芯片21。示例性的，金属线路材料包括铜、钨等金属材料。
示例性的，在另一些实施例中，在形成金属线路214以后，还会在金属线路214的表面沉积介质层材料，以保护金属线路214表面的金属。后续还有可能再进行金属连接工艺，以使得金属线路214与其他的金属布线可以实现电连接。
尽管结合具体特征及其实施例对本申请进行了描述，显而易见的，在不脱离本申请的精神和范围的情况下，可对其进行各种修改和组合。相应地，本说明书和附图仅仅是所附权利要求所界定的本申请的示例性说明，且视为已覆盖本申请范围内的任意和所有修改、变化、组合或等同物。显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (16)

  1. 一种芯片，其特征在于，包括：
    晶片；
    所述晶片中设置有过孔，所述过孔中设置有金属线路，在所述金属线路和所述晶片之间设置有第一介质层；
    所述晶片中还包括环绕所述过孔的第一隔离环，所述第一隔离环的介电常数小于所述第一介质层的材料的介电常数。
  2. 根据权利要求1所述的芯片，其特征在于，
    所述第一隔离环中包括空气隙。
  3. 根据权利要求1或2所述的芯片，其特征在于，
    所述晶片中还包括环绕所述第一隔离环的第二隔离环，所述第二隔离环的介电常数小于所述第一介质层的材料的介电常数。
  4. 根据权利要求3所述的芯片，其特征在于，
    所述第二隔离环中包括空气隙。
  5. 根据权利要求1-4任一项所述的芯片，其特征在于，
    所述第一隔离环与所述过孔之间的距离大于等于0.5微米。
  6. 根据权利要求1-5任一项所述的芯片，其特征在于，
    所述第一隔离环的环宽大于等于0.1微米，小于等于1微米。
  7. 根据权利要求1-6任一项所述的芯片，其特征在于，所述过孔的直径大于等于1微米。
  8. 根据权利要求1-7任一项所述的芯片，其特征在于，所述金属线路的材料包括铜、钨。
  9. 根据权利要求1-8任一项所述的芯片，其特征在于，所述芯片还包括第二介质层，所述第二介质层设置于所述晶片的一侧，所述金属线路与所述第二介质层中的金属布线电连接。
  10. 一种芯片堆叠结构，其特征在于，所述芯片堆叠结构中包括多个堆叠设置的芯片，所述多个堆叠设置的芯片中包括如权利要求1-9任一项所述的芯片。
  11. 根据权利要求10所述的芯片堆叠结构，其特征在于，
    所述多个堆叠设置的芯片包括第一芯片和第二芯片；
    所述第一芯片和所述第二芯片均包括设置于晶片一侧的第二介质层；
    在所述多个堆叠设置的芯片中，所述第一芯片的晶片设置于所述第一芯片的第二介质层与所述第二芯片的第二介质层之间，且，所述第一芯片的第二介质层设置于所述第一芯片的晶片与所述第二芯片的晶片之间；
    所述第一芯片的金属线路的一端与所述第一芯片的第二介质层中的金属布线电连接，所述第一芯片的金属线路的另一端与所述第二芯片的第二介质层中的金属布线电连接。
  12. 根据权利要求10所述的芯片堆叠结构，其特征在于，
    所述多个堆叠设置的芯片包括第一芯片和第二芯片；
    所述第一芯片和所述第二芯片均包括设置于晶片一侧的第二介质层；
    在所述多个堆叠设置的芯片中，所述第二芯片的第二介质层以及所述第一芯片的第二介质层设置于所述第一芯片的晶片与所述第二芯片的晶片之间；
    所述第一芯片的金属线路的一端与所述第一芯片的第二介质层中的金属布线电连接，所述第一芯片的第二介质层中的金属布线与所述第二芯片的第二介质层中的金属布线电连接。
  13. 根据权利要求10所述的芯片堆叠结构，其特征在于，
    所述多个堆叠设置的芯片包括第一芯片和第二芯片；
    所述第一芯片和所述第二芯片均包括设置于晶片一侧的第二介质层；
    在所述多个堆叠设置的芯片中，所述第二芯片的晶片以及所述第一芯片的晶片设置于所述第一芯片的第二介质层与所述第二芯片的第二介质层之间；
    所述第一芯片的金属线路的一端与所述第一芯片的第二介质层中的金属布线电连接，所述第二芯片的金属线路的一端与所述第二芯片的第二介质层中的金属布线电连接，所述第一芯片的金属线路的另一端与所述第二芯片的金属线路的另一端电连接。
  14. 一种芯片封装结构，其特征在于，包括封装基板以及如权利要求10-13任一项所述的芯片堆叠结构；所述芯片堆叠结构与所述封装基板电连接。
  15. 一种电子设备，其特征在于，包括印刷电路板以及如权利要求14所述的芯片封装结构；所述芯片封装结构中的封装基板与所述印刷电路板电连接。
  16. 一种芯片的制作方法，其特征在于，包括：
    在晶片中形成过孔；
    在所述过孔中形成金属线路和第一介质层，其中，所述第一介质层位于所述金属线路与所述晶片之间；
    形成第一隔离环，其中所述第一隔离环绕所述过孔，所述第一隔离环的介电常数小于所述第一介质层的材料的介电常数。
PCT/CN2023/103154 2022-10-31 2023-06-28 芯片、芯片堆叠结构、芯片封装结构以及电子设备 WO2024093288A1 (zh)

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