WO2024092903A1 - 半导体结构及制备方法 - Google Patents

半导体结构及制备方法 Download PDF

Info

Publication number
WO2024092903A1
WO2024092903A1 PCT/CN2022/134056 CN2022134056W WO2024092903A1 WO 2024092903 A1 WO2024092903 A1 WO 2024092903A1 CN 2022134056 W CN2022134056 W CN 2022134056W WO 2024092903 A1 WO2024092903 A1 WO 2024092903A1
Authority
WO
WIPO (PCT)
Prior art keywords
insulating layer
region
groove
sub
layer
Prior art date
Application number
PCT/CN2022/134056
Other languages
English (en)
French (fr)
Inventor
唐衍哲
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Publication of WO2024092903A1 publication Critical patent/WO2024092903A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
    • H10B51/40—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the peripheral circuit region

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a preparation method thereof.
  • connection plugs of the semiconductor structure such as the plugs connecting the source, drain and gate structures
  • the connection plugs of the semiconductor structure are generally formed synchronously at different positions.
  • the connection plugs due to the different formation positions of the connection plugs and the different sizes of the spaces for forming the connection plugs, the formed connection plugs are prone to the risk of misalignment or breakage.
  • the spacing between the gate structures in the core area is smaller than the spacing between the gate structures in the peripheral area.
  • the source and drain plugs are subsequently formed, it is easy to cause the source and drain plugs in the core area to be difficult to align.
  • the source and drain plugs formed are prone to breakage and short circuit.
  • the purpose of the present disclosure is to provide a semiconductor structure and a method for manufacturing the same, which can improve the alignment effect of the connection plug and reduce the risk of breakage and short circuit.
  • a method for preparing a semiconductor structure includes: providing a substrate, the substrate having a first region and a second region; forming a gate structure on the substrate, wherein a spacing between adjacent gate structures located in the first region is smaller than a spacing between adjacent gate structures located in the second region; forming a first insulating layer on the surface of the gate structure, wherein a first groove is formed between the first insulating layers on the side walls of the gate structure in the first region, and the first groove corresponds to a source and drain region in the first region; forming a second insulating layer, wherein the second insulating layer is located on the surface of the first insulating layer on the side walls of the gate structure in the second region, and wherein a second groove is formed between the second insulating layers in the second region, and the second groove corresponds to a source and drain region in the second region; forming a first connecting plug connected to the source and drain region of the first region in the first groove; and forming a second connecting plug
  • the step of forming a first insulating layer on the surface of the gate structure includes: forming a first sub-insulating layer on the surface of the gate structure, a first sub-groove exposing the substrate is formed between the first sub-insulating layers on the side walls of the gate structure; performing a first ion implantation into the substrate along the first sub-groove to form a first doped region in the substrate; forming a second sub-insulating layer on the surface of the first sub-insulating layer, the first sub-insulating layer and the second sub-insulating layer together form the first insulating layer, and the first groove is formed between the second sub-insulating layers in the first region.
  • a third sub-insulating layer is formed on the side wall of the second sub-insulating layer located in the second region, a third sub-groove is formed between the third sub-insulating layers, and the second insulating layer includes the third sub-insulating layer; a second ion implantation is performed on the substrate along the first groove and the third sub-groove to form a source and drain region in the first region and a source and drain region in the second region.
  • the step of forming the second insulating layer further includes forming a fourth sub-insulating layer at least on a surface of the third sub-insulating layer, and the fourth sub-insulating layer and the third sub-insulating layer together form the second insulating layer.
  • the step before forming the fourth sub-insulating layer, the step also includes: forming a first sacrificial layer in the first groove; in the step of forming the fourth sub-insulating layer on the surface of the third sub-insulating layer, the fourth sub-insulating layer is formed on the first insulating layer, the substrate, the first sacrificial layer and the surface of the third sub-insulating layer.
  • the first sacrificial layer is formed by atomic layer deposition.
  • the steps of forming the first connecting plug and the second connecting plug include: forming a second sacrificial layer on the surface of the fourth sub-insulating layer, removing the first sacrificial layer and at least part of the second sacrificial layer to expose the first groove and the second groove, and exposing the source and drain region; forming the first connecting plug in the first groove, and forming the second connecting plug in the second groove.
  • the step of removing the first sacrificial layer and at least part of the second sacrificial layer includes: forming a first mask layer on the surface of the fourth sub-insulating layer and the second sacrificial layer; forming a photoresist layer on the first mask layer, the photoresist layer having photolithography through holes corresponding to the first groove and the second groove; etching the first mask layer along the photolithography through holes, and etching the first sacrificial layer and the second sacrificial layer downward to expose the first groove and the second groove, and expose the source and drain regions; removing the photoresist layer.
  • the steps of forming the first connecting plug in the first groove and forming the second connecting plug in the second groove include: forming an initial connection layer on the surface of the first mask layer, in the first groove and in the second groove; removing part of the initial connection layer located on the surface of the first mask layer, retaining part of the initial connection layer located in the first groove to form the first connecting plug, and retaining part of the initial connection layer located in the second groove to form the second connecting plug.
  • the method for preparing the semiconductor structure further includes: forming a third connecting plug, wherein the third connecting plug is connected to the gate structure.
  • the step of forming the third connecting plug includes: forming a second mask layer on the surfaces of the first insulating layer, the second insulating layer, the first connecting plug and the second connecting plug; patterning the second mask layer to form a through hole, wherein the through hole corresponds to a portion of the gate structure; etching the first insulating layer and the second insulating layer located on the surface of the gate structure along the etched through hole to expose the gate structure; removing the second mask layer to expose the first connecting plug and the second connecting plug; and forming a third connecting plug in the etched through hole.
  • the first insulating layer includes at least one of an oxide layer and the nitride layer.
  • the present disclosure also provides a semiconductor structure.
  • the semiconductor according to the embodiment of the present disclosure includes: a substrate having a first region and a second region, and a gate structure is disposed on the substrate; a spacing between adjacent gate structures located in the first region is smaller than a spacing between adjacent gate structures located in the second region;
  • a first insulating layer is located on the surface of the gate structure, a first groove is formed between the first insulating layers on the sidewalls of the gate structure in the first region, and the first groove corresponds to the source and drain region of the first region;
  • a second insulating layer is formed on the sidewalls of the first insulating layer in the second region, a second groove is formed between the second insulating layers on the sidewalls of the gate structure in the second region, and the second groove corresponds to the source and drain region of the second region;
  • first connecting plug is located in the first groove and connected to the source and drain regions of the first region; and a second connecting plug, the second connecting plug is located in the second groove and connected to the source and drain regions of the second region.
  • the first insulating layer is at least partially located on the source and drain regions of the first region, and the second insulating layer is at least partially located on the source and drain regions of the second region.
  • the semiconductor structure further includes a third connecting plug connected to the gate structure.
  • the first region can be the core region and the induction amplification region
  • the second region can be the peripheral region
  • the spacing between the gate structures in the first region is smaller than the spacing between the gate structures in the second region
  • the sidewalls of the gate structures in the first region are provided with a first insulating layer
  • the sidewalls of the gate structures in the second region are provided with a first insulating layer and a second insulating layer.
  • the number of insulating layers between the gate structures in the first region and the gate structures in the second region are different.
  • the space occupied by the insulating layers can be reduced to increase the space for the first connecting plugs between the gate structures in the first region, which is beneficial to the formation of the first connecting plugs and the self-alignment with the source and drain regions of the first region, and can also prevent the first connecting plugs from being too thin and broken.
  • the number of insulating layers between the gate structures in the second region is relatively large, which can prevent the insulating layers between the gate structures in the second region from being over-etched and causing short circuits.
  • FIG1 is a schematic diagram of a process for preparing a semiconductor structure according to an embodiment of the present disclosure
  • FIGS. 2 to 22 are cross-sectional views corresponding to the steps of the method for preparing a semiconductor structure according to an embodiment of the present disclosure
  • A1 first region
  • A2 second region
  • S1 spacing between adjacent gate structures in the first region
  • S2 spacing S2 between adjacent gate structures in the second region
  • first insulating layer 21: first sub-insulating layer, 211: first initial sub-insulating layer, 22: first oxide layer, 23: first nitride layer, 24: second sub-insulating layer, 241: second initial sub-insulating layer, 25: second oxide layer, 26: second nitride layer;
  • 3 second insulating layer, 31: third sub-insulating layer, 311: third initial sub-insulating layer, 32: fourth sub-insulating layer, 33: first groove, 34: second groove, 35: third sub-groove, 36: first sub-groove
  • 51 first mask layer
  • 52 photoresist layer
  • 53 photolithography through hole
  • 61 second mask layer
  • 62 photoresist pattern
  • 63 etching through hole
  • a semiconductor structure 100 and a method for manufacturing the same proposed in the present disclosure are further described in detail below in conjunction with the accompanying drawings and specific embodiments.
  • the connecting plug is mostly formed by lithography-etching-lithography-etching (Lithography-Etch-Lithography-Etch, LELE), which is also prone to short circuit when it cannot be aligned.
  • the discloser has discovered through research that, in the semiconductor structure of the related technology, when forming connecting plugs, the connecting plugs in different areas are all formed synchronously, and the spacing between the gate structures in different areas is different.
  • the spacing between the gate structures in the core area is smaller than the spacing between the gate structures in the peripheral area.
  • the insulating layers on the gate structures in different areas are formed synchronously, resulting in a smaller space for forming connecting plugs between the gate structures in the core area, and smaller than the space for forming connecting plugs between the gate structures in the peripheral area.
  • the space for forming the connecting plugs in the core area is too small, which makes etching difficult, which easily leads to the formed connecting plugs being difficult to align.
  • the space for forming the connecting plugs is reduced, which also leads to the risk of the formed connecting plugs being easily broken and short-circuited.
  • a self-alignment process is used to form a connecting plug, thereby avoiding problems such as misalignment of the connecting plug and the occurrence of breakage and short circuit.
  • a method for preparing a semiconductor structure 100 may include: S1: providing a substrate 1, wherein the substrate 1 has a first region A1 and a second region A2; S2: forming a gate structure 11 on the substrate 1, wherein a distance between adjacent gate structures 11 located in the first region A1 is smaller than a distance between adjacent gate structures 11 located in the second region A2; S3: forming a first insulating layer 2 on a surface of the gate structure 11, wherein a first groove 33 is formed between the first insulating layer 2 on a side wall of the gate structure 11 in the first region A1, and the first groove 33 is adjacent to the first insulating layer 2 on a side wall of the gate structure 11; Corresponding to the source and drain regions 18 of the first area A1; S4: forming a second insulating layer 3, the second insulating layer 3 is located on the surface of the first insulating layer 2 on the side wall of the gate structure 11 of the second area A2, and
  • FIGS. 2 to 22 are cross-sectional views of the semiconductor structure 100 corresponding to each step of the method for preparing the semiconductor structure 100 according to the embodiment of the present disclosure.
  • the method for preparing the semiconductor structure 100 according to the embodiment of the present disclosure is described below in conjunction with FIGS. 2 to 21 .
  • step S1 providing a substrate 1, wherein the substrate 1 has a first area A1 and a second area A2, wherein the first area A1 may be a core area, and the second area A2 may be a peripheral area.
  • the substrate 1 may include a substrate, wherein the substrate has an active area, and the substrate 1 also includes an isolation area formed between the active areas.
  • the substrate may be, but is not limited to, a silicon substrate. This specific embodiment is described by taking the substrate as a silicon substrate as an example. In other embodiments, the substrate may also be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide or SOI, and the substrate is used to support the device structure thereon.
  • step S2 forming gate structures 11 on the substrate 1 , wherein the spacing between adjacent gate structures 11 in the first area A1 is smaller than the spacing between adjacent gate structures 11 in the second area A2 .
  • the step of forming the gate structure 11 may include: forming a stacked structure on the surface of the substrate 1, etching the stacked structure to form a plurality of gate structures 11, wherein the surfaces of the first region A1 and the second region A2 are both formed with gate structures 11, and the spacing S1 between adjacent gate structures 11 in the first region A1 is smaller than the spacing S2 between adjacent gate structures 11 in the second region A2.
  • the substrate 1 may also include an oxide layer 15 formed on the surface of the substrate and the isolation region, and in the step of forming the gate structure 11, the stacked structure may be etched to the surface of the oxide layer 15 to form the gate structure 11.
  • the gate structure 11 may include a first gate layer 12, a second gate layer 13, and a third gate layer 14, and a silicon nitride capping layer 16 located on the third gate layer 14, wherein the first gate layer 12 may be a polysilicon layer, the second gate layer 13 may be a metal layer, and the third gate layer 14 may be a metal silicide layer.
  • step S3 forming a first insulating layer 2 on the surface of the gate structure 11, a first groove 33 is formed between the first insulating layer 2 on the side wall of the gate structure 11 in the first region A1, and the first groove 33 corresponds to the source and drain region 18 in the first region A1.
  • the first insulating layer 2 is formed on the surface of the gate structure 11 in the first region A1 and the second region A2, and the first insulating layer 2 may include a stacked structure of alternately stacked nitride layers and oxide layers, and the source and drain region 18 is formed in the substrate 1 and corresponds to the position of the first groove 33.
  • the step of forming the first insulating layer 2 on the surface of the gate structure 11 may include:
  • a first sub-insulating layer 21 is formed on the surface of the gate structure 11 , and a first sub-groove 36 exposing the substrate 1 is formed between the first sub-insulating layer 21 on the sidewall of the gate structure 11 ;
  • a second sub-insulating layer 24 is formed on the surface of the first sub-insulating layer 21 .
  • the first sub-insulating layer 21 and the second sub-insulating layer 24 together form the first insulating layer 2 .
  • the first groove 33 is formed between the second sub-insulating layers 24 in the first area A1 .
  • a first initial sub-insulating layer 211 can be formed on the surface of the substrate 1 and the surface of the gate structure 11. As shown in Figure 4, the first initial sub-insulating layer 211 is etched to retain a portion of the first initial sub-insulating layer 211 located on the surface of the gate structure 11 to form a first sub-insulating layer 21.
  • the first sub-insulating layer 21 may include a first oxide layer 22 and a first nitride layer 23.
  • the first oxide layer 22 may be formed on the side walls of the first gate layer 12, and the first nitride layer 23 is formed on the side walls and the upper surface of the gate structure 11 and covers the first oxide layer 22.
  • the thickness of the first oxide layer 22 may be 0-2nm, and the thickness of the first nitride layer 23 may be 0-5nm.
  • a first sub-recess 36 may be formed between the first sub-insulating layer 21 on the side wall of the gate structure 11, and the first sub-recess 36 exposes the substrate 1.
  • the first sub-recess 36 exposes a portion of the active area surface of the substrate 1, and then ions may be implanted into the substrate 1 along the first sub-recess 36 to form a doped region 17 in the substrate 1.
  • the substrate 1 may be lightly doped along the first sub-recess 36 to form a lightly doped source and drain (LDD) structure.
  • LDD lightly doped source and drain
  • At least one of chemical vapor deposition, physical vapor deposition, etc. can be used to form a second initial sub-insulating layer 241 on the surface of the substrate 1 and the first sub-insulating layer 21.
  • the second initial sub-insulating layer 241 can be etched to retain a portion of the second initial sub-insulating layer located on the surface of the first sub-insulating layer 21 to form a second sub-insulating layer 24.
  • the second sub-insulating layer 24 and the first sub-insulating layer 21 are formed on the surface of the gate structure 11 in the first area A1 and the second area A2, and the first sub-insulating layer 21 and the second sub-insulating layer 24 together constitute the first insulating layer 2, that is, the side walls of the gate structure 11 in the first area A1 and the second area A2 are formed with the first insulating layer 2, wherein a first groove 33 can be formed between the second sub-insulating layers 24 located in the first area A1, and the first groove 33 is correspondingly located on the first doping area 17.
  • the second sub-insulating layer 24 may include a second oxide layer 25 and a second nitride layer 26, the second oxide layer 25 is formed on the surface of the first sub-insulating layer 21 and the substrate 1, and the second nitride layer 26 is formed on the surface of the second oxide layer 25, wherein the thickness of the second oxide layer 25 can be 0-2nm, and the thickness of the second nitride layer 26 can be 0-15nm.
  • step S4 forming a second insulating layer 3, the second insulating layer 3 is located on the surface of the first insulating layer 2 on the side wall of the gate structure 11 in the second area A2, and a second groove 34 is formed between the second insulating layers 3 in the second area A2, and the second groove 34 corresponds to the source and drain region 18 of the second area A2.
  • a first insulating layer 2 is formed on the side wall of the gate structure 11 in the first area A1, and a first insulating layer 2 and a second insulating layer 3 are formed on the side wall of the gate structure 11 in the second area A2, so that the number of insulating layers formed on the side walls of the gate structures 11 in the first area A1 and the second area A2 are different, the number of insulating layers on the side walls of the gate structure 11 in the first area A1 is smaller than the number of insulating layers on the side walls of the gate structure 11 in the second area A2, and the thickness of the insulating layer on the side walls of the gate structure 11 in the second area A2 is greater than the thickness of the insulating layer on the side walls of the gate structure 11 in the first area A1, thereby reducing the space occupied by the insulating layer on the side walls of the gate structure 11 in the first area A1, which is beneficial to the subsequent formation of connecting plugs between the gate structures 11.
  • the second insulating layer 3 may include a third sub-insulating layer 31, and the step of forming the second insulating layer 3 may include:
  • a third sub-insulating layer 31 is formed on the sidewall of the second sub-insulating layer 24 located in the second area A2, a third sub-groove 35 is formed between the third sub-insulating layers 31, and the second insulating layer 3 includes the third sub-insulating layer 31;
  • Ions are implanted into the doping region 17 and the substrate 1 along the first groove 33 and the third sub-groove 35 to form source and drain regions 18 in the first area A1 and source and drain regions 18 in the second area A2 .
  • a third initial sub-insulating layer 311 may be formed on the surface of the second initial sub-insulating layer 241 .
  • the third initial sub-insulating layer 311 may be an oxide layer, and the thickness of the third sub-insulating layer 311 may be 0-10 nm.
  • the third initial sub-insulating layer 311 can be etched at the same time. Specifically, the third initial sub-insulating layer 311 located on the upper surface of the second initial sub-insulating layer 241 can be removed, and a portion of the third initial sub-insulating layer 311 located on the side wall of the second sub-insulating layer 24 is retained to form a third sub-insulating layer 31, and the second initial sub-insulating layer is etched along the side wall of the third sub-insulating layer 31 to form the second sub-insulating layer 24.
  • a third sub-recess 35 can be formed between the third sub-insulating layers 31, and the third sub-recess 35 corresponds to being located on the doping region 17 of the second area A2.
  • the spacing between the second sub-insulating layers 24 is small, for example, the spacing between the side walls of the second initial sub-insulating layer 241 is generally less than 67nm
  • the third initial sub-insulating layer 311 is deposited, an air gap can be formed between the side walls of the second initial sub-insulating layer 241 in the first area A1, and the third initial sub-insulating layer 311 is formed on the upper surface of the second initial sub-insulating layer 241.
  • the third initial sub-insulating layer 311 will not be formed on the side walls of the second initial sub-insulating layer 241 in the first area A1, that is, the third initial sub-insulating layer 311 will not be formed between the gate structures 11 in the first area A1.
  • a first insulating layer 2 is formed between the gate structures 11 in the first area A1, and a first insulating layer 2 and a third sub-insulating layer 31 are formed between the gate structures 11 in the second area A2, wherein a first groove 33 is formed between the first insulating layer 2 in the first area A1, and a third sub-groove 35 is formed between the third sub-insulating layer 31 in the second area A2.
  • the second ion implantation can be performed on the substrate 1 along the first groove 33 and the third sub-groove 35 to form the source and drain regions 18 of the first area A1 and the source and drain regions 18 of the second area A2, so that the source and drain regions 18 between the gate structures 11 of the first area A1 correspond to the first groove 33, and the source and drain regions 18 between the gate structures 11 of the second area A2 correspond to the third sub-groove 35, wherein the first ion implantation and the second ion implantation can implant the same type of ions, for example, the first ion implantation and the second ion implantation can both be N-type ion implantations, and the concentration and depth of the second ion implantation are greater than the first ion implantation.
  • the second insulating layer 3 may further include a fourth sub-insulating layer 32, and the step of forming the second insulating layer 3 may further include forming the fourth sub-insulating layer 32 at least on the surface of the third sub-insulating layer 31, wherein the fourth sub-insulating layer 32 and the third sub-insulating layer 31 together form the second insulating layer 3, and the fourth sub-insulating layer 32 is formed on the surface of the third sub-insulating layer 31.
  • the second groove 34 is formed between the fourth sub-insulating layer 32, so that the sidewall of the gate structure 11 of the first region A1 has the first insulating layer 2, and the sidewall of the gate structure 11 of the second region A2 has the first insulating layer 2 and the second insulating layer 3.
  • the insulating layer of the sidewall of the gate structure 11 of the first region A1 is less than the number of insulating layers between the gate structures 11 of the second region A2.
  • the number of insulating layers and the occupied space between the gate structures 11 of the first region A1 are reduced, and the space for forming the first connecting plug 71 between the gate structures 11 of the first region A1 can be increased, and the connecting plug formed between the gate structures 11 with reduced spacing is prevented from being difficult to align or easily broken, and the over-etching between the gate structures 11 of the first region A1 can be avoided to cause a short circuit.
  • it can also prevent the insulating layer of the sidewall of the gate structure 11 with a large spacing from being etched through and causing a short circuit.
  • step S5 forming a first connection plug 71 in the first groove 33 connected to the source/drain region 18 of the first region A1 ;
  • step S6 forming a second connection plug 72 in the second groove 34 connected to the source/drain region 18 of the second region A2 .
  • the method of forming the first connecting plug 71 and the second connecting plug 72 may include the following steps:
  • a first sacrificial layer 41 is formed in the first groove 33; in the step of forming the fourth sub-insulating layer 32 on the surface of the third sub-insulating layer 31, the fourth sub-insulating layer 32 is formed on the first insulating layer 2, the substrate 1, the first sacrificial layer 41 and the surface of the third sub-insulating layer 31.
  • a first sacrificial layer 41 may be formed in the first groove 33.
  • the source and drain regions 18 of the first region A1 are formed by performing the second ion implantation along the first groove 33.
  • the first sacrificial layer 41 fills the first groove 33 to align with the source and drain regions 18 of the first region A1.
  • the first connecting plug 71 can be self-aligned with the source and drain regions 18 of the first region A1.
  • the first sacrificial layer 41 may be formed by atomic layer deposition. Since the space of the first groove 33 is small, the atomic layer deposition method may be used to improve the deposition effect, so that the first sacrificial layer 41 can fill the first groove 33.
  • a fourth sub-insulating layer 32 is deposited on the surface of the substrate 1, the surface of the first insulating layer 2, the surface of the first sacrificial layer 41, and the surface of the third sub-insulating layer 31, wherein the fourth sub-insulating layer 32 is formed on the upper surface of the gate structure 11 in the first area A1, but not on the side wall of the gate structure 11, the fourth sub-insulating layer 32 is formed on the side wall of the gate structure 11 in the second area A2, the fourth sub-insulating layer 32 and the third sub-insulating layer 31 together constitute the second insulating layer 3, and the second groove 34 is formed between the fourth sub-insulating layer 32 on the side wall of the gate structure 11.
  • the method for preparing the semiconductor structure 100 further includes:
  • a second sacrificial layer 42 is formed on the surface of the fourth sub-insulating layer 32.
  • the first sacrificial layer 41 and the second sacrificial layer 42 are etched to expose the first groove 33 and the second groove 34 , and to expose the source and drain region 18 ;
  • the first connecting plug 71 is formed in the first groove 33
  • the second connecting plug 72 is formed in the second groove 34 .
  • At least one of chemical vapor deposition, physical vapor deposition or atomic layer deposition can be used to form a second sacrificial layer 42 on the surface of the fourth sub-insulating layer 32.
  • the second sacrificial layer 42 can be flush with the second insulating layer 3 on the upper surface of the gate structure 11.
  • the second sacrificial layer 42 fills the second groove 34 and a portion thereof corresponds to being located above the source and drain regions 18 of the second area A2.
  • the deposition thickness of the second sacrificial layer 42 can be 0-200nm.
  • the step of etching the first sacrificial layer 41 and the second sacrificial layer 42 to expose the first groove 33 and the second groove 34 may include: as shown in Figure 12, forming a first mask layer 51 on the surface of the fourth sub-insulating layer 32 and the second sacrificial layer 42, the first mask layer 51 covering the upper surface of the fourth sub-insulating layer 32 and the second sacrificial layer 42; as shown in Figure 13, forming a photoresist layer 52 on the first mask layer 51, the photoresist layer 52 having a photolithography through hole 53 corresponding to the first groove 33 and the second groove 34; as shown in Figure 14, etching the first mask layer 51 along the photolithography through hole 53 to expose the first sacrificial layer 41 and the second sacrificial layer 42, and continuing to etch the first sacrificial layer 41 and the second sacrificial layer 42 downward to expose the first groove 33 and the second groove 34; thereby exposing the source and drain regions 18 of the
  • the first mask layer 51 and the fourth sub-insulating layer 32 can be etched through along the photolithography through hole 53 to expose the first sacrificial layer 41, and in the second area A2, the fourth sub-insulating layer 32 can be etched through along the photolithography through hole 53 to expose the second sacrificial layer 42, and then the first sacrificial layer 41 and the second sacrificial layer 42 are removed, wherein in the step of removing the first sacrificial layer 41 and the second sacrificial layer 42, the first insulating layer 2 can form a stop layer for etching the first sacrificial layer 41, and the second insulating layer 3 can form a stop layer for etching the second sacrificial layer 42.
  • an anisotropic etching process can be used for etching in this step, wherein the first sacrificial layer 41 and the second sacrificial layer 42 can be the same material, and are different from the materials of the fourth sub-insulating layer 32 and the second sub-insulating layer 24.
  • the first sacrificial layer 41 and the second sacrificial layer 42 can be silicon oxide layers
  • the fourth sub-insulating layer 32 and the second sub-insulating layer 24 can be silicon nitride layers.
  • an etchant with a low etching rate for the silicon oxide layer and a high etching rate for the silicon nitride layer can be selected for anisotropic etching.
  • a first connection plug 71 is formed in the first groove 33
  • a second connection plug 72 is formed in the second groove 34 .
  • the first connection plug 71 is connected to the source/drain region 18 of the first area A1
  • the second connection plug 72 is connected to the source/drain region 18 of the second area A2 .
  • the steps of forming the first connection plug 71 and the second connection plug 72 may include: as shown in FIG15, forming an initial connection layer 73 on the surface of the first mask layer 51 and in the first groove 33 and the second groove 34; as shown in FIG16, removing part of the initial connection layer 73 located on the surface of the first mask layer 51, retaining part of the initial connection layer 73 located in the first groove 33 to form the first connection plug 71, and retaining part of the initial connection layer 73 located in the second groove 34 to form the second connection plug 72.
  • a chemical mechanical polishing process may be used to remove part of the initial connection layer 73 located on the surface of the first mask layer 51.
  • the materials of the first connection plug 71 and the second connection plug 72 may be metal materials or metal silicide materials.
  • the method for preparing the semiconductor structure 100 further includes: forming a third connecting plug 74 , wherein the third connecting plug 74 is connected to the gate structure 11 and can be used to lead out the gate structure 11 so as to apply voltage to the gate structure 11 .
  • the method for forming the third connecting plug 74 may include the following steps:
  • a second mask layer 61 is formed on the surface of the first insulating layer 2, the second insulating layer 3, the first connecting plug 71 and the second connecting plug 72, and the second mask layer 61 covers the first connecting plug 71 and the second connecting plug 72.
  • the second mask layer 61 can cover the surface of the first connecting plug 71, the second connecting plug 72 and the first mask layer 51.
  • the second mask layer 61 can be a silicon oxide layer, and the thickness of the second mask layer 61 can be 0-20nm.
  • the second mask layer 61 is patterned to form an etched through hole 63, and the etched through hole 63 corresponds to the portion of the gate structure 11 located outside the second area A2.
  • a photoresist pattern 62 can be formed on the surface of the second mask layer 61, and the photoresist pattern 62 has a photolithography hole corresponding to the gate structure 11 outside the second area A2.
  • the gate structure 11 outside the second area A2 may refer to the gate structure 11 located in the gate pickup area.
  • the first insulating layer 2 and the second insulating layer 3 located on the surface of the gate structure 11 are etched along the etched through hole to expose the gate structure 11, and then as shown in FIG. 20, the second mask layer 61 and the photoresist pattern 62 are removed to expose the first connecting plug 71 and the second connecting plug 72; as shown in FIG. 21, a third initial connecting plug 75 is formed on the first connecting plug 71 and the second connecting plug 72 and the exposed surface of the gate structure 11, and as shown in FIG. 22, a portion of the third initial connecting plug 75 is removed, and a portion of the third initial connecting plug 75 located in the etched through hole 63 is retained to form a third connecting plug 74.
  • the deposition thickness of the third initial connecting plug 75 may be 10-25 nm, for example, the deposition thickness of the third initial connecting plug 75 may be 20 nm.
  • the present disclosure further proposes a semiconductor structure 100 .
  • the semiconductor structure 100 according to the embodiment of the present disclosure can be prepared by using the preparation method of the semiconductor structure 100 of the above-mentioned embodiment.
  • the semiconductor structure 100 may include a substrate 1 , a first insulating layer 2 , a second insulating layer 3 , a first connecting plug 71 , and a second connecting plug 72 .
  • the substrate 1 has a first area A1 and a second area A2, and a gate structure 11 is provided on the substrate 1; a spacing S1 between adjacent gate structures 11 located in the first area A1 is smaller than a spacing S2 between adjacent gate structures 11 located in the second area A2; the first insulating layer 2 is located on the surface of the gate structure 11, and a first groove 33 is formed between the first insulating layer 2 on the side wall of the gate structure 11 in the first area A1, and the first groove 33 corresponds to the position of the source and drain region 18 in the first area A1; the second insulating layer 3 is located on the side wall of the first insulating layer 2 in the second area A2, and a second groove 34 is formed between the second insulating layer 3 on the side wall of the gate structure 11 in the second area A2, and the second groove 34 corresponds to the position of the source and drain region 18 in the second area A2;
  • the first connecting plug 71 is located in the first groove 33 and connected to the source and drain regions 18 of the first area A1
  • the second connecting plug 72 is located in the second groove 34 and connected to the source and drain regions 18 of the second area A2 .
  • the first insulating layer 2 is at least partially located on the source and drain regions 18 of the first area A1
  • the second insulating layer 3 is at least partially located on the source and drain regions 18 of the second area A2.
  • the semiconductor structure 100 further includes a third connecting plug 74 .
  • the third connecting plug 74 is connected to the gate structure 11 and can be used to connect the gate structure 11 so as to apply pressure to the gate structure 11 .
  • the first region A1 may be a core region, and the second region A2 may be a peripheral region.
  • the spacing S1 between the gate structures 11 of the first region A1 is smaller than the spacing S2 between the gate structures 11 of the second region A2.
  • the sidewalls of the gate structures 11 of the first region A1 are provided with a first insulating layer 2, and the sidewalls of the gate structures 11 of the second region A2 are provided with a first insulating layer 2 and a second insulating layer 3.
  • the number of insulating layers between the gate structures 11 of the first region A1 and the number of insulating layers between the gate structures 11 of the second region A2 are different.
  • the space occupied by the insulating layers can be reduced, so as to increase the space between the gate structures 11 of the first region A1 for forming the first connecting plug 71, which is beneficial to the formation of the first connecting plug 71 and the self-alignment with the source and drain regions 18 of the first region A1, and can also prevent the first connecting plug 71 from being too thin and broken.
  • the number of insulating layers between the gate structures 11 of the second region A2 is relatively large, which can prevent the insulating layers between the gate structures 11 of the second region A2 from being over-etched and causing a short circuit.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

该公开涉及一种半导体结构及其制备方法，所述制备方法包括：提供基底，基底具有第一区域和第二区域；于基底上形成栅极结构，位于第一区域的相邻的栅极结构的间距小于位于第二区域的相邻的栅极结构的间距；于栅极结构表面形成第一绝缘层，在第一区域，栅极结构侧壁的第一绝缘层之间形成有第一凹槽，第一凹槽与第一区域的源漏区对应；形成第二绝缘层，第二绝缘层位于第二区域的栅极结构侧壁的第一绝缘层表面，在第二区域，第二绝缘层之间形成有第二凹槽，第二凹槽与第二区域的源漏区对应，根据本发明实施例的半导体结构及其制备方法，能够提高第一连接插塞和第二插塞的对准效果，降低断裂和短路的风险。

Description

半导体结构及制备方法
相关申请引用说明
本申请要求于2022年11月01日递交的中国专利申请号2022113667836、申请名为“半导体结构及制备方法”的优先权，其全部内容以引用的形式附录于此。
技术领域
本公开涉及半导体技术领域，具体涉及一种半导体结构及制备方法。
背景技术
现有技术的半导体结构的连接插塞例如连接源漏以及栅极结构的插塞，不同位置的连接插塞一般采用同步形成，但由于连接插塞的形成位置不同，形成连接插塞的空间大小不同，导致形成的连接插塞容易产生不对准或断裂的风险，例如相关技术中核心区域的栅极结构之间的间距小于***区域的栅极结构之间的间距，后续形成源漏插塞时，容易导致核心区域的源漏插塞不易对准，而且由于形成空间较小形成的源漏插塞容易发生断裂，也容易发生短路现象。
发明内容
本公开的目的在于提供一种半导体结构及其制备方法，能够提高连接插塞的对准效果，降低断裂和短路的风险。
根据本公开实施例的半导体结构的制备方法，包括：提供基底，所述基底具有第一区域和第二区域；于所述基底上形成栅极结构，位于所述第一区域的相邻的栅极结构的间距小于位于所述第二区域的相邻的栅极结构的间距；于所述栅极结构表面形成第一绝缘层，在所述第一区域，所述栅极结构侧壁的第一绝缘层之间形成有第一凹槽，所述第一凹槽与所述第一区域的源漏区对应；形成第二绝缘层，所述第二绝缘层位于所述第二区域的栅极结构侧壁的所述第一绝缘层表面，在所述第二区域，所述第二绝缘层之间形成有第二凹槽，所述第二凹槽与所述第二区域的源漏区对应；于所述第一凹槽形成与所述第一区域的源漏区连接的第一连接插塞；于所述第二凹槽形成与所述第二区域的源漏区连接的第二连接插塞。
根据本公开的一些实施例，于所述栅极结构表面形成第一绝缘层的步骤包括：于所述栅极结构表面形成第一子绝缘层，所述栅极结构侧壁的所述第一子绝缘层之间形成有暴露所述基底的第一子凹槽；沿所述第一子凹槽对所述基底进行第一离子注入以在所述基底内形成第一掺杂区；于所述第一子绝缘层的表面形成第二子绝缘层，所述第一子绝缘层和所述第二子绝缘层共同形成所述第一绝缘层，所述第一凹槽形成在所述第一区域的所述第二子绝缘层之间。
根据本公开的一些实施例，在形成第二绝缘层的步骤中，于位于所述第二区域的所述第二子绝缘层的侧壁形成第三子绝缘层，所述第三子绝缘层之间形成第三子凹槽，所述第二绝缘层包括第三子绝缘层；沿所述第一凹槽和所述第三子凹槽对所述基底进行第二离子注入，以形成所述第一区域的源漏区和所述第二区域的源漏区。
根据本公开的一些实施例，形成所述第二绝缘层的步骤还包括至少于所述第三子绝缘层的表面形成第四子绝缘层，所述第四子绝缘层和所述第三子绝缘层共同形成所述第二绝缘层。
根据本公开的一些实施例，在形成所述第四子绝缘层之前还包括：于所述第一凹槽内形成第一牺牲层；在于所述第三子绝缘层表面形成第四子绝缘层的步骤中，所述第四子绝缘层形成在所述第一绝缘层、所述基底、所述第一牺牲层和所述第三子绝缘层表面。
根据本公开的一些实施例，采用原子层沉积法形成所述第一牺牲层。
根据本公开的一些实施例，形成所述第一连接插塞和所述第二连接插塞的步骤包括：于所述第四子绝缘层表面形成第二牺牲层，去除所述第一牺牲层和至少部分所述第二牺牲层以暴露所述第一凹槽和所述第二凹槽，并暴露所述源漏区；于所述第一凹槽内形成所述第一连接插塞，于所述第二凹槽内形成第二连接插塞。
根据本公开的一些实施例，去除所述第一牺牲层和至少部分所述第二牺牲层的步骤包括：于所述第四子绝缘层和所述第二牺牲层表面形成第一掩膜层；于所述第一掩膜层上形成光刻胶层，所述光刻胶层具有与所述第一凹槽和所述第二凹槽对应的光刻通孔；沿所述光刻通孔刻蚀所述第一掩膜层，并向下刻蚀所述第一牺牲层和第二牺牲层以暴露所述第一凹槽和所述第二凹槽，并暴露所述源漏区；去除所述光刻胶层。
根据本公开的一些实施例，于所述第一凹槽内形成所述第一连接插塞，于所述第二凹槽内形成第二连接插塞的步骤包括：于所述第一掩膜层表面、所述第一凹槽和所述第二凹槽内形成初始连接层；去除位于所述第一掩膜层表面的部分初始连接层，保留位于所述第一凹槽内的部分所述初始连接层以形成所述第一连接插塞，保留位于所述第二凹槽内的部分所述初始连接层以形成所述第二连接插塞。
根据本公开的一些实施例，所述半导体结构的制备方法还包括：形成第三连接插塞，所述第三连接插塞与所述栅极结构连接。
根据本公开的一些实施例，形成所述第三连接插塞的步骤包括：于所述第一绝缘层、所述第二绝缘层、所述第一连接插塞和所述第二连接插塞表面形成第二掩膜层；图形化所述第二掩膜层以形成通孔，所述通孔与部分所述栅极结构对应；沿所述刻蚀通孔刻蚀位于所述栅极结构表面的所述第一绝缘层和所述第二绝缘层以暴露所述栅极结构；去除所述第二掩膜层以暴露所述第一连接插塞和所述第二连接插塞；于所述刻蚀通孔内形成第三连接插塞。
根据本公开的一些实施例，所述第一绝缘层包括氧化物层和所述氮化物层中的至少一种。
本公开还提出了一种半导体结构。
根据本公开实施例的半导体包括：基底，所述基底具有第一区域和第二区域，所述基底上设有栅极结构；位于所述第一区域的相邻的栅极结构的间距小于位于所述第二区域的相邻的栅极结构的间距；
第一绝缘层，所述第一绝缘层位于所述栅极结构表面，在所述第一区域，所述栅极结构侧壁的所述第一绝缘层之间形成有第一凹槽，所述第一凹槽与所述第一区域的源漏区位置对应；第二绝缘层，所述第二绝缘层形成在所述第二区域的第一绝缘层的侧壁，在所述第二区域，所述栅极结构的侧壁的所述第二绝缘层之间形成有第二凹槽，所述第二凹槽与所述第二区域的源漏区位置对应；
第一连接插塞，所述第一连接插塞位于所述第一凹槽内且与所述第一区域的所述源漏区连接；第二连接插塞，所述第二连接插塞位于所述第二凹槽内且与所述第二区域的所述源漏区连接。
根据本公开的一些实施例，所述第一绝缘层至少部分位于所述第一区域的所述源漏区上，所述第二绝缘层至少部分位于所述第二区域的所述源漏区上。
根据本公开的一些实施例，所述半导体结构还包括第三连接插塞，所述第三连接插塞与所述栅极结构相连。
由此根据本公开实施例的半导体结构及其制备方法，第一区域可以为核心区域和感应放大区域，第二区域可以为***区域，第一区域的栅极结构之间的间距小于第二区域的栅极结构之间的间距，第一区域的栅极结构的侧壁设有第一绝缘层，第二区域的栅极结构侧壁设有第一绝缘层和第二绝缘层，第一区域的栅极结构之间和第二区域的栅极结构之间的绝缘层层数不同，通过减小第一区域的栅极结构之间的绝缘层层数，可减小绝缘层的占据空间，以增大第一区域的栅极结构之间的第一连接插塞的空间，有利于第一连接插塞的形成和与第一区域的源漏区的自对准，也能够防止第一连接插塞过细而断裂，而且第二区域的栅极结构之间的绝缘层数相对较多，可防止第二区域的栅极结构之间的绝缘层被过刻穿而导致出现短路现象。
附图说明
图1为根据本公开实施例的半导体结构的制备方法的流程示意图；
图2-图22为根据本公开实施例的半导体结构的制备方法的各步骤对应的剖视图；
附图标记：
100：半导体结构，A1：第一区域，A2：第二区域，S1：第一区域的相邻的栅极结构之间的间距，S2：第二区域的相邻的栅极结构之间的间距S2；
1：基底，11：栅极结构，12：第一栅极层，13：第二栅极层，14：第三栅极层，15：基底顶部的氧化物层，16：氮化物盖帽层，17：第一掺杂区，18：源漏区；
2：第一绝缘层，21：第一子绝缘层，211：第一初始子绝缘层，22：第一氧化物层，23：第一氮化物层，24：第二子绝缘层，241：第二初始子绝缘层，25第二氧化物层，26：第二氮化物层；
3：第二绝缘层，31：第三子绝缘层，311：第三初始子绝缘层，32：第四子绝缘层，33：第一凹槽，34：第二凹槽，35：第三子凹槽，36：第一子凹槽
41：第一牺牲层，42：第二牺牲层；
51：第一掩膜层，52：光刻胶层，53：光刻通孔；
61：第二掩膜层，62：光刻胶图案，63：刻蚀通孔，
71：第一连接插塞，72：第二连接插塞，73：初始连接层，74：第三连接插塞。
具体实施方式
以下结合附图和具体实施方式对本公开提出的一种半导体结构100及其制备方法进一步详细说明。
相关技术的半导体结构，在形成连接插塞的过程中，例如在栅极结构之间形成源漏插塞时，由于栅极结构之间空间较小，一方面源漏插塞不容易与源漏区对准，另一方面，由于形成源漏插塞的空间较小也导致形成的插塞容易发生断裂的现象，导致连接效果不佳，而且连接插塞多采用光刻-刻蚀-光刻-刻蚀(Lithography-Etch-Lithography-Etch，LELE)形成，无法对准时也容易导致发生短路现象。具体地，经公开人研究发现，相关技术的半导体结构在形成连接插塞时，不同区域的连接插塞均采用同步形成，不同区域的栅极结构之间间距大小不同，例如核心区域的栅极结构之间的间距小于***区域的栅极结构之间的间距，不同区域的栅极结构上绝缘层同步形成，导致核心区域的栅极结构之间用于形成连接插塞的空间较小，且小于***区域的栅极结构之间用于形成连接插塞的空间，后续采用光刻工艺(LELE)形成连接插塞时，由于核心区域用于形成连接插塞的空间过小，导致刻蚀不易，从而容易导致形成的连接插塞不易对准，而且形成连接插塞的空间减小，也导致形成的连接插塞容易发生断裂和短路的风险。
下面参考附图描述根据本公开实施例的半导体结构100的制备方法，根据本公开实施例的半导体结构100的制备方法，采用自对准工艺形成连接插塞，从而能够避免连接插塞不对准以及发生断裂和短路的问题。
如图1所示，根据本公开实施例的半导体结构100的制备方法可以包括：S1：提供基底1，所述基底1具有第一区域A1和第二区域A2；S2：于所述基底1上形成栅极结构11，位于所述第一区域A1的相邻的栅极结构11的间距小于位于所述第二区域A2的相邻的栅极结构11的间距；S3：于所述栅极结构11表面形成第一绝缘层2，在所述第一区域A1，所述栅极结构11侧壁的第一绝缘层2之间形成有第一凹槽33，所述第一凹槽33与所述第一区域A1的源漏区18对应；S4：形成第二绝缘层3，所述第二绝缘层3位于所述第二区域A2的栅极结构11侧壁的所述第一绝缘层2表面，在所述第二区域A2，所述第二绝缘层3之间形成有第二凹槽34，所述第二凹槽34与所述第二区域A2的源漏区18对应；S5：于所述第一凹槽33形成与所述第一区域A1的源漏区18连接的第一连接插塞71；S6：于所述第二凹槽34形成与所述第二区域A2的源漏区18连接的第二连接插塞72。
图2-图22为根据本公开实施例的半导体结构100的制备方法对应的各步骤的半导体结构100的剖视图，下面结合图2-图21描述根据本公开实施例的半导体结构100的制备方法。
如图2所示，步骤S1：提供基底1，所述基底1具有第一区域A1和第二区域A2，其中所述第一区域A1可以为核心区域，所述第二区域A2可以为***区域。所述基底1可以包括衬底，所述衬底具有有源区，所述基底1还包括形成在有源区之间的隔离区，所述衬底可以是但不限于硅衬底，本具体实施方式以所述衬底为硅衬底为例进行说明。在其他实施例中，所述衬底还可以为氮化镓、砷化镓、碳化镓、碳化硅或SOI等半导体衬底，所述衬底用于支撑在其上的器件结构。
如图2所示，步骤S2：于基底1上形成栅极结构11，位于第一区域A1的相邻的栅极结构11的间距小于位于第二区域A2的相邻的栅极结构11的间距。
具体地，形成栅极结构11的步骤可以包括：可在基底1表面形成叠层结构，对所述叠层结构进行刻蚀以形成多个栅极结构11，其中所述第一区域A1和所述第二区域A2的表面均形成有栅极结构11，第一区域A1的相邻的栅极结构11之间的间距S1小于第二区域A2的相邻的栅极结构11之间的间距S2。如图2所示，基底1还可以包括形成在衬底和隔离区表面的氧化层15，在形成栅极结构11的步骤中，可刻蚀叠层结构至氧化层15表面停止以形成栅极结构11。在如图2所示的示例中，所述栅极结构11可以包括第一栅极层12、第二栅极层13和第三栅极层14以及位于第三栅极层14上的氮化硅盖帽层16，其中，所述第一栅极层12可以为多晶硅层，第二栅极层13可以为金属层，第三栅极层14可以为金属硅化物层。
结合图3-图7所示，步骤S3：于栅极结构11表面形成第一绝缘层2，在所述第一区域A1，所述栅极结构11侧壁的第一绝缘层2之间形成有第一凹槽33，所述第一凹槽33与所述第一区域A1的源漏区18对应。其中在第一区域A1和第二区域A2的栅极结构11的表面均形成第一绝缘层2，第一绝缘层2可以包括为氮化物层和氧化物层的交替堆叠的堆叠结构，源漏区18形成在所述基底1内且与第一凹槽33位置对应。
如图3-图7所示，于栅极结构11表面形成第一绝缘层2的步骤可以包括：
于所述栅极结构11表面形成第一子绝缘层21，所述栅极结构11侧壁的所述第一子绝缘层21之间形成有暴露所述基底1的第一子凹槽36；
沿所述第一子凹槽36对所述基底1进行第一离子注入以在所述基底1内形成第一掺杂区17；
于所述第一子绝缘层21的表面形成第二子绝缘层24，所述第一子绝缘层21和所述第二子绝缘层24共同形成所述第一绝缘层2，所述第一凹槽33形成在所述第一区域A1的所述第二子绝缘层24之间。
具体地，如图3所示，可在基底1表面和栅极结构11的表面形成第一初始子绝缘层211，如图4所示，对第一初始子绝缘层211进行刻蚀，保留位于栅极结构11表面的部分第一初始子绝缘层211以形成第一子绝缘层21，在如图4所示的示例中，所述第一子绝缘层21可以包括第一氧化层22和第一氮化物层23，第一氧化物层22可形成在第一栅极层12的侧壁，第一氮化物层23形成在栅极结构11的侧壁和上表面，且覆盖第一氧化层22，可选地，第一氧化物层22的厚度可以为0-2nm，第一氮化物层23的厚度可以为0-5nm。
如图4所示，在第一区域A1，栅极结构11侧壁的第一子绝缘层21之间可形成第一子凹槽36，第一子凹槽36暴露基底1，具体地，第一子凹槽36暴露基底1的部分有源区表面，然后可沿第一子凹槽36对基底1进行离子注入以在基底1内形成掺杂区17，例如可沿第一子凹槽36对基底1进行轻掺杂以形成轻掺杂源漏(light dopant drain LDD)结构。
如图5所示，可采用化学气相沉积法、物理气相沉积法等中的至少一种于基底1和第一子绝缘层21的表面形成第二初始子绝缘层241，结合图6-图7所示，可对第二初始子绝缘层241进行刻蚀，保留位于第一子绝缘层21表面的部分第二初始子绝缘层以形成第二子绝缘层24，这样，在第一区域A1和第二区域A2的栅极结构11的表面均形成有第二子绝缘层24和第一子绝缘层21，第一子绝缘层21和第二子绝缘层24共同构成第一绝缘层2，即第一区域A1和第二区域A2的栅极结构11的侧壁均形成有第一绝缘层2，其中位于第一 区域A1的第二子绝缘层24之间可形成第一凹槽33，第一凹槽33对应位于第一掺杂区17上。
如图7所示，第二子绝缘层24可以包括第二氧化物层25和第二氮化物层26，第二氧化层25形成在第一子绝缘层21和基底1的表面，第二氮化层26形成在第二氧化物层25的表面，其中第二氧化物层25的厚度可以为0-2nm，第二氮化物层26的厚度可以为0-15nm。
结合图6-图10所示，步骤S4：形成第二绝缘层3，所述第二绝缘层3位于所述第二区域A2的栅极结构11侧壁的所述第一绝缘层2表面，在所述第二区域A2，所述第二绝缘层3之间形成有第二凹槽34，所述第二凹槽34与所述第二区域A2的源漏区18对应。
由此，在第一区域A1的栅极结构11的侧壁形成有第一绝缘层2，在第二区域A2的栅极结构11的侧壁形成有第一绝缘层2和第二绝缘层3，这样在第一区域A1和第二区域A2的栅极结构11的侧壁形成的绝缘层的层数不同，第一区域A1的栅极结构11侧壁的绝缘层层数小于第二区域A2的栅极结构11侧壁的绝缘层层数，第二区域A2的栅极结构11侧壁的绝缘层厚度大于第一区域A1的栅极结构11侧壁的绝缘层厚度，从而可减少第一区域A1的栅极结构11侧壁的绝缘层的占据空间，有利于后续在栅极结构11之间形成连接插塞。
在本公开的一些实施例中，第二绝缘层3可以包括第三子绝缘层31，形成第二绝缘层3的步骤可以包括：
于位于所述第二区域A2的所述第二子绝缘层24的侧壁形成第三子绝缘层31，所述第三子绝缘层31之间形成第三子凹槽35，所述第二绝缘层3包括第三子绝缘层31；
沿所述第一凹槽33和所述第三子凹槽35对所述掺杂区17和所述基底1进行离子注入，以形成所述第一区域A1的源漏区18和所述第二区域A2的源漏区18。
具体地，如图6所示，在形成第二初始子绝缘层241后，可在第二初始子绝缘层241的表面形成第三初始子绝缘层311，所述第三初始子绝缘层311可以为氧化物层，第三子绝缘层31的厚度可以为0-10nm。
如图7所示，在对第二初始子绝缘层241进行刻蚀的步骤中，可同时刻蚀第三初始子绝缘层311，具体而言，可去除位于第二初始子绝缘层241上表面的第三初始子绝缘层311，保留位于第二子绝缘层24侧壁的部分第三初始子绝缘层311以形成第三子绝缘层31，并沿第三子绝缘层31的侧壁刻蚀第二初始子绝缘层以形成第二子绝缘层24，同时在第三子绝缘层31之间可形成第三子凹槽35，第三子凹槽35对应位于第二区域A2的掺杂区17上。
如图6所示，在形成第三初始子绝缘层311的步骤中，在第一区域A1内，由于第二子绝缘层24之间的间距较小，例如第二初始子绝缘层241侧壁之间的间距一般小于67nm，这样在沉积第三初始子绝缘层311时，第一区域A1的第二初始子绝缘层241侧壁之间可形成有空气间隙，第三初始子绝缘层311形成在第二初始子绝缘层241的上表面，在第一区域A1的第二初始子绝缘层241的侧壁不会形成第三初始子绝缘层311，即在第一区域A1的栅极结构11之间不会形成第三初始子绝缘层311。
如图7所示，在对第二初始子绝缘层241和第三初始子绝缘层311进行刻蚀后，在第一区域A1的栅极结构11之间形成第一绝缘层2，在第二区域A2的栅极结构11之间形成有第一绝缘层2和第三子绝缘层31，其中第一凹槽33形成在第一区域A1的第一绝缘层2之间，第三子凹槽35形成在第二区域A2的第三子绝缘层31之间。
如图8所示，可沿第一凹槽33和第三子凹槽35对基底1进行第二离子注入以形成第一区域A1的源漏区18和第二区域A2的源漏区18，这样第一区域A1的栅极结构11之间的源漏区18与第一凹槽33对应，第二区域A2的栅极结构11之间的源漏区18与第三子凹槽35对应，其中第一离子注入和第二离子注入可注入同类型离子，例如第一离子注入和第二离子注入均可以为N型离子注入，第二离子注入的浓度和深度均大于第一离子注入。
在本公开的一些实施例中，第二绝缘层3还可以包括第四子绝缘层32，形成第二绝缘层3的步骤还可以包括至少于所述第三子绝缘层31的表面形成第四子绝缘层32，所述第四子绝缘层32和所述第三子绝缘层31共同形成所述第二绝缘层3，第四子绝缘层32形成在 第三子凹槽35内，第二凹槽34形成在第四子绝缘层32之间，由此，第一区域A1的栅极结构11的侧壁具有第一绝缘层2，第二区域A2的栅极结构11的侧壁具有第一绝缘层2和第二绝缘层3，第一区域A1的栅极结构11侧壁的绝缘层少于第二区域A2的栅极结构11之间的绝缘层层数，通过控制不同区域的栅极结构11之间的绝缘层，从而减少了第一区域A1的栅极结构11之间的绝缘层的层数和占据空间，可增大第一区域A1的栅极结构11之间用于形成第一连接插塞71的空间，防止间距减小的栅极结构11之间形成的连接插塞不易对准或容易发生断裂的现象，也可避免对第一区域A1的栅极结构11之间过刻蚀而导致发生短路。同时也可防止间距大的栅极结构11侧壁的绝缘层较薄被刻穿而发生短路现象。
结合图9-图16所示，步骤S5：于所述第一凹槽33形成与所述第一区域A1的源漏区18连接的第一连接插塞71；步骤S6：于所述第二凹槽34形成与所述第二区域A2的源漏区18连接的第二连接插塞72。
在一些实施例中，形成第一连接插塞71和第二连接插塞72的方法可以包括以下步骤：
在形成所述第四子绝缘层32之前，于所述第一凹槽33形成第一牺牲层41；在于所述第三子绝缘层31表面形成第四子绝缘层32的步骤中，所述第四子绝缘层32形成在所述第一绝缘层2、所述基底1、所述第一牺牲层41和所述第三子绝缘层31表面。
具体地，如图9所示，在进行第二离子注入形成源漏区18之后，可于第一凹槽33内形成第一牺牲层41，第一区域A1的源漏区18通过沿第一凹槽33进行第二离子注入形成，第一牺牲层41填充第一凹槽33以与第一区域A1的源漏区18对准，在后续步骤去除第一牺牲层41形成第一连接插塞71时，使得第一连接插塞71能够与第一区域A1的源漏区18自对准。可选地，在此步骤中，可采用原子层沉积法形成第一牺牲层41，由于第一凹槽33的空间较小，采用原子层沉积法从而能够提高沉积效果，使得第一牺牲层41能够填满第一凹槽33。
如图10所示，于基底1表面、第一绝缘层2表面、第一牺牲层41表面和第三子绝缘层31表面沉积形成第四子绝缘层32，其中第四子绝缘层32形成在第一区域A1的栅极结构11的上表面，而并不形成在栅极结构11的侧壁，第二区域A2的栅极结构11的侧壁形成有第四子绝缘层32，第四子绝缘层32和第三子绝缘层31共同构成第二绝缘层3，第二凹槽34形成在栅极结构11侧壁的第四子绝缘层32之间，
如图11-图16所示，在形成第四子绝缘层32后，所述半导体结构100的制备方法还包括：
于所述第四子绝缘层32表面形成第二牺牲层42，
在形成所述第一连接插塞71和所述第二连接插塞72的步骤中，刻蚀所述第一牺牲层41和所述第二牺牲层42以暴露所述第一凹槽33和所述第二凹槽34，并暴露所述源漏区18；
于所述第一凹槽33内形成所述第一连接插塞71，于所述第二凹槽34内形成第二连接插塞72。
具体地，如图11所示，可采用化学气相沉积法、物理气相沉积法或原子层沉积法中的至少一种于第四子绝缘层32的表面形成第二牺牲层42，所述第二牺牲层42可与栅极结构11上表面的第二绝缘层3平齐，第二牺牲层42填充第二凹槽34且部分对应位于第二区域A2的源漏区18的上方，在后续形成第二连接插塞72的步骤中，可去除位于第二区域A2的栅极结构11之间的部分第二牺牲层42以用于形成第二连接插塞72，从而使得第二连接插塞72能够与第二区域A2的源漏区18自对准，可选地，第二牺牲层42的沉积厚度可以为0-200nm。
结合图12-图14所示，刻蚀所述第一牺牲层41和所述第二牺牲层42以暴露所述第一凹槽33和所述第二凹槽34的步骤可以包括：如图12所示，于所述第四子绝缘层32和所述第二牺牲层42表面形成第一掩膜层51，第一掩膜层51覆盖第四子绝缘层32和第二牺牲层42的上表面；如图13所示，于所述第一掩膜层51上形成光刻胶层52，所述光刻胶层52具有与所述第一凹槽33和所述第二凹槽34对应的光刻通孔53；如图14所示，沿所述 光刻通孔53刻蚀所述第一掩膜层51以暴露第一牺牲层41和第二牺牲层42，并继续向下刻蚀所述第一牺牲层41和第二牺牲层42，以暴露所述第一凹槽33和所述第二凹槽34；从而可暴露出第一区域A1的源漏区18和第二区域A2的源漏区18，最后去除所述光刻胶层52。
具体地，在第一区域A1，可沿光刻通孔53刻穿第一掩膜层51和第四子绝缘层32以暴露第一牺牲层41，在第二区域A2可沿光刻通孔53可刻穿第四子绝缘层32至暴露第二牺牲层42停止，然后去除第一牺牲层41和第二牺牲层42，其中在去除第一牺牲层41和第二牺牲层42的步骤中，第一绝缘层2可形成刻蚀第一牺牲层41的停止层，第二绝缘层3可形成为刻蚀第二牺牲层42的停止层。可选地，在此步骤中可采用各向异性刻蚀工艺进行刻蚀，其中，第一牺牲层41和第二牺牲层42可以为相同材料，且与第四子绝缘层32和第二子绝缘层24的材料均不同，例如第一牺牲层41和第二牺牲层42可以为氧化硅层，第四子绝缘层32和第二子绝缘层24可以为氮化硅层，在刻蚀第一牺牲层41和第二牺牲层42的步骤中，可选择对氧化硅层刻蚀速率低而氮化硅层刻蚀速率高的刻蚀剂进行各向异性刻蚀。
结合图15-图16所示，于第一凹槽33内形成第一连接插塞71，于第二凹槽34内形成第二连接插塞72，第一连接插塞71与第一区域A1的源漏区18连接，第二连接插塞72与第二区域A2的源漏区18连接。
在本公开的一些实施例中，形成所述第一连接插塞71和第二连接插塞72的步骤可以包括：如图15所示，于所述第一掩膜层51表面形成、所述第一凹槽33和所述第二凹槽34内形成初始连接层73；如图16所示，去除位于所述第一掩膜层51表面的部分初始连接层73，保留位于所述第一凹槽33内的部分所述初始连接层73以形成所述第一连接插塞71，保留位于所述第二凹槽34内的部分所述初始连接层73以形成所述第二连接插塞72。可选地，可采用化学机械研磨工艺去除位于第一掩膜层51表面的部分初始连接层73。进一步地，第一连接插塞71和第二连接插塞72的材料可以为金属材料或金属硅化物材料。
在本公开的一些实施例中，所述半导体结构100的制备方法还包括：形成第三连接插塞74，所述第三连接插塞74与所述栅极结构11连接，可用于将栅极结构11引出，以便于对栅极结构11施加电压。
结合图17-图22所示，形成所述第三连接插塞74的方法可以包括以下步骤：
如图17所示，于所述第一绝缘层2、所述第二绝缘层3、所述第一连接插塞71和所述第二连接插塞72表面形成第二掩膜层61，第二掩膜层61遮挡第一连接插塞71和第二连接插塞72，在如图17所示的示例中，第二掩膜层61可覆盖第一连接插塞71、第二连接插塞72和第一掩膜层51的表面，所述第二掩膜层61可以为氧化硅层，所述第二掩膜层61的厚度可以为0-20nm。
如图18-图20所示，图形化所述第二掩膜层61以形成刻蚀通孔63，所述刻蚀通孔63与位于所述第二区域A2外侧的部分所述栅极结构11对应，具体地，如图18所示，可在第二掩膜层61的表面形成光刻胶图案62，光刻胶图案62具有与第二区域A2外侧的栅极结构11对应的光刻孔，第二区域A2外侧的栅极结构11可指位于栅极拾取区的栅极结构11。
如图19-图20所示，沿所述刻蚀通孔刻蚀位于所述栅极结构11表面的所述第一绝缘层2和所述第二绝缘层3以暴露所述栅极结构11，之后如图20所示，去除第二掩膜层61和光刻胶图案62，以暴露第一连接插塞71和第二连接插塞72；如图21所示，于所述第一连接插塞71和所述第二连接插塞72上和暴露的所述栅极结构11表面形成第三初始连接插塞75，如图22所示，去除部分所述第三初始连接插塞75，保留位于刻蚀通孔63内的部分第三初始连接插塞75以形成第三连接插塞74。其中第三初始连接插塞75的沉积厚度可以为10-25nm，例如第三初始连接插塞75的沉积厚度可以为20nm。
本公开还提出了一种半导体结构100，根据本公开实施例的半导体结构100可采用上述实施例的半导体结构100的制备方法制备形成。
如图22所示，根据本公开实施例的半导体结构100可以包括基底1、第一绝缘层2、 第二绝缘层3、第一连接插塞71和第二连接插塞72。
所述基底1具有第一区域A1和第二区域A2，所述基底1上设有栅极结构11；位于所述第一区域A1的相邻的栅极结构11的间距S1小于位于所述第二区域A2的相邻的栅极结构11的间距S2；所述第一绝缘层2位于所述栅极结构11表面，在所述第一区域A1，所述栅极结构11侧壁的所述第一绝缘层2之间形成有第一凹槽33，所述第一凹槽33与所述第一区域A1的源漏区18位置对应；所述第二绝缘层3位于所述第二区域A2的第一绝缘层2的侧壁，在所述第二区域A2，所述栅极结构11的侧壁的所述第二绝缘层3之间形成有第二凹槽34，所述第二凹槽34与所述第二区域A2的源漏区18位置对应；
所述第一连接插塞71位于所述第一凹槽33内且与所述第一区域A1的所述源漏区18连接，所述第二连接插塞72位于所述第二凹槽34内且与所述第二区域A2的所述源漏区18连接。
根据本公开的一些实施例，所述第一绝缘层2至少部分位于所述第一区域A1的所述源漏区18上，所述第二绝缘层3至少部分位于所述第二区域A2的所述源漏区18上。
根据本公开的一些实施例，所述半导体结构100还包括第三连接插塞74，所述第三连接插塞74与所述栅极结构11相连，可用于将栅极结构11，以便于对栅极结构11施压。
由此根据本公开实施例的半导体结构及其制备方法，第一区域A1可以为核心区域，第二区域A2可以为***区域，第一区域A1的栅极结构11之间的间距S1小于第二区域A2的栅极结构11之间的间距S2，第一区域A1的栅极结构11的侧壁设有第一绝缘层2，第二区域A2的栅极结构11侧壁设有第一绝缘层2和第二绝缘层3，第一区域A1的栅极结构11之间和第二区域A2的栅极结构11之间的绝缘层层数不同，通过减小第一区域A1的栅极结构11之间的绝缘层层数，可减小绝缘层的占据空间，以增大第一区域A1的栅极结构11之间用于形成第一连接插塞71的空间，有利于第一连接插塞71的形成和与第一区域A1的源漏区18的自对准，也能够防止第一连接插塞71过细而断裂，而且第二区域A2的栅极结构11之间的绝缘层数相对较多，可防止第二区域A2的栅极结构11之间的绝缘层被过刻穿而导致出现短路现象。
以上所述仅是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本公开原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (15)

  1. 一种半导体结构的制备方法，包括：
    提供基底，所述基底具有第一区域和第二区域；
    于所述基底上形成栅极结构，位于所述第一区域的相邻的栅极结构的间距小于位于所述第二区域的相邻的栅极结构的间距；
    于所述栅极结构表面形成第一绝缘层，在所述第一区域，所述栅极结构侧壁的第一绝缘层之间形成有第一凹槽，所述第一凹槽与所述第一区域的源漏区对应；
    形成第二绝缘层，所述第二绝缘层位于所述第二区域的栅极结构侧壁的所述第一绝缘层表面，在所述第二区域，所述第二绝缘层之间形成有第二凹槽，所述第二凹槽与所述第二区域的源漏区对应；
    于所述第一凹槽形成与所述第一区域的源漏区连接的第一连接插塞；
    于所述第二凹槽形成与所述第二区域的源漏区连接的第二连接插塞。
  2. 根据权利要求1所述半导体结构的制备方法，其中，于所述栅极结构表面形成第一绝缘层的步骤包括：
    于所述栅极结构表面形成第一子绝缘层，所述栅极结构侧壁的所述第一子绝缘层之间形成有暴露所述基底的第一子凹槽；
    沿所述第一子凹槽对所述基底进行第一离子注入以在所述基底内形成第一掺杂区；
    于所述第一子绝缘层的表面形成第二子绝缘层，所述第一子绝缘层和所述第二子绝缘层共同形成所述第一绝缘层，所述第一凹槽形成在所述第一区域的所述第二子绝缘层之间。
  3. 根据权利要求2所述半导体结构的制备方法，其中，在形成第二绝缘层的步骤中，于位于所述第二区域的所述第二子绝缘层的侧壁形成第三子绝缘层，所述第三子绝缘层之间形成第三子凹槽，所述第二绝缘层包括第三子绝缘层；
    沿所述第一凹槽和所述第三子凹槽对所述基底进行第二离子注入，以形成所述第一区域的源漏区和所述第二区域的源漏区。
  4. 根据权利要求3所述半导体结构的制备方法，其中，形成所述第二绝缘层的步骤还包括至少于所述第三子绝缘层的表面形成第四子绝缘层，所述第四子绝缘层和所述第三子绝缘层共同形成所述第二绝缘层。
  5. 根据权利要求4所述半导体结构的制备方法，其中，在形成所述第四子绝缘层之前还包括：
    于所述第一凹槽内形成第一牺牲层；
    在于所述第三子绝缘层表面形成第四子绝缘层的步骤中，所述第四子绝缘层形成在所述第一绝缘层、所述基底、所述第一牺牲层和所述第三子绝缘层表面。
  6. 根据权利要求5所述半导体结构的制备方法，其中，采用原子层沉积法形成所述第一牺牲层。
  7. 根据权利要求5所述半导体结构的制备方法，其中，形成所述第一连接插塞和所述第二连接插塞的步骤包括：
    于所述第四子绝缘层表面形成第二牺牲层，
    去除所述第一牺牲层和至少部分所述第二牺牲层以暴露所述第一凹槽和所述第二凹槽，并暴露所述源漏区；
    于所述第一凹槽内形成所述第一连接插塞，于所述第二凹槽内形成第二连接插塞。
  8. 根据权利要求7所述半导体结构的制备方法，其中，去除所述第一牺牲层和至少部分所述第二牺牲层的步骤包括：
    于所述第四子绝缘层和所述第二牺牲层表面形成第一掩膜层；
    于所述第一掩膜层上形成光刻胶层，所述光刻胶层具有与所述第一凹槽和所述第二凹槽对应的光刻通孔；
    沿所述光刻通孔刻蚀所述第一掩膜层，并向下刻蚀所述第一牺牲层和第二牺牲层以暴露 所述第一凹槽和所述第二凹槽，并暴露所述源漏区；
    去除所述光刻胶层。
  9. 根据权利要求8所述半导体结构的制备方法，其中，于所述第一凹槽内形成所述第一连接插塞，于所述第二凹槽内形成第二连接插塞的步骤包括：
    于所述第一掩膜层表面、所述第一凹槽和所述第二凹槽内形成初始连接层；
    去除位于所述第一掩膜层表面的部分初始连接层，保留位于所述第一凹槽内的部分所述初始连接层以形成所述第一连接插塞，保留位于所述第二凹槽内的部分所述初始连接层以形成所述第二连接插塞。
  10. 根据权利要求1所述半导体结构的制备方法，还包括：
    形成第三连接插塞，所述第三连接插塞与所述栅极结构连接。
  11. 根据权利要求10所述半导体结构的制备方法，其中，形成所述第三连接插塞的步骤包括：
    于所述第一绝缘层、所述第二绝缘层、所述第一连接插塞和所述第二连接插塞表面形成第二掩膜层；
    图形化所述第二掩膜层以形成通孔，所述通孔与部分所述栅极结构对应；
    沿所述通孔向下刻蚀位于所述栅极结构表面的所述第一绝缘层和所述第二绝缘层以暴露所述栅极结构；
    去除所述第二掩膜层以暴露所述第一连接插塞和所述第二连接插塞；
    于所述通孔内形成第三连接插塞。
  12. 根据权利要求10所述半导体结构的制备方法，其中，所述第一绝缘层包括氧化物层和氮化物层中的至少一种。
  13. 一种半导体结构，包括：
    基底，所述基底具有第一区域和第二区域，所述基底上设有栅极结构；位于所述第一区域的相邻的栅极结构的间距小于位于所述第二区域的相邻栅极结构的间距；
    第一绝缘层，所述第一绝缘层位于所述栅极结构表面，在所述第一区域，所述栅极结构侧壁的所述第一绝缘层之间形成有第一凹槽，所述第一凹槽与所述第一区域的源漏区位置对应；
    第二绝缘层，所述第二绝缘层形成在所述第二区域的第一绝缘层的侧壁，在所述第二区域，所述栅极结构的侧壁的所述第二绝缘层之间形成有第二凹槽，所述第二凹槽与所述第二区域的源漏区位置对应；
    第一连接插塞，所述第一连接插塞位于所述第一凹槽内且与所述第一区域的所述源漏区连接；
    第二连接插塞，所述第二连接插塞位于所述第二凹槽内且与所述第二区域的所述源漏区连接。
  14. 根据权利要求13所述半导体结构，其中，所述第一绝缘层至少部分位于所述第一区域的所述源漏区上，所述第二绝缘层至少部分位于所述第二区域的所述源漏区上。
  15. 根据权利要求13所述半导体结构，还包括第三连接插塞，所述第三连接插塞与所述栅极结构相连。
PCT/CN2022/134056 2022-11-01 2022-11-24 半导体结构及制备方法 WO2024092903A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202211366783.6A CN118039566A (zh) 2022-11-01 2022-11-01 半导体结构及制备方法
CN202211366783.6 2022-11-01

Publications (1)

Publication Number Publication Date
WO2024092903A1 true WO2024092903A1 (zh) 2024-05-10

Family

ID=90929546

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/134056 WO2024092903A1 (zh) 2022-11-01 2022-11-24 半导体结构及制备方法

Country Status (2)

Country Link
CN (1) CN118039566A (zh)
WO (1) WO2024092903A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090209100A1 (en) * 2008-02-18 2009-08-20 Inotera Memories, Inc. Fabrication method for memory device
CN102810505A (zh) * 2011-06-03 2012-12-05 南亚科技股份有限公司 半导体制程
CN104979292A (zh) * 2015-05-15 2015-10-14 上海华力微电子有限公司 一种形成不同侧墙结构的方法
CN110190058A (zh) * 2019-05-27 2019-08-30 武汉新芯集成电路制造有限公司 半导体器件及其制造方法
CN114220816A (zh) * 2021-12-13 2022-03-22 华虹半导体(无锡)有限公司 半导体结构的形成方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090209100A1 (en) * 2008-02-18 2009-08-20 Inotera Memories, Inc. Fabrication method for memory device
CN102810505A (zh) * 2011-06-03 2012-12-05 南亚科技股份有限公司 半导体制程
CN104979292A (zh) * 2015-05-15 2015-10-14 上海华力微电子有限公司 一种形成不同侧墙结构的方法
CN110190058A (zh) * 2019-05-27 2019-08-30 武汉新芯集成电路制造有限公司 半导体器件及其制造方法
CN114220816A (zh) * 2021-12-13 2022-03-22 华虹半导体(无锡)有限公司 半导体结构的形成方法

Also Published As

Publication number Publication date
CN118039566A (zh) 2024-05-14

Similar Documents

Publication Publication Date Title
KR100370129B1 (ko) 반도체 소자 및 그의 제조방법
KR20000004553A (ko) 반도체 소자의 소자분리방법
US6380088B1 (en) Method to form a recessed source drain on a trench side wall with a replacement gate technique
JPH05166835A (ja) 自己整合ポリシリコン接触
WO2024092903A1 (zh) 半导体结构及制备方法
KR20000051318A (ko) 반도체소자 및 그의 제조방법
KR20050009482A (ko) 반도체 소자의 제조방법
KR20060073818A (ko) 반도체 소자의 콘택 제조 방법
TWI755734B (zh) 半導體元件及其製造方法
KR100359162B1 (ko) 트랜지스터의 제조 방법
KR100271661B1 (ko) 반도체 소자 제조방법
JP4078887B2 (ja) 半導体装置及び同半導体装置の製造方法
KR20010054168A (ko) 반도체소자의 콘택홀 및 그 형성방법
KR20020058512A (ko) 반도체 소자의 제조 방법
KR19980037651A (ko) 반도체 메모리 소자의 패드 및 그 제조방법
KR100314478B1 (ko) 반도체소자의 게이트전극 형성방법
KR100266687B1 (ko) 트랜지스터 제조방법
KR100323725B1 (ko) 반도체소자 및 그의 제조방법
KR100290912B1 (ko) 반도체소자의 격리막 형성방법
KR100400320B1 (ko) 반도체소자의 게이트전극 형성 방법
KR100604760B1 (ko) 반도체소자의 제조방법
KR100266028B1 (ko) 반도체장치 및 그 제조방법
TWI242238B (en) Manufacturing method for dual gate oxide layer
KR20010060039A (ko) 반도체 소자의 제조방법
JPH11354787A (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22964200

Country of ref document: EP

Kind code of ref document: A1