WO2024087514A1 - 半导体结构及其制备方法 - Google Patents

半导体结构及其制备方法 Download PDF

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Publication number
WO2024087514A1
WO2024087514A1 PCT/CN2023/086029 CN2023086029W WO2024087514A1 WO 2024087514 A1 WO2024087514 A1 WO 2024087514A1 CN 2023086029 W CN2023086029 W CN 2023086029W WO 2024087514 A1 WO2024087514 A1 WO 2024087514A1
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channel region
gate trench
doping
gate
region
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PCT/CN2023/086029
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English (en)
French (fr)
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孟雅
徐亚超
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长鑫存储技术有限公司
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Publication of WO2024087514A1 publication Critical patent/WO2024087514A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched

Definitions

  • the embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for preparing the same.
  • MOS transistors are important components in integrated circuit manufacturing. MOS transistors are usually formed on a substrate. The MOS transistor includes a gate, and a source region and a drain region are formed in the substrate on both sides of the gate. A voltage is applied to the gate to control the current flowing between the source region and the drain region, thereby controlling the on and off of the MOS transistor.
  • the gate has different control capabilities over different regions of the channel, affecting the performance of the semiconductor structure.
  • a first aspect of an embodiment of the present disclosure provides a semiconductor structure, comprising:
  • the substrate comprising a gate trench
  • a gate structure wherein the gate structure is disposed in the gate trench
  • a channel region is located in the substrate, the channel region includes a first channel region and a second channel region, the first channel region wraps the bottom of the gate trench, the second channel region wraps the first channel region and the sidewalls of the gate trench not wrapped by the first channel region; the carrier mobility in the first channel region is less than the carrier mobility in the second channel region.
  • a second aspect of the present disclosure provides a method for preparing a semiconductor structure.
  • the method is used to prepare the semiconductor structure described in the first aspect, which comprises the following steps:
  • the substrate comprising a gate trench and a well region, the well region wrapping the outside of the gate trench;
  • a first channel region is formed in the well region, wherein the first channel region wraps the bottom of the gate trench, wherein the well region adjacent to the first channel region and the sidewall of the gate trench not wrapped by the first channel region constitutes a second channel region; and the carrier mobility in the first channel region is less than the carrier mobility in the second channel region;
  • a gate structure is formed in the gate trench.
  • the first channel region is located above the second channel region, and the first channel region wraps the bottom of the gate trench.
  • FIG1 is a schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG2 is a process flow chart of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG3 is a schematic diagram of forming a doping layer in a method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG4 is a schematic diagram of forming a gate trench in a method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG5 is a schematic diagram of forming a first channel region in a method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG6 is a schematic diagram of forming a gate dielectric layer in a method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG7 is a schematic diagram of forming a barrier material layer in a method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG8 is a schematic diagram of forming a barrier layer in a method for preparing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 9 is a schematic diagram of forming a conductive material layer in the method for preparing a semiconductor structure provided in an embodiment of the present disclosure.
  • 100 substrate; 110: gate trench; 120: first doping region; 130: second doping region; 140: doping layer;
  • 200 gate structure; 210: barrier layer; 211: barrier material layer; 220: conductive layer; 221: conductive material layer;
  • 300 channel region; 310: first channel region; 320: second channel region; 311: first edge; 312: second edge; 313: first intersection; 314: second intersection;
  • the thickness of the gate dielectric layer formed on the inner wall of the gate trench due to the deposition process has a large step coverage, that is, the thickness of the gate dielectric layer at the top of the gate trench is greater than the thickness of the gate dielectric layer at the bottom of the gate trench, resulting in the gate structure's control ability over the channel region at the bottom of the gate trench being greater than the gate structure's control ability over the channel region at the top of the gate trench, causing the channel region at the bottom of the gate trench to be more easily opened or closed when a certain voltage is applied to the gate structure, thereby making the channel region at the bottom of the gate trench more likely to be opened or closed, and thus making the channel region at the bottom of the gate trench and the channel region at the top of the gate trench open or close to different degrees, causing leakage in the channel region that is
  • the thickness of the gate dielectric layer near the top of the gate trench is usually reduced to improve the control capability of the gate structure over the channel region at the top of the gate trench.
  • the above-mentioned pair causes the gate dielectric layer near the top of the gate trench to be broken down, making the gate structure leakage more serious, and reducing the performance of the semiconductor structure.
  • the embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same.
  • the sensitivity of the gate structure to the opening or closing of the first channel region can be reduced, thereby balancing the gate structure to The difference in control sensitivity between the first channel region and the second channel region improves the performance of the semiconductor structure.
  • the present embodiment does not limit the semiconductor structure.
  • the semiconductor structure will be described below by taking a dynamic random access memory (DRAM) as an example, but the present embodiment is not limited thereto.
  • DRAM dynamic random access memory
  • the semiconductor structure in the present embodiment may also be other structures.
  • an embodiment of the present disclosure provides a semiconductor structure including a substrate 100 , a gate structure 200 and a channel region 300 .
  • the substrate 100 is a carrier of the gate structure 200, the channel region 300 or other semiconductor devices.
  • the substrate 100 may be a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (GeSi) substrate, a silicon carbide (SiC) substrate, a silicon on insulator (SOI) substrate or a germanium on insulator (GOI) substrate.
  • STI shallow trench isolation
  • a shallow trench is formed in the substrate by a patterning process, and an insulating material is filled in the shallow trench, so as to define a plurality of active areas separated by shallow trench isolation structures on the substrate.
  • the patterning process may be a self-aligned double patterning (SADP) process or a self-aligned quadruple patterning (SAQP) process.
  • SADP self-aligned double patterning
  • SAQP self-aligned quadruple patterning
  • the insulating material may include silicon oxide, but is not limited thereto.
  • the substrate 100 includes a gate trench 110, the depth direction of the gate trench 110 is parallel to the direction perpendicular to the substrate 100, and the bottom of the gate trench 110 is located in the substrate 100. It should be noted that, taking the section perpendicular to the substrate 100 as the longitudinal section, the longitudinal section of the gate trench 110 can be rectangular or conical.
  • the channel region 300 is located in the substrate 100, and includes a first channel region 310 and a second channel region 320.
  • the first channel region 310 wraps the bottom of the gate trench 110. It should be noted that the bottom of the gate trench 110 can be understood as the bottom wall of the gate trench 110 and part of the side wall of the gate trench 110.
  • the second channel region 320 wraps around the outer surface of the first channel region 310 and the sidewall of the gate trench 110 not wrapped by the first channel region 310 ; the carrier mobility in the first channel region 310 is smaller than the carrier mobility in the second channel region 320 .
  • the gate structure 200 is disposed in the gate trench 110, and is used to control the opening or closing of the first channel region 310 and the second channel region 320.
  • the carriers such as holes or electrons
  • the channel region 300 will move approximately along the extension direction of the inner wall of the gate trench 110, that is, approximately along the direction from one end of the inner wall of the gate trench 110 to the other end, so as to realize the gate structure 200 opening the channel region 300.
  • the carriers in the channel region 300 move along the direction of the arrow shown in FIG. 1 .
  • the embodiment of the present disclosure changes the difference between the carrier mobility in the first channel region 310 and the carrier mobility in the second channel region 320 so that the carrier mobility in the first channel region 310 is smaller than the carrier mobility in the second channel region 320, thereby reducing the sensitivity of the gate structure 200 to opening or closing the first channel region 310, thereby balancing the difference in control sensitivity of the gate structure 200 to the first channel region 310 and the second channel region 320, thereby improving the performance of the semiconductor structure.
  • the first channel region 310 includes first doping ions and second doping ions
  • the second channel region 320 includes second doping ions
  • the types of the first doping ions and the second doping ions are different.
  • the first channel region 310 includes a first doping ion and a second doping ion
  • the second channel region 320 includes a second doping ion.
  • the second doping ion is the doping ion originally existing in the first channel region 310 and the second channel region 320.
  • the first channel region 310 has the first doping ion, and the type of the first doping ion is different from the type of the second doping ion.
  • the form of the carriers formed is also different.
  • the type of the first doping ion is N-type
  • the type of the second doping ion is P-type.
  • the voltage When a certain voltage is applied to the gate structure 200, the voltage will excite the first doping ion to induce electrons and excite the second doping ion to induce holes.
  • the electrons will combine with part of the holes and consume part of the holes, thereby reducing the concentration of carriers in the first channel region 310, thereby increasing the concentration of carriers in the first channel region 310.
  • the carrier mobility is lower than the carrier mobility in the second channel region 320 to reduce the sensitivity of the gate structure 200 to the opening or closing of the first channel region 310, thereby balancing the control sensitivity difference of the gate structure 200 to the first channel region 310 and the second channel region 320 and improving the performance of the semiconductor structure.
  • the type of the first doping ion and the type of the second doping ion are not limited to the above description, for example, the type of the first doping ion is P-type, the type of the second doping ion is N-type, and the N-type second doping ion is used as the original doping ion of the first channel region 310 and the second channel region 320.
  • the voltage will excite the second doping ion to induce electrons and excite the first doping ion to induce holes, and the holes will combine with some electrons to consume some electrons, thereby reducing the concentration of carriers in the first channel region 310.
  • the concentration of the first doping ions in the first channel region 310 corresponding to the bottom wall of the gate trench 110 is greater than the concentration of the first doping ions in the first channel region 310 corresponding to the side wall of the gate trench 110 .
  • a gate dielectric layer 400 is disposed between the inner wall of the gate trench 110 and the gate structure 200 , wherein the top surface of the gate dielectric layer 400 is higher than the top surface of the gate structure 200 and flush with the top surface of the substrate 100 .
  • the gate dielectric layer 400 has a high dielectric constant, for example, the material of the gate dielectric layer 400 includes one or more of silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), aluminum oxide (Al 2 O2 3 ), tantalum pentoxide (Ta 2 O 5 ), yttrium oxide (Y 2 O 3 ), hafnium oxide silicate (HfSi 4 ), hafnium dioxide (HfO 2 ), lanthanum oxide (La 2 O 3 ), zirconium dioxide (ZrO 2 ), strontium titanate (SrTiO 3 ), and zirconium oxide silicate (ZrSiO 4 ).
  • the leakage current between the gate structure 200 and the first doping region 120 or between the gate structure 200 and the second doping region 130 can be reduced, thereby improving the performance of the semiconductor structure.
  • the thickness of the gate dielectric layer 400 is not uniform.
  • the thickness of the gate dielectric layer 400 located at the bottom wall of the gate trench 110 is smaller than the thickness of the gate dielectric layer 400 located at the side wall of the gate trench 110. This will shorten the distance between the gate structure 200 and the channel region corresponding to the bottom wall of the gate trench 110, thereby increasing the control sensitivity of the gate structure 200 to the channel region corresponding to the bottom wall of the gate trench 110.
  • the electric field generated by the gate structure 200 at the bottom wall of the gate trench 110 is higher than the electric field generated by the gate structure 200 at the side wall of the gate trench 110. This will also increase the difference between the control ability of the gate structure 200 over the channel region at the top of the gate trench 110 and the control ability of the gate structure 200 over the channel region at the bottom of the gate trench 110.
  • the first channel region 310 corresponding to the bottom wall of the gate trench 110 is The concentration of the first doped ions is greater than the concentration of the first doped ions in the first channel region 310 corresponding to the sidewall of the gate trench 110.
  • more holes or electrons formed by the second doped ions can be consumed, thereby reducing the mobility of carriers in the first channel region 310, thereby reducing the sensitivity of the gate structure 200 to opening or closing the first channel region 310, thereby achieving the purpose of balancing the control sensitivity difference of the gate structure 200 to the first channel region 310 and the second channel region 320, and improving the performance of the semiconductor structure.
  • the concentration of the first doping ions in the first channel region 310 corresponding to the sidewall of the gate trench 110 gradually increases in a direction from the sidewall of the gate trench 110 to the bottom wall of the gate trench 110 .
  • the concentration of the first doping ions in the first channel region 310 corresponding to the side wall of the gate trench 110 gradually increases. In this way, the concentration of the first doping ions in the first channel region 310 corresponding to the bottom wall of the gate trench 110 can be guaranteed to be the highest, and the control capability of the gate structure over each region of the first channel region 310 can be balanced as much as possible, thereby improving the performance of the semiconductor structure.
  • the first channel region 310 includes a first edge 311 and a second edge 312, wherein the first edge 311 is the bottom wall of the gate trench 110 and a portion of the side wall connected to the bottom wall, and the second edge 312 is located on a side of the first edge 311 away from the gate structure 200, and the first edge 311 and the second edge 312 intersect at both ends, so that the first channel region 310 forms a shape similar to a crescent.
  • the first edge 311 can also serve as a partial edge of the second channel region 320.
  • intersections of the first edge 311 and the second edge 312 points in the direction of the other intersection.
  • the intersection on the left side of the gate trench 110 may be recorded as the first intersection 313, and the intersection on the right side of the gate trench 110 may be recorded as the second intersection 314.
  • the distance between the first edge 311 and the second edge 312 tends to increase first and then decrease, that is, the closer the area is to the bottom wall of the gate trench 110, the larger the distance between the first edge 311 and the second edge 312.
  • the distance between the gate structure 200 and the second edge 312 can be increased, and the distance between the gate structure 200 and the second channel region 320 with a larger carrier mobility can be increased, thereby reducing the sensitivity of the gate structure 200 to opening or closing the first channel region 310 near the second edge 312, thereby achieving the purpose of balancing the control sensitivity difference of the gate structure 200 to the first channel region 310 and the second channel region 320, and improving the performance of the semiconductor structure.
  • the first channel region 310 is aligned with the bottom wall of the gate trench 110.
  • the distance between the first edge 311 and the second edge 312 corresponding to the sidewall of the first channel region 310 and the gate trench 110 is greater than the distance between the first edge 311 and the second edge 312 corresponding to the sidewall of the first channel region 310 and the gate trench 110 .
  • the distance between the first edge 311 and the second edge 312 corresponding to the bottom wall of the first channel region 310 and the gate trench 110 is the maximum value.
  • the control ability of the gate structure 200 over the first channel region 310 corresponding to the bottom wall of the gate trench 110 can be slowed down to the greatest extent, thereby achieving the purpose of balancing the control sensitivity difference of the gate structure 200 over the first channel region 310 and the second channel region 320, thereby improving the performance of the semiconductor structure.
  • two intersections of the first edge 311 and the second edge 312 are flush, that is, the first intersection 313 and the second intersection 314 are flush, and a line connecting the first intersection 313 and the second intersection 314 is parallel to the substrate 100 .
  • the distance between the intersection and the top surface of the substrate 100 is three-quarters to four-fifths of the depth of the gate trench 110. This arrangement can not only balance the difference in control sensitivity of the gate structure 200 to the first channel region 310 and the second channel region 320, thereby improving the performance of the semiconductor structure, but also avoid excessive reduction in the control capability of the gate structure 200 to the entire channel region 300.
  • the substrate 100 further includes a first doping region 120 and a second doping region 130 doped with third doping ions; the first doping region 120 and the second doping region 130 are respectively located on both sides of the gate trench 110 and above the channel region 300.
  • the type of the third doping ions is the same as the type of the first doping ions.
  • One of the first doping region 120 and the second doping region 130 is used as a source region, and the other of the first doping region 120 and the second doping region 130 is used as a drain region.
  • the source region can be used to connect to a subsequent bit line structure, and the drain region is used to connect to a capacitor structure formed subsequently.
  • the bit line structure is used to write stored data into the capacitor structure, or read data in the capacitor structure.
  • the gate structure 200 includes a barrier layer 210 and a conductive layer 220, wherein the barrier layer 210 is disposed on the gate dielectric layer 400, and the top surface of the barrier layer 210 is lower than the gate dielectric layer 400.
  • the barrier layer 210 is made of titanium nitride, which prevents the conductive material in the conductive layer 220 from penetrating into the substrate 100 while also having conductivity, thereby ensuring the performance of the semiconductor structure.
  • the conductive layer 220 is disposed on the barrier layer 210, and the top surface of the conductive layer 220 is higher than the barrier layer 210 and lower than the top surface of the gate trench 110, and the top surface of the conductive layer 220 is an arc-shaped surface. In this way, there is a gap between the top of the conductive layer 220 and the first doping region 120, and between the top of the conductive layer 220 and the second doping region 130, thereby reducing the electric field at the interface between the gate structure 200 and the first doping region 120 and/or the second doping region 130, and reducing the gate induced drain leakage current.
  • FIG. 2 a method for preparing a semiconductor structure provided in an embodiment of the present disclosure, the method for preparing the semiconductor structure in Embodiment 1, and comprising the following steps:
  • Step S100 providing a substrate, wherein the substrate comprises a gate trench and a well region, wherein the well region surrounds the outside of the gate trench.
  • a substrate may be provided, and the substrate may be ion-doped using an ion implantation process to form a substrate 100 having a well region.
  • the well region has second doping ions, wherein the type of the second doping ions may be P-type ions, so that the well region is a P-type well region.
  • the type of the second doping ions may be N-type ions, so that the well region is an N-type well region.
  • the well region is a P-type well region, that is, it is formed by injecting P-type ions (group III element ions such as boron B or gallium Ga) into the substrate using an ion implantation process.
  • P-type ions group III element ions such as boron B or gallium Ga
  • N-type well region that is, it is formed by injecting N-type ions (group V element ions such as phosphorus P or arsenic As) into the substrate using an ion implantation process.
  • a first doping region 120 and a second doping region 130 need to be formed on the substrate.
  • a doping layer 140 with a preset thickness is formed in the substrate 100.
  • the doping layer 140 is formed by an ion implantation process, wherein the doping layer 140 has a third doping ion, and the type of the third doping ion is different from the type of the second doping ion. For example, if the second doping ion is a P-type ion, the third doping ion is an N-type ion accordingly.
  • the substrate 100 is patterned to form a gate trench 110 in the substrate 100 ; wherein the doping layer 140 retained on both sides of the gate trench 110 respectively constitutes a first doping region 120 and a second doping region 130 .
  • the gate trench 110 exposes the well region, the first doping region 120 and the second doping region 130 , that is, the well region is wrapped outside the gate trench 110 .
  • a mask layer 500 having a mask opening may be formed on the doping layer 140 , and an etching solution or etching gas may be used to remove the doping layer 140 and a portion of the thickness of the substrate 100 exposed in the mask opening to form a gate trench 110 , a first doping region 120 , and a second doping region 130 .
  • one of the first doping region 120 and the second doping region 130 serves as a source region, and the other of the first doping region 120 and the second doping region 130 serves as a drain region.
  • Step S200 forming a first channel region in the well region, wherein the first channel region wraps around the bottom of the gate trench, wherein the well region adjacent to the first channel region and the sidewall of the gate trench not wrapped by the first channel region constitutes a second channel region; the carrier mobility in the first channel region is less than that in the second channel region. Carrier mobility.
  • a plasma implantation technique is used to implant first doping ions into the bottom of the gate trench 110 to form a first channel region 310 in the well region; the type of the first doping ions is different from the type of the second doping ions.
  • the bottom of the gate trench 110 includes the bottom wall of the gate trench 110 and part of the sidewall of the gate trench 110 .
  • the following describes the formation process of the first channel region 310 and the second channel region 320 assuming that the first doping ions are N-type ions and the second doping ions are P-type ions.
  • N-type ions are injected into the bottom of the gate trench 110 by plasma injection technology, and the N-type ions are doped into the area of the well region near the bottom of the gate trench 110, so that the area of the well region near the bottom of the gate trench 110 has both N-type ions and P-type ions to form the first channel region 310.
  • the voltage will excite the first doped ions to induce electrons and excite the second doped ions to induce holes.
  • the electrons will combine with some of the holes and consume some of the holes, thereby reducing the concentration of carriers in the first channel region 310, and further making the carrier mobility in the first channel region 310 less than the carrier mobility in the second channel region 320.
  • the ion implantation direction in the plasma implantation technology is perpendicular to the substrate, which reduces or even avoids the probability of the first doping ions being injected into the side wall of the gate trench 110 close to the top surface of the substrate 100, thereby preventing the reduction of the carrier mobility in the second channel region 320 and improving the performance of the semiconductor structure.
  • the method for preparing the semiconductor structure further includes: forming a gate dielectric layer 400 on the inner wall of the gate trench 110, wherein the gate dielectric layer 400 has a high dielectric constant. In this way, the leakage current between the first doping region 120 and the second doping region 130 and the subsequently formed gate structure 200 can be reduced, thereby improving the performance of the semiconductor structure.
  • the gate dielectric layer 400 may be formed by an atomic layer deposition process or an in-situ formation process.
  • Step S300 forming a gate structure in the gate trench.
  • Step S310 forming a barrier layer, wherein the barrier layer is disposed on the gate dielectric layer, and a top surface of the barrier layer is lower than a top surface of the gate dielectric layer.
  • an atomic layer deposition process is used to form a barrier material layer 211 on the gate dielectric layer 400 .
  • the barrier material layer 211 extends to the outside of the gate trench 110 and covers the first doping region 120 and the second doping region 130 .
  • the blocking material layer 211 is etched back, that is, the first doping
  • the barrier material layer 211 on the region 120 and the second doped region 130 and the barrier material layer 211 located in the gate trench 110 are formed so that the barrier material layer retained in the gate trench 110 constitutes a barrier layer 210, and the top surface of the barrier layer 210 is lower than the top surface of the gate dielectric layer 400.
  • Step S320 forming a conductive layer, the conductive layer fills the area surrounded by the barrier layer, the top surface of the conductive layer is higher than the top surface of the barrier layer, the top surface of the conductive layer is lower than the top surface of the gate trench, and the top surface of the conductive layer is an arc surface.
  • a conductive material layer 221 is deposited in the gate trench 110 by chemical vapor deposition (CVD) and physical vapor deposition (PVD) processes, and the conductive material layer 221 fills the gate trench 110 .
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • the conductive material layer 221 is etched back, that is, a portion of the conductive material layer 221 located in the gate trench 110 is removed, and the remaining conductive material layer 221 constitutes the conductive layer 220.
  • the barrier layer 210 and the conductive layer 220 constitute the gate structure 200. Please refer to FIG. 1 for its structure.
  • the conductive layer 220 fills the area surrounded by the barrier layer 210, the top surface of the conductive layer 220 is higher than the top surface of the barrier layer 210, the top surface of the conductive layer 220 is lower than the top surface of the gate trench 110, and the top surface of the conductive layer 220 is an arc-shaped surface, that is, the top surface of the conductive layer 220 is a structure with low sides and high in the middle.
  • the gate structure 200 , the channel region 300 , the first doping region 120 and the second doping region 130 constitute a buried transistor.
  • the carriers in the first doped region 120 will move to the first channel region 310 along the second channel region 320 on one side adjacent to the gate trench 110, and then move to the second doped region 130 through the second channel region 320 on the other side adjacent to the gate trench 110 to realize the opening of the buried transistor.
  • the mobility of the carriers in the first channel region 310 is reduced, so that the carrier mobility in the first channel region is smaller than the carrier mobility in the second channel region, thereby achieving the difference between the control ability of the gate structure 200 over the first channel region 310 and the control ability of the gate structure 200 over the second channel region 320, thereby improving the performance of the semiconductor structure.

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Abstract

一种半导体结构及其制备方法。该半导体结构包括基底（100）、栅极结构（200）和沟道区（300），基底（100）包括栅极沟槽（110）。沟道区（300）包括第一沟道区（310）和第二沟道区（320），第一沟道区（310）包裹栅极沟槽（110）的底部，第二沟道区（320）包裹第一沟道区（310）以及未被第一沟道区（310）包裹的栅极沟槽（110）的侧壁；第一沟道区（310）中载流子迁移率小于第二沟道区（320）中载流子迁移率。栅极结构（200）设置在栅极沟槽（110）内。

Description

半导体结构及其制备方法
本公开要求于2022年10月28日提交中国专利局、申请号为202211332587.7、申请名称为“半导体结构及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开实施例涉及半导体技术领域，尤其涉及一种半导体结构及其制备方法。
背景技术
金属氧化物半导体(Metal oxide semiconductor，简称MOS)晶体管是集成电路制造中的重要元件，通常将MOS晶体管形成在衬底上，MOS晶体管包括栅极，在栅极的两侧衬底中形成源极区和漏极区，通过在栅极上施加电压以控制流经源极区和漏极区之间的电流，进而控制MOS晶体管的通断。
但是，栅极对沟道的不同区域的控制能力不同，影响半导体结构的性能。
发明内容
本公开实施例的第一方面提供一种半导体结构，其包括：
基底，所述基底包括栅极沟槽；
栅极结构，所述栅极结构设置在所述栅极沟槽内；
位于所述基底内的沟道区，所述沟道区包括第一沟道区和第二沟道区，所述第一沟道区包裹所述栅极沟槽的底部，所述第二沟道区包裹所述第一沟道区以及未被所述第一沟道区包裹的所述栅极沟槽的侧壁；所述第一沟道区中载流子迁移率小于所述第二沟道区中的载流子迁移率。
本公开实施例的第二方面提供一种半导体结构的制备方法，该制备方 法用于制备上述第一方面所述的半导体结构，其包括如下步骤：
提供基底，所述基底包括栅极沟槽和阱区，所述阱区包裹所述栅极沟槽外部；
在所述阱区内形成第一沟道区，所述第一沟道区包裹所述栅极沟槽的底部，其中，与所述第一沟道区以及未被所述第一沟道区包裹的所述栅极沟槽侧壁相邻的所述阱区构成第二沟道区；所述第一沟道区中载流子迁移率小于所述第二沟道区中的载流子迁移率；
在所述栅极沟槽内形成栅极结构。
本公开实施例所提供的半导体结构及其制备方法中，第一沟道区位于第二沟道区的上方，且第一沟道区包裹栅极沟槽的底部，通过使第一沟道区中载流子迁移率小于第二沟道区中载流子迁移率，可以降低栅极结构对第一沟道区的开启或者关闭的灵敏度，进而均衡栅极结构对第一沟道区和第二沟道区的控制灵敏度差异，提高了半导体结构的性能。
附图说明
图1为本公开实施例提供的半导体结构的结构示意图；
图2为本公开实施例提供的半导体结构的制备方法的工艺流程图；
图3为本公开实施例提供的半导体结构的制备方法中形成掺杂层的示意图；
图4为本公开实施例提供的半导体结构的制备方法中形成栅极沟槽的示意图；
图5为本公开实施例提供的半导体结构的制备方法中形成第一沟道区的示意图；
图6为本公开实施例提供的半导体结构的制备方法中形成栅介质层的示意图；
图7为本公开实施例提供的半导体结构的制备方法中形成阻挡材料层的示意图；
图8为本公开实施例提供的半导体结构的制备方法中形成阻挡层的示意图；
图9为本公开实施例提供的半导体结构的制备方法中形成导电材料层的示意图。
附图标记：
100：基底；110：栅极沟槽；120：第一掺杂区；130：第二掺杂区；140：掺杂层；
200：栅极结构；210：阻挡层；211：阻挡材料层；220：导电层；221：导电材料层；
300：沟道区；310：第一沟道区；320：第二沟道区；311：第一边缘；312：第二边缘；313：第一交点；314：第二交点；
400：栅介质层；
500：掩膜层。
具体实施方式
正如背景技术所述，相关技术的半导体结构中有栅极结构对沟道区的不同区域的控制灵敏度存在差异问题，经发明人研究发现，出现这种问题的原因在于，受沉积工艺的影响形成在栅极沟槽内壁上的栅介质层的厚度具有较大台阶覆盖率，即位于栅极沟槽的顶部的栅介质层的厚度，大于位于栅极沟槽的底部的栅介质层的厚度，导致栅极结构对位于栅极沟槽底部的沟道区的控制能力，大于栅极结构对位于栅极沟槽顶部的沟道区的控制能力，致使在给栅极结构施加一定电压时，位于栅极沟槽底部的沟道区更容易被打开或者关闭，进而使得位于栅极沟槽底部的沟道区和位于栅极沟槽顶部的沟道区的打开或者关闭程度不同，造成关闭或者打开较晚的沟道区存在漏电，降低半导体结构的性能。
而相关技术中，为了均衡栅极结构对位于栅极沟槽底部的沟道区的控制能力，与栅极结构对位于栅极沟槽顶部的沟道区的控制能力，通常会降低栅介质层靠近栅极沟槽顶部的厚度，提高栅极结构对位于栅极沟槽顶部的沟道区的控制能力。但是上述对造成靠近栅极沟槽顶部的栅介质层被击穿，使得栅极结构漏电更加严重，降低半导体结构的性能。
有鉴于此，本公开实施例提供了一种半导体结构及其制备方法，通过使第一沟道区位于第二沟道区的上方，且第一沟道区包裹栅极沟槽的底部，并使第一沟道区中载流子迁移率小于第二沟道区中载流子迁移率，可以降低栅极结构对第一沟道区的开启或者关闭的灵敏度，进而均衡栅极结构对 第一沟道区和第二沟道区的控制灵敏度差异，提高了半导体结构的性能。
为了使本公开实施例的上述目的、特征和优点能够更加明显易懂，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本公开的一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其它实施例，均属于本公开保护的范围。
本实施例对半导体结构不作限制，下面将以半导体结构为动态随机存储器(DRAM)为例进行介绍，但本实施例并不以此为限，本实施例中的半导体结构还可以为其他的结构。
实施例一
请参考附图1，本公开实施例提供一种半导体结构，其包括基底100、栅极结构200和沟道区300。
基底100为栅极结构200、沟道区300或者其他半导体器件的承载主体。基底100可以为硅(Si)基底、锗(Ge)基底、硅锗(GeSi)基底、碳化硅(SiC)基底、绝缘体上硅(Silicon on Insulator，简称SOI)基底或者绝缘体上锗(Germanium on Insulator，简称GOI)基底等。
需要说明的是，基底100内具有多个有源区。其中，栅极结构200和沟道区300均位于有源区内。多个有源区之间可以设置浅槽隔离(Shallow Trench Isolation，简称STI)结构，通过浅沟槽隔离结构将多个有源区之间隔开来，以保证各有源区之间彼此独立。
示例性的，通过图案化制作工艺在基底内形成浅沟槽，并在浅沟槽内填充绝缘材料，从而在基底上定义出多个由浅沟槽隔离结构分离的有源区。其中，图案化制作工艺可以为自对准双图形(Self-Aligned Double Patterning，简称SADP)工艺或者自对准四重图形(Self-Aligned Quadruple Patterning，简称SAQP)工艺。其中，绝缘材料可以包括氧化硅，但不仅限于此。
基底100包括栅极沟槽110，栅极沟槽110的深度方向与垂直于基底100的方向相互平行，且栅极沟槽110的底部位于基底100内。需要说明的是，以垂直于基底100的截面为纵截面，栅极沟槽110的纵截面形状可以为矩形也可以圆锥形。
沟道区300位于基底100内，沟道区300包括第一沟道区310和第二沟道区320，第一沟道区310包裹栅极沟槽110的底部。需要说明的是，栅极沟槽110的底部可以理解为栅极沟槽110的底壁和栅极沟槽110的部分侧壁。
第二沟道区320包裹第一沟道区310的外表面以及未被第一沟道区310包裹的栅极沟槽110的侧壁；第一沟道区310中载流子迁移率小于第二沟道区320中载流子迁移率。
栅极结构200设置在栅极沟槽110内，用于控制第一沟道区310和第二沟道区320的打开或者关闭。当给栅极结构200施加一定电压时，位于沟道区300中载流子(例如空穴或者电子)，会近似沿着栅极沟槽110内壁延伸方向移动，即，近似沿着栅极沟槽110的内壁一端指向另一端的方向移动，以实现栅极结构200对沟道区300的打开。
为了方便对载流子的移动方向进行明确，不妨假设沟道区300中载流子沿着附图1中所示的箭头方向移动。
本公开实施例通过改变第一沟道区310中载流子迁移率和第二沟道区320中载流子迁移率的差异，使得第一沟道区310中载流子迁移率小于第二沟道区320中载流子迁移率，可以降低栅极结构200对第一沟道区310的开启或者关闭的灵敏度，进而均衡栅极结构200对第一沟道区310和第二沟道区320的控制灵敏度差异，提高了半导体结构的性能。
在一种可能的实施方式中，第一沟道区310包括第一掺杂离子和第二掺杂离子，第二沟道区320包括第二掺杂离子，第一掺杂离子的类型和第二掺杂离子的类型不同。
本实施例中，第一沟道区310包括第一掺杂离子和第二掺杂离子，第二沟道区320包括第二掺杂离子。第二掺杂离子为第一沟道区310和第二沟道区320原本存在的掺杂离子，通过对第一沟道区310进行反型处理，使得第一沟道区310具有第一掺杂离子，第一掺杂离子的类型与第二掺杂离子的类型不同。鉴于掺杂离子的类型不同，所形成载流子的形式也不同。例如，第一掺杂离子的类型为N型，第二掺杂离子的类型为P型，当给栅极结构200施加一定电压时，该电压会激发第一掺杂离子诱导出电子，激发第二掺杂离子诱导出空穴，电子会与部分的空穴结合，消耗部分的空穴，从而降低第一沟道区310中载流子的浓度，进而使得第一沟道区310中载 流子迁移率小于第二沟道区320中载流子迁移率，以降低栅极结构200对第一沟道区310的开启或者关闭的灵敏度，达到均衡栅极结构200对第一沟道区310和第二沟道区320的控制灵敏度差异，提高半导体结构的性能的目的。
需要说明的是，第一掺杂离子的类型和第二掺杂离子的类型并不仅限于上述的描述，例如，第一掺杂离子的类型为P型，第二掺杂离子的类型为N型，N型第二掺杂离子作为第一沟道区310和第二沟道区320原本的掺杂离子。如此，当给栅极结构200施加一定电压时，该电压会激发第二掺杂离子诱导出电子，激发第一掺杂离子诱导出空穴，空穴会与部分电子的结合，消耗部分的电子，从而降低第一沟道区310中载流子的浓度。
在一种可能的实施方式中，与栅极沟槽110的底壁所对应的第一沟道区310中的第一掺杂离子的浓度，大于与栅极沟槽110的侧壁所对应的第一沟道区310中的第一掺杂离子的浓度。
需要说明的是，栅极沟槽110的内壁与栅极结构200之间还设置有栅介质层400，其中，栅介质层400的顶面高于栅极结构200的顶面，并与基底100的顶面平齐。
栅介质层400具有高介电常数，例如，栅介质层400的材质包括二氧化硅(SiO2)、氮化硅(Si3N4)、三氧化二铝(Al2O23)、五氧化二钽(Ta2O5)、氧化钇(Y2O3)、硅酸铪氧化合物(HfSi4)、二氧化铪(HfO2)、氧化镧(La2O3)、二氧化锆(ZrO2)、钛酸锶(SrTiO3)、硅酸锆氧化合物(ZrSiO4)中的一种或者多种。如此，可以降低栅极结构200与第一掺杂区120之间，或者，栅极结构200与第二掺杂区130之间泄露电流，提高了半导体结构的性能。
栅介质层400的厚度并非均匀，例如，位于栅极沟槽110底壁的栅介质层400的厚度小于位于栅极沟槽110侧壁的栅介质层400的厚度，如此，会缩短栅极结构200与栅极沟槽110底壁对应的沟道区之间距离，进而会增大栅极结构200对与栅极沟槽110底壁对应的沟道区控制灵敏度。
此外，当给栅极结构200施加电压时，栅极结构200在栅极沟槽110底壁处所产生电场，高于栅极结构200在栅极沟槽110的侧壁处所产生电场，如此，也会增大栅极结构200对栅极沟槽110顶部的沟道区的控制能力，与栅极结构200对栅极沟槽110底部的沟道区的控制能力的差异性。
本实施例通过使与栅极沟槽110的底壁所对应的第一沟道区310中的 第一掺杂离子的浓度，大于与栅极沟槽110的侧壁所对应的第一沟道区310中的第一掺杂离子的浓度，如此，在后续给栅极结构施加电压的过程，能够消耗更多第二掺杂离子所形成的空穴或者电子，降低第一沟道区310中载流子的迁移率，以降低栅极结构200对第一沟道区310的开启或者关闭的灵敏度，达到均衡栅极结构200对第一沟道区310和第二沟道区320的控制灵敏度差异，提高半导体结构的性能的目的。
在一种可能的实施方式中，从栅极沟槽110的侧壁指向栅极沟槽110的底壁的方向，与栅极沟槽110的侧壁所对应的第一沟道区310中的第一掺杂离子的浓度逐渐增加。
沿附图1中的第一交点313与栅极沟槽110的底壁的方向，与栅极沟槽110的侧壁所对应的第一沟道区310中的第一掺杂离子的浓度逐渐增加。如此设置，可以保证与栅极沟槽110的底壁所对应的第一沟道区310中的第一掺杂离子的浓度最高，尽可能均衡栅极结构对第一沟道区310各个区域的控制能力，提高了半导体结构的性能。
在一种可能的实施方式中，第一沟道区310包括第一边缘311和第二边缘312，第一边缘311为栅极沟槽110的底壁和与底壁连接的部分侧壁，第二边缘312位于第一边缘311背离栅极结构200的一侧，且第一边缘311与第二边缘312的两端分别相交，以使得第一沟道区310形成类似于月牙的形状。第一边缘311也可以作为第二沟道区320的部分边缘。
第一边缘311与第二边缘312的其中一个交点指向另外一个交点的方向，以附图1所示的方位，不妨将位于栅极沟槽110左侧的交点记为第一交点313，将位于栅极沟槽110右侧的交点记为第二交点314，从第一交点313指向第二交点314，且沿第一边缘311的延伸方向，即附图1中虚线箭头方向，第一边缘311和第二边缘312之间的距离呈先增加后减小的趋势，即，越靠近栅极沟槽110的底壁的区域，第一边缘311和第二边缘312之间的间距越大。如此，可以增大栅极结构200与第二边缘312的距离，可以增大栅极结构200与载流子迁移率较大的第二沟道区320的距离，进而降低栅极结构200对第一沟道区310临近第二边缘312区域的开启或者关闭的灵敏度，达到均衡栅极结构200对第一沟道区310和第二沟道区320的控制灵敏度差异，提高半导体结构的性能的目的。
在一种可能的实施方式中，第一沟道区310与栅极沟槽110的底壁对 应的第一边缘311与第二边缘312之间的距离，大于第一沟道区310与栅极沟槽110的侧壁对应的第一边缘311与第二边缘312之间的距离。
也就是说，第一沟道区310与栅极沟槽110的底壁对应的第一边缘311与第二边缘312之间的距离为最大值，如此，可以最大程度地减缓栅极结构200对与栅极沟槽110的底壁对应的第一沟道区310的控制能力，进而达到均衡栅极结构200对第一沟道区310和第二沟道区320的控制灵敏度差异，提高半导体结构的性能的目的。
在一种可能的实施方式中，第一边缘311与第二边缘312的两个交点平齐，即第一交点313和第二交点314平齐，第一交点313与第二交点314的连线与基底100相互平行。
交点与基底100的顶面的距离，占栅极沟槽110深度的四分之三到五分之四。如此设置，既能够均衡栅极结构200对第一沟道区310和第二沟道区320的控制灵敏度差异，提高半导体结构的性能的目的，也能避免过渡降低栅极结构200对整个沟道区300的控制能力。
在一种可能的实施方式中，基底100内还包括掺杂有第三掺杂离子的第一掺杂区120和第二掺杂区130；第一掺杂区120和第二掺杂区130分别位于栅极沟槽110的两侧，且位于沟道区300上方。第三掺杂离子的类型与第一掺杂离子的类型相同。
第一掺杂区120和第二掺杂区130中之一作为源极区，第一掺杂区120和第二掺杂区130中另外一个作为漏极区。源极区可以用于与后续的位线结构连接，漏极区用于与后续形成的电容结构连接。通过位线结构实现将存储数据写入电容结构，或者将位于电容结构中的数据读出。
栅极结构200包括阻挡层210和导电层220，阻挡层210设置在栅介质层400上，且阻挡层210的顶面低于栅介质层400。其中，阻挡层210的材质包括氮化钛，氮化钛在阻止导电层220中导电材料与基底100之间发生渗透的同时，也同时具备导电性，保证了半导体结构的性能。
导电层220设置在阻挡层210上，且导电层220的顶面高于阻挡层210且低于栅极沟槽110的顶面，且导电层220的顶面为弧形面。如此设置，使得导电层220的顶部与第一掺杂区120之间，以及导电层220的顶部与第二掺杂区130之间均具有间距，降低栅极结构200与第一掺杂区120和/或第二掺杂区130交界区域的电场，降低了栅极诱导漏极泄露电流。
实施例二
请参考附图2，本公开实施例提供的一种半导体结构的制备方法，该制备方法用于制备实施例一中的半导体结构，其包括如下的步骤：
步骤S100：提供基底，基底包括栅极沟槽和阱区，阱区包裹栅极沟槽外部。
在本实施例中，可以提供衬底，利用离子注入工艺对衬底进行离子掺杂，以形成具有阱区的基底100。阱区中具有第二掺杂离子，其中，第二掺杂离子的类型可以为P型离子，以使得阱区为P型阱区。第二掺杂离子的类型可以为N型离子，以使得阱区为N型阱区。
示例性地，当阱区为P型阱区时，即，采用离子注入工艺向衬底注入P型离子(硼B或镓Ga等Ⅲ族元素离子)形成的。当阱区为N型阱区时，即采用离子注入工艺向衬底注入N型离子(磷P或砷As等Ⅴ族元素离子)形成的。
请参考附图3，在此步骤之后，还需要在基底上形成第一掺杂区120和第二掺杂区130。示例性地：在基底100内形成预设厚度的掺杂层140，此掺杂层140采用离子注入工艺形成，其中，掺杂层140具有第三掺杂离子，第三掺杂离子的类型与第二掺杂离子的类型不同。例如，若第二掺杂离子为P型离子，相应地，第三掺杂离子为N型离子。
之后，请参考附图4，图案化基底100，以在基底100内形成栅极沟槽110；其中，保留在栅极沟槽110两侧的掺杂层140分别构成第一掺杂区120和第二掺杂区130。栅极沟槽110的暴露出阱区、第一掺杂区120和第二掺杂区130，即，阱区包裹在栅极沟槽110的外部。
示例性地，可以在掺杂层140上形成具有掩膜开口的掩膜层500，利用刻蚀液或者刻蚀气体，去除暴露在掩膜开口内的掺杂层140和部分厚度的基底100，以形成栅极沟槽110、第一掺杂区120和第二掺杂区130。
在本示例中，第一掺杂区120和第二掺杂区130中之一作为源极区，第一掺杂区120和第二掺杂区130中另外一个作为漏极区。
步骤S200：在阱区内形成第一沟道区，第一沟道区包裹栅极沟槽的底部，其中，与第一沟道区以及未被第一沟道区包裹的栅极沟槽侧壁相邻的阱区构成第二沟道区；第一沟道区中载流子迁移率小于第二沟道区中的载 流子迁移率。
请参考附图5，示例性地，采用等离子体注入技术向栅极沟槽110底部注入第一掺杂离子，以在阱区内形成第一沟道区310；第一掺杂离子的类型与第二掺杂离子的类型不同。其中，栅极沟槽110的底部包括栅极沟槽110的底壁和栅极沟槽110的部分侧壁。
以下以第一掺杂离子为N型离子，第二掺杂离子为P型离子，对第一沟道区310和第二沟道区320的形成过程进行描述。
采用等离子体注入技术向栅极沟槽110底部注入N型离子，N型离子掺杂至阱区靠近栅极沟槽110底部的区域，使得阱区靠近栅极沟槽110底部的区域既具有N型离子，也具有P型离子，以形成第一沟道区310。当给后续所形成栅极结构200施加一定电压时，该电压会激发第一掺杂离子诱导出电子，激发第二掺杂离子诱导出空穴，电子会与部分的空穴结合，消耗部分的空穴，从而降低第一沟道区310中载流子的浓度，进而使得第一沟道区310中载流子迁移率小于第二沟道区320中载流子迁移率。
在本实施例中，等离子体注入技术中的离子注入方向垂直于基底，降低甚至避免向栅极沟槽110靠近基底100顶面的侧壁被注入第一掺杂离子的几率，进而防止降低第二沟道区320中载流子迁移率，提高了半导体结构的性能。
请参考附图6，在阱区内形成第一沟道区310的步骤之后，半导体结构的制备方法还包括：在栅极沟槽110的内壁上形成栅介质层400，栅介质层400具有高介电常数。如此，可以降低第一掺杂区120和第二掺杂区130与后续形成的栅极结构200之间泄露电流，提高了半导体结构的性能。
其中，栅介质层400的形成工艺可以为原子层沉积工艺，也可以原位生成工艺。
步骤S300：在栅极沟槽内形成栅极结构。
步骤S310：形成阻挡层，阻挡层设置在栅介质层上，且阻挡层的顶面低于栅介质层的顶面。
请参考附图7，示例性地，采用原子层沉积工艺在栅介质层400上形成阻挡材料层211，阻挡材料层211延伸至栅极沟槽110的外部，并覆盖第一掺杂区120和第二掺杂区130上。
请参考附图8，之后，回刻蚀阻挡材料层211，即，去除位于第一掺杂 区120和第二掺杂区130上的阻挡材料层211，以及位于栅极沟槽110内部分的阻挡材料层211，以使得保留着在栅极沟槽110内的阻挡材料层构成阻挡层210，且阻挡层210的顶面低于栅介质层400的顶面。
步骤S320：形成导电层，导电层填充满阻挡层围成的区域，导电层的顶面高于阻挡层的顶面，导电层的顶面低于栅极沟槽的顶面，且导电层的顶面为弧形面。
请参考附图9，示例性地，通过化学气相沉积(Chemical Vapor Deposition，简称CVD)和物理气相沉积(Physical Vapor Deposition，简称PVD)工艺在栅极沟槽110内沉积导电材料层221，导电材料层221填充满栅极沟槽110。
回刻蚀导电材料层221，即，去除位于栅极沟槽110内的部分导电材料层221，保留下来的导电材料层221构成导电层220。阻挡层210和导电层220构成栅极结构200。其结构请继续参考附图1。
导电层220填充满阻挡层210围成的区域，导电层220的顶面高于阻挡层210的顶面，导电层220的顶面低于栅极沟槽110的顶面，且导电层220的顶面为弧形面，即，导电层220的顶面为两边低中间高的结构。如此设置，使得导电层220的顶部与第一掺杂区120之间，以及导电层220的顶部与第二掺杂区130之间均具有间距，降低栅极结构200与第一掺杂区120和/或第二掺杂区130交界区域的电场，降低了栅极诱导漏极泄露电流。
栅极结构200、沟道区300、第一掺杂区120和第二掺杂区130构成埋入式晶体管。
当给栅极结构200施加一定电压时，第一掺杂区120中载流子会沿着临近栅极沟槽110的一侧第二沟道区320移动至第一沟道区310，之后，再通过临近栅极沟槽110的另一侧的第二沟道区320移动至第二掺杂区130，以实现埋入式晶体管的打开。
在上述过程中，由于第一沟道区310中进行反型离子的掺杂，如此，会降低第一沟道区310中的载流子的迁移率，使得第一沟道区中载流子迁移率小于第二沟道区中载流子迁移率，达到了均衡栅极结构200对第一沟道区310的控制能力，和栅极结构200对第二沟道区320的控制能力的差异，提高了半导体结构的性能。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“一个实施方式”、“一些实施方式”、“示意性实施方式”、“示例”、“具体示例”、或“一些示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。

Claims (18)

  1. 一种半导体结构，包括：
    基底(100)，所述基底(100)包括栅极沟槽(110)；
    栅极结构(200)，所述栅极结构(200)设置在所述栅极沟槽(110)内；
    位于所述基底(100)内的沟道区(300)，所述沟道区(300)包括第一沟道区(310)和第二沟道区(320)，所述第一沟道区(310)包裹所述栅极沟槽(110)的底部，所述第二沟道区(320)包裹所述第一沟道区(310)以及未被所述第一沟道区(310)包裹的所述栅极沟槽(110)的侧壁；所述第一沟道区(310)中载流子迁移率小于所述第二沟道区(320)中载流子迁移率。
  2. 根据权利要求1所述的半导体结构，其中，所述第一沟道区(310)包括第一掺杂离子和第二掺杂离子，所述第二沟道区(320)包括所述第二掺杂离子，所述第一掺杂离子的类型和所述第二掺杂离子的类型不同。
  3. 根据权利要求2所述的半导体结构，其中，所述第一掺杂离子的类型为N型，所述第二掺杂离子的类型P型。
  4. 根据权利要求2或3所述的半导体结构，其中，与所述栅极沟槽(110)的底壁所对应的所述第一沟道区(310)中的所述第一掺杂离子的浓度，大于与所述栅极沟槽(110)的侧壁所对应的所述第一沟道区(310)中的所述第一掺杂离子的浓度。
  5. 根据权利要求2-4任一项所述的半导体结构，其中，从所述栅极沟槽(110)的侧壁指向所述栅极沟槽(110)的底壁的方向，与所述栅极沟槽(110)的侧壁所对应的所述第一沟道区(310)中的所述第一掺杂离子的浓度逐渐增加。
  6. 根据权利要求1-5任一项所述的半导体结构，其中，所述第一沟道区(310)包括第一边缘(311)和第二边缘(312)，所述第一边缘(311)为所述栅极沟槽(110)的底壁和与底壁连接的部分侧壁，所述第二边缘(312)位于所述第一边缘(311)背离所述栅极结构(200)的一侧，且所述第一边缘(311)与所述第二边缘(312)的两端分别相交；
    所述第一边缘(311)与所述第二边缘(312)的其中一个交点指向另 外一个交点的方向，所述第一边缘(311)和所述第二边缘(312)之间的距离呈先增加后减小的趋势。
  7. 根据权利要求6所述的半导体结构，其中，所述第一沟道区(310)与所述栅极沟槽(110)的底壁对应的所述第一边缘(311)与所述第二边缘(312)之间的距离，大于所述第一沟道区(310)与所述栅极沟槽(110)的侧壁对应的所述第一边缘(311)与所述第二边缘(312)之间的距离。
  8. 根据权利要求7所述的半导体结构，其中，所述第一边缘(311)与所述第二边缘(312)的两个交点平齐，且所述交点与所述基底(100)的顶面的距离，占所述栅极沟槽(110)深度的四分之三到五分之四。
  9. 根据权利要求2-8任一项所述的半导体结构，其中，所述基底(100)内还包括掺杂有第三掺杂离子的第一掺杂区(120)和第二掺杂区(130)；所述第一掺杂区(120)和所述第二掺杂区(130)分别位于所述栅极沟槽(110)的两侧，且位于所述沟道区(300)上；
    所述第三掺杂离子的类型与所述第一掺杂离子的类型相同。
  10. 根据权利要求1-9任一项所述的半导体结构，其特征在于，以垂直于所述基底(100)的截面为纵截面，所述栅极沟槽(110)的纵截面形状包括矩形或者圆锥形。
  11. 根据权利要求1-9任一项所述的半导体结构，其特征在于，所述基底(100)与栅极结构(200)之间设置有栅介质层(400)。
  12. 根据权利要求11所述的半导体结构，其特征在于，所述栅极结构(200)包括阻挡层(210)和导电层(220)，所述阻挡层(210)设置在所述栅介质层(400)上，且所述阻挡层(210)的顶面低于所述栅介质层(400)；
    所述导电层(220)设置在所述阻挡层(210)上，所述导电层(220)的顶面高于所述阻挡层(210)的顶面，所述导电层(220)的顶面低于所述栅极沟槽(110)的顶面，且所述导电层(220)的顶面为弧形面。
  13. 一种半导体结构的制备方法，所述制备方法用于制备权利要求1-12任一项所述的半导体结构，所述制备方法包括如下步骤：
    提供基底(100)，所述基底(100)包括栅极沟槽(110)和阱区，所述阱区包裹所述栅极沟槽(110)外部；
    在所述阱区内形成第一沟道区(310)，所述第一沟道区(310)包裹 所述栅极沟槽(110)的底部，其中，与所述第一沟道区(310)以及未被所述第一沟道区(310)包裹的所述栅极沟槽(110)侧壁相邻的所述阱区构成第二沟道区(320)；所述第一沟道区(310)中载流子迁移率小于所述第二沟道区(320)中的载流子迁移率；
    在所述栅极沟槽(110)内形成栅极结构(200)。
  14. 根据权利要求13所述的半导体结构的制备方法，其中，所述阱区具有第二掺杂离子；在所述阱区内形成所述第一沟道区的步骤包括：
    采用等离子体注入技术向所述栅极沟槽(110)底部注入第一掺杂离子，以在所述阱区内形成所述第一沟道区(310)；所述第一掺杂离子的类型与所述第二掺杂离子的类型不同。
  15. 根据权利要求14所述的半导体结构的制备方法，其中，所述等离子体注入技术中的离子注入方向垂直于所述基底(100)。
  16. 根据权利要求13-15任一项所述的半导体结构的制备方法，其中，所述阱区具有第二掺杂离子时，提供基底的步骤包括：
    在所述基底(100)内形成预设厚度的掺杂层(140)，所述掺杂层(140)具有第三掺杂离子，所述第三掺杂离子的类型与所述第二掺杂离子的类型不同；
    图案化所述基底(100)，以在所述基底内形成栅极沟槽(110)；其中，保留在所述栅极沟槽(110)两侧的掺杂层(140)分别构成第一掺杂区(120)和第二掺杂区(130)。
  17. 根据权利要求13所述的半导体结构的制备方法，其中，所述方法还包括：在所述阱区内形成所述第一沟道区的步骤之后，在所述栅极沟槽内形成所述栅极结构的步骤之前，
    在所述栅极沟槽(110)的内壁上形成栅介质层(400)，所述栅介质层(400)具有高介电常数。
  18. 根据权利要求14所述的半导体结构的制备方法，其中，在所述栅极沟槽内形成所述栅极结构的步骤包括：
    形成阻挡层(210)，所述阻挡层(210)设置在所述栅介质层(400)上，且所述阻挡层(210)的顶面低于所述栅介质层(400)的顶面；
    形成导电层(220)，所述导电层(220)填充满所述阻挡层(210)围成的区域，所述导电层(220)的顶面高于所述阻挡层(210)的顶面，所 述导电层(220)的顶面低于所述栅极沟槽(110)的顶面，且所述导电层(220)的顶面为弧形面。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6225659B1 (en) * 1998-03-30 2001-05-01 Advanced Micro Devices, Inc. Trenched gate semiconductor device and method for low power applications
CN1663041A (zh) * 2002-06-17 2005-08-31 因芬尼昂技术股份公司 氮化物只读存储器记忆胞元配置制造方法
US20050196923A1 (en) * 2002-09-04 2005-09-08 Joachim Deppe SONOS memory cells and arrays and method of forming the same
CN102468169A (zh) * 2010-11-01 2012-05-23 中芯国际集成电路制造(上海)有限公司 Umos晶体管及其形成方法
CN115224111A (zh) * 2022-07-26 2022-10-21 中芯越州集成电路制造(绍兴)有限公司 沟槽栅器件的制备方法及沟槽栅器件

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6225659B1 (en) * 1998-03-30 2001-05-01 Advanced Micro Devices, Inc. Trenched gate semiconductor device and method for low power applications
CN1663041A (zh) * 2002-06-17 2005-08-31 因芬尼昂技术股份公司 氮化物只读存储器记忆胞元配置制造方法
US20050196923A1 (en) * 2002-09-04 2005-09-08 Joachim Deppe SONOS memory cells and arrays and method of forming the same
CN102468169A (zh) * 2010-11-01 2012-05-23 中芯国际集成电路制造(上海)有限公司 Umos晶体管及其形成方法
CN115224111A (zh) * 2022-07-26 2022-10-21 中芯越州集成电路制造(绍兴)有限公司 沟槽栅器件的制备方法及沟槽栅器件

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