CN115719736A - Chip stacking structure and manufacturing method thereof - Google Patents
Chip stacking structure and manufacturing method thereof Download PDFInfo
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- CN115719736A CN115719736A CN202211525053.6A CN202211525053A CN115719736A CN 115719736 A CN115719736 A CN 115719736A CN 202211525053 A CN202211525053 A CN 202211525053A CN 115719736 A CN115719736 A CN 115719736A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 238000000034 method Methods 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 14
- 238000001465 metallisation Methods 0.000 claims description 11
- 230000007704 transition Effects 0.000 claims description 11
- 238000005520 cutting process Methods 0.000 claims description 10
- 230000017525 heat dissipation Effects 0.000 claims description 6
- 238000004806 packaging method and process Methods 0.000 claims description 6
- 230000001681 protective effect Effects 0.000 claims description 4
- 238000003466 welding Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 142
- 235000012431 wafers Nutrition 0.000 description 17
- 238000010586 diagram Methods 0.000 description 8
- 229910000679 solder Inorganic materials 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 3
- 239000012790 adhesive layer Substances 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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Abstract
The invention discloses a chip stacking structure and a manufacturing method thereof. The method comprises the following steps: at least two stacks arranged in a stack, wherein the stacks comprise a first chip layer, a second chip layer, and a first circuit reconstruction layer; the first bonding pad of the first chip layer and the second bonding pad of the second chip layer are arranged on one side close to the first circuit reconstruction layer; the first circuit reconfiguration layer includes at least one first connection structure and at least one second connection structure; the first bonding pad is electrically connected with the second bonding pad through the first connecting structure; the second connecting structure is electrically connected with the first bonding pad and/or the second bonding pad; and the surface of at least one side of the first circuit reconstruction layer is exposed with part of the second connection structure for electrically connecting with the outside. The technical scheme provided by the invention reduces the connection quantity of external side interconnection between chips, reduces the wiring difficulty and saves the area of the chip.
Description
Technical Field
The embodiment of the invention relates to the technical field of semiconductors, in particular to a chip stacking structure and a manufacturing method thereof.
Background
In a semiconductor manufacturing process, in order to increase a storage capacity of a product or to embody multi-functions, a product may be manufactured by stacking a plurality of chips within one package structure, which is collectively referred to as a stack packaging process.
The existing multi-chip stacking packaging technology mainly comprises a multi-chip interconnection technology, wherein a side wiring interconnection mode is utilized, welding spots of chips are extended to the edges of the chips, then the chips are integrally stacked, and side interconnection is finally carried out. In this way, the chip needs an extra fan-out area to extend, which wastes chip area, and when the function of the chip is complex, the interconnection between the chips becomes complex, and the wiring difficulty is high.
Disclosure of Invention
The invention provides a chip stacking structure and a manufacturing method thereof, which can reduce the number of external side interconnection connections among chips, reduce the wiring difficulty and save the area of the chips.
In a first aspect, an embodiment of the present invention provides a chip stacking structure, including: at least two stacks arranged in a stack, wherein the stacks comprise a first chip layer, a second chip layer, and a first circuit reconstruction layer;
the first chip layer, the first circuit reconstruction layer and the second chip layer are sequentially stacked; the first bonding pad of the first chip layer and the second bonding pad of the second chip layer are arranged on one side close to the first circuit reconstruction layer;
the first circuit reconfiguration layer includes at least one first connection structure and at least one second connection structure; the second connection structure is arranged in the first circuit reconstruction layer, wherein the first bonding pad is electrically connected with the second bonding pad through the first connection structure; the second connecting structure is electrically connected with the first bonding pad and/or the second bonding pad; and the surface of at least one side of the first circuit reconstruction layer is exposed with part of the second connection structure for electrically connecting with the outside.
Optionally, the first connection structure includes a metallization transition layer and a first connection line; the metallization transition layer is arranged on the surface of the first circuit reconstruction layer far away from the first chip layer; the first connecting line is arranged in the first circuit reconstruction layer, and two ends of the first connecting line are respectively connected with the metallization transition layer and the first bonding pad.
Optionally, the second connection structure includes a fourth pad and a second connection line; the fourth bonding pad and the second connecting line are arranged in the first circuit reconstruction layer, wherein the end face of the fourth bonding pad is exposed on the surface of at least one side of the first circuit reconstruction layer; one end of the second connecting line is electrically connected with the fourth bonding pad, and the other end of the second connecting line is electrically connected with the first bonding pad and/or the second bonding pad.
Optionally, vertical projections of the fourth pads in each of the stacks in the stacking direction coincide.
Optionally, the chip stacking structure further includes a second circuit reconstruction layer and a third connection structure;
the second circuit reconstruction layer is arranged on the surface of the first circuit reconstruction layer, which exposes part of the second connection structure; the second circuit reconstruction layer is used for reconstructing a signal circuit which is electrically connected with the outside through the second connection structure; the third connecting structure is arranged on the surface of the second circuit reconstruction layer far away from the stacked body; and the third connecting structure is used for leading out a connecting welding spot according to the signal line.
Optionally, the chip stacking structure further includes a substrate; the substrate is arranged on the surface of the second circuit reconstruction layer far away from the stacked body; the third connecting structure is disposed on a surface of the substrate away from the stacked body.
Optionally, the chip stacking structure further includes a heat sink; the heat dissipation fins are provided on a first surface and a second surface of the stacked body after the stacked body is stacked, wherein the first surface and the second surface are opposite surfaces in a stacking direction of the stacked body after the stacked body is stacked.
In a second aspect, an embodiment of the present invention provides a method for manufacturing a chip stacking structure, including:
arranging and reconstructing a first packaged chip array to form the first chip layer;
forming the first circuit reconstruction layer on the surface of the first chip layer through a rewiring process;
a second packaging chip which is attached to the surface of the first circuit reconstruction layer and is correspondingly interconnected with the first packaging chip, wherein the first bonding pad is electrically connected with the second bonding pad through the first connecting structure, and the stacked body is formed after a protective material is filled;
forming another stack again on the first surface and/or the second surface of the stack to form a stacked structure; wherein the first surface and the second surface are opposite surfaces in a stacking direction of the stack;
and cutting the stacked structure according to the position of the second connecting structure, and exposing a part of the second connecting structure on the surface of at least one side of the first circuit reconstruction layer for electrically connecting with the outside.
Optionally, when the stacked structure includes a plurality of the stacked bodies, another stacked body is formed again on the first surface and/or the second surface of the stacked body to form a stacked structure, including:
forming a 2 nd of the stacks on a first surface of the stacks and a 3 rd of the stacks on a second surface of the stacks; forming a 4 th said stack on a first surface of a 2 nd said stack; forming a 5 th said stack on a second surface of a 3 rd said stack; … … form 2n +2 of said stacks on a first surface of a 2n of said stacks; forming 2n +3 said stacks on a second surface of 2n +1 said stacks, forming said stacked structure; wherein n is greater than or equal to 1 and is a positive integer.
Optionally, after the cutting the stacked structure according to the position of the second connecting structure, the method further includes:
arranging the surfaces of the stacked body, which are exposed out of the second connecting structures, and reconstructing to form a reconstructed wafer;
and forming a second circuit reconstruction layer on the surface of the reconstruction wafer, and arranging a third connection structure on the surface of the second circuit reconstruction layer.
According to the technical scheme provided by the embodiment of the invention, the bonding pads of the chips in the first chip layer and the second chip layer are oppositely arranged, the chips in the first chip layer and the second chip layer can be mounted face to face by using the first circuit reconstruction layer, the signal interconnection of the first chip layer and the second chip layer is realized, the short-distance wiring of the first chip layer and the second chip layer is realized by using the first circuit reconstruction layer, the chips in the first chip layer and the second chip layer are interconnected in the stacked structure, the connection number of external side edge interconnection among the chips is reduced, and the wiring difficulty is reduced. Signals required to be led out to the outside of the chips in the first chip layer and the second chip layer are led out from the side face of the stacked structure through the second connecting structure, extra fan-out areas are not needed to extend the signals in the first chip layer and the second chip layer, and the area of the chips is saved.
Drawings
Fig. 1 is a schematic structural diagram of a chip stacking structure according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of a stacked body stacking arrangement according to an embodiment of the present invention.
Fig. 3 is a rotated schematic view of the structural diagram shown in fig. 2.
Fig. 4 is a schematic top view of another chip stacking structure according to an embodiment of the invention.
Fig. 5 is a schematic flow chart of a method for manufacturing a chip stack structure according to an embodiment of the present invention.
Fig. 6-10 are schematic structural views illustrating a manufacturing process of a chip stack structure.
Fig. 11 is a schematic structural diagram of another chip stacking structure according to an embodiment of the invention.
Fig. 12 is a flowchart illustrating a method for manufacturing a chip stack structure according to another embodiment of the invention.
Fig. 13 provides a top view of a wafer with a completed stack.
Fig. 14 is a schematic top view of the arrangement structure.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1 is a schematic structural diagram of a chip stacking structure according to an embodiment of the present invention, and fig. 2 is a schematic structural diagram of a stacked body stacking arrangement according to an embodiment of the present invention, and referring to fig. 1 and fig. 2, the chip stacking structure includes: at least two stacks 120, the stacks 120 being stacked to form a stacked structure 110, wherein the stacks 120 comprise a first chip layer 130, a second chip layer 140 and a first circuit reconstruction layer 150;
the first chip layer 130, the first circuit reconstruction layer 150, and the second chip layer 140 are sequentially stacked; the first bonding pads 141 of the first chip layer 130 and the second bonding pads 142 of the second chip layer 140 are disposed at a side close to the first circuit reconstruction layer 150;
the first circuit reconstruction layer 150 includes at least one first connection structure and at least one second connection structure; the second connection structure is disposed within the first circuit reconstruction layer 150, wherein the first pads 141 are electrically connected with the second pads 142 through the first connection structure 151; the second connection structure 152 is electrically connected to the first pad 141 and/or the second pad 142; wherein a portion of the second connection structure 152 is exposed on a surface of at least one side of the first circuit reconstruction layer 150 for making an electrical connection with the outside.
Specifically, the chip stacking structure is formed by stacking and combining at least two stacks 120, wherein an adhesive layer 160 may be disposed between each stack 120, so that the stack 120 is attached to a fixed position, wherein the stack 120 includes, in the stacking direction X, a first chip layer 130, a first circuit reconstruction layer 150, and a second chip layer 140, in order, wherein one or more first packaged chips 131 may be disposed in the first chip layer 130 in the horizontal direction Y according to packaging requirements, for example, in an embodiment of the present invention, one first packaged chip 131 is taken as an example, and the first pads 141 are signal pads of the first packaged chip 131 and are disposed on a surface of the first packaged chip 131. A first circuit reconstruction layer 150 is disposed on the surface of the first packaged chip 131, the first circuit reconstruction layer 150 is a redistribution layer, and a signal of the first pad 141 interconnected with the first packaged chip 131 is led out by using a first connection structure 151, wherein the position where the first connection structure 151 is led out can be adjusted according to the position where the second packaged chip 132 in the second chip layer 140 needs to be electrically connected. The second package chip 132 is attached face to face, and signal interconnection is achieved through the first connection structure 151 and the first package chip 131, wherein the sizes of the first package chip 131 and the second package chip 132 may be different, and after the second package chip 132 is attached, the mechanical structure is protected by using a wafer protection material 220 such as underfill and a plastic package material 210, so that the second chip layer 140 is formed.
According to the functional requirements of the chip, the interconnection signal which needs to be led out from the side of the chip stacking structure can be electrically connected to the outside through the second connection structure 152, wherein one end of the second connection structure 152 leaks out from the side portion of the chip stacking structure, and the leaked portion can be electrically connected to the outside through one or more methods such as solder bonding, rewiring, substrate expansion and the like. In the first circuit reconfiguration layer 150, the other end of the second connection structure 152 is connected to the first package chip 131 and/or the second package chip 132, so as to extract signals from the first package chip 131 and/or the second package chip 132, for example, the first package chip 131 may be connected to the first second connection structure 230, so that the first second connection structure 230 may extract signals from the first package chip 131, and the second package chip 132 may be connected to the second connection structure 240, so that the second connection structure 240 may extract signals from the second package chip 132. For example, signals such as power, ground, and the like of the first packaged chip 131/the second packaged chip 132, and storage and high-speed signal extensions required to be interconnected with the outside can be led out through the second connection structure 152, wherein the same type of signals can be led out to the same position area of the side surface of the chip stack structure through the second connection structure 152, thereby facilitating the overall signal layout.
According to the technical scheme provided by the embodiment of the invention, the bonding pads of the chips in the first chip layer and the second chip layer are oppositely arranged, the chips in the first chip layer and the second chip layer can be mounted face to face by using the first circuit reconstruction layer, the signal interconnection of the first chip layer and the second chip layer is realized, the short-distance wiring of the first chip layer and the second chip layer is realized by using the first circuit reconstruction layer, the chips in the first chip layer and the second chip layer are interconnected in the stacked structure, the connection number of external side edge interconnection among the chips is reduced, and the wiring difficulty is reduced. Signals required to be led out to the outside of the chips in the first chip layer and the second chip layer are led out from the side face of the stacked structure through the second connecting structure, extra fan-out areas are not needed to extend the signals in the first chip layer and the second chip layer, and the area of the chips is saved.
With continued reference to fig. 2, optionally, the first connection structure 151 includes a metallization transition layer 250 and a first connection line 260; the metallization transition layer 250 is disposed on a surface of the first circuit reconstruction layer 150 away from the first chip layer 130; the first connection line 260 is disposed in the first circuit reconstruction layer 150, and both ends of the first connection line 260 are connected to the metallization transition layer 250 and the first pad 141, respectively.
Specifically, one end of the first connection line 260 in the first circuit reconfiguration layer 150 is electrically connected to the first pad 141 of the first packaged chip 131, and the metallization transition layer 250 is disposed on the surface of the first circuit reconfiguration layer 150 and is electrically connected to the second pad 142 of the second packaged chip 132, wherein the metallization transition layer 250 and the first connection line 260 may be formed by a rewiring process, and the contact position of the first pad 141 of the first packaged chip 131 is changed by a wafer-level metal wiring process and a bump process, so that the first pad 141 is electrically extended.
Optionally, the second connection structure 152 includes a fourth pad 270 and a second connection line 280; the fourth pad 270 and the second connection line 280 are both disposed within the first circuit reconstruction layer 150, wherein an end face of the fourth pad 270 is exposed on a surface of at least one side of the first circuit reconstruction layer 150; one end of the second connection line 280 is electrically connected to the fourth pad 270, and the other end of the second connection line 280 is electrically connected to the first pad 141 and/or the second pad 142.
Specifically, a plurality of fourth pads 270 may be disposed in the first circuit reconstruction layer 150, the fourth pads 270 are stacked and distributed at a certain distance in the stacking direction X, and different fourth pads 270 are isolated from each other by a photosensitive insulating material, wherein an end surface of the fourth pad 270 is exposed on a side surface of the first circuit reconstruction layer 150, and an end surface of the fourth pad 270 serves as a connection pad electrically connected to the outside, and is electrically connected to the outside by one or more methods such as direct solder bonding, rewiring, and substrate expansion. One end of the second connection line 280 is electrically connected to the fourth pad 270, and the other end of the second connection line 280 may be correspondingly connected to the first pad 141 of the first packaged chip 131 and/or the second pad 142 of the second packaged chip 132 according to the requirement of connecting the first packaged chip 131 and the second packaged chip 132 to the outside.
Alternatively, the vertical projections of the fourth pads 270 in each stack 120 in the stacking direction coincide.
Specifically, the stacking direction is the stacking direction X, the fourth pads 270 are distributed at intervals in the first reconstruction layer, and the projection positions of the fourth pads are overlapped in the vertical direction, so that the fourth pads can be separated from the adjacent stacking structure in a cutting manner in the manufacturing process, and the side surfaces of the chip stacking structure can obtain exposed portions of the end surfaces of the fourth pads 270 which are regularly arranged, so as to facilitate layout of connection leads of the side surface lead-out portions. Here, the mounting position of the second package chip 132 in the second chip layer 140 should not affect the cutting preparation of the exposed portion of the end surface of the fourth pad 270, for example, the vertical projection of the second package chip 132 in the vertical direction does not overlap with the fourth pad 270, so as to avoid the cutting route of the fourth pad 270.
Fig. 3 is a rotated schematic view of the structure shown in fig. 2, and referring to fig. 3 in conjunction with fig. 2, the chip stacking structure further includes a second circuit reconstruction layer 310 and a third connection structure 320;
the second circuit reconstruction layer 310 is disposed on the surface of the first circuit reconstruction layer 150 where a portion of the second connection structure 152 is exposed; the second circuit reconfiguration layer 310 is used for reconfiguring a signal line of the second connection structure 152 for electrical connection with the outside; the third connection structure 320 is disposed on a surface of the second circuit reconstruction layer 310 away from the stack 120; the third connection structure 320 is used for leading out a connection pad according to a signal line.
Specifically, the second circuit reconstruction layer 310 is disposed on the side surface of the chip stacking structure, the second circuit reconstruction layer 310 is disposed by a rewiring process through photolithography or the like, the exposed signal terminals of the second connection structures 152 are rewired by the second circuit reconstruction layer 310, and finally, the signal arrangement layout is realized, and the third connection structures 320 are led out from the second circuit reconstruction layer 310, for example, the third connection structures 320 may be connection solder balls. Fig. 4 is a schematic top view of a chip stacking structure according to another embodiment of the present invention, wherein the top view is a stacking direction X, and four sides of the chip stacking structure can rewire the exposed signal terminal of the second connection structure 152 and lead out the signal on the four sides of the chip stacking structure.
Optionally, referring to fig. 1, the chip stacking structure further includes a substrate 330; the substrate 330 is disposed on a surface of the second circuit reconstruction layer 310 away from the stack 120; third connection structure 320 is disposed on a surface of substrate 330 remote from stack 120.
Specifically, the second circuit reconfiguration layer 310 is disposed by a rewiring process through photolithography and the like, the exposed signal end of the second connection structure 152 is rewired by the second circuit reconfiguration layer 310, and the signal end is led to the third connection structure 320 through the substrate 330, so that the led-out signal of the chip stack structure is interconnected and conducted with other devices through the substrate 330, and the layout of the third connection structure 320 on the substrate 330 can be further planned and arranged, thereby further improving the scalability of side signal extraction and the flexibility of layout.
Referring to fig. 1, optionally, the chip stacking structure further includes a heat sink 340; the fins 340 are provided on a first surface and a second surface of the stack 120 after the stack is arranged in a stacked state, wherein the first surface and the second surface are opposite surfaces in a stacking direction of the stack 120 after the stack is arranged in a stacked state.
Specifically, in the stacking direction X, the heat dissipation fins 340 are respectively disposed on two surfaces of the chip stacking structure, namely, a first surface and a second surface of the opposite surfaces, and the heat dissipation performance of the chip stacking structure is enhanced by the heat dissipation fins 340 at the two ends.
Fig. 5 is a schematic flowchart of a method for manufacturing a chip stack structure according to an embodiment of the present invention, and fig. 6 to 10 are schematic structural diagrams of a manufacturing process of the chip stack structure, where the flowchart includes:
s110, arranging and reconstructing the first packaged chips 131 in an array to form a first chip layer 130;
specifically, the first package chips 131 are tested normal chips, the first package chips 131 are arranged in an array, and the reconstituted wafer, i.e., the first chip layer 130, is fanned out by using a solidified material such as a plastic package material, so as to form the schematic structure shown in fig. 6.
S120, forming a first circuit reconfiguration layer 150 on the surface of the first chip layer 130 through a rewiring process;
specifically, signals required to be interconnected with other chips in the first pad 141 of the first packaged chip 131 are connected to the first connection structure 151 formed by rewiring, so that the signals of the first pad 141 are led out to the surface of the first circuit reconstruction layer 150, and are conveniently mounted with a second packaged chip in the second chip layer, and the position where the first connection structure 151 is led out can be adjusted according to the position where the second packaged chip in the second chip layer is required to be electrically connected. Wherein signals that need to be interconnected from the side are connected to the second connection structure 152 formed by means of rerouting. According to specific chip connection requirements, in a case that a plurality of second connection structures 152 are required, the plurality of second connection structures 152 may be arranged at intervals, for example, the second connection structures 152 include fourth pads 270 and second connection lines 280, signals required to be interconnected from the side of the chip stacking structure are led to the position of the first fourth pad 270 through the rewired second connection line 280, and then the rewired manner is used to reserve the second fourth pad 270 required to be led out from the upper layer. The thickness of the fourth pad 270 is increased to about 10um through the mode of electroplating many times, and photosensitive insulating layer separation such as PI is passed through to different layers of pads. Since the first packaged chips 131 are arranged in an array, the adjacent first packaged chips 131 can be connected to the same fourth bonding pad 270 in the middle of preparation at the position of the first bonding pad 141 which is required to be laterally led out from the same layer and adjacent first packaged chips 131, so as to form the schematic structure shown in fig. 7.
S130, mounting the second package chip 132 on the surface of the first circuit reconstruction layer 150, and interconnecting the first package chip 131 correspondingly, wherein the first pad 141 is electrically connected to the second pad 142 through the first connection structure 151, and the stacked body 120 is formed after filling the protective material;
specifically, the second package chip 132 corresponding to the interconnection relationship is mounted on the surface of the first circuit reconfiguration layer 150, wherein the sizes of the first package chip 131 and the second package chip 132 may be different, and according to the corresponding interconnection relationship, the signal interconnection between the first package chip 131 and the second package chip 132 is ensured to be completed through the first connection structure 151, and according to the side signal leading-out relationship, the signal of the first package chip 131 is guided to the first fourth pad 270 through the second connection line 280, and the signal of the second package chip 132 is guided to the second fourth pad 270 through the second connection line 280. After the second packaged chip 132 is mounted, the mechanical structure of the second packaged chip is protected by using a wafer protection material such as underfill, and after all mounting is completed, the second packaged chip is packaged into a whole wafer by using a solidified material such as a plastic package material through a wafer plastic package mode, so that the back surfaces of the first packaged chip 131 and the second packaged chip 132 are exposed in a mode of thinning the packaged wafer to achieve a better heat dissipation effect, and finally two layers of interconnected reconstituted wafers, namely the stacked body 120, are formed. Resulting in the schematic structure shown in fig. 8.
S140, forming another stack 120 again on the first surface and/or the second surface of the stack 120 to form a stacked structure; wherein the first surface and the second surface are opposite surfaces in the stacking direction X of the stack 120;
specifically, an adhesive layer for adhesion is coated on the back surface area of the first package chip 131 and/or the second package chip 132 that need to be stacked and mounted, so that a new chip is mounted at a fixed position, and the position cannot be mounted in the area corresponding to the lead-out fourth pad 270, thereby avoiding affecting the subsequent processing. And forming a new layer of chip layer wafer by using a solidified material such as a molding compound in combination with the steps S110 to S130, and correspondingly completing chip surface-to-surface interconnection and mounting by using structures such as interconnection signals, external interconnection signals, a fourth pad 270 and the like through a rewiring process, thereby forming another stacked body 120. Note that the application chips of each stack 120 may be the same or different. Resulting in the schematic structure shown in fig. 9.
S150, cutting the stacked structure according to the position of the second connection structure 152, and exposing a portion of the second connection structure 152 on the surface of at least one side of the first circuit reconstruction layer 150 for electrical connection with the outside.
Specifically, the adjacent stacked structures are cut along the second connection structures 152, and for example, the cut may be made at a center line of the fourth pad 270, so that the side surfaces of the stacked structures may be exposed out of the second connection structures 152 for electrical connection with the outside. Resulting in the schematic structure shown in fig. 10.
Fig. 11 is a schematic structural diagram of another chip stacking structure provided in an embodiment of the present invention, and referring to fig. 11, when the stacking structure includes a plurality of stacks 120, another stack 120 is formed again on the first surface and/or the second surface of the stack 120, and the stacking structure is formed, including:
forming a 2 nd stack 120 on a first surface of stack 120 and a 3 rd stack 120 on a second surface of stack 120; forming a 4 th stack 120 on a first surface of the 2 nd stack 120; forming a 5 th stack 120 on a second surface of the 3 rd stack 120; … … forms 2n +2 stacks 120 on the first surface of 2n stack 120; forming 2n +3 stacks 120 on a second surface of 2n +1 stacks 120, forming a stacked structure; wherein n is greater than or equal to 1 and is a positive integer.
Specifically, with the 1 st stack body 120 as a core, mounting reconstruction stacking is performed for multiple times on the first front surface and the second surface of the stack body, the 2 nd stack body 121 is reconstructed and stacked on the first surface of the 1 st stack body 120, the 3 rd stack body 122 is reconstructed and stacked on the second surface of the 1 st stack body 120, the 4 th stack body 123 is reconstructed and stacked on the first surface of the 2 nd stack body 121, the 5 th stack body 124 is reconstructed and stacked on the second surface of the 3 rd stack body 122, the 6 th stack body 120 is reconstructed and stacked on the first surface of the 4 th stack body 120, the 7 th stack body 120 is reconstructed and stacked on the second surface of the 5 th stack body 120, and so on, the stack bodies 120 are formed in an interlaced manner, and therefore, warping of a stack structure in a stacking process can be avoided.
Fig. 12 is a schematic flow chart of a method for manufacturing a chip stack structure according to another embodiment of the present invention, referring to fig. 12, including:
s210, arranging and reconstructing the first packaging chips 131 in an array to form a first chip layer 130;
s220, forming a first circuit reconfiguration layer 150 on the surface of the first chip layer 130 by a rewiring process;
s230, mounting the second package chip 132 on the surface of the first circuit reconstruction layer 150, and interconnecting the first package chip 131 correspondingly, wherein the first pad 141 is electrically connected to the second pad 142 through the first connection structure 151, and the stacked body 120 is formed after filling the protective material;
s240, forming another stack 120 again on the first surface and/or the second surface of the stack 120 to form a stacked structure; wherein the first surface and the second surface are opposite surfaces in the stacking direction X of the stack 120;
and S250, cutting the stacked structure according to the position of the second connection structure 152, and exposing a portion of the second connection structure 152 on the surface of at least one side of the first circuit reconstruction layer 150 for electrical connection with the outside.
Specifically, fig. 13 provides a schematic top view of a wafer that is completely stacked, i.e., a stacked structure, which is cut along the dotted line according to the position of the second connecting structure 152, so as to be divided into strip-shaped small blocks 600 with different lengths.
S260, arranging the surfaces of the exposed parts of the second connecting structures 152 of the stacked body 120, and reconstructing to form a reconstructed wafer 700;
specifically, the strip-shaped small blocks are turned over, the surface where the second connection structures 152 are visible after cutting is exposed, and arranged according to a preset arrangement rule, for example, fig. 14 is a schematic top view of the arrangement structure, the arrangement structure is arranged in a manner that the middle is long and the edge is short, the recombined strip-shaped small blocks are reconstructed into a reconstituted wafer 700 by using a solidified material such as a molding compound, and the exposed portions of all the second connection structures 152 are thinned to the same plane by using a thinning method.
S270, forming a second circuit reconstruction layer 310 on the surface of the reconstructed wafer, and disposing a third connection structure 320 on the surface of the second circuit reconstruction layer 310.
Specifically, a photosensitive material is spin-coated on the surface of the reconstituted wafer, and the exposed signal metal is re-wired by means of photolithography or the like to form the second circuit reconstituted layer 310, and finally led out onto the third connection structure 320, for example, the third connection structure 320 may be a connection solder ball. The second circuit reconstruction layer 310 and the third connection structure 320 may be provided with the connection substrate 330 to further improve the wiring efficiency, and the second circuit reconstruction layer 310 may be provided on the other surface of the surface where the second connection structure 152 is provided to complete signal extraction on the other surface. And repeating the steps S250, S260 and S270 to finally complete the signal wiring and leading-out of four sides of the stacked structure, so as to form the structure shown in FIG. 1.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A chip stacking structure, comprising: at least two stacks, the stacks being arranged in a stack, wherein the stacks comprise a first chip layer, a second chip layer and a first circuit reconstruction layer;
the first chip layer, the first circuit reconstruction layer and the second chip layer are sequentially stacked; the first bonding pad of the first chip layer and the second bonding pad of the second chip layer are arranged on one side close to the first circuit reconstruction layer;
the first circuit reconfiguration layer includes at least one first connection structure and at least one second connection structure; the second connection structure is arranged in the first circuit reconstruction layer, wherein the first bonding pad is electrically connected with the second bonding pad through the first connection structure; the second connecting structure is electrically connected with the first bonding pad and/or the second bonding pad; and the surface of at least one side of the first circuit reconstruction layer is exposed with part of the second connection structure for electrically connecting with the outside.
2. The chip stack structure of claim 1, wherein the first connection structure comprises a metallization transition layer and a first connection line; the metallization transition layer is arranged on the surface of the first circuit reconstruction layer far away from the first chip layer; the first connecting line is arranged in the first circuit reconstruction layer, and two ends of the first connecting line are respectively connected with the metallization transition layer and the first bonding pad.
3. The chip stack structure according to claim 1, wherein the second connection structure comprises a fourth pad and a second connection line; the fourth bonding pad and the second connecting line are arranged in the first circuit reconstruction layer, wherein the end face of the fourth bonding pad is exposed on the surface of at least one side of the first circuit reconstruction layer; one end of the second connecting line is electrically connected with the fourth bonding pad, and the other end of the second connecting line is electrically connected with the first bonding pad and/or the second bonding pad.
4. The chip stack structure according to claim 3, wherein vertical projections of the fourth pads in each of the stacks in the stacking direction coincide.
5. The chip stack structure according to claim 1, further comprising a second circuit reconstruction layer and a third connection structure;
the second circuit reconstruction layer is arranged on the surface of the first circuit reconstruction layer, which exposes part of the second connection structure; the second circuit reconstruction layer is used for reconstructing a signal circuit which is electrically connected with the outside through the second connection structure; the third connecting structure is arranged on the surface of the second circuit reconstruction layer far away from the stacked body; and the third connecting structure is used for leading out a connecting welding spot according to the signal line.
6. The chip stack structure of claim 5, further comprising a substrate; the substrate is arranged on the surface of the second circuit reconstruction layer far away from the stacked body; the third connecting structure is disposed on a surface of the substrate away from the stacked body.
7. The chip stack structure according to any one of claims 1 to 6, further comprising a heat sink; the heat dissipation fins are provided on a first surface and a second surface of the stacked body after the stacked body is stacked, wherein the first surface and the second surface are opposite surfaces in a stacking direction of the stacked body after the stacked body is stacked.
8. A method for fabricating a chip stack structure according to any one of claims 1 to 7, comprising:
arranging and reconstructing a first packaged chip array to form the first chip layer;
forming the first circuit reconstruction layer on the surface of the first chip layer through a rewiring process;
a second packaging chip which is attached to the surface of the first circuit reconstruction layer and is correspondingly interconnected with the first packaging chip, wherein the first bonding pad is electrically connected with the second bonding pad through the first connecting structure, and the stacked body is formed after a protective material is filled;
forming another stack again on the first surface and/or the second surface of the stack to form a stacked structure; wherein the first surface and the second surface are opposite surfaces in a stacking direction of the stack;
and cutting the stacked structure according to the position of the second connecting structure, and exposing a part of the second connecting structure on the surface of at least one side of the first circuit reconstruction layer for electrically connecting with the outside.
9. The method for manufacturing a chip stacking structure according to claim 8, wherein when the stacking structure comprises a plurality of stacks, another stack is formed again on the first surface and/or the second surface of the stack to form a stacking structure, comprising:
forming a 2 nd of the stacks on a first surface of the stacks and a 3 rd of the stacks on a second surface of the stacks; forming a 4 th said stack on a first surface of a 2 nd said stack; forming a 5 th said stack on a second surface of a 3 rd said stack; … … form 2n +2 said stacks on a first surface of the 2n said stacks; forming 2n +3 said stacks on a second surface of 2n +1 said stacks, forming said stacked structure; wherein n is a positive integer greater than or equal to 1.
10. The method for manufacturing a chip stack structure according to any one of claims 8, further comprising, after the step of cutting the stack structure according to the position of the second connecting structure:
arranging the surfaces of the stacked body, which are exposed out of the second connecting structures, and reconstructing to form a reconstructed wafer;
and forming a second circuit reconstruction layer on the surface of the reconstruction wafer, and arranging a third connection structure on the surface of the second circuit reconstruction layer.
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