WO2024037276A1 - 一种深缓冲层高密度沟槽的igbt器件及其制备方法 - Google Patents

一种深缓冲层高密度沟槽的igbt器件及其制备方法 Download PDF

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Publication number
WO2024037276A1
WO2024037276A1 PCT/CN2023/108471 CN2023108471W WO2024037276A1 WO 2024037276 A1 WO2024037276 A1 WO 2024037276A1 CN 2023108471 W CN2023108471 W CN 2023108471W WO 2024037276 A1 WO2024037276 A1 WO 2024037276A1
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layer
igbt device
density
trench
trenches
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PCT/CN2023/108471
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English (en)
French (fr)
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秦潇峰
石亮
胡玮
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重庆万国半导体科技有限公司
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Publication of WO2024037276A1 publication Critical patent/WO2024037276A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side

Definitions

  • the invention relates to the field of semiconductor device manufacturing, and in particular to an IGBT device with a deep buffer layer and high-density trench and a preparation method thereof.
  • the existing backside electric field cutoff layer of traditional IGBT is often implemented by high-energy ion implantation, and is achieved by thermal annealing or laser annealing.
  • the implantation depth is 2-3um, and through laser annealing, It can achieve a depth range of 3-6um and a concentration range of 1e16-1e17/ cm3 ; when using light ions such as protons and helium, the implantation depth can be between 2-40um, and through thermal annealing, a depth range of 3-40um can be achieved. , and a concentration range of 1e16-1e17/cm 3 .
  • Such high-energy injection machines are costly and have high requirements for annealing. It is necessary to increase the activation rate as much as possible while the activation temperature is low.
  • the wafer Due to the trench depth of 4-7um and the increasing trench density of existing traditional IGBT devices, the wafer is prone to very large warpage during the production process, and after thinning, high-energy implantation and annealing on the backside are performed. , it is prone to uneven stress distribution and wafer breakage, making it difficult to promote the production of IGBTs on larger wafer sizes.
  • the object of the present invention is to provide a method for preparing an IGBT device with a deep buffer layer and high-density trench.
  • a method for preparing an IGBT device with a deep buffer layer and high-density trench including the following steps:
  • the high-density trenches include several cell active trenches, cell pseudo trenches, and dicing track trenches;
  • step A specifically includes the following steps:
  • the first epitaxial layer is a buffer layer
  • the second epitaxial layer is a voltage-resistant layer
  • the polarity of the element doped in the second epitaxial layer is the same as the polarity of the element doped in the first epitaxial layer, so
  • the trivalent elements include boron
  • the pentavalent elements include arsenic and phosphorus.
  • step B specifically includes the following steps:
  • the impurities implanted by the ions include trivalent elements or pentavalent elements.
  • the implanted impurities are thermally activated to obtain the terminal implantation region; the number of ion implantations is one or more times.
  • step C specifically includes the following steps:
  • the hard film is made of silicon dioxide and is produced through low-temperature chemical vapor deposition or high-temperature furnace tube technology;
  • the high-density trenches include a number of cell active trenches, Cell pseudo-grooves and dicing grooves;
  • the body region is produced by performing body region ion implantation on the second epitaxial layer.
  • the ion implanted impurities include trivalent elements or pentavalent elements, and the implanted impurities are thermally activated;
  • the active region is produced by implanting the active region into the second epitaxial layer.
  • the ion implanted impurities include trivalent elements. element or pentavalent element to thermally activate the injected impurities;
  • the cell active groove and the cell pseudo groove are located in the middle, and the scribing grooves are located on both sides of the cell active groove and the cell pseudo groove;
  • the cell pseudo groove includes a cell Cell floating pseudo trench, cell source pseudo trench, cell gate pseudo trench.
  • step D specifically includes the following steps:
  • the contact hole includes a gate contact hole, emitter contact hole, terminal contact hole;
  • step E specifically includes the following steps:
  • An IGBT device with a deep buffer layer and a high-density trench is prepared according to a method for preparing an IGBT device with a deep buffer layer and a high-density trench.
  • the device includes a terminal area, a scribing track area, and an active area, and the dicing track area and the active area are provided with a number of trench structures.
  • the present invention has the following beneficial effects:
  • the IGBT device of the present invention adds the same trench structure as the active area in the dicing lane, which reduces the degree of wafer warpage and enables the production of high-density trench IGBTs on large wafer sizes;
  • the front-side structure of the device according to the present invention can achieve very high trench density, and can adopt different front-side technologies without increasing process costs, including injection enhancement, carrier storage and other technologies, and can be very easy Adjust the capacitance composition ratio of the device of the present invention to meet the needs of different application scenarios;
  • the depth and concentration of the backside buffer layer of the IGBT device according to the present invention can be adjusted very easily. Therefore, the backside injection efficiency and transport coefficient of the IGBT can be adjusted to achieve different turn-off characteristics and meet different application scenarios. needs.
  • Figure 1 is a top view of an IGBT device with a deep buffer layer and high-density trench
  • FIG. 2 is a schematic diagram of the processing of specific step S1 in step A of a method for preparing an IGBT device with a deep buffer layer and high-density trench;
  • FIG. 3 is a schematic diagram of the processing of specific step S2 in step A in a method for preparing an IGBT device with a deep buffer layer and high-density trench;
  • FIG. 4 is a schematic diagram of the processing of specific step S3 in step B in a method for preparing an IGBT device with a deep buffer layer and high-density trench;
  • FIG. 5 is a schematic diagram of the processing of specific step S4 in step B in a method for preparing an IGBT device with a deep buffer layer and high-density trench;
  • FIG. 6 is a schematic diagram of the processing of specific step S5 in step B in a method for preparing an IGBT device with a deep buffer layer and high-density trench;
  • FIG. 7 is a schematic diagram of the processing of specific step S6 in step B in a method for preparing an IGBT device with a deep buffer layer and high-density trench;
  • FIG. 8 is a schematic diagram of the processing of specific step S7 in step C in a method for preparing an IGBT device with a deep buffer layer and high-density trench;
  • FIG. 9 is a schematic diagram of the processing of specific step S8 in step C in a method for preparing an IGBT device with a deep buffer layer and high-density trench;
  • FIG. 10 is a schematic diagram of the processing of specific step S9 in step C in a method for preparing an IGBT device with a deep buffer layer and high-density trench;
  • FIG 11 is a schematic diagram of the processing of specific step S10 in step C in a method for preparing an IGBT device with a deep buffer layer and high-density trench;
  • Figure 12 shows the addition of specific step S11 in step C in a method for preparing an IGBT device with a deep buffer layer and high density trench.
  • Figure 13 is a schematic diagram of the processing of specific step S12 in step C in a method for preparing an IGBT device with a deep buffer layer and high-density trench;
  • Figure 14 is a schematic diagram of the processing of specific step S13 in step C in a method for preparing an IGBT device with a deep buffer layer and high-density trench;
  • Figure 15 is a schematic diagram of the processing of specific step S14 in step C in a method for preparing an IGBT device with a deep buffer layer and high-density trench;
  • Figure 16 is a schematic diagram of the processing of specific step S15 in step C in a method for preparing an IGBT device with a deep buffer layer and high-density trench;
  • FIG 17 is a schematic diagram of the processing of specific step S16 in step C in a method for preparing an IGBT device with a deep buffer layer and high-density trench;
  • Figure 18 is a schematic diagram of the processing of specific step S17 in step C in a method for preparing an IGBT device with a deep buffer layer and high-density trench;
  • Figure 19 is a schematic diagram of the processing of specific step S18 in step C in a method for preparing an IGBT device with a deep buffer layer and high-density trench;
  • Figure 20 is a schematic diagram of the processing of specific step S19 in step D in a method for preparing an IGBT device with a deep buffer layer and high-density trench;
  • Figure 21 is a schematic diagram of the processing of specific step S20 in step D in a method for preparing an IGBT device with a deep buffer layer and high density trench;
  • Figure 22 is a schematic diagram of the processing of specific step S21 in step D in a method for preparing an IGBT device with a deep buffer layer and high-density trench;
  • Figure 23 is a schematic diagram of the processing of specific step S22 in step D in a method for preparing an IGBT device with a deep buffer layer and high density trench;
  • Figure 24 is a schematic diagram of the processing of specific step S23 in step D in a method for preparing an IGBT device with a deep buffer layer and high density trench;
  • Figure 25 is a schematic diagram of the processing of specific step S24 in step E in a method for preparing an IGBT device with a deep buffer layer and high density trench;
  • Figure 26 is a schematic diagram of the processing of specific step S25 in step E in a method for preparing an IGBT device with a deep buffer layer and high density trench;
  • Figure 27 is a schematic diagram of the processing of specific step S26 in step E in a method for preparing an IGBT device with a deep buffer layer and high density trench;
  • Figure 28 shows the addition of specific step S27 in step E in a method for preparing an IGBT device with a deep buffer layer and high density trench.
  • Figure 29 is a schematic cross-sectional view along A-A in Figure 1;
  • Embodiments of the present invention provide a method for preparing an IGBT device with a deep buffer layer and high-density trenches as shown in Figure 1 and Figure 29.
  • the method is used to achieve very high performance on the front structure of the device.
  • the trench density of the present invention allows different front-side technologies to be adopted without increasing process costs, including injection enhancement, carrier storage and other technologies, and the capacitance composition ratio of the device of the present invention can be adjusted very easily to meet the requirements
  • the requirements of different application scenarios reduce the degree of wafer warpage and achieve the production of high-density trench IGBTs on large wafer sizes.
  • the specific steps include the following:
  • Step A Preparation of epitaxial layer.
  • Step B Preparation of front-side terminal structure.
  • Step C Preparation of a front-side high-density trench MOSFET structure.
  • the high-density trenches include a number of cell active trenches, cell pseudo trenches, and dicing track trenches.
  • Step D preparation of circuit link layer and passivation layer 28.
  • Step E Preparation of the backside of the wafer.
  • step A may specifically include:
  • a first epitaxial layer 2 is grown on the upper surface of the semiconductor substrate by vapor deposition as a buffer layer of the device of the present invention.
  • the semiconductor substrate is specifically a silicon substrate 1 , depending on the polarity of the device, you can choose to dope trivalent elements (boron) to prepare P-type devices or pentavalent elements (arsenic, phosphorus) to prepare N-type devices.
  • the thickness and concentration of the first epitaxial layer 2 may vary depending on the depth and concentration of the buffer layer required by the application scenario.
  • Step S2 As shown in FIG. 3, a second epitaxial layer 3 is grown on the first epitaxial layer 2 by vapor deposition as a voltage-resistant layer of the device of the present invention.
  • a second epitaxial layer 3 is grown on the first epitaxial layer 2 by vapor deposition as a voltage-resistant layer of the device of the present invention.
  • the polarity of the doping element is related to the doping of the first epitaxial layer 2
  • the polarity of the complex is the same.
  • the depth and concentration of the second epitaxial layer 3 can be changed according to the requirements of the application scenario.
  • step B may specifically include:
  • Step S3 deposit silicon dioxide on the second epitaxial layer 3 as a thick oxide layer 4 required for the terminal structure.
  • Step S4 as shown in FIG. 5, the first photoresist layer 5 is spin-coated on the thick oxide layer 4, and the circuit pattern on the mask is defined on the first photoresist layer 5 through exposure with a photolithography machine.
  • Step S5 as shown in FIG. 6, use dry or wet etching to transfer the circuit pattern to the thick oxide layer 4, and remove the photoresist.
  • a group of two strip-shaped thick oxide layers 4 are obtained on both sides of the second epitaxial layer 3 .
  • Step S6 ion implantation is performed on the second epitaxial layer 3 region between two groups of strip-shaped thick oxide layers 4, each with a number of two, to produce a terminal region 6 (as shown in Figure 29 ).
  • the impurities implanted by ions include trivalent elements (N-type MOSFET) or pentavalent elements (P-type MOSFET).
  • the implanted impurities are thermally activated to obtain two terminal implantation regions 161.
  • the ion implantation terminal implantation region 161 can be repeated one or more times to achieve different withstand voltage values.
  • step C may specifically include:
  • Step S7 deposit a silicon dioxide film on the second epitaxial layer 3 as a hard film 7 required for trench etching.
  • the hard film 7 can be prepared by low-temperature chemical vapor deposition or high-temperature furnace tube process.
  • Step S8 as shown in Figure 9, the second photoresist layer 8 is spin-coated on the hard film 7, and the pattern of the high-density grooves on the mask corresponding to step S10 is defined in the photolithography machine. on the second photoresist layer 8.
  • Step S9 as shown in Figure 10, after forming a circuit pattern on the second photoresist layer 8, dry etching is used to transfer the circuit pattern to the silicon dioxide hard film 7, and the second photoresist layer 8 is Remove.
  • Step S10 as shown in FIG. 11, after forming a circuit pattern on the hard film 7, dry etching is used to form high-density trenches on the second epitaxial layer 3, and the hard film 7 is removed.
  • this method requires defining three types of grooves at the same time.
  • the high-density grooves include cell active grooves 9, cell pseudo grooves, and dicing channel grooves 11.
  • Cell active grooves 9, The cell pseudo-groove is located in the middle, and the dicing channel grooves 11 are located on both sides.
  • Two cell active trenches 9 are located in the center of the second epitaxial layer 3 and are used for the conduction effect of the actual transistor.
  • cellular pseudo-trench It includes two cell floating pseudo trenches 10 located on both sides of the cell active trench 9, and a cell source pseudo trench located on the side of the cell floating pseudo trench 10 away from the cell active trench 9. 101.
  • a cell gate dummy trench 102 located on the side of the cell floating dummy trench 10 away from the cell source dummy trench 101.
  • the cell dummy trench is selected to be floating, connected to the gate 26, and emits
  • the pole 27 method can improve the withstand voltage, capacitance adjustment, and carrier distribution adjustment during turn-on.
  • Two sets of dicing track trenches 11 are respectively located on both sides of the second epitaxial layer 3. The number of dicing track trenches 11 in each set is two, which is beneficial to reducing the warpage of large-size wafers.
  • trenches of the same density that are parallel or perpendicular to the main chip in the dicing lane area 31 , thereby achieving high-density trenches.
  • the above quantity is not a limitation of the present invention, but is an example of an implementable form, and different quantities can be selected according to specific requirements.
  • Step S11 as shown in FIG. 12, a furnace tube thermal oxidation process is used to grow a sacrificial oxide layer 12 on the side walls of the high-density trench.
  • Step S12 as shown in FIG. 13, the sacrificial oxide layer 12 is removed by wet etching, and then the gate oxide layer 13 is grown using a high-temperature furnace tube thermal oxidation process.
  • Step S13 as shown in FIG. 14, a layer of polysilicon 14 is deposited on the high-density trench and the second epitaxial layer 3 using low-pressure chemical vapor deposition.
  • Step S14 as shown in Figure 15, the third photoresist layer 15 is spin-coated on the polysilicon 14, and the trench pattern on the mask is defined on the third photoresist layer 15 through photolithography machine exposure, as shown in Figure 16
  • dry etching is used to transfer the trench pattern to the polysilicon 14, and then the third photoresist layer 15 is removed.
  • the polysilicon 14 retained by this method can connect the trenches of the gate electrodes 26 together, and can also serve as a field plate structure for the terminal region 6 .
  • Step S15 as shown in FIG. 16, the body region 16 in the middle and the scribe line implantation regions 162 on both sides are produced by ion implanting the body region 16 of the second epitaxial layer 3.
  • the ion implanted impurities include trivalent elements (N-type MOSFET) or pentavalent element (P-type MOSFET), which thermally activates the injected impurities.
  • Step S16 as shown in Figure 17, the fourth photoresist layer 17 is spin-coated on the upper surface of the epitaxial wafer, and the pattern of the active area 18 on the mask is defined on the fourth photoresist layer 17 through exposure with a photolithography machine. Thus, the active area 18 pattern is realized.
  • Step S17 as shown in Figure 18, the active region 18 between the two cell active trenches 9 is produced by implanting the active region 18 into the second epitaxial layer 3.
  • the ion implanted impurities include trivalent elements (P Type MOSFET) or pentavalent element (N-type MOSFET), which thermally activates the injected impurities.
  • Step S18 as shown in Figure 19, a silicon dioxide insulating layer 19 is grown on the upper surface of the epitaxial wafer.
  • step D may specifically include:
  • Step S19 as shown in Figure 20, the fifth photoresist layer 20 is spin-coated on the surface of the silicon dioxide insulating layer 19, and the contact hole pattern on the mask plate is defined on the fifth photoresist layer through exposure with a photolithography machine. 20 on.
  • the contact holes include gate contact holes 21, emitter contact holes 22, and terminal contact holes 23 corresponding to those in FIG. 23.
  • Step S20 as shown in FIG. 21, after the contact hole pattern is realized on the fifth photoresist layer 20, dry etching is used to transfer the pattern to the silicon dioxide insulating layer 19.
  • Step S21 use ion implantation to dope high-concentration impurities into the bottoms of the gate contact holes 21, emitter contact holes 22, and terminal contact holes 23 corresponding to Figure 23, and anneal the impurities to activate them to make contacts.
  • Hole ohmic contact layer 211 use ion implantation to dope high-concentration impurities into the bottoms of the gate contact holes 21, emitter contact holes 22, and terminal contact holes 23 corresponding to Figure 23, and anneal the impurities to activate them to make contacts.
  • Hole ohmic contact layer 211 use ion implantation to dope high-concentration impurities into the bottoms of the gate contact holes 21, emitter contact holes 22, and terminal contact holes 23 corresponding to Figure 23, and anneal the impurities to activate them to make contacts.
  • Hole ohmic contact layer 211 use ion implantation to dope high-concentration impurities into the bottoms of the gate contact holes 21, emitter contact holes 22, and terminal contact holes 23 corresponding to Figure 23, and anneal the im
  • Step S22 as shown in Figure 23, use vapor deposition to deposit titanium metal as a bonding layer, and use rapid thermal annealing to form silicide. Then, tungsten metal is isotropically deposited, and the contact is removed by dry etching. The metal tungsten outside the holes forms tungsten plugs in the gate contact hole 21, the emitter contact hole 22, and the terminal contact hole 23.
  • Step S23 deposit metal 24 by sputtering, and then spin-coat the sixth photoresist layer 25. After exposure, use a dry method or a dry-wet mixed method to form a circuit link layer, and remove the sixth photoresist layer. Resist layer 25. In particular, this method defines the terminal metal field plate 241 and two electrodes, one of which is the gate electrode 26 and the other is the emitter electrode 27.
  • Step S24 deposit the passivation layer 28, and use photolithography and etching processes to open the pad areas of the gate 26 and the emitter 27.
  • step E may specifically include:
  • Step S25 as shown in FIG. 26, the back silicon substrate 1 of the IGBT device is thinned until it is thinned to the range of the first epitaxial layer 2.
  • Step S26 use ion implantation to inject low-energy, low-dose particles into the back of the IGBT device, including trivalent elements (N-type IGBT) or pentavalent elements (P-type IGBT), with an energy range of 10- 40k, the dose range is 1e12-1e13/cm 2 , and the implanted impurities are activated to form the collector 29 .
  • N-type IGBT trivalent elements
  • P-type IGBT pentavalent elements
  • Step S27 as shown in FIG. 28, the back side of the IGBT device is alloyed by evaporation or sputtering, and annealed to achieve ohmic contact to form the back metal 30.
  • the embodiment of the present invention also proposes an IGBT device with a deep buffer layer and high-density trench, as shown in Figure 1 and Figure 29, including a terminal area 6, a scribing track area 31, and an active area 32.
  • the scribing track area of the IGBT device 31 and the active area 32 are provided with a high-density trench structure.
  • the high-density trenches include several cell active trenches, cell pseudo trenches, and dicing track trenches.
  • the terminal area 6 can be repeated for different times according to different voltage levels; the scribing track area 31 can be repeated for different times according to different widths; the active area 32 can be repeated for different times according to different current specifications.
  • the area of the 12-inch wafer is 2.25 times that of the 8-inch wafer and 4 times that of the 6-inch wafer. Therefore, under the same production efficiency, the chip output rate of the larger wafer is doubled.
  • the present invention It can alleviate the warpage problem when producing IGBT devices on large-size wafers, and the depth and concentration of the buffer layer can be easily adjusted.
  • the invention can fully meet the requirements for trench density, trench type, and buffer layer in different application scenarios, and improve the output rate of IGBT chips.

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Abstract

本发明公开了一种深缓冲层高密度沟槽的IGBT器件及其制备方法，涉及半导体器件制造领域，包括如下步骤：A、外延层的制备；B、正面终端结构的制备；C、正面高密度沟槽MOSFET结构的制备；所述高密度沟槽包括若干元胞活性沟槽、元胞伪沟槽、划片道沟槽；D、电路链接层和钝化层的制备；E、晶圆背面的制备。本发明有利于缓解在大尺寸晶圆上生产IGBT器件的翘曲问题，并且缓冲层的深度以及浓度易于调节，可以充分满足应用的需求，并提高IGBT芯片的产出率。

Description

一种深缓冲层高密度沟槽的IGBT器件及其制备方法 技术领域
本发明涉及半导体器件制造领域，具体涉及一种深缓冲层高密度沟槽的IGBT器件及其制备方法。
背景技术
现有的传统IGBT的背面电场截止层，往往采用高能量的离子注入来实现，并通过热退火或激光退火来实现，例如当采用磷或砷时，注入深度在2-3um，通过激光退火，可以实现3-6um的深度范围，以及1e16-1e17/cm3的浓度范围；当采用质子、氦等轻离子时，注入深度可以在2-40um，通过热退火，可以实现3-40um的深度范围，以及1e16-1e17/cm3的浓度范围。这样的高能量注入机台成本较高，且对退火的要求也较高，需要在激活温度较低的情况下，尽可能的提高激活率。
现有的传统IGBT器件由于4-7um的沟槽深度，且沟槽密度不断增加导致晶圆在生产过程中容易产生非常大的翘曲度，并且在减薄后，进行背面高能注入以及退火时，容易发生应力分布不均匀，发生晶圆破碎，导致IGBT在更大的晶圆尺寸上难以推广生产。
发明内容
为解决现有技术中的缺陷，本发明的目的在于提供一种深缓冲层高密度沟槽的IGBT器件的制备方法。
本发明的目的是通过以下技术方案实现的：一种深缓冲层高密度沟槽的IGBT器件的制备方法，包括如下步骤：
A、外延层的制备；
B、正面终端结构的制备；
C、正面高密度沟槽MOSFET结构的制备；所述高密度沟槽包括若干元胞活性沟槽、元胞伪沟槽、划片道沟槽；
D、电路链接层和钝化层的制备；
E、晶圆背面的制备。
进一步地，所述步骤A具体包括如下步骤：
S1、在半导体衬底上表面采用气相沉积的方式生长第一外延层，所述第一外延层掺杂三价元素或五价元素；
S2、在第一外延层上采用气相沉积的方式生长第二外延层，所述第二外延层掺杂三价元素或五价元素。
进一步地，所述第一外延层为缓冲层，第二外延层为耐压层，所述第二外延层掺杂的元素的极性与第一外延层掺杂的元素的极性相同，所述三价元素包括硼，所述五价元素包括砷、磷。
进一步地，所述步骤B正面终端结构的制备具体包括如下步骤：
S3、在第二外延层上沉积二氧化硅得到厚氧化层；
S4、在厚氧化层上进行第一光刻胶层旋涂，通过光刻机曝光将掩膜版上电路图形定义在第一光刻胶层上；
S5、通过干法或湿法刻蚀将电路图形转移到厚氧化层上，并将第一光刻胶层去除；
S6、对第二外延层进行离子注入得到终端区域，离子注入的杂质包括三价元素或五价元素，对注入杂质进行热激活得到终端注入区；所述离子注入次数为一次或多次。
进一步地，所述步骤C具体包括如下步骤：
S7、在第二外延层上表面制作硬膜，所述硬膜的材质为二氧化硅，通过低温化学气相沉积或者高温炉管工艺制得；
S8、在硬膜上进行第二光刻胶层旋涂，通过光刻机曝光将掩模版上高密度的沟槽的图形定义在第二光刻胶层上；
S9、在第二光刻胶层上形成电路图形后，通过干法刻蚀将电路图形转移到二氧化硅的硬膜上，并将第二光刻胶层去除；
S10、在硬膜上形成电路图形后，利用干法刻蚀在第二外延层上形成若干高密度沟槽，并将硬膜去除；所述高密度沟槽包括若干元胞活性沟槽、元胞伪沟槽、划片道沟槽；
S11、通过炉管热氧化工艺，在沟槽的侧壁生长一层牺牲氧化层；
S12、通过湿法刻蚀，将牺牲氧化层去除，然后通过高温炉管热氧化工艺生长栅极氧化层；
S13、通过低压化学气相沉积方式在高密度沟槽和第二外延层上方沉积一层多晶硅；
S14、在多晶硅上进行第三光刻胶层旋涂，通过光刻机曝光将掩模版上沟槽图形定义在第三光刻胶层上，并采用干法刻蚀，将沟槽图形转移到多晶硅上后，去除第三光刻胶层；
S15、通过对第二外延层进行体区离子注入制作得到体区，离子注入的杂质包括三价元素或五价元素，对注入杂质进行热激活；
S16、在外延片上表面进行第四光刻胶层旋涂，通过光刻机曝光将掩膜版上有源区图形定义在第四光刻胶层上，从而实现有源区图形；
S17、通过对第二外延层进行有源区注入制作得到有源区，离子注入的杂质包括三价元 素或五价元素，对注入杂质进行热激活；
S18、在外延片表面生长二氧化硅绝缘层。
进一步地，所述元胞活性沟槽、元胞伪沟槽位于中部，所述划片道沟槽位于元胞活性沟槽、元胞伪沟槽的两侧；所述元胞伪沟槽包括元胞浮空伪沟槽、元胞源极伪沟槽、元胞栅极伪沟槽。
进一步地，所述步骤D具体包括如下步骤：
S19、在二氧化硅绝缘层表面进行第五光刻胶层旋涂，通过光刻机曝光将掩膜板上接触孔图形定义在第五光刻胶层上；所述接触孔包括栅极接触孔、发射极接触孔、终端接触孔；
S20、在第五光刻胶层上实现了栅极接触孔、发射极接触孔、终端接触孔图形后，利用干法刻蚀将图形转移到二氧化硅上；
S21、通过离子注入掺杂高浓度杂质到栅极接触孔、发射极接触孔、终端接触孔的底部，退火激活杂质以制作欧姆接触层；
S22、通过气相沉积的方式，沉积金属钛作为粘结层，并利用快速热退火形成硅化物，随后各向同性的沉积金属钨，并通过干法刻蚀去除掉接触孔以外的金属钨，形成钨栓；
S23、通过溅射的方式沉积金属铝，旋涂第六光刻胶层，曝光后用干法或者干湿混合的方式形成电路链接层，并去除第六光刻胶层；
S24、沉积钝化层，通过光刻工艺和刻蚀工艺将焊盘区域打开。
进一步地，所述步骤E具体包括如下步骤：
S25、对IGBT器件的背面硅衬底进行减薄，直至减薄到第一外延层；
S26、通过离子注入，对IGBT器件的背面注入低能量、低剂量的三价元素或五价元素，能量范围在10-40k，剂量范围在1e12-1e13/cm2激活后形成集电极；
S27、通过蒸发或者溅射的方式，对IGBT器件背面进行合金，并退火后实现欧姆接触，形成背面金属。
一种深缓冲层高密度沟槽的IGBT器件，所述深缓冲层高密度沟槽的IGBT器件根据深缓冲层高密度沟槽的IGBT器件的制备方法制备得到。
进一步地，所述器件包括终端区域、划片道区域、活性区域，所述划片道区域与活性区域设置有若干沟槽结构。
综上所述，与现有技术相比，本发明具有如下的有益效果：
(1)本发明所述的IGBT器件在划片道中加入与活性区相同的沟槽结构，降低了晶圆翘曲的程度，实现了在大晶圆尺寸上进行高密度沟槽IGBT的生产；
(2)本发明所述的器件的正面结构，可以实现非常高的沟槽密度，可以在不增加工艺成本的情况下，采用不同的正面技术，包括注入增强、载流子存储等技术，并且可以非常容易 的调整本发明所述器件的电容组成占比，满足不同应用的场景的需求；
(3)本发明所述的IGBT器件的背面缓冲层的形成，不需要高能量注入以及退火，在进行背面工艺时，降低了这一步工艺带来的碎片风险；
(4)本发明所述的IGBT器件的背面缓冲层深度以及浓度可以非常容易的进行调节，因此IGBT的背面注入效率以及输运系数均可以调节，可以实现不同的关断特性，满足不同应用场景的需求。
附图说明
通过阅读参照以下附图对非限制性实施例所作的详细描述，本发明的其它特征、目的和优点将会变得更明显：
图1为一种深缓冲层高密度沟槽的IGBT器件的俯视图；
图2为一种深缓冲层高密度沟槽的IGBT器件的制备方法中步骤A中具体步骤S1的加工示意图；
图3为一种深缓冲层高密度沟槽的IGBT器件的制备方法中步骤A中具体步骤S2的加工示意图；
图4为一种深缓冲层高密度沟槽的IGBT器件的制备方法中步骤B中具体步骤S3的加工示意图；
图5为一种深缓冲层高密度沟槽的IGBT器件的制备方法中步骤B中具体步骤S4的加工示意图；
图6为一种深缓冲层高密度沟槽的IGBT器件的制备方法中步骤B中具体步骤S5的加工示意图；
图7为一种深缓冲层高密度沟槽的IGBT器件的制备方法中步骤B中具体步骤S6的加工示意图；
图8为一种深缓冲层高密度沟槽的IGBT器件的制备方法中步骤C中具体步骤S7的加工示意图；
图9为一种深缓冲层高密度沟槽的IGBT器件的制备方法中步骤C中具体步骤S8的加工示意图；
图10为一种深缓冲层高密度沟槽的IGBT器件的制备方法中步骤C中具体步骤S9的加工示意图；
图11为一种深缓冲层高密度沟槽的IGBT器件的制备方法中步骤C中具体步骤S10的加工示意图；
图12为一种深缓冲层高密度沟槽的IGBT器件的制备方法中步骤C中具体步骤S11的加 工示意图；
图13为一种深缓冲层高密度沟槽的IGBT器件的制备方法中步骤C中具体步骤S12的加工示意图；
图14为一种深缓冲层高密度沟槽的IGBT器件的制备方法中步骤C中具体步骤S13的加工示意图；
图15为一种深缓冲层高密度沟槽的IGBT器件的制备方法中步骤C中具体步骤S14的加工示意图；
图16为一种深缓冲层高密度沟槽的IGBT器件的制备方法中步骤C中具体步骤S15的加工示意图；
图17为一种深缓冲层高密度沟槽的IGBT器件的制备方法中步骤C中具体步骤S16的加工示意图；
图18为一种深缓冲层高密度沟槽的IGBT器件的制备方法中步骤C中具体步骤S17的加工示意图；
图19为一种深缓冲层高密度沟槽的IGBT器件的制备方法中步骤C中具体步骤S18的加工示意图；
图20为一种深缓冲层高密度沟槽的IGBT器件的制备方法中步骤D中具体步骤S19的加工示意图；
图21为一种深缓冲层高密度沟槽的IGBT器件的制备方法中步骤D中具体步骤S20的加工示意图；
图22为一种深缓冲层高密度沟槽的IGBT器件的制备方法中步骤D中具体步骤S21的加工示意图；
图23为一种深缓冲层高密度沟槽的IGBT器件的制备方法中步骤D中具体步骤S22的加工示意图；
图24为一种深缓冲层高密度沟槽的IGBT器件的制备方法中步骤D中具体步骤S23的加工示意图；
图25为一种深缓冲层高密度沟槽的IGBT器件的制备方法中步骤E中具体步骤S24的加工示意图；
图26为一种深缓冲层高密度沟槽的IGBT器件的制备方法中步骤E中具体步骤S25的加工示意图；
图27为一种深缓冲层高密度沟槽的IGBT器件的制备方法中步骤E中具体步骤S26的加工示意图；
图28为一种深缓冲层高密度沟槽的IGBT器件的制备方法中步骤E中具体步骤S27的加 工示意图；
图29为图1中沿A-A的剖面示意图；
附图标记：
1、硅衬底；2、第一外延层；3、第二外延层；4、厚氧化层；5、第一光刻胶层；6、终端区域；7、硬膜；8、第二光刻胶层；9、元胞活性沟槽；10、元胞浮空伪沟槽；101、元胞源极伪沟槽；102、元胞栅极伪沟槽；11、划片道沟槽；12、牺牲氧化层；13、栅极氧化层；14、多晶硅；15、第三光刻胶层；16、体区；161、终端注入区；162、划片道注入区；17、第四光刻胶层；18、有源区；19、绝缘层；20、第五光刻胶层；21、栅极接触孔；211、欧姆接触层；22、发射极接触孔；23、终端接触孔；24、金属；241、终端金属场版；25、第六光刻胶层；26、栅极；27、发射极；28、钝化层；29、集电极；30、背面金属；31、划片道区域；32、活性区域。
具体实施方式
以下实施例将有助于本领域的技术人员进一步理解本发明，但不以任何形式限制本发明。对本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变化和改进，这些都属于本发明的保护范围。在本文中所披露的范围的端点和任何值都不限于该精确的范围或值，这些范围或值应当理解为包含接近这些范围或值的值。对于数值范围来说，各个范围的端点值之间、各个范围的端点值和单独的点值之间，以及单独的点值之间可以彼此组合而得到一个或多个新的数值范围，这些数值范围应被视为在本文中具体公开，下面结合具体实施例对本发明进行详细说明：
本发明实施例提供了一种如图1、图29所示的深缓冲层高密度沟槽的IGBT器件的制备方法，在一个具体实施例中，该方法用于在器件的正面结构实现非常高的沟槽密度，可以在不增加工艺成本的情况下，采用不同的正面技术，包括注入增强、载流子存储等技术，并且可以非常容易的调整本发明所述器件的电容组成占比，满足不同应用的场景的需求降低晶圆翘曲的程度，实现了在大晶圆尺寸上进行高密度沟槽IGBT的生产，具体包括如下步骤：
步骤A、外延层的制备。
步骤B、正面终端结构的制备。
步骤C、正面高密度沟槽MOSFET结构的制备，高密度沟槽包括若干元胞活性沟槽、元胞伪沟槽、划片道沟槽。
步骤D、电路链接层和钝化层28的制备。
步骤E、晶圆背面的制备。
作为一种具体实施方式，步骤A可具体包括：
步骤S1、如图2所示，在半导体衬底上表面采用气相沉积的方式生长第一外延层2，作为本发明所述器件的缓冲层，本实施例中半导体衬底具体为硅衬底1，根据器件极性的不同，可以选择掺杂三价元素(硼)以制备P型器件或五价元素(砷、磷)以制备N型器件。第一外延层2根据应用场景所需要的缓冲层的深度以及浓度的不同，厚度以及浓度会有变化。
步骤S2、如图3所示，在第一外延层2上采用气相沉积的方式生长第二外延层3，作为本发明所述器件的耐压层。根据器件极性的不同，可以选择掺杂三价元素(硼)以制备P型器件或五价元素(砷、磷)以制备N型器件，掺杂元素的极性与第一外延层2掺杂的极性相同。第二外延层3根据应用场景的需求，深度以及浓度可以变化。
作为一种具体实施方式，步骤B可具体包括：
步骤S3、如图4所示，在第二外延层3上沉积二氧化硅作为终端结构所需要的厚氧化层4。
步骤S4、如图5所示，在厚氧化层4上进行第一光刻胶层5旋涂，通过光刻机曝光将掩膜版上的电路图形定义在第一光刻胶层5上。
步骤S5、如图6所示，利用干法或湿法刻蚀将电路图形转移到厚氧化层4上，并将光刻胶去除。第二外延层3上两侧分别得到一组，每组数量为2个的条状厚氧化层4。
步骤S6、如图7所示，通过分别对两组每组数量为2个的条状厚氧化层4之间的第二外延层3区域进行离子注入制作得到终端区域6(如图29所示)。离子注入的杂质包括三价元素(N型MOSFET)或五价元素(P型MOSFET)，对注入杂质进行热激活得到两个终端注入区161。特别的，离子注入终端注入区161可以重复一次或多次，以实现不同的耐压值。
作为一种具体实施方式，步骤C可具体包括：
步骤S7、如图8所示，在第二外延层3上沉积二氧化硅薄膜作为沟槽刻蚀所需的硬膜7，该硬膜7可由低温化学气相沉积或者高温炉管工艺制备。
步骤S8、如图9所示，在硬膜7上进行第二光刻胶层8旋涂，通过光刻机曝光将掩模版上与步骤S10中相对应的高密度沟槽的图形定义在第二光刻胶层8上。
步骤S9、如图10所示，在第二光刻胶层8上形成电路图形后，利用干法刻蚀将电路图转移到二氧化硅的硬膜7上，并将第二光刻胶层8去除。
步骤S10、如图11所示，在硬膜7上形成电路图形后，利用干法刻蚀在第二外延层3上形成高密度沟槽，并将硬膜7去除。
特别的作为一种具体实施方式，此方法需要同时定义三种沟槽，高密度沟槽包括元胞活性沟槽9、元胞伪沟槽、划片道沟槽11，元胞活性沟槽9、元胞伪沟槽位于中部，划片道沟槽11位于两侧。
两个元胞活性沟槽9位于第二外延层3中央，用于实际晶体管的导通效果。元胞伪沟槽 包括两个分别位于元胞活性沟槽9两侧的元胞浮空伪沟槽10、一个位于元胞浮空伪沟槽10远离元胞活性沟槽9一侧的元胞源极伪沟槽101、一个位于元胞浮空伪沟槽10远离元胞源极伪沟槽101一侧的元胞栅极伪沟槽102，元胞伪沟槽通过选择浮空、连接到栅极26、发射极27的方式，可以实现提高耐压、电容调整、导通时载流子分布调整效果。两组划片道沟槽11分别位于第二外延层3两侧，每组划片道沟槽11的数量为2个，有利于降低大尺寸晶圆的翘曲程度。
如图1所示，在划片道区域31中存在与主芯片相互平行或垂直的同等密度的沟槽，从而实现高密度沟槽。以上数量并非对本发明的限制，而是举例一个可实施的形式，可以根据具体的需求选择不同的数量。
步骤S11、如图12所示，利用炉管热氧化工艺，在高密度沟槽的侧壁生长一层牺牲氧化层12。
步骤S12、如图13所示，通过湿法刻蚀，将牺牲氧化层12去除，然后利用高温炉管热氧化工艺生长栅极氧化层13。
步骤S13、如图14所示，采用低压化学气相沉积方式在高密度沟槽和第二外延层3上方沉积一层多晶硅14。
步骤S14、如图15所示，在多晶硅14上进行第三光刻胶层15旋涂，通过光刻机曝光将掩模版上沟槽图形定义在第三光刻胶层15上如图16所示，并采用干法刻蚀，将沟槽图形转移到多晶硅14上后，去除第三光刻胶层15。特别的，此方法保留的多晶硅14，可以将栅极26沟槽连接在一起，也可以作为终端区域6的场版结构。
步骤S15、如图16所示，通过对第二外延层3进行体区16离子注入制作得到中部的体区16以及两侧的划片道注入区162，离子注入的杂质包括三价元素(N型MOSFET)或五价元素(P型MOSFET)，对注入杂质进行热激活。
步骤S16、如图17所示，在外延片上表面进行第四光刻胶层17旋涂，通过光刻机曝光将掩膜版上有源区18图形定义在第四光刻胶层17上，从而实现有源区18图形。
步骤S17、如图18所示，通过对第二外延层3进行有源区18注入制作得到两个元胞活性沟槽9之间的有源区18，离子注入的杂质包括三价元素(P型MOSFET)或五价元素(N型MOSFET)，对注入杂质进行热激活。
步骤S18、如图19所示，在外延片上表面生长二氧化硅绝缘层19。
作为一种具体实施方式，步骤D可具体包括：
步骤S19、如图20所示，在二氧化硅绝缘层19表面进行第五光刻胶层20旋涂，通过光刻机曝光将掩膜板上的接触孔图形定义在第五光刻胶层20上。接触孔包括与图23中相对应的栅极接触孔21、发射极接触孔22、终端接触孔23。
步骤S20、如图21所示，在第五光刻胶层20上实现了接触孔图形后，利用干法刻蚀将图形转移到二氧化硅绝缘层19上。
步骤S21、如图22所示，利用离子注入掺杂高浓度杂质到与图23中相对应的栅极接触孔21、发射极接触孔22、终端接触孔23的底部，退火激活杂质以制作接触孔的欧姆接触层211。
步骤S22、如图23所示，利用气相沉积的方式，沉积金属钛作为粘结层，并利用快速热退火形成硅化物，随后各向同性的沉积金属钨，并通过干法刻蚀去除掉接触孔以外的金属钨，在栅极接触孔21、发射极接触孔22、终端接触孔23内形成钨栓。
步骤S23、如图24所示，利用溅射的方式沉积金属24，随后旋涂第六光刻胶层25，曝光后用干法或者干湿混合的方式形成电路链接层，并去除第六光刻胶层25。特别的，此方法定义了终端金属场版241，两个电极,其一为栅极26，其二为发射极27。
步骤S24、如图25所示，沉积钝化层28，并用光刻工艺和刻蚀工艺将栅极26、发射极27焊盘区域打开。
作为一种具体实施方式，步骤E可具体包括：
步骤S25、如图26所示，对IGBT器件的背面硅衬底1进行减薄，直至减薄到第一外延层2的范围内。
步骤S26、如图27所示，利用离子注入，对IGBT器件背面注入低能量、低剂量的粒子，包括三价元素(N型IGBT)或五价元素(P型IGBT)，能量范围在10-40k，剂量范围在1e12-1e13/cm2，对注入杂质进行激活形成集电极29。
步骤S27、如图28所示，利用蒸发或者溅射的方式，对IGBT器件背面进行合金，并退火后实现欧姆接触，形成背面金属30。
本发明实施例还提出了一种深缓冲层高密度沟槽的IGBT器件，如图1、图29所示，包括终端区域6、划片道区域31、活性区域32，该IGBT器件的划片道区域31与活性区域32设置有高密度沟槽结构，高密度沟槽包括若干元胞活性沟槽、元胞伪沟槽、划片道沟槽。其中终端区域6可以根据不同的电压等级，进行不同的重复次数；划片道区域31可以根据不同的宽度进行不同的重复次数；活性区域32可以根据不同而电流规格，进行不同的重复次数。
12寸晶圆的面积分别是8寸晶圆的2.25倍，6寸晶圆的4倍面积，因此在相同的生产效率下，更大的晶圆，其芯片产出率成倍增加，本发明可以缓解在大尺寸晶圆上生产IGBT器件时的翘曲问题，并且缓冲层的深度以及浓度易于调节。本发明可以充分满足不同的应用场景对沟槽密度、沟槽类型、缓冲层的要求，并提高IGBT芯片的产出率。
对于本领域技术人员而言，显然本发明不限于上述示范性实施例的细节，而且在不背离 本发明的精神或基本特征的情况下，能够以其他的具体形式实现本发明。因此，无论从哪一点来看，均应将实施例看作是示范性的，而且是非限制性的，本发明的范围由所附权利要求而不是上述说明限定，因此旨在将落在权利要求的等同要件的含义和范围内的所有变化囊括在本发明内。不应将权利要求中的任何附图标记视为限制所涉及的权利要求。
此外，应当理解，虽然本说明书按照实施方式加以描述，但并非每个实施方式仅包含一个独立的技术方案，说明书的这种叙述方式仅仅是为清楚起见，本领域技术人员应当将说明书作为一个整体，各实施例中的技术方案也可以经适当组合，形成本领域技术人员可以理解的其他实施方式。

Claims (10)

  1. 一种深缓冲层高密度沟槽的IGBT器件的制备方法，其特征在于，包括如下步骤：
    A、外延层的制备；
    B、正面终端结构的制备；
    C、正面高密度沟槽MOSFET结构的制备；所述高密度沟槽包括若干元胞活性沟槽(9)、元胞伪沟槽、划片道沟槽(11)；
    D、电路链接层和钝化层(28)的制备；
    E、晶圆背面的制备。
  2. 根据权利要求1所述的深缓冲层高密度沟槽的IGBT器件的制备方法，其特征在于，所述步骤A具体包括如下步骤：
    S1、在半导体衬底上表面采用气相沉积的方式生长第一外延层(2)，所述第一外延层(2)掺杂三价元素或五价元素；
    S2、在第一外延层(2)上采用气相沉积的方式生长第二外延层(3)，所述第二外延层(3)掺杂三价元素或五价元素。
  3. 根据权利要求2所述的深缓冲层高密度沟槽的IGBT器件的制备方法，其特征在于，所述第一外延层(2)为缓冲层，第二外延层(3)为耐压层，所述第二外延层(3)掺杂的元素的极性与第一外延层(2)掺杂的元素的极性相同，所述三价元素包括硼，所述五价元素包括砷、磷。
  4. 根据权利要求1所述的深缓冲层高密度沟槽的IGBT器件的制备方法，其特征在于，所述步骤B正面终端结构的制备具体包括如下步骤：
    S3、在第二外延层(3)上沉积二氧化硅得到厚氧化层(4)；
    S4、在厚氧化层(4)上进行第一光刻胶层(5)旋涂，通过光刻机曝光将掩膜版上电路图形定义在第一光刻胶层(5)上；
    S5、通过干法或湿法刻蚀将电路图形转移到厚氧化层(4)上，并将第一光刻胶层(5)去除；
    S6、对第二外延层(3)进行离子注入得到终端区域(6)，离子注入的杂质包括三价元素或五价元素，对注入杂质进行热激活得到终端注入区(161)；所述离子注入次数为一次或多次。
  5. 根据权利要求4所述的深缓冲层高密度沟槽的IGBT器件的制备方法，其特征在于，所述步骤C具体包括如下步骤：
    S7、在第二外延层(3)上表面制作硬膜(7)，所述硬膜(7)的材质为二氧化硅，通过低温化学气相沉积或者高温炉管工艺制得；
    S8、在硬膜(7)上进行第二光刻胶层(8)旋涂，通过光刻机曝光将掩模版上高密度的沟槽的图形定义在第二光刻胶层(8)上；
    S9、在第二光刻胶层(8)上形成电路图形后，通过干法刻蚀将电路图形转移到二氧化硅 的硬膜(7)上，并将第二光刻胶层(8)去除；
    S10、在硬膜(7)上形成电路图形后，利用干法刻蚀在第二外延层(3)上形成若干高密度沟槽，并将硬膜(7)去除；所述高密度沟槽包括若干元胞活性沟槽(9)、元胞伪沟槽、划片道沟槽(11)；
    S11、通过炉管热氧化工艺，在沟槽的侧壁生长一层牺牲氧化层(12)；
    S12、通过湿法刻蚀，将牺牲氧化层(12)去除，然后通过高温炉管热氧化工艺生长栅极氧化层(13)；
    S13、通过低压化学气相沉积方式在高密度沟槽和第二外延层(3)上方沉积一层多晶硅(14)；
    S14、在多晶硅(14)上进行第三光刻胶层(15)旋涂，通过光刻机曝光将掩模版上沟槽图形定义在第三光刻胶层(15)上，并采用干法刻蚀，将沟槽图形转移到多晶硅(14)上后，去除第三光刻胶层(15)；
    S15、通过对第二外延层(3)进行体区(16)离子注入制作得到体区(16)，离子注入的杂质包括三价元素或五价元素，对注入杂质进行热激活；
    S16、在外延片上表面进行第四光刻胶层(17)旋涂，通过光刻机曝光将掩膜版上有源区(18)图形定义在第四光刻胶层(17)上，从而实现有源区(18)图形；
    S17、通过对第二外延层(3)进行有源区(18)注入制作得到有源区(18)，离子注入的杂质包括三价元素或五价元素，对注入杂质进行热激活；
    S18、在外延片表面生长二氧化硅绝缘层(19)。
  6. 根据权利要求5所述的深缓冲层高密度沟槽的IGBT器件的制备方法，其特征在于，所述元胞活性沟槽(9)、元胞伪沟槽位于中部，所述划片道沟槽(11)位于元胞活性沟槽(9)、元胞伪沟槽的两侧；所述元胞伪沟槽包括元胞浮空伪沟槽(10)、元胞源极伪沟槽(101)、元胞栅极伪沟槽(102)。
  7. 根据权利要求5所述的深缓冲层高密度沟槽的IGBT器件的制备方法，其特征在于，所述步骤D具体包括如下步骤：
    S19、在二氧化硅绝缘层(19)表面进行第五光刻胶层(20)旋涂，通过光刻机曝光将掩膜板上接触孔图形定义在第五光刻胶层(20)上；所述接触孔包括栅极接触孔(21)、发射极接触孔(22)、终端接触孔(23)；
    S20、在第五光刻胶层(20)上实现了栅极接触孔(21)、发射极接触孔(22)、终端接触孔(23)图形后，利用干法刻蚀将图形转移到二氧化硅上；
    S21、通过离子注入掺杂高浓度杂质到栅极接触孔(21)、发射极接触孔(22)、终端接触孔(23)的底部，退火激活杂质以制作欧姆接触层(211)；
    S22、通过气相沉积的方式，沉积金属(24)钛作为粘结层，并利用快速热退火形成硅化物，随后各向同性的沉积金属(24)钨，并通过干法刻蚀去除掉接触孔以外的金属(24)钨，形成钨栓；
    S23、通过溅射的方式沉积金属(24)铝，旋涂第六光刻胶层(25)，曝光后用干法或者干湿混合的方式形成电路链接层，并去除第六光刻胶层(25)；
    S24、沉积钝化层(28)，通过光刻工艺和刻蚀工艺将焊盘区域打开。
  8. 根据权利要求1所述的深缓冲层高密度沟槽的IGBT器件的制备方法，其特征在于，所述步骤E具体包括如下步骤：
    S25、对IGBT器件的背面硅衬底(1)进行减薄，直至减薄到第一外延层(2)；
    S26、通过离子注入，对IGBT器件的背面注入低能量、低剂量的三价元素或五价元素，能量范围在10-40k，剂量范围在1e12-1e13/cm2激活后形成集电极(29)；
    S27、通过蒸发或者溅射的方式，对IGBT器件背面进行合金，并退火后实现欧姆接触，形成背面金属(30)。
  9. 一种深缓冲层高密度沟槽的IGBT器件，其特征在于，所述深缓冲层高密度沟槽的IGBT器件根据权利要求1-8任意一种所述的深缓冲层高密度沟槽的IGBT器件的制备方法制备得到。
  10. 根据权利要求9所述的深缓冲层高密度沟槽的IGBT器件，其特征在于，所述器件包括终端区域(6)、划片道区域(31)、活性区域(32)，所述划片道区域(31)与活性区域(32)设置有若干高密度沟槽结构，所述高密度沟槽包括若干元胞活性沟槽(9)、元胞伪沟槽、划片道沟槽(11)。
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