WO2023274062A1 - Symmetric field effect transistor and manufacturing method therefor - Google Patents

Symmetric field effect transistor and manufacturing method therefor Download PDF

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Publication number
WO2023274062A1
WO2023274062A1 PCT/CN2022/101103 CN2022101103W WO2023274062A1 WO 2023274062 A1 WO2023274062 A1 WO 2023274062A1 CN 2022101103 W CN2022101103 W CN 2022101103W WO 2023274062 A1 WO2023274062 A1 WO 2023274062A1
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conductivity type
region
substrate
regions
doped
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PCT/CN2022/101103
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French (fr)
Chinese (zh)
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金华俊
宋亮
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无锡华润上华科技有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the invention belongs to the field of design and manufacture of semiconductor devices, in particular to a symmetrical field effect transistor and a manufacturing method thereof.
  • MOS devices metal-oxide-semiconductor field-effect transistors
  • N-type and P-type MOS devices MOS devices
  • MOS devices are also developing in the direction of miniaturization, which requires continuous reduction of the channel length of MOS devices.
  • a symmetrical field effect transistor is a device in which the source and drain are interchangeable, which requires the same and symmetrical structure of the source and drain.
  • the channel length of the symmetrical field effect transistor is too long, the on-resistance will increase, and if the channel length is too small, leakage will easily occur; on the other hand, the gate structure of the existing symmetrical field effect transistor structure is a whole, so Before the fabrication of the gate structure, it is necessary to form a channel well region under the gate structure in advance by means of implantation. In order to balance on-resistance, leakage and alignment accuracy, etc., the channel length of existing symmetric field effect transistors is relatively large, and usually needs to be set between 0.6 micron and 1 micron.
  • the implantation of the channel well region requires strict alignment, otherwise the dimension between the drain region and the channel well region on both sides of the channel well region will be affected by the alignment deviation of the lithography, resulting in the source and drain regions of the device.
  • the characteristics of the device change when the area is interchanged, which greatly reduces the stability of the device.
  • the purpose of the present invention is to provide a symmetrical field effect transistor and its manufacturing method, which is used to solve the problem that the length of the conductive channel of the symmetrical field effect transistor in the prior art is relatively large, and due to the Quasi-leading to the problem that the distance between the source region and the drain region and the channel well region is different, so that the device characteristics change when the source region and the drain region of the device are interchanged.
  • the present invention provides a method for manufacturing a symmetric field effect transistor.
  • the method includes the steps of: providing a substrate, forming a gate structure on the substrate, and Two pole regions of the first conductivity type on both sides of the structure, the substrate has the second conductivity type; a groove is formed in the middle of the gate structure through a photolithography process and an etching process;
  • the substrate is implanted with ions of the second conductivity type, and the ions of the second conductivity type are laterally diffused below the gate structure to form a channel well region of the second conductivity type, and the channel of the second conductivity type
  • the two pole regions of the first conductivity type are arranged mirror-symmetrically, and the distance between the two pole regions of the first conductivity type and the channel well region of the second conductivity type is equal.
  • it further includes the step of: forming two substrate-extracting doped regions of the second conductivity type in the substrate, and the two substrate-extracting doped regions are formed on two electrodes of the first conductivity type. outside of the area.
  • the method further includes the step of: forming two second conductivity type body region deriving doped regions in the substrate, and the two body region deriving doped regions are formed between the pole region of the first conductivity type and the electrode region of the first conductivity type. between the substrate-derived doped regions; two isolation doped regions of the first conductivity type are formed between the body region-derived doped region and the substrate-derived doped region, and between the isolation doped regions An isolated deep well region of the first conductivity type is formed at the bottom of the impurity region, and the isolated doped region and the isolated deep well region are used to electrically isolate the doped region derived from the body region and the doped region derived from the substrate .
  • the two doped regions derived from the body region are arranged in mirror symmetry
  • the two doped regions derived from the substrate are arranged in mirror symmetry
  • the two isolation doped regions are arranged in mirror symmetry.
  • the present invention also provides a symmetrical field effect transistor, comprising: a substrate on which a gate structure is formed and two electrode regions of the first conductivity type located on both sides of the gate structure, the substrate has a first Two conductivity types, a trench is formed in the middle of the gate structure; a channel well region of the second conductivity type is formed in the substrate below the trench, and the channel well region of the second conductivity type The area diffuses laterally below the gate structure, the channel well region of the second conductivity type has a distance from the pole region of the first conductivity type; the connection doped region of the first conductivity type is formed in the trench The groove corresponds to the channel well region of the second conductivity type.
  • the two polar regions of the first conductivity type are mirror-symmetrically arranged, and the distance between the two polar regions of the first conductivity type and the channel well region of the second conductivity type is equal.
  • two substrate-derived doped regions of the second conductivity type are also formed in the substrate, and the two substrate-derived doped regions are formed outside the two polar regions of the first conductivity type .
  • two body region-extracting doped regions of the second conductivity type are also formed in the substrate, and the two body region-extracting doped regions are formed between the electrode region of the first conductivity type and the substrate.
  • Two isolation doped regions of the first conductivity type are formed between the bottom extraction doped regions, between the body region extraction doping regions and the substrate extraction doping regions, and the isolation doping regions
  • An isolated deep well region of the first conductivity type is formed at the bottom; the isolated doped region and the isolated deep well region are used to electrically isolate the doped region derived from the body region and the doped region derived from the substrate.
  • the two doped regions derived from the body region are arranged in mirror symmetry
  • the two doped regions derived from the substrate are arranged in mirror symmetry
  • the two isolation doped regions are arranged in mirror symmetry.
  • the width of the trench is between 0.4 micron and 1 micron, and the width of the channel well region is between 0.8 micron and 1.6 micron.
  • the symmetrical field effect transistor and its manufacturing method of the present invention have the following beneficial effects:
  • a trench is formed in the middle of the gate structure by photolithography and etching processes, and the channel well region is formed by self-aligned ion implantation and lateral diffusion after the trench of the gate structure is etched. form.
  • the channel well region is formed after the gate structure is formed, and since the trench used to form the channel well region is formed by the photolithography process and etching process of the gate structure, it has very high alignment accuracy .
  • the process of the present invention is stable, and can ensure precise control of the position and size of the channel well region under the premise of avoiding electric leakage. Therefore, the size of the channel well region produced by the present invention can be smaller, so that the on-resistance of the device is lower.
  • connection doping region is formed in the substrate through implantation in the region where the gate structure forms the groove, which can further reduce the resistance on the current flow path.
  • FIG. 1 to 4 are schematic structural diagrams of each step in the manufacturing method of the symmetric field effect transistor according to Embodiment 1 of the present invention.
  • 5 to 8 are schematic structural diagrams of each step of the manufacturing method of the symmetric field effect transistor according to the second embodiment of the present invention.
  • spatial relation terms such as “below”, “below”, “below”, “below”, “above”, “on” etc. may be used herein to describe an element or element shown in the drawings.
  • a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
  • structures described as having a first feature "on top of" a second feature may include embodiments where the first and second features are formed in direct contact, as well as additional features formed between the first and second features. Embodiments between the second feature such that the first and second features may not be in direct contact.
  • this embodiment provides a method for manufacturing a symmetrical field effect transistor, and the method includes steps:
  • step 1) is first performed, a substrate 10 is provided, and a gate structure 106 and two pole regions of the first conductivity type respectively located on both sides of the gate structure 106 are formed on the substrate 10 107'.
  • the substrate 10 may be a semiconductor substrate, such as a Si substrate, a Ge substrate, a SiGe substrate, SOI (silicon on insulator) or GOI (germanium on insulator) and the like.
  • the semiconductor substrate can also be a substrate including other elemental semiconductors or compound semiconductors, such as GaAs, InP or SiC, etc., or a stacked structure, such as Si/SiGe, etc., or other Epitaxial structure, such as SGOI (silicon germanium on insulator), etc.
  • the substrate is a Si substrate.
  • step 1) includes:
  • Step 1-1 providing a substrate 10 .
  • Step 1-2 forming a plurality of isolation structures 101 arranged at intervals in the substrate 10 , the isolation structures 101 may be, for example, shallow trench isolation structures STI or field oxygen structures locos.
  • Step 1-3 forming a gate structure 106 on the substrate 10, the gate structure 106 may include a gate dielectric layer on the surface of the substrate 10 and a polysilicon layer on the gate dielectric layer.
  • Step 1-4 form two pole regions 107' of the first conductivity type on both sides of the gate structure 106 by ion implantation process, the size and doping of the two pole regions 107' of the first conductivity type The concentration is kept the same, and the two first conductivity type pole regions 107' are mirror-symmetrically arranged, and further ion implantation is performed to form the drift region 107 of the first conductivity type pole region 107', so as to increase the breakdown voltage.
  • Step 1-5) using the isolation structure 101 as a self-aligned barrier layer to perform an ion implantation process to form two substrate-extracting doped regions 102 of the second conductivity type in the substrate 10, the two Substrate extraction doped regions 102 are respectively formed on the outer sides of the two first conductivity type pole regions 107', and ion implantation is further performed to form contact regions 102' of the two substrate extraction doping regions 102, so as to reduce The contact resistance derived later.
  • the two substrate-derived doped regions 102 are mirror-symmetrically arranged, and the mirror-symmetric centers of the two substrate-derived doped regions 102 are strictly aligned with the two first conductivity type polar regions 107. 'The center of mirror symmetry coincides to ensure the symmetry of the device.
  • steps 1-4) and steps 1-5) can replace the process sequence, and at the same time, the above steps 1-4) and steps 1-5) can carry out ion diffusion or ion activation in a separate annealing process, or in Ion diffusion or ion activation is performed in the same annealing process.
  • step 2) is then performed to form a trench 108 in the middle of the gate structure 106 through a photolithography process and an etching process.
  • the groove 108 is formed by using a high-precision mask, and the groove 108 is located in the center of the two pole regions 107' of the first conductivity type. It can also be understood that the groove 108 The center of symmetry strictly coincides with the center of mirror symmetry of the two pole regions 107' of the first conductivity type, and the width of the groove 108 may be 1/3 of the distance between the two pole regions 107' of the first conductivity type Between one and one-half, for example, in this embodiment, the width of the trench 108 is between 0.4 micron and 1 micron, and the bottom of the trench 108 exposes the substrate 10 . Since the trench 108 is formed on the flat gate structure 106 through a photolithography process and an etching process, its size and formation position have very high precision.
  • step 3 is finally performed, implanting ions of the second conductivity type into the substrate 10 through the trench 108, and laterally diffusing the ions of the second conductivity type to the gate.
  • pole structure 106 to form a channel well region 109 of the second conductivity type, and the channel well region 109 of the second conductivity type has a distance from the pole region 107' of the first conductivity type; through the trench 108 Ion implantation of the first conductivity type is performed on the substrate 10 to form a connection doped region 110 of the first conductivity type in the substrate 10 below the trench 108 .
  • the channel well region 109 of the second conductivity type is formed on the upper surface layer of the substrate 10, and the connection doped region 110 of the first conductivity type is formed in the substrate 10 below the trench 108 and formed in the second The upper surface layer of the channel well region 109 of two conductivity types.
  • the doping depth of the channel well region 109 of the second conductivity type is greater than or equal to the doping depth of the drift region 107 .
  • this embodiment can make the two pole regions 107' of the first conductivity type and the pole regions of the second conductivity type
  • the spacing between the channel and well regions 109 of the type is equal, based on which, when the source region and the drain region of the final device are interchanged, the device characteristics can be kept unchanged.
  • ion implantation of the first conductivity type is performed on the substrate 10 through the trench 108 to form a connection doped region 110 of the first conductivity type in the substrate 10 below the trench 108.
  • the doped region 110 can compensate for the increase in on-resistance caused by the missing gate structure 106 at the trench 108 , thereby effectively reducing the on-resistance of the device.
  • the width of the channel well region 109 of the second conductivity type is between 0.8 ⁇ m and 1.6 ⁇ m, and the channel well region 109 of the second conductivity type is located under the gate structure 106
  • the lengths of the parts are respectively between 0.2 micron and 0.3 micron.
  • the first conductivity type is N-type conductivity
  • the second conductivity type is P-type conductivity
  • the first conductivity type can also be P-type conductivity
  • the second conductivity type can also be N-type conductivity
  • this embodiment also provides a symmetrical field effect transistor.
  • the symmetrical field effect transistor includes: a substrate 10, a gate structure 106 is formed on the substrate 10, and gate structures 106 are respectively located Two pole regions 107' of the first conductivity type on both sides, a trench 108 is formed in the middle of the gate structure 106; a channel well region 109 of the second conductivity type is formed in the trench 108 below the In the substrate 10, the channel well region 109 of the second conductivity type is laterally diffused to below the gate structure 106, and the channel well region 109 of the second conductivity type is connected to the electrode region of the first conductivity type 107 ′ has a pitch; the connection doped region 110 of the first conductivity type is formed in the channel well region 109 of the second conductivity type corresponding to the trench 108 .
  • the connection doped region 110 can compensate for the increase in on-resistance caused by the missing gate structure 106 at the trench 108, thereby effectively reducing the on-resistance of the device
  • the substrate 10 may be a semiconductor substrate, such as a Si substrate, a Ge substrate, a SiGe substrate, SOI (silicon on insulator) or GOI (germanium on insulator) and the like.
  • the semiconductor substrate can also be a substrate including other elemental semiconductors or compound semiconductors, such as GaAs, InP or SiC, etc., or a stacked structure, such as Si/SiGe, etc., or other Epitaxial structure, such as SGOI (silicon germanium on insulator), etc.
  • the substrate is a Si substrate.
  • the gate structure 106 may include a gate dielectric layer on the surface of the substrate 10 and a polysilicon layer on the gate dielectric layer.
  • the size and doping concentration of the two pole regions 107' of the first conductivity type are kept the same, and the two pole regions 107' of the first conductivity type use the channel of the second conductivity type
  • the well region 109 is mirror-symmetrically arranged at the center, and at the same time, a drift region 107 of the first conductivity type pole region 107 ′ is formed around the first conductivity type pole region 107 ′, so as to increase the breakdown voltage.
  • two substrate-leading doped regions 102 of the second conductivity type are formed in the substrate 10, and the two substrate-leading doped regions 102 are respectively formed in the two first
  • contact regions 102 ′ of the substrate-extracting doped region 102 are also formed in the two substrate-extracting doped regions 102 , so as to reduce the contact resistance for subsequent extraction.
  • the two substrate-leading doped regions 102 are also arranged mirror-symmetrically with the channel well region 109 of the second conductivity type as the center, so as to ensure the symmetry of the device.
  • the trench 108 is located at the center of the two pole regions 107' of the first conductivity type, and the width of the trench 108 may be between the two pole regions 107' of the first conductivity type. Between one-third and one-half of the distance between the grooves, for example, in this embodiment, the width of the trench 108 is between 0.4 micron and 1 micron. Since the trench 108 is formed on the flat gate structure 106 through a photolithography process and an etching process, and the mask used is a high-precision mask, its size and position have very high precision.
  • the distances between the two pole regions 107' of the first conductivity type and the channel well regions 109 of the second conductivity type on both sides are equal. Based on this, the final device is in the source When the region and drain region are interchanged, the device characteristics can be kept unchanged.
  • the width of the channel well region 109 of the second conductivity type is between 0.8 ⁇ m and 1.6 ⁇ m, and the channel well region 109 of the second conductivity type is located under the gate structure 106
  • the lengths of the parts are respectively between 0.2 micron and 0.3 micron.
  • the first conductivity type is N-type conductivity
  • the second conductivity type is P-type conductivity
  • the first conductivity type can also be P-type conductivity
  • the second conductivity type can also be N-type conductivity
  • this embodiment provides a method for manufacturing a symmetrical field effect transistor, the basic steps of which are as in Embodiment 1, where the difference from Embodiment 1 lies in:
  • the preparation method also includes the steps of:
  • two body region-extracting doped regions 103 of the second conductivity type are formed.
  • the substrate is extracted between the doped regions 102 , and ion implantation is further performed to form the contact region 103 ′ of the body region of the second conductivity type to extract the doped regions 103 , so as to reduce the contact resistance of the later extraction.
  • the two doped regions 103 drawn out from the body region are arranged mirror-symmetrically.
  • Two isolating doped regions 104 of the first conductivity type are formed between the doped regions 103 derived from the body region and the doped regions 102 derived from the substrate, and a first doped region is formed at the bottom of the doped regions 104.
  • Conductive type isolated deep well region 105 are used for electrically isolating the body region-derived doped region 103 and the substrate-derived doped region 102 .
  • ion implantation is further performed to form the contact region 104' of the first conductivity type isolating the doped region 104, so as to reduce the contact resistance of the later extraction.
  • the two isolation doped regions 104 are arranged mirror-symmetrically, and the mirror symmetrical centers of the two isolated doped regions 104 are strictly the same as the mirror symmetrical centers of the two body-extracting doped regions 103. coincide, and the center of symmetry of the trench 108 formed in the subsequent steps strictly coincides with the center of symmetry of the mirrors of the two isolated doped regions 104 .
  • isolation structure 101 is formed between the isolation doped region 104 and the substrate extraction doped region 102 , and the isolation structure 101 may be, for example, a shallow trench isolation structure STI or a field oxygen structure locos.
  • the doped region 103 derived from the body region and the doped region 102 derived from the substrate are formed in the same doping process, and the doping process uses the isolation structure 101 as a barrier layer to realize self- alignment.
  • the isolation doped region 104 of the first conductivity type can also be formed in the same doping process as the pole region 107' of the first conductivity type, and the doping process uses the isolation structure 101 and the gate
  • the pole structure 106 serves as a barrier layer to achieve self-alignment.
  • the above-mentioned doping process may be, for example, an ion implantation process and an annealing process, but is not limited to the examples listed here.
  • this embodiment also provides a symmetrical field effect transistor, the basic structure of which is as in Embodiment 1, wherein the difference from Embodiment 1 lies in:
  • Two doped regions 103 for deriving body regions of the second conductivity type are also formed in the substrate 10, and the two doped regions 103 for deriving body regions 103 are respectively formed between the pole region 107' of the first conductivity type and the pole region 107' of the first conductivity type.
  • the substrate leads out between the doped regions 102.
  • a contact region 103' of the second conductivity type body region extraction doped region 103 is also formed in the second conductivity type body region extraction doped region 103, so as to reduce the contact resistance of the later extraction.
  • the two doped regions 103 drawn out from the body region are arranged mirror-symmetrically.
  • Two isolation doped regions 104 of the first conductivity type are also formed between the body region extraction doped region 103 and the substrate extraction doping region 102, and the bottom of the isolation doping regions 104 is formed with a second An isolated deep well region 105 of one conductivity type, the isolated doped region 104 and the isolated deep well region 105 are used for electrically isolating the body region-derived doped region 103 and the substrate-derived doped region 102 .
  • a contact region 104' of the isolated doped region 104 of the first conductivity type is also formed in the isolated doped region 104 of the first conductivity type.
  • the two isolated doped regions 104 are arranged mirror-symmetrically.
  • isolation structure 101 is formed between the isolation doped region 104 and the substrate extraction doped region 102 , and the isolation structure 101 may be, for example, a shallow trench isolation structure STI or a field oxygen structure locos.
  • the body-extracting doped region 103 is used to extract the body region, ensuring that the device can be grounded or raised potential; on the other hand, the body-extracting doped region 103 can ensure the surrounding The junction breakdown voltage is high enough.
  • the isolated doped region 104 and the isolated deep well region 105 are used to electrically isolate the body-extracted doped region 103 and the substrate-extracted doped region 102, so that the symmetrical field effect transistor can be made
  • the isolation tube that is, the doped region 103 derived from the body region and the doped region 102 derived from the substrate can independently raise the potential for the device, which can greatly improve the performance of the device.
  • the symmetrical field effect transistor and its manufacturing method of the present invention have the following beneficial effects:
  • a trench 108 is formed in the middle of the gate structure 106 by a photolithography process and an etching process, and the channel well region 109 is formed by self-alignment after the trench 108 of the gate structure 106 is etched. Formed by ion implantation and lateral diffusion, since the trench 108 is formed through a photolithography process and an etching process of the gate structure, it has very high alignment accuracy. In addition, the process of the present invention is stable, and the position and size of the channel well region 109 can be precisely controlled. Therefore, the size of the channel well region 109 produced in the present invention can be smaller, so that the on-resistance of the device is lower.
  • the connecting doped region 110 is formed in the substrate by implantation, which can further reduce the resistance on the current flow path.
  • the present invention effectively overcomes various shortcomings in the prior art and has high industrial application value.

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Abstract

The present invention provides a symmetric field effect transistor and a manufacturing method therefor. The method comprises the steps: forming, on a substrate, a gate structure and two first conductive type pole regions located at two sides of the gate structure; forming a trench at the middle portion of the gate structure by means of a photoetching process and an etching process; performing second conductive type ion implantation on the trench, and enabling second conductive type ions to transversely diffuse to the lower portion of the gate structure so as to form a second conductive type of a channel well region, wherein there is a distance between the channel well region and each pole region; and performing first conductive type ion implantation on the substrate by means of the trench so as to form a first conductive type of a connection doped region in the substrate below the trench. According to the present invention, the process is stable, the position and size of the channel well region can be accurately controlled, and the size of the manufactured channel well region can be smaller, so that the on-resistance of a device is lower. Further, the present invention forms the connection doped region in the region of the gate structure where the trench is formed, and thus can reduce the resistance of a path through which current flows.

Description

对称场效应晶体管及其制作方法Symmetrical Field Effect Transistor and Method for Making the Same
相关申请的交叉引用Cross References to Related Applications
本申请要求于2021年7月1日提交中国专利局、申请号为202110745665.5、发明名称为“对称场效应晶体管及其制作方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。This application claims the priority of the Chinese patent application with the application number 202110745665.5 and the title of the invention "Symmetric Field Effect Transistor and Its Fabrication Method" filed with the China Patent Office on July 1, 2021, the entire contents of which are incorporated by reference in this application middle.
技术领域technical field
本发明属于半导体器件设计及制造领域，特别是涉及一种对称场效应晶体管及其制作方法。The invention belongs to the field of design and manufacture of semiconductor devices, in particular to a symmetrical field effect transistor and a manufacturing method thereof.
背景技术Background technique
MOS器件(金属-氧化物-半导体场效应晶体管)是现代集成电路中的主要器件，其按照沟道极性的不同可分为N型和P型MOS器件。随着半导体技术的飞速发展，MOS器件也在向小型化方向发展，这就需要不断减小MOS器件的沟道长度。MOS devices (metal-oxide-semiconductor field-effect transistors) are the main devices in modern integrated circuits, which can be divided into N-type and P-type MOS devices according to the polarity of the channel. With the rapid development of semiconductor technology, MOS devices are also developing in the direction of miniaturization, which requires continuous reduction of the channel length of MOS devices.
对称场效应晶体管是一种源极和漏极可以互换的器件，这样就要求源极和漏极的结构相同且对称。一方面，对称场效应晶体管的沟道长度过长会导致导通电阻变大，长度过小则容易出现漏电；另一方面，现有对称场效应晶体管结构的栅极结构是一根整体，因此在栅极结构制作之前，需要提前在栅极结构下方通过注入形成的方式形成沟道阱区。为了平衡导通电阻、漏电以及对准精度等问题，现有的对称场效应晶体管的沟道长度相对较大，通常需要设置在0.6微米至1微米之间。进一步地，沟道阱区的注入需要严格对位，否则沟道阱区两侧的漏区与沟道阱区之间的尺寸会受光刻对位偏差的影响，导致器件的源区和漏区在互换时器件特性发生变化，从而使得器件使用的稳定性大大降低。A symmetrical field effect transistor is a device in which the source and drain are interchangeable, which requires the same and symmetrical structure of the source and drain. On the one hand, if the channel length of the symmetrical field effect transistor is too long, the on-resistance will increase, and if the channel length is too small, leakage will easily occur; on the other hand, the gate structure of the existing symmetrical field effect transistor structure is a whole, so Before the fabrication of the gate structure, it is necessary to form a channel well region under the gate structure in advance by means of implantation. In order to balance on-resistance, leakage and alignment accuracy, etc., the channel length of existing symmetric field effect transistors is relatively large, and usually needs to be set between 0.6 micron and 1 micron. Furthermore, the implantation of the channel well region requires strict alignment, otherwise the dimension between the drain region and the channel well region on both sides of the channel well region will be affected by the alignment deviation of the lithography, resulting in the source and drain regions of the device The characteristics of the device change when the area is interchanged, which greatly reduces the stability of the device.
发明内容Contents of the invention
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种对称场效应晶体管及其制作方法，用于解决现有技术中对称场效应晶体管的导电沟道的长度较大，且由于对准导致源区和漏区与沟道阱区之间的间距不同，使得器件的源区和漏区互换时器件特性发生变化的问题。In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a symmetrical field effect transistor and its manufacturing method, which is used to solve the problem that the length of the conductive channel of the symmetrical field effect transistor in the prior art is relatively large, and due to the Quasi-leading to the problem that the distance between the source region and the drain region and the channel well region is different, so that the device characteristics change when the source region and the drain region of the device are interchanged.
为实现上述目的及其他相关目的，本发明提供一种对称场效应晶体管的制作方法，所 述制作方法包括步骤：提供一衬底，于所述衬底上形成栅极结构以及位于所述栅极结构两侧的两个第一导电类型极区，所述衬底具有第二导电类型；通过光刻工艺及刻蚀工艺于所述栅极结构的中部形成沟槽；通过所述沟槽对所述衬底进行第二导电类型离子注入，并使所述第二导电类型离子横向扩散至所述栅极结构的下方以形成第二导电类型的沟道阱区，所述第二导电类型的沟道阱区与所述第一导电类型极区具有间距；通过所述沟槽对所述衬底进行第一导电类型离子注入，以在所述沟槽下方的衬底中形成第一导电类型的连接掺杂区。In order to achieve the above object and other related objects, the present invention provides a method for manufacturing a symmetric field effect transistor. The method includes the steps of: providing a substrate, forming a gate structure on the substrate, and Two pole regions of the first conductivity type on both sides of the structure, the substrate has the second conductivity type; a groove is formed in the middle of the gate structure through a photolithography process and an etching process; The substrate is implanted with ions of the second conductivity type, and the ions of the second conductivity type are laterally diffused below the gate structure to form a channel well region of the second conductivity type, and the channel of the second conductivity type There is a distance between the track well region and the pole region of the first conductivity type; ion implantation of the first conductivity type is performed on the substrate through the trench, so as to form an ion implantation of the first conductivity type in the substrate below the trench. Connect the doped region.
可选地，两个所述第一导电类型极区为镜面对称设置，且两个所述第一导电类型极区与所述第二导电类型沟道阱区之间的间距相等。Optionally, the two pole regions of the first conductivity type are arranged mirror-symmetrically, and the distance between the two pole regions of the first conductivity type and the channel well region of the second conductivity type is equal.
可选地，还包括步骤：于所述衬底中形成两个第二导电类型的衬底引出掺杂区，两个所述衬底引出掺杂区形成于两个所述第一导电类型极区的外侧。Optionally, it further includes the step of: forming two substrate-extracting doped regions of the second conductivity type in the substrate, and the two substrate-extracting doped regions are formed on two electrodes of the first conductivity type. outside of the area.
可选地，还包括步骤：于所述衬底中形成两个第二导电类型的体区引出掺杂区，两个所述体区引出掺杂区形成于所述第一导电类型极区与所述衬底引出掺杂区之间；于所述体区引出掺杂区和所述衬底引出掺杂区之间形成两个第一导电类型的隔离掺杂区，以及于所述隔离掺杂区的底部形成第一导电类型的隔离深阱区，所述隔离掺杂区与所述隔离深阱区用于将所述体区引出掺杂区和所述衬底引出掺杂区电隔离。Optionally, the method further includes the step of: forming two second conductivity type body region deriving doped regions in the substrate, and the two body region deriving doped regions are formed between the pole region of the first conductivity type and the electrode region of the first conductivity type. between the substrate-derived doped regions; two isolation doped regions of the first conductivity type are formed between the body region-derived doped region and the substrate-derived doped region, and between the isolation doped regions An isolated deep well region of the first conductivity type is formed at the bottom of the impurity region, and the isolated doped region and the isolated deep well region are used to electrically isolate the doped region derived from the body region and the doped region derived from the substrate .
可选地，两个所述体区引出掺杂区为镜面对称设置，两个所述衬底引出掺杂区为镜面对称设置，两个所述隔离掺杂区为镜面对称设置。Optionally, the two doped regions derived from the body region are arranged in mirror symmetry, the two doped regions derived from the substrate are arranged in mirror symmetry, and the two isolation doped regions are arranged in mirror symmetry.
本发明还提供一种对称场效应晶体管，包括：衬底，所述衬底上形成栅极结构以及位于所述栅极结构两侧的两个第一导电类型极区，所述衬底具有第二导电类型，所述栅极结构的中部形成有沟槽；第二导电类型的沟道阱区，形成于所述沟槽下方的所述衬底中，所述第二导电类型的沟道阱区横向扩散至所述栅极结构的下方，所述第二导电类型的沟道阱区与所述第一导电类型极区具有间距；第一导电类型的连接掺杂区，形成于所述沟槽对应的所述第二导电类型的沟道阱区内。The present invention also provides a symmetrical field effect transistor, comprising: a substrate on which a gate structure is formed and two electrode regions of the first conductivity type located on both sides of the gate structure, the substrate has a first Two conductivity types, a trench is formed in the middle of the gate structure; a channel well region of the second conductivity type is formed in the substrate below the trench, and the channel well region of the second conductivity type The area diffuses laterally below the gate structure, the channel well region of the second conductivity type has a distance from the pole region of the first conductivity type; the connection doped region of the first conductivity type is formed in the trench The groove corresponds to the channel well region of the second conductivity type.
可选地，两个所述第一导电类型极区为镜面对称设置，且两个所述第一导电类型极区与所述第二导电类型的沟道阱区之间的间距相等。Optionally, the two polar regions of the first conductivity type are mirror-symmetrically arranged, and the distance between the two polar regions of the first conductivity type and the channel well region of the second conductivity type is equal.
可选地，所述衬底中还形成有两个第二导电类型的衬底引出掺杂区，两个所述衬底引出掺杂区形成于两个所述第一导电类型极区的外侧。Optionally, two substrate-derived doped regions of the second conductivity type are also formed in the substrate, and the two substrate-derived doped regions are formed outside the two polar regions of the first conductivity type .
可选地，所述衬底中还形成有两个第二导电类型的体区引出掺杂区，两个所述体区引出掺杂区形成于所述第一导电类型极区与所述衬底引出掺杂区之间，所述体区引出掺杂区和所述衬底引出掺杂区之间还形成有两个第一导电类型的隔离掺杂区，以及所述隔离掺杂 区的底部形成有第一导电类型的隔离深阱区；所述隔离掺杂区与所述隔离深阱区用于将所述体区引出掺杂区和所述衬底引出掺杂区电隔离。Optionally, two body region-extracting doped regions of the second conductivity type are also formed in the substrate, and the two body region-extracting doped regions are formed between the electrode region of the first conductivity type and the substrate. Two isolation doped regions of the first conductivity type are formed between the bottom extraction doped regions, between the body region extraction doping regions and the substrate extraction doping regions, and the isolation doping regions An isolated deep well region of the first conductivity type is formed at the bottom; the isolated doped region and the isolated deep well region are used to electrically isolate the doped region derived from the body region and the doped region derived from the substrate.
可选地，两个所述体区引出掺杂区为镜面对称设置，两个所述衬底引出掺杂区为镜面对称设置，两个所述隔离掺杂区为镜面对称设置。Optionally, the two doped regions derived from the body region are arranged in mirror symmetry, the two doped regions derived from the substrate are arranged in mirror symmetry, and the two isolation doped regions are arranged in mirror symmetry.
可选地，所述沟槽的宽度为0.4微米～1微米之间，所述沟道阱区的宽度为0.8微米～1.6微米之间。Optionally, the width of the trench is between 0.4 micron and 1 micron, and the width of the channel well region is between 0.8 micron and 1.6 micron.
如上所述，本发明的对称场效应晶体管及其制作方法，具有以下有益效果：As mentioned above, the symmetrical field effect transistor and its manufacturing method of the present invention have the following beneficial effects:
本发明的对称场效应晶体管，在栅极结构中部通过光刻工艺及刻蚀工艺形成沟槽，沟道阱区是在栅极结构的沟槽刻蚀完之后通过自对准离子注入和横向扩散形成。沟道阱区是在栅极结构形成之后形成的，且由于用来形成沟道阱区的沟槽是通过栅极结构的光刻工艺及刻蚀工艺形成的，其具有非常高的对准精度。此外，本发明工艺稳定，能够确保在避免漏电的前提下实现沟道阱区的位置和尺寸的精确控制。因此，本发明所制作的沟道阱区的尺寸可以更小，从而使器件的导通电阻更低。In the symmetrical field effect transistor of the present invention, a trench is formed in the middle of the gate structure by photolithography and etching processes, and the channel well region is formed by self-aligned ion implantation and lateral diffusion after the trench of the gate structure is etched. form. The channel well region is formed after the gate structure is formed, and since the trench used to form the channel well region is formed by the photolithography process and etching process of the gate structure, it has very high alignment accuracy . In addition, the process of the present invention is stable, and can ensure precise control of the position and size of the channel well region under the premise of avoiding electric leakage. Therefore, the size of the channel well region produced by the present invention can be smaller, so that the on-resistance of the device is lower.
本发明在栅极结构形成沟槽的区域通过注入在衬底中形成连接掺杂区，可以进一步降低电流流经路径上的电阻。In the present invention, the connection doping region is formed in the substrate through implantation in the region where the gate structure forms the groove, which can further reduce the resistance on the current flow path.
附图说明Description of drawings
图1～图4显示为本发明实施例1的对称场效应晶体管的制作方法各步骤所呈现的结构示意图。1 to 4 are schematic structural diagrams of each step in the manufacturing method of the symmetric field effect transistor according to Embodiment 1 of the present invention.
图5～图8显示为本发明实施例2的对称场效应晶体管的制作方法各步骤所呈现的结构示意图。5 to 8 are schematic structural diagrams of each step of the manufacturing method of the symmetric field effect transistor according to the second embodiment of the present invention.
元件标号说明Component designation description
10                     衬底10 Substrate
101                    隔离结构101 Isolation structure
102                    衬底引出掺杂区102 Substrate lead out doped region
103                    体区引出掺杂区103 Body region lead out doping region
104                    隔离掺杂区104 Isolation doped region
105                    隔离深阱区105 Isolation deep well area
106                    栅极结构106 Gate Structure
107                    漂移区107 Drift Zone
108                    沟槽108 Groove
109                    沟道阱区109 channel well region
110                    连接掺杂区110 Connecting the doped region
102’、103’、104’    接触区102’, 103’, 104’ contact area
107’                  第一导电类型极区107' Pole region of the first conductivity type
具体实施方式detailed description
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.
如在详述本发明实施例时，为便于说明，表示器件结构的剖面图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本发明保护的范围。此外，在实际制作中应包含长度、宽度及深度的三维空间尺寸。For example, when describing the embodiments of the present invention in detail, for the convenience of explanation, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic diagram is only an example, which should not limit the protection scope of the present invention. In addition, the three-dimensional space dimensions of length, width and depth should be included in actual production.
为了方便描述，此处可能使用诸如“之下”、“下方”、“低于”、“下面”、“上方”、“上”等的空间关系词语来描述附图中所示的一个元件或特征与其他元件或特征的关系。需要理解的是，这些空间关系词语意图包含使用中或操作中的器件的、除了附图中描绘的方向之外的其他方向。此外，当一层被称为在两层“之间”时，它可以是所述两层之间仅有的层，或者也可以存在一个或多个介于其间的层。For the convenience of description, spatial relation terms such as "below", "below", "below", "below", "above", "on" etc. may be used herein to describe an element or element shown in the drawings. The relationship of a feature to other components or features. It is to be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
在本申请的上下文中，所描述的第一特征在第二特征“之上”的结构可以包括第一和第二特征形成为直接接触的实施例，也可以包括另外的特征形成在第一和第二特征之间的实施例，这样第一和第二特征可能不是直接接触。In the context of this application, structures described as having a first feature "on top of" a second feature may include embodiments where the first and second features are formed in direct contact, as well as additional features formed between the first and second features. Embodiments between the second feature such that the first and second features may not be in direct contact.
需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图示中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic idea of the present invention, so that only the components related to the present invention are shown in the diagrams rather than the number, shape and Dimensional drawing, the type, quantity and proportion of each component can be changed arbitrarily during actual implementation, and the component layout type may also be more complicated.
实施例1Example 1
如图1～图4所示，本实施例提供一种对称场效应晶体管的制作方法，所述制作方法包括步骤：As shown in Figures 1 to 4, this embodiment provides a method for manufacturing a symmetrical field effect transistor, and the method includes steps:
如图1所示，首先进行步骤1)，提供一衬底10，于所述衬底10上形成栅极结构106以及分别位于所述栅极结构106两侧的两个第一导电类型极区107’。As shown in FIG. 1 , step 1) is first performed, a substrate 10 is provided, and a gate structure 106 and two pole regions of the first conductivity type respectively located on both sides of the gate structure 106 are formed on the substrate 10 107'.
作为示例，所述衬底10可以为半导体衬底，例如可以为Si衬底、Ge衬底、SiGe衬底、SOI(绝缘体上硅)或GOI(绝缘体上锗)等。在其它实施例中，所述半导体衬底还可以为包括其它元素半导体或化合物半导体的衬底，例如GaAs、InP或SiC等，还可以为叠层结构，例如Si/SiGe等，还可以为其它外延结构，例如SGOI(绝缘体上锗硅)等。在本实施例中，所述衬底为Si衬底。As an example, the substrate 10 may be a semiconductor substrate, such as a Si substrate, a Ge substrate, a SiGe substrate, SOI (silicon on insulator) or GOI (germanium on insulator) and the like. In other embodiments, the semiconductor substrate can also be a substrate including other elemental semiconductors or compound semiconductors, such as GaAs, InP or SiC, etc., or a stacked structure, such as Si/SiGe, etc., or other Epitaxial structure, such as SGOI (silicon germanium on insulator), etc. In this embodiment, the substrate is a Si substrate.
在本实施例中，步骤1)包括：In this embodiment, step 1) includes:
步骤1-1)，提供一衬底10。Step 1-1), providing a substrate 10 .
步骤1-2)，于所述衬底10中形成多个间隔排布的隔离结构101，所述隔离结构101例如可以为浅沟道隔离结构STI或场氧结构locos。Step 1-2), forming a plurality of isolation structures 101 arranged at intervals in the substrate 10 , the isolation structures 101 may be, for example, shallow trench isolation structures STI or field oxygen structures locos.
步骤1-3)，于所述衬底10上形成栅极结构106，所述栅极结构106可以包括位于所述衬底10表面的栅介质层和位于所述栅介质层上的多晶硅层。Step 1-3), forming a gate structure 106 on the substrate 10, the gate structure 106 may include a gate dielectric layer on the surface of the substrate 10 and a polysilicon layer on the gate dielectric layer.
步骤1-4)，通过离子注入工艺分别于所述栅极结构106的两侧形成两个第一导电类型极区107’，两个所述第一导电类型极区107’的尺寸和掺杂浓度保持一致，且两个所述第一导电类型极区107’为镜面对称设置，并进一步进行离子注入形成第一导电类型极区107’的漂移区107，以提高击穿电压。Step 1-4), form two pole regions 107' of the first conductivity type on both sides of the gate structure 106 by ion implantation process, the size and doping of the two pole regions 107' of the first conductivity type The concentration is kept the same, and the two first conductivity type pole regions 107' are mirror-symmetrically arranged, and further ion implantation is performed to form the drift region 107 of the first conductivity type pole region 107', so as to increase the breakdown voltage.
步骤1-5)，以所述隔离结构101为自对准的阻挡层进行离子注入工艺于所述衬底10中形成两个第二导电类型的衬底引出掺杂区102，两个所述衬底引出掺杂区102分别形成于两个所述第一导电类型极区107’的外侧，并进一步进行离子注入形成两个所述衬底引出掺杂区102的接触区102’，以降低后期引出的接触电阻。在本实施例中，两个所述衬底引出掺杂区102为镜面对称设置，两个所述衬底引出掺杂区102的镜面对称中心严格与两个所述第一导电类型极区107’的镜面对称中心重合，以保证器件的对称性。Step 1-5), using the isolation structure 101 as a self-aligned barrier layer to perform an ion implantation process to form two substrate-extracting doped regions 102 of the second conductivity type in the substrate 10, the two Substrate extraction doped regions 102 are respectively formed on the outer sides of the two first conductivity type pole regions 107', and ion implantation is further performed to form contact regions 102' of the two substrate extraction doping regions 102, so as to reduce The contact resistance derived later. In this embodiment, the two substrate-derived doped regions 102 are mirror-symmetrically arranged, and the mirror-symmetric centers of the two substrate-derived doped regions 102 are strictly aligned with the two first conductivity type polar regions 107. 'The center of mirror symmetry coincides to ensure the symmetry of the device.
其中，上述步骤1-4)和步骤1-5)可以更换工艺顺序，同时，上述步骤1-4)和步骤1-5)可以在分别的退火工艺中进行离子扩散或离子激活，也可以在同一退火工艺中进行离子扩散或离子激活。Wherein, the above steps 1-4) and steps 1-5) can replace the process sequence, and at the same time, the above steps 1-4) and steps 1-5) can carry out ion diffusion or ion activation in a separate annealing process, or in Ion diffusion or ion activation is performed in the same annealing process.
如图2所示，然后进行步骤2)，通过光刻工艺及刻蚀工艺于所述栅极结构106的中部形成沟槽108。As shown in FIG. 2 , step 2) is then performed to form a trench 108 in the middle of the gate structure 106 through a photolithography process and an etching process.
在本实施例中，采用高精度掩模版形成所述沟槽108，所述沟槽108位于两所述第一导电类型极区107’的正中央，也可以理解为，所述沟槽108的对称中心严格与两个所述第一导电类型极区107’的镜面对称中心重合，所述沟槽108的宽度可以为两个所述第一导电 类型极区107’之间间距的三分之一至二分之一之间，例如，在本实施例中，所述沟槽108的宽度为0.4微米～1微米之间，沟槽108的底部暴露衬底10。由于所述沟槽108是在平整的栅极结构106上通过光刻工艺及刻蚀工艺形成，因此，其尺寸和形成位置具有非常高的精度。In this embodiment, the groove 108 is formed by using a high-precision mask, and the groove 108 is located in the center of the two pole regions 107' of the first conductivity type. It can also be understood that the groove 108 The center of symmetry strictly coincides with the center of mirror symmetry of the two pole regions 107' of the first conductivity type, and the width of the groove 108 may be 1/3 of the distance between the two pole regions 107' of the first conductivity type Between one and one-half, for example, in this embodiment, the width of the trench 108 is between 0.4 micron and 1 micron, and the bottom of the trench 108 exposes the substrate 10 . Since the trench 108 is formed on the flat gate structure 106 through a photolithography process and an etching process, its size and formation position have very high precision.
如图3～图4所示，最后进行步骤3)，通过所述沟槽108对所述衬底10进行第二导电类型离子注入，并使所述第二导电类型离子横向扩散至所述栅极结构106的下方以形成第二导电类型的沟道阱区109，所述第二导电类型的沟道阱区109与所述第一导电类型极区107’具有间距；通过所述沟槽108对所述衬底10进行第一导电类型离子注入，以在所述沟槽108下方的衬底10中形成第一导电类型的连接掺杂区110。在其他实施例中，第二导电类型的沟道阱区109形成于衬底10的上表层，第一导电类型的连接掺杂区110形成在沟槽108下方的衬底10中且形成于第二导电类型的沟道阱区109的上表层。第二导电类型的沟道阱区109的掺杂深度大于等于漂移区107的掺杂深度。As shown in FIGS. 3 to 4 , step 3) is finally performed, implanting ions of the second conductivity type into the substrate 10 through the trench 108, and laterally diffusing the ions of the second conductivity type to the gate. pole structure 106 to form a channel well region 109 of the second conductivity type, and the channel well region 109 of the second conductivity type has a distance from the pole region 107' of the first conductivity type; through the trench 108 Ion implantation of the first conductivity type is performed on the substrate 10 to form a connection doped region 110 of the first conductivity type in the substrate 10 below the trench 108 . In other embodiments, the channel well region 109 of the second conductivity type is formed on the upper surface layer of the substrate 10, and the connection doped region 110 of the first conductivity type is formed in the substrate 10 below the trench 108 and formed in the second The upper surface layer of the channel well region 109 of two conductivity types. The doping depth of the channel well region 109 of the second conductivity type is greater than or equal to the doping depth of the drift region 107 .
由于所述沟槽108可以严格地形成于两个所述第一导电类型极区107’的正中央，本实施例可以使得两个所述第一导电类型极区107’与所述第二导电类型的沟道阱区109之间的间距相等，基于此，最终的器件在源区和漏区互换时，可以保持器件特性不变。Since the trench 108 can be strictly formed in the center of the two pole regions 107' of the first conductivity type, this embodiment can make the two pole regions 107' of the first conductivity type and the pole regions of the second conductivity type The spacing between the channel and well regions 109 of the type is equal, based on which, when the source region and the drain region of the final device are interchanged, the device characteristics can be kept unchanged.
本实施例通过所述沟槽108对所述衬底10进行第一导电类型离子注入，以在所述沟槽108下方的衬底10中形成第一导电类型的连接掺杂区110，该连接掺杂区110可以补偿沟槽108处缺失的栅极结构106所导致的导通电阻的增大，从而有效降低器件的导通电阻。In this embodiment, ion implantation of the first conductivity type is performed on the substrate 10 through the trench 108 to form a connection doped region 110 of the first conductivity type in the substrate 10 below the trench 108. The doped region 110 can compensate for the increase in on-resistance caused by the missing gate structure 106 at the trench 108 , thereby effectively reducing the on-resistance of the device.
在本实施例中，所述第二导电类型的沟道阱区109的宽度为0.8微米～1.6微米之间，所述第二导电类型的沟道阱区109位于所述栅极结构106下方的部分的长度分别为0.2微米～0.3微米之间。In this embodiment, the width of the channel well region 109 of the second conductivity type is between 0.8 μm and 1.6 μm, and the channel well region 109 of the second conductivity type is located under the gate structure 106 The lengths of the parts are respectively between 0.2 micron and 0.3 micron.
在本实施例中，所述第一导电类型为N型导电，所述第二导电类型为P型导电，当然，在其它的实施中，所述第一导电类型也可以为P型导电，所述第二导电类型也可以为N型导电。In this embodiment, the first conductivity type is N-type conductivity, and the second conductivity type is P-type conductivity. Of course, in other implementations, the first conductivity type can also be P-type conductivity, so The second conductivity type can also be N-type conductivity.
如图4所示，本实施例还提供一种对称场效应晶体管，所述对称场效应晶体管包括：衬底10，所述衬底10上形成栅极结构106以及分别位于所述栅极结构106两侧的两个第一导电类型极区107’，所述栅极结构106的中部形成有沟槽108；第二导电类型的沟道阱区109，形成于所述沟槽108下方的所述衬底10中，所述第二导电类型的沟道阱区109横向扩散至所述栅极结构106的下方，所述第二导电类型的沟道阱区109与所述第一导电类型极区107’具有间距；第一导电类型的连接掺杂区110，形成于所述沟槽108对应的所述第二导电类型的沟道阱区109内。所述连接掺杂区110可以补偿沟槽108处缺失的栅极结 构106所导致的导通电阻的增大，从而有效降低器件的导通电阻。As shown in FIG. 4 , this embodiment also provides a symmetrical field effect transistor. The symmetrical field effect transistor includes: a substrate 10, a gate structure 106 is formed on the substrate 10, and gate structures 106 are respectively located Two pole regions 107' of the first conductivity type on both sides, a trench 108 is formed in the middle of the gate structure 106; a channel well region 109 of the second conductivity type is formed in the trench 108 below the In the substrate 10, the channel well region 109 of the second conductivity type is laterally diffused to below the gate structure 106, and the channel well region 109 of the second conductivity type is connected to the electrode region of the first conductivity type 107 ′ has a pitch; the connection doped region 110 of the first conductivity type is formed in the channel well region 109 of the second conductivity type corresponding to the trench 108 . The connection doped region 110 can compensate for the increase in on-resistance caused by the missing gate structure 106 at the trench 108, thereby effectively reducing the on-resistance of the device.
作为示例，所述衬底10可以为半导体衬底，例如可以为Si衬底、Ge衬底、SiGe衬底、SOI(绝缘体上硅)或GOI(绝缘体上锗)等。在其它实施例中，所述半导体衬底还可以为包括其它元素半导体或化合物半导体的衬底，例如GaAs、InP或SiC等，还可以为叠层结构，例如Si/SiGe等，还可以为其它外延结构，例如SGOI(绝缘体上锗硅)等。在本实施例中，所述衬底为Si衬底。As an example, the substrate 10 may be a semiconductor substrate, such as a Si substrate, a Ge substrate, a SiGe substrate, SOI (silicon on insulator) or GOI (germanium on insulator) and the like. In other embodiments, the semiconductor substrate can also be a substrate including other elemental semiconductors or compound semiconductors, such as GaAs, InP or SiC, etc., or a stacked structure, such as Si/SiGe, etc., or other Epitaxial structure, such as SGOI (silicon germanium on insulator), etc. In this embodiment, the substrate is a Si substrate.
作为示例，所述栅极结构106可以包括位于所述衬底10表面的栅介质层和位于所述栅介质层上的多晶硅层。As an example, the gate structure 106 may include a gate dielectric layer on the surface of the substrate 10 and a polysilicon layer on the gate dielectric layer.
在本实施例中，两个所述第一导电类型极区107’的尺寸和掺杂浓度保持一致，且两个所述第一导电类型极区107’以所述第二导电类型的沟道阱区109为中心镜面对称设置，同时，所述第一导电类型极区107’***还形成有第一导电类型极区107’的漂移区107，以提高击穿电压。In this embodiment, the size and doping concentration of the two pole regions 107' of the first conductivity type are kept the same, and the two pole regions 107' of the first conductivity type use the channel of the second conductivity type The well region 109 is mirror-symmetrically arranged at the center, and at the same time, a drift region 107 of the first conductivity type pole region 107 ′ is formed around the first conductivity type pole region 107 ′, so as to increase the breakdown voltage.
在本实施例中，所述衬底10中还形成有两个第二导电类型的衬底引出掺杂区102，两个所述衬底引出掺杂区102分别形成于两个所述第一导电类型极区107’的两外侧，两个所述衬底引出掺杂区102中还形成有衬底引出掺杂区102的接触区102’，以降低后期引出的接触电阻。在本实施例中，两个所述衬底引出掺杂区102也以所述第二导电类型的沟道阱区109为中心镜面对称设置，以保证器件的对称性。In this embodiment, two substrate-leading doped regions 102 of the second conductivity type are formed in the substrate 10, and the two substrate-leading doped regions 102 are respectively formed in the two first On the two outer sides of the conductivity-type pole region 107 ′, contact regions 102 ′ of the substrate-extracting doped region 102 are also formed in the two substrate-extracting doped regions 102 , so as to reduce the contact resistance for subsequent extraction. In this embodiment, the two substrate-leading doped regions 102 are also arranged mirror-symmetrically with the channel well region 109 of the second conductivity type as the center, so as to ensure the symmetry of the device.
在本实施例中，所述沟槽108位于两个所述第一导电类型极区107’的正中央，所述沟槽108的宽度可以为两个所述第一导电类型极区107’之间间距的三分之一至二分之一之间，例如，在本实施例中，所述沟槽108的宽度为0.4微米～1微米之间。由于所述沟槽108是在平整的栅极结构106上通过光刻工艺及刻蚀工艺形成，且所用掩模版为高精度掩模版，因此，其尺寸和位置具有非常高的精度。In this embodiment, the trench 108 is located at the center of the two pole regions 107' of the first conductivity type, and the width of the trench 108 may be between the two pole regions 107' of the first conductivity type. Between one-third and one-half of the distance between the grooves, for example, in this embodiment, the width of the trench 108 is between 0.4 micron and 1 micron. Since the trench 108 is formed on the flat gate structure 106 through a photolithography process and an etching process, and the mask used is a high-precision mask, its size and position have very high precision.
在本实施例中，分别位于两侧的两个所述第一导电类型极区107’与所述第二导电类型的沟道阱区109之间的间距相等，基于此，最终的器件在源区和漏区互换时，可以保持器件特性不变。In this embodiment, the distances between the two pole regions 107' of the first conductivity type and the channel well regions 109 of the second conductivity type on both sides are equal. Based on this, the final device is in the source When the region and drain region are interchanged, the device characteristics can be kept unchanged.
在本实施例中，所述第二导电类型的沟道阱区109的宽度为0.8微米～1.6微米之间，所述第二导电类型的沟道阱区109位于所述栅极结构106的下方部分的长度分别为0.2微米～0.3微米之间。In this embodiment, the width of the channel well region 109 of the second conductivity type is between 0.8 μm and 1.6 μm, and the channel well region 109 of the second conductivity type is located under the gate structure 106 The lengths of the parts are respectively between 0.2 micron and 0.3 micron.
在本实施例中，所述第一导电类型为N型导电，所述第二导电类型为P型导电，当然，在其它的实施中，所述第一导电类型也可以为P型导电，所述第二导电类型也可以为N型导电。In this embodiment, the first conductivity type is N-type conductivity, and the second conductivity type is P-type conductivity. Of course, in other implementations, the first conductivity type can also be P-type conductivity, so The second conductivity type can also be N-type conductivity.
实施例2Example 2
如图5～图8所示，本实施例提供一种对称场效应晶体管的制作方法，其基本步骤如实施例1，其中，与实施例1的不同之处在于：As shown in Figures 5 to 8, this embodiment provides a method for manufacturing a symmetrical field effect transistor, the basic steps of which are as in Embodiment 1, where the difference from Embodiment 1 lies in:
所述制作方法还包括步骤：The preparation method also includes the steps of:
于所述衬底10中形成两个第二导电类型的体区引出掺杂区103，两个所述体区引出掺杂区103分别形成于所述第一导电类型极区107’与所述衬底引出掺杂区102之间，并进一步进行离子注入形成第二导电类型的体区引出掺杂区103的接触区103’，以降低后期引出的接触电阻。在本实施例中，两个所述体区引出掺杂区103为镜面对称设置。In the substrate 10, two body region-extracting doped regions 103 of the second conductivity type are formed. The substrate is extracted between the doped regions 102 , and ion implantation is further performed to form the contact region 103 ′ of the body region of the second conductivity type to extract the doped regions 103 , so as to reduce the contact resistance of the later extraction. In this embodiment, the two doped regions 103 drawn out from the body region are arranged mirror-symmetrically.
于所述体区引出掺杂区103和所述衬底引出掺杂区102之间形成两个第一导电类型的隔离掺杂区104，以及于所述隔离掺杂区104的底部形成第一导电类型的隔离深阱区105。所述隔离掺杂区104与所述隔离深阱区105用于将所述体区引出掺杂区103和所述衬底引出掺杂区102电隔离。在本实施例中，进一步进行离子注入形成第一导电类型的隔离掺杂区104的接触区104’，以降低后期引出的接触电阻。在本实施例中，两个所述隔离掺杂区104为镜面对称设置，两个所述隔离掺杂区104的镜面对称中心严格与两个所述体区引出掺杂区103的镜面对称中心重合，且后续步骤形成的沟槽108的对称中心也严格与两个所述隔离掺杂区104的镜面对称中心重合。Two isolating doped regions 104 of the first conductivity type are formed between the doped regions 103 derived from the body region and the doped regions 102 derived from the substrate, and a first doped region is formed at the bottom of the doped regions 104. Conductive type isolated deep well region 105 . The isolation doped region 104 and the isolation deep well region 105 are used for electrically isolating the body region-derived doped region 103 and the substrate-derived doped region 102 . In this embodiment, ion implantation is further performed to form the contact region 104' of the first conductivity type isolating the doped region 104, so as to reduce the contact resistance of the later extraction. In this embodiment, the two isolation doped regions 104 are arranged mirror-symmetrically, and the mirror symmetrical centers of the two isolated doped regions 104 are strictly the same as the mirror symmetrical centers of the two body-extracting doped regions 103. coincide, and the center of symmetry of the trench 108 formed in the subsequent steps strictly coincides with the center of symmetry of the mirrors of the two isolated doped regions 104 .
在本实施例中，所述第一导电类型极区107’与所述体区引出掺杂区103之间、所述体区引出掺杂区103与所述隔离掺杂区104之间、以及所述隔离掺杂区104与所述衬底引出掺杂区102之间均形成有隔离结构101，所述隔离结构101例如可以为浅沟道隔离结构STI或场氧结构locos。In this embodiment, between the pole region 107' of the first conductivity type and the body-extracted doped region 103, between the body-extracted doped region 103 and the isolation doped region 104, and An isolation structure 101 is formed between the isolation doped region 104 and the substrate extraction doped region 102 , and the isolation structure 101 may be, for example, a shallow trench isolation structure STI or a field oxygen structure locos.
在本实施例中，所述体区引出掺杂区103与所述衬底引出掺杂区102在同一掺杂工艺中形成，且所述掺杂工艺以所述隔离结构101为阻挡层实现自对准。所述第一导电类型的隔离掺杂区104也可以与所述第一导电类型极区107’在同一掺杂工艺中形成，且所述掺杂工艺分别以所述隔离结构101和所述栅极结构106作为阻挡层实现自对准。上述掺杂工艺例如可以为离子注入工艺和退火工艺，但并不限于此处所列举的示例。In this embodiment, the doped region 103 derived from the body region and the doped region 102 derived from the substrate are formed in the same doping process, and the doping process uses the isolation structure 101 as a barrier layer to realize self- alignment. The isolation doped region 104 of the first conductivity type can also be formed in the same doping process as the pole region 107' of the first conductivity type, and the doping process uses the isolation structure 101 and the gate The pole structure 106 serves as a barrier layer to achieve self-alignment. The above-mentioned doping process may be, for example, an ion implantation process and an annealing process, but is not limited to the examples listed here.
如图8所示，本实施例还提供一种对称场效应晶体管，其基本结构如实施例1，其中，与实施例1的不同之处在于：As shown in FIG. 8 , this embodiment also provides a symmetrical field effect transistor, the basic structure of which is as in Embodiment 1, wherein the difference from Embodiment 1 lies in:
所述衬底10中还形成有两个第二导电类型的体区引出掺杂区103，两个所述体区引出掺杂区103分别形成于所述第一导电类型极区107’与所述衬底引出掺杂区102之间。所述第二导电类型的体区引出掺杂区103中还形成有第二导电类型的体区引出掺杂区103的接 触区103’，以降低后期引出的接触电阻。两个所述体区引出掺杂区103为镜面对称设置。Two doped regions 103 for deriving body regions of the second conductivity type are also formed in the substrate 10, and the two doped regions 103 for deriving body regions 103 are respectively formed between the pole region 107' of the first conductivity type and the pole region 107' of the first conductivity type. The substrate leads out between the doped regions 102. A contact region 103' of the second conductivity type body region extraction doped region 103 is also formed in the second conductivity type body region extraction doped region 103, so as to reduce the contact resistance of the later extraction. The two doped regions 103 drawn out from the body region are arranged mirror-symmetrically.
所述体区引出掺杂区103和所述衬底引出掺杂区102之间还形成有两个第一导电类型的隔离掺杂区104，以及所述隔离掺杂区104的底部形成有第一导电类型的隔离深阱区105，所述隔离掺杂区104与所述隔离深阱区105用于将所述体区引出掺杂区103和所述衬底引出掺杂区102电隔离。所述第一导电类型的隔离掺杂区104中还形成有第一导电类型的隔离掺杂区104的接触区104’。在本实施例中，两个所述隔离掺杂区104为镜面对称设置。Two isolation doped regions 104 of the first conductivity type are also formed between the body region extraction doped region 103 and the substrate extraction doping region 102, and the bottom of the isolation doping regions 104 is formed with a second An isolated deep well region 105 of one conductivity type, the isolated doped region 104 and the isolated deep well region 105 are used for electrically isolating the body region-derived doped region 103 and the substrate-derived doped region 102 . A contact region 104' of the isolated doped region 104 of the first conductivity type is also formed in the isolated doped region 104 of the first conductivity type. In this embodiment, the two isolated doped regions 104 are arranged mirror-symmetrically.
在本实施例中，所述第一导电类型极区107’与所述体区引出掺杂区103之间、所述体区引出掺杂区103与所述隔离掺杂区104之间、以及所述隔离掺杂区104与所述衬底引出掺杂区102之间均形成有隔离结构101，所述隔离结构101例如可以为浅沟道隔离结构STI或场氧结构locos。In this embodiment, between the pole region 107' of the first conductivity type and the body-extracted doped region 103, between the body-extracted doped region 103 and the isolation doped region 104, and An isolation structure 101 is formed between the isolation doped region 104 and the substrate extraction doped region 102 , and the isolation structure 101 may be, for example, a shallow trench isolation structure STI or a field oxygen structure locos.
在本实施例中，一方面，所述体区引出掺杂区103用于体区的引出，保证器件可以接地或者抬电位，另一方面，所述体区引出掺杂区103可以保证周围的结击穿电压足够高。所述隔离掺杂区104与所述隔离深阱区105用于将所述体区引出掺杂区103和所述衬底引出掺杂区102电隔离，以将所述对称场效应晶体管做成隔离管，即体区引出掺杂区103和衬底引出掺杂区102可以分开独立地为器件进行抬电位，可大大提升器件性能。In this embodiment, on the one hand, the body-extracting doped region 103 is used to extract the body region, ensuring that the device can be grounded or raised potential; on the other hand, the body-extracting doped region 103 can ensure the surrounding The junction breakdown voltage is high enough. The isolated doped region 104 and the isolated deep well region 105 are used to electrically isolate the body-extracted doped region 103 and the substrate-extracted doped region 102, so that the symmetrical field effect transistor can be made The isolation tube, that is, the doped region 103 derived from the body region and the doped region 102 derived from the substrate can independently raise the potential for the device, which can greatly improve the performance of the device.
如上所述，本发明的对称场效应晶体管及其制作方法，具有以下有益效果：As mentioned above, the symmetrical field effect transistor and its manufacturing method of the present invention have the following beneficial effects:
本发明的对称场效应晶体管，在栅极结构106中部通过光刻工艺及刻蚀工艺形成沟槽108，沟道阱区109是在栅极结构106的沟槽108刻蚀完之后通过自对准离子注入和横向扩散形成，由于沟槽108是通过栅极结构的光刻工艺及刻蚀工艺形成的，其具有非常高的对准精度。此外，本发明工艺稳定，沟道阱区109的位置和尺寸可以精确控制。因此，本发明所制作的沟道阱区109的尺寸可以更小，从而使器件的导通电阻更低。In the symmetrical field effect transistor of the present invention, a trench 108 is formed in the middle of the gate structure 106 by a photolithography process and an etching process, and the channel well region 109 is formed by self-alignment after the trench 108 of the gate structure 106 is etched. Formed by ion implantation and lateral diffusion, since the trench 108 is formed through a photolithography process and an etching process of the gate structure, it has very high alignment accuracy. In addition, the process of the present invention is stable, and the position and size of the channel well region 109 can be precisely controlled. Therefore, the size of the channel well region 109 produced in the present invention can be smaller, so that the on-resistance of the device is lower.
本发明在栅极结构106形成沟槽108的区域通过注入在衬底中形成连接掺杂区110，可以进一步降低电流流经路径上的电阻。In the present invention, in the area where the trench 108 is formed in the gate structure 106, the connecting doped region 110 is formed in the substrate by implantation, which can further reduce the resistance on the current flow path.
所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial application value.
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。The above-mentioned embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention shall still be covered by the claims of the present invention.

Claims (15)

  1. 一种对称场效应晶体管的制作方法，其特征在于，所述制作方法包括步骤：A method for manufacturing a symmetrical field effect transistor, characterized in that the method includes the steps of:
    提供一衬底，于所述衬底上形成栅极结构以及位于所述栅极结构两侧的两个第一导电类型极区，所述衬底具有第二导电类型；providing a substrate, forming a gate structure and two pole regions of the first conductivity type on both sides of the gate structure on the substrate, the substrate having a second conductivity type;
    通过光刻工艺及刻蚀工艺于所述栅极结构的中部形成沟槽；forming a trench in the middle of the gate structure through a photolithography process and an etching process;
    通过所述沟槽对所述衬底进行第二导电类型离子注入，并使所述第二导电类型离子横向扩散至所述栅极结构的下方以形成第二导电类型的沟道阱区，所述第二导电类型的沟道阱区与所述第一导电类型极区具有间距；Implanting ions of the second conductivity type into the substrate through the trench, and laterally diffusing the ions of the second conductivity type below the gate structure to form a channel well region of the second conductivity type, There is a distance between the channel well region of the second conductivity type and the electrode region of the first conductivity type;
    通过所述沟槽对所述衬底进行第一导电类型离子注入，以在所述沟槽下方的衬底中形成第一导电类型的连接掺杂区。Ion implantation of the first conductivity type is performed on the substrate through the trench to form a connection doped region of the first conductivity type in the substrate below the trench.
  2. 根据权利要求1所述的对称场效应晶体管的制作方法，其特征在于：设置所述沟槽于两个所述第一导电类型极区的对称中心，使两个所述第一导电类型极区为镜面对称设置，两个所述第一导电类型极区与所述沟槽之间的间距相等；且使两个所述第一导电类型极区与所述第二导电类型的沟道阱区之间的间距相等。The manufacturing method of a symmetrical field effect transistor according to claim 1, characterized in that: the trench is arranged at the symmetrical center of the two first conductivity type pole regions, so that the two first conductivity type pole regions For mirror symmetrical arrangement, the distance between the two polar regions of the first conductivity type and the trench is equal; and the two polar regions of the first conductivity type and the channel well region of the second conductivity type The spacing between them is equal.
  3. 根据权利要求1所述的对称场效应晶体管的制作方法，其特征在于：使所述沟槽的底部暴露所述衬底。The manufacturing method of a symmetrical field effect transistor according to claim 1, characterized in that: the bottom of the groove exposes the substrate.
  4. 根据权利要求1所述的对称场效应晶体管的制作方法，其特征在于：使所述第二导电类型的沟道阱区位于所述栅极结构下方的部分的长度分别为0.2微米～0.3微米之间。The method for manufacturing a symmetric field effect transistor according to claim 1, characterized in that: the lengths of the parts of the channel well region of the second conductivity type located below the gate structure are respectively between 0.2 μm and 0.3 μm between.
  5. 根据权利要求1所述的对称场效应晶体管的制作方法，其特征在于，还包括步骤：于所述衬底中形成两个第二导电类型的衬底引出掺杂区，两个所述衬底引出掺杂区形成于两个所述第一导电类型极区的外侧。The manufacturing method of a symmetric field effect transistor according to claim 1, further comprising the step of: forming two substrate-extracting doped regions of the second conductivity type in the substrate, and the two substrates The extraction doped region is formed outside the two pole regions of the first conductivity type.
  6. 根据权利要求5所述的对称场效应晶体管的制作方法，其特征在于，还包括步骤：于所述衬底中形成两个第二导电类型的体区引出掺杂区，两个所述体区引出掺杂区形成于所述第一导电类型极区与所述衬底引出掺杂区之间；于所述体区引出掺杂区和所述衬底引出掺杂区之间形成两个第一导电类型的隔离掺杂区以及于所述隔离掺杂区的底部形成第一导电类型的隔离深阱区，所述隔离掺杂区与所述隔离深阱区用于将所述体区引出掺杂区和所述衬底引出掺杂区电隔离。The method for manufacturing a symmetric field effect transistor according to claim 5, further comprising the step of: forming two body regions of the second conductivity type in the substrate to lead out doped regions, and the two body regions An extraction doping region is formed between the first conductivity type electrode region and the substrate extraction doping region; two second doping regions are formed between the body region extraction doping region and the substrate extraction doping region An isolated doped region of a conductivity type and an isolated deep well region of the first conductivity type are formed at the bottom of the isolated doped region, the isolated doped region and the isolated deep well region are used to lead the body region out The doped region is electrically isolated from the doped region derived from the substrate.
  7. 根据权利要求6所述的对称场效应晶体管的制作方法，其特征在于：两个所述体区引出掺杂区为镜面对称设置，两个所述衬底引出掺杂区为镜面对称设置，两个所述隔离掺杂区为镜面对称设置。The manufacturing method of a symmetrical field effect transistor according to claim 6, characterized in that: the two doped regions drawn out from the body region are arranged mirror-symmetrically, the two doped regions drawn out from the substrate are arranged mirror-symmetrically, and the two doped regions drawn out from the substrate are arranged mirror-symmetrically. The isolated doped regions are arranged mirror-symmetrically.
  8. 一种对称场效应晶体管，其特征在于，包括：A symmetrical field effect transistor is characterized in that it comprises:
    衬底，所述衬底上形成栅极结构以及位于所述栅极结构两侧的两个第一导电类型极区，所述衬底具有第二导电类型，所述栅极结构的中部形成有沟槽；A substrate, on which a gate structure and two electrode regions of the first conductivity type are formed on both sides of the gate structure, the substrate has a second conductivity type, and the middle part of the gate structure is formed with groove;
    第二导电类型沟道阱区，形成于所述沟槽下方的所述衬底中，所述第二导电类型沟道阱区横向扩散至所述栅极结构的下方，所述第二导电类型沟道阱区与所述第一导电类型极区具有间距；A channel well region of a second conductivity type is formed in the substrate below the trench, and the channel well region of the second conductivity type laterally diffuses below the gate structure, and the channel well region of the second conductivity type There is a distance between the channel well region and the pole region of the first conductivity type;
    第一导电类型连接掺杂区，形成于所述沟槽对应的所述第二导电类型沟道阱区内。The first conductivity type connection doped region is formed in the second conductivity type channel well region corresponding to the trench.
  9. 根据权利要求8所述的对称场效应晶体管，其特征在于：所述沟槽位于两个所述第一导电类型极区的对称中心，两个所述第一导电类型极区为镜面对称设置，两个所述第一导电类型极区与所述沟槽之间的间距相等；且两个所述第一导电类型极区与所述第二导电类型沟道阱区之间的间距相等。The symmetrical field effect transistor according to claim 8, characterized in that: the trench is located at the symmetrical center of the two pole regions of the first conductivity type, and the two pole regions of the first conductivity type are mirror-symmetrically arranged, The distance between the two pole regions of the first conductivity type and the trench is equal; and the distance between the two pole regions of the first conductivity type and the channel well region of the second conductivity type is equal.
  10. 根据权利要求8所述的对称场效应晶体管，其特征在于：所述衬底中还形成有两个第二导电类型的衬底引出掺杂区，两个所述衬底引出掺杂区形成于两个所述第一导电类型极区的外侧。The symmetric field effect transistor according to claim 8, characterized in that: two substrate-extracting doped regions of the second conductivity type are formed in the substrate, and the two substrate-extracting doped regions are formed in The outer sides of the two polar regions of the first conductivity type.
  11. 根据权利要求10所述的对称场效应晶体管，其特征在于：所述衬底中还形成有两个第二导电类型的体区引出掺杂区，两个所述体区引出掺杂区形成于所述第一导电类型极区与所述衬底引出掺杂区之间，所述体区引出掺杂区和所述衬底引出掺杂区之间还形成有两个第一导电类型的隔离掺杂区以及于所述隔离掺杂区的底部形成第一导电类型的隔离深阱区，所述隔离掺杂区与所述隔离深阱区用于将所述体区引出掺杂区和所述衬底引出掺杂区电隔离。The symmetric field effect transistor according to claim 10, characterized in that: there are two second conductivity-type body-extracting doped regions formed in the substrate, and the two body-extracting doped regions are formed in Between the pole region of the first conductivity type and the substrate-derived doped region, and between the body region-derived doped region and the substrate-derived doped region, two isolations of the first conductivity type are formed. doped region and an isolated deep well region of the first conductivity type is formed at the bottom of the isolated doped region, the isolated doped region and the isolated deep well region are used to lead the body region out of the doped region and the isolated deep well region The doped region is electrically isolated from the substrate.
  12. 根据权利要求11所述的对称场效应晶体管，其特征在于：两个所述体区引出掺杂区为镜面对称设置，两个所述衬底引出掺杂区为镜面对称设置，两个所述隔离掺杂区为镜面对 称设置。The symmetric field effect transistor according to claim 11, characterized in that: the two doped regions drawn out from the body region are arranged mirror-symmetrically, the two doped regions drawn out from the substrate are arranged mirror-symmetrically, and the two doped regions drawn out from the substrate are arranged symmetrically. The isolated doped region is arranged mirror-symmetrically.
  13. 根据权利要求11所述的对称场效应晶体管，其特征在于：所述体区引出掺杂区中还形成有所述体区引出掺杂区的接触区。The symmetric field effect transistor according to claim 11, wherein a contact region of the body-extracting doped region is also formed in the body-extracting doped area.
  14. 根据权利要求8所述的对称场效应晶体管，其特征在于：所述第一导电类型极区***还形成有第一导电类型极区的漂移区，以提高击穿电压；所述第二导电类型的沟道阱区的掺杂深度大于等于所述漂移区的掺杂深度。The symmetric field effect transistor according to claim 8, characterized in that: a drift region of the first conductivity type pole region is formed around the periphery of the first conductivity type pole region to increase the breakdown voltage; the second conductivity type The doping depth of the channel well region is greater than or equal to the doping depth of the drift region.
  15. 根据权利要求8所述的对称场效应晶体管，其特征在于：所述沟槽的宽度为0.4微米～1微米之间，所述沟道阱区的宽度为0.8微米～1.6微米之间。The symmetric field effect transistor according to claim 8, characterized in that: the width of the trench is between 0.4 micron and 1 micron, and the width of the channel well region is between 0.8 micron and 1.6 micron.
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