TWI798809B - Semiconductor structure and the forming method thereof - Google Patents
Semiconductor structure and the forming method thereof Download PDFInfo
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本發明係有關於半導體結構,尤指一種橫向擴散金氧半導體(lateral diffused metal oxide semiconductor,LDMOS)電晶體元件及其製作方法。 The present invention relates to semiconductor structures, in particular to a lateral diffused metal oxide semiconductor (LDMOS) transistor element and a manufacturing method thereof.
橫向擴散金氧半導體(laterally diffused metal-oxide-semiconductor,LDMOS)元件是一種常見的功率半導體元件。由於橫向擴散金氧半導體元件具有水準式的結構,容易製造且易於和現行的半導體技術整合,進而減少製作成本。同時,其可以耐較高的崩潰電壓而具有高的輸出功率,因此被廣泛應用於功率轉換器(power converter)、功率放大器(power amplifier)、切換開關(switch)、整流器(rectifier)等元件。 A laterally diffused metal-oxide-semiconductor (LDMOS) device is a common power semiconductor device. Since the laterally diffused metal oxide semiconductor device has a horizontal structure, it is easy to manufacture and easy to integrate with the current semiconductor technology, thereby reducing the production cost. At the same time, it can withstand high breakdown voltage and has high output power, so it is widely used in power converters, power amplifiers, switches, rectifiers and other components.
然而由於LDMOS等元件通常面積較大,因此也佔用整個半導體結構將近約一半的面積。因此如何改進元件結構,使得LDMOS的面積縮減,將是業界的研究方向之一。 However, since components such as LDMOS usually have a relatively large area, they also occupy nearly half of the area of the entire semiconductor structure. Therefore, how to improve the device structure so as to reduce the area of the LDMOS will be one of the research directions in the industry.
本發明提供一種半導體結構,包含一基底,該基底具有一第一導電型態,一橫向擴散金氧半導體(laterally diffused metal-oxide-semiconductor, LDMOS)元件位於該基底上,其中該LDMOS元件包含一第一井區,位於該基底上,該第一井區有一第一導電型態,一第二井區,位於該第一井區之內,且其中一部分的該第二井區的上下兩面被該第一井區所包圍,其中該第二井區具有一第二導電型態,其中該第二導電型態與該第一導電型態互補,一源極摻雜區,位於該第二井區之內,該源極摻雜區具有該第一導電型態,以及一深汲極摻雜區,位於第一井區之內,深汲極摻雜區具有第一導電型態。 The present invention provides a semiconductor structure, including a substrate, the substrate has a first conductivity type, a laterally diffused metal-oxide-semiconductor (laterally diffused metal-oxide-semiconductor, LDMOS) element is located on the substrate, wherein the LDMOS element includes a first well area, located on the substrate, the first well area has a first conductivity type, a second well area, located within the first well area , and the upper and lower sides of a part of the second well area are surrounded by the first well area, wherein the second well area has a second conductivity type, wherein the second conductivity type is the same as the first conductivity type Complementary, a source doped region, located in the second well region, the source doped region has the first conductivity type, and a deep drain doped region, located in the first well region, deep The drain doped region has a first conductivity type.
本發明另提供一種半導體結構的形成方法,包含提供一基底,該基底具有一第一導電型態,形成一橫向擴散金氧半導體(laterally diffused metal-oxide-semiconductor,LDMOS)元件於該基底上,其中該LDMOS元件包含形成一第一井區於該基底上,該第一井區有一第一導電型態,形成一第二井區於該第一井區之內,且其中一部分的該第二井區的上下兩面被該第一井區所包圍,其中該第二井區具有一第二導電型態,其中該第二導電型態與該第一導電型態互補,形成一源極摻雜區,位於該第二井區之內,該源極摻雜區具有該第一導電型態,以及在該第一井區中形成一凹槽,並且在凹槽中形成一深汲極摻雜區於第一井區之內,深汲極摻雜區具有第一導電型態。 The present invention further provides a method for forming a semiconductor structure, including providing a substrate having a first conductivity type, forming a laterally diffused metal-oxide-semiconductor (LDMOS) device on the substrate, Wherein the LDMOS device includes forming a first well region on the substrate, the first well region has a first conductivity type, forming a second well region within the first well region, and a part of the second well region The upper and lower sides of the well region are surrounded by the first well region, wherein the second well region has a second conductivity type, wherein the second conductivity type is complementary to the first conductivity type, forming a source doped region, located within the second well region, the source doped region has the first conductivity type, and a groove is formed in the first well region, and a deep drain doped region is formed in the groove The region is within the first well region, and the deep drain doped region has the first conductivity type.
本發明的特徵在於,提供一種降低表面場的橫向擴散金屬氧化物半導體場效應電晶體(Reduced Surface Field Laterally Diffused MOSFET,簡稱為RESURF LDMOS)。該RESURF LDMOS的形成過程中,在一第一井區中形成一凹槽,接著在該凹槽中填入高摻雜濃度的多晶矽材質,或是以摻雜方式形成U型剖面的離子摻雜區,以在第一井區中形成一深汲極摻雜區。有別於習知方式在第一井區中以離子佈植與加熱擴散的方式形成深汲極摻雜區,本案的深汲極摻雜區所需面積大幅減少,因此也可減少元件的總面積,達到微型化的效果。此 外深汲極摻雜區具有高摻雜濃度,較不容易產生電壓降,也因此可以提高產品的品質。 The present invention is characterized in that it provides a reduced surface field laterally diffused metal oxide semiconductor field effect transistor (Reduced Surface Field Laterally Diffused MOSFET, referred to as RESURF LDMOS). In the formation process of the RESURF LDMOS, a groove is formed in a first well region, and then polysilicon material with a high doping concentration is filled in the groove, or ion doping to form a U-shaped profile by doping region to form a deep drain doped region in the first well region. Different from the conventional method in which the deep drain doped region is formed by ion implantation and heating diffusion in the first well region, the required area of the deep drain doped region in this case is greatly reduced, so the total size of the device can also be reduced. area, to achieve the effect of miniaturization. this The outer deep drain doped region has a high doping concentration, which is less prone to voltage drop, and thus can improve product quality.
1:降低表面場的橫向擴散金屬氧化物半導體場效應電晶體(RESURF LDMOS)結構 1: Laterally diffused metal-oxide-semiconductor field-effect transistor (RESURF LDMOS) structure with reduced surface field
10:基底 10: Base
12:第一井區 12: The first well area
14:阻障層 14: Barrier layer
16:漂移區 16: Drift zone
20:第二井區 20: Second well area
22:絕緣層 22: Insulation layer
24:凹槽 24: Groove
25:光阻層 25: photoresist layer
26:多晶矽層 26: Polysilicon layer
27:深汲極摻雜區 27: Deep drain doped region
27A:深汲極摻雜區 27A: Deep drain doped region
28:閘極結構 28:Gate structure
29:閘極介電層 29: Gate dielectric layer
30:閘極導電層 30: Gate conductive layer
32:源極摻雜區 32: Source doped region
34:淺汲極摻雜區 34: shallow drain doped region
34A:離子摻雜區 34A: Ion-doped area
36:基體區 36: Matrix area
40:金屬矽化物層 40: metal silicide layer
42:介電層 42: Dielectric layer
44:接觸結構 44: Contact structure
44A:接觸結構 44A: Contact structure
45:襯墊層 45: Cushion layer
46:導電層 46: Conductive layer
50:絕緣層 50: insulating layer
60:絕緣層 60: insulation layer
A:區域 A: area
B:區域 B: area
C:區域 C: area
G:間距 G: Spacing
P1:摻雜步驟 P1: Doping step
第1圖至第7圖繪示本發明形成一降低表面場的橫向擴散金屬氧化物半導體場效應電晶體(Reduced Surface Field Laterally Diffused MOSFET,簡稱為RESURF LDMOS)的流程示意圖。 FIG. 1 to FIG. 7 are schematic flow charts of forming a Reduced Surface Field Laterally Diffused MOSFET (RESURF LDMOS for short) according to the present invention.
第8圖繪示一以離子佈植與加熱步驟形成深汲極摻雜區的RESURF LDMOS的結構示意圖。 FIG. 8 shows a schematic structure diagram of a RESURF LDMOS in which a deep drain doped region is formed by ion implantation and heating steps.
第9圖繪示一P型RESURF LDMOS的結構示意圖。 FIG. 9 shows a schematic structure diagram of a P-type RESURF LDMOS.
第10-11圖分別繪示根據本發明另兩個實施例的RESURF LDMOS的結構示意圖。 10-11 are schematic structural diagrams of RESURF LDMOS according to two other embodiments of the present invention, respectively.
第12-14圖繪示根據本發明另一個實施例的RESURF LDMOS的結構示意圖。 12-14 are schematic structural diagrams of RESURF LDMOS according to another embodiment of the present invention.
為使熟習本發明所屬技術領域之一般技藝者能更進一步了解本發明,下文特列舉本發明之較佳實施例,並配合所附圖式,詳細說明本發明的構成內容及所欲達成之功效。 In order to enable those who are familiar with the general skills in the technical field of the present invention to further understand the present invention, the preferred embodiments of the present invention are enumerated below, together with the accompanying drawings, the composition of the present invention and the desired effects are described in detail. .
為了方便說明,本發明之各圖式僅為示意以更容易了解本發明,其詳細的比例可依照設計的需求進行調整。在文中所描述對於圖形中相對元件之上下關係,在本領域之人皆應能理解其係指物件之相對位置而言,因此皆可以翻轉而呈現相同之構件,此皆應同屬本說明書所揭露之範圍,在此容先敘明。 For the convenience of description, the drawings of the present invention are only schematic diagrams for easier understanding of the present invention, and the detailed proportions thereof can be adjusted according to design requirements. As for the up-down relationship of relative elements in the figures described in the text, those skilled in the art should understand that they refer to the relative positions of objects, so they can be reversed to present the same components, which should all belong to this specification. The scope of disclosure is described here first.
請參考第1圖至第7圖,第1圖至第7圖繪示本發明形成一降低表面場的橫向擴散金屬氧化物半導體場效應電晶體(Reduced Surface Field Laterally Diffused MOSFET,簡稱為RESURF LDMOS)的流程示意圖。如第1圖所示,提供一基底10,在基底10內以例如摻雜等方式形成一第一井區12以及一第二井區20。值得注意的是,基底10例如為矽基底(單晶矽),第一井區12位於基底10上,包含有一第一導電型態(例如N型,第一井區12可以包含有一阻障層14以及一漂移區16,兩者相互連接且具有同樣導電型態(例如N型)。第二井區20則包含有與第一導電型態互補的第二導電型態(例如P型)。本實施例中,基底10例如為P型基底。
Please refer to FIG. 1 to FIG. 7. FIG. 1 to FIG. 7 illustrate the formation of a reduced surface field laterally diffused metal-oxide-semiconductor field-effect transistor (Reduced Surface Field Laterally Diffused MOSFET, referred to as RESURF LDMOS) according to the present invention. schematic diagram of the process. As shown in FIG. 1 , a
值得注意的是,如第1圖所示,有一部分的第二井區20橫向深入第一井區12之內,且部分第二井區20的上下兩面被第一井區12所包圍,形成第一井區12與第二井區20相互交錯的結構。換句話說,一部分第二井區20的延伸部,位於第一井區12的阻障層14以及漂移區16之間。在實際製作過程中,可以先在基底10上形成阻障層14,然後形成第二井區20之後,再於一部分的第二井區20中摻雜離子而形成漂移區16。
It is worth noting that, as shown in Figure 1, part of the
後續步驟中,將這種井區的分佈結構製成LDMOS元件時,有利於在N-P介面處形成空乏區阻擋電流通過,讓LDMOS在關閉狀態時可承受較大的電壓差,此種結構比起一般的LDMOS所需要的面積更小,因此上述LDMOS也可簡稱為降低表面場的橫向擴散金屬氧化物半導體場效應電晶體(Reduced Surface Field Laterally Diffused MOSFET,簡稱為RESURF LDMOS)。關於RESURF LDMOS的其他介紹,已經揭露於部分先前技術中(例如美國專利證書號US 9484454),因此在此不多加贅述。 In the subsequent steps, when the distribution structure of this well region is made into LDMOS elements, it is beneficial to form a depletion region at the N-P interface to block the passage of current, so that the LDMOS can withstand a large voltage difference when it is off. The area required by the LDMOS is smaller, so the above LDMOS can also be referred to as a Reduced Surface Field Laterally Diffused MOSFET (Resurf LDMOS for short). Other introductions about RESURF LDMOS have already been disclosed in some prior art (such as US Patent No. US 9484454), so details will not be repeated here.
本發明在RESURF LDMOS的架構下進行改進,以達到減少元件面積以及增加元件品質的效果。如第2圖所示,形成一圖案化的絕緣層22位於第一井區12以及第二井區20的表面,絕緣層22例如為氧化矽或是氮化矽,但不限於此。然後以絕緣層22為遮罩,在第一井區12中形成一凹槽24,凹槽24例如可以用圖案化與蝕刻等方式形成,但不限於此。另外本實施例中,凹槽24的寬度較佳小於0.5微米,深度大於8微米,但不限於此。本實施例中,凹槽24的寬度約為0.3微米,而深度較佳大於阻障層14與第二井區20的交界面。
The present invention is improved under the structure of RESURF LDMOS, so as to achieve the effect of reducing the element area and increasing the element quality. As shown in FIG. 2 , a patterned insulating
接著如第3圖所示,形成一多晶矽層26填滿凹槽24,其中多晶矽層26例如為具有高摻雜濃度的多晶矽層,可以藉由原位(in-situ)摻雜製程形成,其具有第一導電型態(例如N型)。本實施例中,多晶矽層26的濃度較佳大於1E18cm3上述濃度較習知步驟中,以離子佈植與加熱步驟等方式所形成的摻雜區濃度更高。
Next, as shown in FIG. 3, a
接著如第4圖所示,以回蝕刻或是化學機械研磨等方式,移除多餘的多晶矽層26與絕緣層22,以曝露出第一井區12與第二井區20的表面。此處剩餘在凹槽24內的多晶矽層26,又可以被定義為深汲極摻雜區27,其作用將會在下面段落繼續描述。
Next, as shown in FIG. 4 , the
如第5圖所示,形成一閘極結構28於第一井區12以及第二井區20上,其中閘極結構28包含有閘極介電層29以及閘極導電層30,其中閘極介電層29在漂移區16上方的厚度較厚,而在第一井區12以及第二井區20在表面的交界處附近則具有較薄的厚度。上述閘極結構28屬於RESURF LDMOS的習知技術,其餘
特徵不多加贅述。
As shown in FIG. 5, a
繼續參考第6圖,在閘極結構28完成後,以離子摻雜與加熱步驟等方式分別在第一井區12以及第二井區14內至少形成源極(source)摻雜區32以及淺汲極(drain)摻雜區34。其中源極摻雜區32與淺汲極摻雜區34都包含有第一導電型態(例如N型),且淺汲極摻雜區34與上述深汲極摻雜區27連接。值得注意的是,由於源極摻雜區32與淺汲極摻雜區34都是以離子摻雜以及加熱的步驟形成於單晶矽成分的井區之中,因此其材質也是單晶矽,且材質不同於深汲極摻雜區27。另外,本實施例中,源極摻雜區32以及淺汲極摻雜區34的離子摻雜濃度例如為大於1E20cm3。除此之外,在一些實施例中,可以在源極摻雜區32旁另外形成有基體區(body)36,其中基體區36例如為包含有第二導電型態(例如P型)的摻雜區。
Continuing to refer to FIG. 6, after the
如第7圖所示,可以選擇性地在閘極結構28、第一井區12與第二井區20的表面形成金屬矽化物層40。接著形成一介電層42覆蓋於上述元件後,在介電層42中形成接觸結構44,接觸結構連接到源極摻雜區32與淺汲極摻雜區34。其中在一些實施例中,金屬矽化物層40可以省略不形成,或是在介電層42完成後,將金屬矽化物層40形成於接觸結構44底下。介電層42例如為氧化矽或氮化矽,而接觸結構44可能包含有襯墊層45,其材質例如為鈦/氮化鈦,以及導電層46,其材質例如為鎢(W)。上述元件的其他細節與製作方法,屬於本領域的習知技術,在此不多贅述。至此已完成本發明所述的RESURF LDMOS結構1。由於本實施例中RESURF LDMOS結構1的第一井區12為N型,因此本實施例的RESURF LDMOS結構1又可定義為N型RESURF LDMOS結構。
As shown in FIG. 7 , the
本發明的RESURF LDMOS結構1,在閘極結構28關閉時,源極端與
汲極端仍具有電位差,例如在汲極端上方的接觸結構44導入高電壓(例如100V),而源極端維持0電位,此時由於深汲極摻雜區27的摻雜濃度高且導電性佳,因此傳導至下方的電壓僅有少量降低。電壓會使得第一井區12維持高電位,而第二井區20保持低電位,使得位於RESURF LDMOS結構1中央部分的N-P交界面產生空乏區。例如第7圖中的區域A、B、C,皆是可能產生空乏區的區域。也就是說,當RESURF LDMOS結構1的閘極結構28關閉時,除了通道區關閉可以造成隔絕之外,中央產生的空乏區也能進一步隔絕電流,讓RESURF LDMOS結構1可以承受高電壓的運作模式。
In the RESURF LDMOS structure 1 of the present invention, when the
為了讓上述空乏區可以順利形成,習知技術中較佳將深汲極摻雜區的深度製作得更深,以讓電壓可以順利傳導至下方靠近阻障層14的部分,並且順利產生空乏區。第8圖繪示一以離子佈植與加熱步驟形成深汲極摻雜區的RESURF LDMOS的結構示意圖。習知技術中,以離子佈植與加熱步驟來增加深汲極摻雜區的深度,然而,離子在加熱的同時也會朝向橫向擴散,因此習知技術中深汲極摻雜區的寬度較大(如第8圖中的離子摻雜區34A),如此一來將會導致元件的面積過大,不利於元件的微小化。舉例來說,習知技術中離子摻雜區34A的深度若要達到8微米,則其寬度約會擴散到12微米左右。此外,離子摻雜區34A的摻雜濃度不如本發明的深汲極摻雜區27,故導電性也不如深汲極摻雜區27。當從離子摻雜區34A上方導入高電壓(例如100V)時,傳導至離子摻雜區34A下方的電壓將會下降得更多,如此不利於空乏區的形成。
In order to smoothly form the above-mentioned depletion region, it is preferable to make the depth of the deep-drain doped region deeper in the prior art, so that the voltage can be smoothly transmitted to the lower part close to the
本發明的RESURF LDMOS結構1與習知技術中的RESURF LDMOS結構的主要不同處在於形成深汲極摻雜區27取代部份的離子摻雜區,上述深汲極摻雜區27以蝕刻凹槽24與回填多晶矽層26的方式所形成。其中,凹槽24的寬
度可以遠小於上述習知技術中離子摻雜區34A的寬度,另一個特徵是在凹槽24中填入更高摻雜濃度且導電性更好的多晶矽層26,不但可以大幅度減少元件面積(因為深汲極摻雜區27的寬度較小),且深汲極摻雜區27的導電效果更佳,使得來自上方接觸結構44的高電壓,可以順利地傳導至深汲極摻雜區27的下方,進一步再傳導到第一井區12內,讓空乏區可以順利形成。總之,本發明具有減少元件面積、提高元件品質以及與現有製程相容等優點。
The main difference between the RESURF LDMOS structure 1 of the present invention and the RESURF LDMOS structure in the prior art is that a deep drain doped
在上述實施例中(第1圖到第7圖),以製作N型RESURF LDMOS結構為例,也就是第一井區12以及深汲極摻雜區27為N型、第二井區20為P型。但在本發明的其他實施例中,也可以製作P型RESURF LDMOS結構。如第9圖所示,第9圖繪示一P型RESURF LDMOS的結構示意圖。其中,多數元件的結構、材質與製作方法與上述第一較佳實施例相同而不多贅述,與上述實施例不同之處在於,本實施例中基底10、第一井區12、深汲極摻雜區27、源極摻雜區32與淺汲極摻雜區34為P型,而第二井區20與基體區36則是N型。值得注意的是,本實施例中深汲極摻雜區27並不接觸第二井區20,且深汲極摻雜區27以及第二井區20之間維持有一間距G,以避免在汲極端導入高電位時,具有較高摻雜濃度的深汲極摻雜區27與具有較低摻雜濃度的第二井區20之間產生電流擊穿(punch through)而引起元件崩潰(breakdown)。
In the above-mentioned embodiments (Fig. 1 to Fig. 7), the N-type RESURF LDMOS structure is taken as an example, that is, the
同樣地,在本發明的其他實施例中,為了避免橫向的電流擊穿,可以在深汲極摻雜區27旁邊或是下方設置絕緣層。請參考第10-11圖,第10-11圖分別繪示根據本發明另兩個實施例的RESURF LDMOS的結構示意圖。如第10圖所示,本實施例中額外形成一絕緣層50在深汲極摻雜區27旁邊,絕緣層50例如為氧化矽、或是外圍被氧化矽所包圍的多晶矽層。絕緣層50的深度可以比深汲極
摻雜區27的深度更深,且絕緣層50設置在第一井區12旁的基底10內,在一些實施例中,深溝渠隔離(deep trench isolation,DTI)可以當作此處的絕緣層50。絕緣層50具有防止深汲極摻雜區27擊穿第一井區12而影響其他相鄰元件的功能。
Likewise, in other embodiments of the present invention, in order to avoid lateral current breakdown, an insulating layer may be disposed beside or below the deep drain doped
在另一實施例中,如第11圖所示,除了設置上述的絕緣層50以外,本實施例中將部分的阻障層14以另一絕緣層60取代。絕緣層60例如為氧化矽。在一些實施例中,可以用矽覆絕緣層(silicon on substrate,SOI)基底來代替原本的矽基底,以達到如第11圖所示的結構。在本實施例中,絕緣層60同樣可以防止縱向方向的電流擊穿。
In another embodiment, as shown in FIG. 11 , in addition to the above-mentioned insulating
在本發明的其他實施例中,也可以在同一基底上形成不同的LDMOS。舉例來說,可以將N型RESURF LDMOS(第7圖所示的結構)與P型RESURF LDMOS(第9圖所示的結構)一起形成在同一基底的不同區域上。此結構也屬於本發明的涵蓋範圍內。 In other embodiments of the present invention, different LDMOSs can also be formed on the same substrate. For example, N-type RESURF LDMOS (structure shown in FIG. 7 ) and P-type RESURF LDMOS (structure shown in FIG. 9 ) can be formed together on different regions of the same substrate. This structure also falls within the scope of the present invention.
在以上的實施例中,在凹槽24中填入高摻雜濃度的多晶矽層26,藉以形成寬度較窄的多晶矽深汲極摻雜區27。另外在本發明的其他實施例中,也可以藉由在凹槽24內以摻雜或是電漿佈植等其他方式,在第一井區12內形成寬度較窄且深度足夠的深汲極摻雜區,詳細如下第12圖至第14圖所示。
In the above embodiments, the
如第12圖所示,在本實施例中,形成凹槽24之後(接續第一實施例的第1圖與第2圖的步驟),先形成一光阻層25覆蓋部分的第一井區12與第二井區20,並且同時曝露出部分的第一井區12與第二井區20,其中被曝露的區域包含有凹槽24、以及第二井區20中預定要形成源極摻雜區32的位置。接下來,進行
一摻雜步驟P1,對未被光阻層25覆蓋的區域進行摻雜,在本實施例中,以摻雜高濃度的N型離子為例,但本發明的其他實施例中,也可能摻雜高濃度的P型離子,本發明不以此為限制。此外,凹槽24、源極摻雜區32、閘極結構28也可以分別用不同光罩進行個別獨立的摻雜,本發明不以此為限制。
As shown in Figure 12, in this embodiment, after forming the groove 24 (continuing the steps in Figure 1 and Figure 2 of the first embodiment), a
值得注意的是,本實施例中離子摻雜步驟P1過程中可以調整其摻雜角度,例如以斜向方向進行摻雜,因此所摻雜的離子,可以深入至凹槽24的底面以及側壁,在凹槽24的底面與側壁形成深汲極摻雜區27A。與前述實施例所提及的深汲極摻雜區27不同的是,本實施例中的深汲極摻雜區27A因為以離子摻雜的方式形成在第一井區12的凹槽24外圍,因此具有U型的剖面輪廓,且深汲極摻雜區27A的材質與第一井區12相同,兩者均為單晶矽。此外,本實施例中在形成深汲極摻雜區27A的同時,也同時可在第二井區20內形成源極摻雜區32,因此可以達到節省步驟的功效。此外凹槽24亦可以使用電漿摻雜(plasma doping)方式進行摻雜,本發明不以此為限制。
It is worth noting that the doping angle can be adjusted during the ion doping step P1 in this embodiment, for example, doping in an oblique direction, so that the doped ions can penetrate deep into the bottom surface and sidewall of the
接著,如第13圖所示,移除光阻層25,之後在源極摻雜區32旁邊形成基體區36,此處的基體區36例如是以摻雜的方式形成的一P型摻雜區。然後再形成金屬矽化物層40,其中金屬矽化物層40覆蓋在閘極結構28、第一井區12、第二井區20與凹槽24(即深汲極摻雜區27A)的表面。此外本發明亦可以不用形成金屬矽化物層、或選擇性的形成金屬矽化物層於基底,或閘極結構,或凹槽內表面,本發明不以此為限制。
Next, as shown in FIG. 13, the
然後如第14圖所示,形成介電層42以及接觸結構44以及接觸結構44A。其中介電層42例如為氧化矽或氮化矽,而接觸結構44與接觸結構44A可能
包含有襯墊層45,其材質例如為鈦/氮化鈦,以及導電層46,其材質例如為鎢(W)。此處關於形成基體區36、金屬矽化物層40與接觸結構44、44A的步驟與上述實施例相似(可參考第6圖與第7圖的描述)相似,在此不多加贅述。值得注意的是,本實施例中的接觸結構44A形成在凹槽24內,也就是形成在深汲極摻雜區27A上。接觸結構44A深入第一井區12內,也就是接觸結構44A的底面低於第一井區12的頂面,因此可以有效地將來自上方其他元件的電流傳導至下方。
Then, as shown in FIG. 14 , a
綜合以上第12圖至第14圖,本實施例以另一種方式形成深汲極摻雜區27A,其在凹槽中藉由摻雜或是離子佈植等方式形成深汲極摻雜區。其中深汲極摻雜區的深度足夠將來自上方的電流傳導至下方。在另一實施例中,深汲極摻雜區的寬度也小於0.5微米,同樣具有節省空間的功效。此外本實施例也與現有的製程相容。此外,本實施例中以製作N型RESURF LDMOS結構為例,但可以調整摻雜離子的種類,而製作P型的RESURF LDMOS結構。也就是將本實施例中在凹槽內摻雜離子的方法,應用於第9圖的實施例中,也屬於本發明的涵蓋範圍。
Based on the above-mentioned FIG. 12 to FIG. 14 , this embodiment forms the deep-drain doped
綜合以上說明書與圖式,本發明提供一種半導體結構,包含一基底10,一橫向擴散金氧半導體(laterally diffused metal-oxide-semiconductor,LDMOS)元件位於該基底10上,其中該LDMOS元件包含:一第一井區12,位於該基底10上,該第一井區12有一第一導電型態,一第二井區20,位於該第一井區12之內,且其中一部分的該第二井區20的上下兩面被該第一井區12所包圍,其中該第二井區20具有一第二導電型態,其中該第二導電型態與該第一導電型態互補,一源極摻雜區32,位於該第二井區20之內,該源極摻雜區32具有該第一導電型態,以及一深汲極摻雜區(27或27A),位於第一井區12之內,深汲極摻
雜區(27或27A)具有第一導電型態。在另一實施例中,其深汲極摻雜區(27或27A)的一寬度小於0.5微米。
Based on the above description and drawings, the present invention provides a semiconductor structure, including a
本發明另提供一種半導體結構的形成方法,包含提供一基底10,形成一橫向擴散金氧半導體(laterally diffused metal-oxide-semiconductor,LDMOS)元件位於基底上,其中形成LDMOS元件的步驟包含:形成一第一井區12於基底10上,第一井區12有一第一導電型態,形成一第二井區20於第一井區12之內,且其中一部分的第二井區20的上下兩面被第一井區12所包圍,其中第二井區20具有一第二導電型態,其中第二導電型態與第一導電型態互補,形成一源極摻雜區32,位於第二井區20之內,源極摻雜區32具有第一導電型態,以及在第一井區12中形成一凹槽24,並且在凹槽24中形成一深汲極摻雜區(27或27A)於第一井區12之內,深汲極摻雜區(27或27A)具有第一導電型態。在另一實施例中,其深汲極摻雜區(27或27A)的一寬度小於0.5微米。
The present invention further provides a method for forming a semiconductor structure, including providing a
在一些實施例中,其中第一井區12與第二井區20的材質均包含單晶矽,而深汲極摻雜區27的材質包含多晶矽,且深汲極摻雜區27的形狀包含一柱狀體。
In some embodiments, the materials of the
在一些實施例中,其中第一井區12、第二井區20與深汲極摻雜區27A的材質均包含單晶矽,深汲極摻雜區27A具有一U型剖面輪廓
In some embodiments, the materials of the
在一些實施例中,其中更包含有一接觸結構44A,位於第一井區12上,並且與深汲極摻雜區27A電性連接,其中接觸結構44A的一底面低於該第一井區12的一頂面。
In some embodiments, it further includes a
在一些實施例中,其中深汲極摻雜區27的一摻雜濃度高於1E18cm3。
In some embodiments, a doping concentration of the deep-drain doped
在一些實施例中,更包含有一淺汲極摻雜區34,位於第一井區12之內,並且連接深汲極摻雜區27。
In some embodiments, it further includes a shallow drain doped
在一些實施例中,其中第一井區12包含有一阻障層14以及一漂移區16相互連接,且部分第二井區20位元於阻障層14與漂移區16之間。
In some embodiments, the
在一些實施例中,更包含有至少一絕緣結構50,位於深汲極摻雜區27旁邊。
In some embodiments, at least one insulating
在一些實施例中,其中第一導電型態包含N型,第二導電型態包含P型。 In some embodiments, the first conductivity type includes N type, and the second conductivity type includes P type.
在一些實施例中,其中第一導電型態包含P型,第二導電型態包含N型。 In some embodiments, the first conductivity type includes P type, and the second conductivity type includes N type.
本發明的特徵在於,提供一種降低表面場的橫向擴散金屬氧化物半導體場效應電晶體(Reduced Surface Field Laterally Diffused MOSFET,簡稱為RESURF LDMOS)。該RESURF LDMOS的形成過程中,在一第一井區中形成一凹槽,接著在該凹槽中填入高摻雜濃度的多晶矽材質,或是以摻雜方式形成U型剖面的離子摻雜區,以在第一井區中形成一深汲極摻雜區。有別於習知方式在第一井區中以離子佈植與加熱擴散的方式形成深汲極摻雜區,本案的深汲極摻 雜區所需面積大幅減少,因此也可減少元件的總面積,達到微型化的效果。此外深汲極摻雜區具有高摻雜濃度,較不容易產生壓降,也因此可以提高產品的品質。 The present invention is characterized in that it provides a reduced surface field laterally diffused metal oxide semiconductor field effect transistor (Reduced Surface Field Laterally Diffused MOSFET, referred to as RESURF LDMOS). In the formation process of the RESURF LDMOS, a groove is formed in a first well region, and then polysilicon material with a high doping concentration is filled in the groove, or ion doping to form a U-shaped profile by doping region to form a deep drain doped region in the first well region. Different from the conventional method in which the deep drain doped region is formed by ion implantation and heating diffusion in the first well area, the deep drain doped region in this case The required area of the miscellaneous area is greatly reduced, so the total area of the components can also be reduced to achieve the effect of miniaturization. In addition, the deep-drain doped region has a high doping concentration, which is less prone to voltage drop, and thus can improve product quality.
以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。 The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.
1:降低表面場的橫向擴散金屬氧化物半導體場效應電晶體(RESURF LDMOS)結構 1: Laterally diffused metal-oxide-semiconductor field-effect transistor (RESURF LDMOS) structure with reduced surface field
10:基底 10: Base
12:第一井區 12: The first well area
20:第二井區 20: Second well area
27:深汲極摻雜區 27: Deep drain doped region
28:閘極結構 28:Gate structure
32:源極摻雜區 32: Source doped region
34:深汲極摻雜區 34: Deep drain doped region
36:基體區 36: Matrix area
40:金屬矽化物層 40: metal silicide layer
42:介電層 42: Dielectric layer
44:接觸結構 44: Contact structure
45:襯墊層 45: Cushion layer
46:導電層 46: Conductive layer
A:區域 A: area
B:區域 B: area
C:區域 C: area
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