TWI798809B

TWI798809B - Semiconductor structure and the forming method thereof

Info

Publication number: TWI798809B
Application number: TW110132665A
Authority: TW
Inventors: 藤卷浩和; 蔡博安; 李世平
Original assignee: 力晶積成電子製造股份有限公司
Priority date: 2021-06-18
Filing date: 2021-09-02
Publication date: 2023-04-11
Also published as: TW202301676A

Abstract

A semiconductor structure, the semiconductor structure includes a substrate with a first conductivity type and a laterally diffused metal-oxide-semiconductor (LDMOS) device on the substrate, the LDMOS device includes a first well region on the substrate, and the first well region has a first conductivity type. A second well region with a second conductivity type, the second conductivity type is complementary to the first conductivity type, a source doped region in the second well region with the first conductivity type, and a deep drain doped region located in the first well region, the deep drain doped region has a first conductivity type.

Description

半導體結構以及其形成方法 Semiconductor structure and method of forming same

本發明係有關於半導體結構，尤指一種橫向擴散金氧半導體(lateral diffused metal oxide semiconductor，LDMOS)電晶體元件及其製作方法。 The present invention relates to semiconductor structures, in particular to a lateral diffused metal oxide semiconductor (LDMOS) transistor element and a manufacturing method thereof.

橫向擴散金氧半導體(laterally diffused metal-oxide-semiconductor，LDMOS)元件是一種常見的功率半導體元件。由於橫向擴散金氧半導體元件具有水準式的結構，容易製造且易於和現行的半導體技術整合，進而減少製作成本。同時，其可以耐較高的崩潰電壓而具有高的輸出功率，因此被廣泛應用於功率轉換器(power converter)、功率放大器(power amplifier)、切換開關(switch)、整流器(rectifier)等元件。 A laterally diffused metal-oxide-semiconductor (LDMOS) device is a common power semiconductor device. Since the laterally diffused metal oxide semiconductor device has a horizontal structure, it is easy to manufacture and easy to integrate with the current semiconductor technology, thereby reducing the production cost. At the same time, it can withstand high breakdown voltage and has high output power, so it is widely used in power converters, power amplifiers, switches, rectifiers and other components.

然而由於LDMOS等元件通常面積較大，因此也佔用整個半導體結構將近約一半的面積。因此如何改進元件結構，使得LDMOS的面積縮減，將是業界的研究方向之一。 However, since components such as LDMOS usually have a relatively large area, they also occupy nearly half of the area of the entire semiconductor structure. Therefore, how to improve the device structure so as to reduce the area of the LDMOS will be one of the research directions in the industry.

本發明提供一種半導體結構，包含一基底，該基底具有一第一導電型態，一橫向擴散金氧半導體(laterally diffused metal-oxide-semiconductor， LDMOS)元件位於該基底上，其中該LDMOS元件包含一第一井區，位於該基底上，該第一井區有一第一導電型態，一第二井區，位於該第一井區之內，且其中一部分的該第二井區的上下兩面被該第一井區所包圍，其中該第二井區具有一第二導電型態，其中該第二導電型態與該第一導電型態互補，一源極摻雜區，位於該第二井區之內，該源極摻雜區具有該第一導電型態，以及一深汲極摻雜區，位於第一井區之內，深汲極摻雜區具有第一導電型態。 The present invention provides a semiconductor structure, including a substrate, the substrate has a first conductivity type, a laterally diffused metal-oxide-semiconductor (laterally diffused metal-oxide-semiconductor, LDMOS) element is located on the substrate, wherein the LDMOS element includes a first well area, located on the substrate, the first well area has a first conductivity type, a second well area, located within the first well area , and the upper and lower sides of a part of the second well area are surrounded by the first well area, wherein the second well area has a second conductivity type, wherein the second conductivity type is the same as the first conductivity type Complementary, a source doped region, located in the second well region, the source doped region has the first conductivity type, and a deep drain doped region, located in the first well region, deep The drain doped region has a first conductivity type.

本發明另提供一種半導體結構的形成方法，包含提供一基底，該基底具有一第一導電型態，形成一橫向擴散金氧半導體(laterally diffused metal-oxide-semiconductor，LDMOS)元件於該基底上，其中該LDMOS元件包含形成一第一井區於該基底上，該第一井區有一第一導電型態，形成一第二井區於該第一井區之內，且其中一部分的該第二井區的上下兩面被該第一井區所包圍，其中該第二井區具有一第二導電型態，其中該第二導電型態與該第一導電型態互補，形成一源極摻雜區，位於該第二井區之內，該源極摻雜區具有該第一導電型態，以及在該第一井區中形成一凹槽，並且在凹槽中形成一深汲極摻雜區於第一井區之內，深汲極摻雜區具有第一導電型態。 The present invention further provides a method for forming a semiconductor structure, including providing a substrate having a first conductivity type, forming a laterally diffused metal-oxide-semiconductor (LDMOS) device on the substrate, Wherein the LDMOS device includes forming a first well region on the substrate, the first well region has a first conductivity type, forming a second well region within the first well region, and a part of the second well region The upper and lower sides of the well region are surrounded by the first well region, wherein the second well region has a second conductivity type, wherein the second conductivity type is complementary to the first conductivity type, forming a source doped region, located within the second well region, the source doped region has the first conductivity type, and a groove is formed in the first well region, and a deep drain doped region is formed in the groove The region is within the first well region, and the deep drain doped region has the first conductivity type.

本發明的特徵在於，提供一種降低表面場的橫向擴散金屬氧化物半導體場效應電晶體(Reduced Surface Field Laterally Diffused MOSFET，簡稱為RESURF LDMOS)。該RESURF LDMOS的形成過程中，在一第一井區中形成一凹槽，接著在該凹槽中填入高摻雜濃度的多晶矽材質，或是以摻雜方式形成U型剖面的離子摻雜區，以在第一井區中形成一深汲極摻雜區。有別於習知方式在第一井區中以離子佈植與加熱擴散的方式形成深汲極摻雜區，本案的深汲極摻雜區所需面積大幅減少，因此也可減少元件的總面積，達到微型化的效果。此外深汲極摻雜區具有高摻雜濃度，較不容易產生電壓降，也因此可以提高產品的品質。 The present invention is characterized in that it provides a reduced surface field laterally diffused metal oxide semiconductor field effect transistor (Reduced Surface Field Laterally Diffused MOSFET, referred to as RESURF LDMOS). In the formation process of the RESURF LDMOS, a groove is formed in a first well region, and then polysilicon material with a high doping concentration is filled in the groove, or ion doping to form a U-shaped profile by doping region to form a deep drain doped region in the first well region. Different from the conventional method in which the deep drain doped region is formed by ion implantation and heating diffusion in the first well region, the required area of the deep drain doped region in this case is greatly reduced, so the total size of the device can also be reduced. area, to achieve the effect of miniaturization. this The outer deep drain doped region has a high doping concentration, which is less prone to voltage drop, and thus can improve product quality.

1:降低表面場的橫向擴散金屬氧化物半導體場效應電晶體(RESURF LDMOS)結構 1: Laterally diffused metal-oxide-semiconductor field-effect transistor (RESURF LDMOS) structure with reduced surface field

10:基底 10: Base

12:第一井區 12: The first well area

14:阻障層 14: Barrier layer

16:漂移區 16: Drift zone

20:第二井區 20: Second well area

22:絕緣層 22: Insulation layer

24:凹槽 24: Groove

25:光阻層 25: photoresist layer

26:多晶矽層 26: Polysilicon layer

27:深汲極摻雜區 27: Deep drain doped region

27A:深汲極摻雜區 27A: Deep drain doped region

28:閘極結構 28:Gate structure

29:閘極介電層 29: Gate dielectric layer

30:閘極導電層 30: Gate conductive layer

32:源極摻雜區 32: Source doped region

34:淺汲極摻雜區 34: shallow drain doped region

34A:離子摻雜區 34A: Ion-doped area

36:基體區 36: Matrix area

40:金屬矽化物層 40: metal silicide layer

42:介電層 42: Dielectric layer

44:接觸結構 44: Contact structure

44A:接觸結構 44A: Contact structure

45:襯墊層 45: Cushion layer

46:導電層 46: Conductive layer

50:絕緣層 50: insulating layer

60:絕緣層 60: insulation layer

A:區域 A: area

B:區域 B: area

C:區域 C: area

G:間距 G: Spacing

P1:摻雜步驟 P1: Doping step

第1圖至第7圖繪示本發明形成一降低表面場的橫向擴散金屬氧化物半導體場效應電晶體(Reduced Surface Field Laterally Diffused MOSFET，簡稱為RESURF LDMOS)的流程示意圖。 FIG. 1 to FIG. 7 are schematic flow charts of forming a Reduced Surface Field Laterally Diffused MOSFET (RESURF LDMOS for short) according to the present invention.

第8圖繪示一以離子佈植與加熱步驟形成深汲極摻雜區的RESURF LDMOS的結構示意圖。 FIG. 8 shows a schematic structure diagram of a RESURF LDMOS in which a deep drain doped region is formed by ion implantation and heating steps.

第9圖繪示一P型RESURF LDMOS的結構示意圖。 FIG. 9 shows a schematic structure diagram of a P-type RESURF LDMOS.

第10-11圖分別繪示根據本發明另兩個實施例的RESURF LDMOS的結構示意圖。 10-11 are schematic structural diagrams of RESURF LDMOS according to two other embodiments of the present invention, respectively.

第12-14圖繪示根據本發明另一個實施例的RESURF LDMOS的結構示意圖。 12-14 are schematic structural diagrams of RESURF LDMOS according to another embodiment of the present invention.

為使熟習本發明所屬技術領域之一般技藝者能更進一步了解本發明，下文特列舉本發明之較佳實施例，並配合所附圖式，詳細說明本發明的構成內容及所欲達成之功效。 In order to enable those who are familiar with the general skills in the technical field of the present invention to further understand the present invention, the preferred embodiments of the present invention are enumerated below, together with the accompanying drawings, the composition of the present invention and the desired effects are described in detail. .

為了方便說明，本發明之各圖式僅為示意以更容易了解本發明，其詳細的比例可依照設計的需求進行調整。在文中所描述對於圖形中相對元件之上下關係，在本領域之人皆應能理解其係指物件之相對位置而言，因此皆可以翻轉而呈現相同之構件，此皆應同屬本說明書所揭露之範圍，在此容先敘明。 For the convenience of description, the drawings of the present invention are only schematic diagrams for easier understanding of the present invention, and the detailed proportions thereof can be adjusted according to design requirements. As for the up-down relationship of relative elements in the figures described in the text, those skilled in the art should understand that they refer to the relative positions of objects, so they can be reversed to present the same components, which should all belong to this specification. The scope of disclosure is described here first.

請參考第1圖至第7圖，第1圖至第7圖繪示本發明形成一降低表面場的橫向擴散金屬氧化物半導體場效應電晶體(Reduced Surface Field Laterally Diffused MOSFET，簡稱為RESURF LDMOS)的流程示意圖。如第1圖所示，提供一基底10，在基底10內以例如摻雜等方式形成一第一井區12以及一第二井區20。值得注意的是，基底10例如為矽基底(單晶矽)，第一井區12位於基底10上，包含有一第一導電型態(例如N型，第一井區12可以包含有一阻障層14以及一漂移區16，兩者相互連接且具有同樣導電型態(例如N型)。第二井區20則包含有與第一導電型態互補的第二導電型態(例如P型)。本實施例中，基底10例如為P型基底。 Please refer to FIG. 1 to FIG. 7. FIG. 1 to FIG. 7 illustrate the formation of a reduced surface field laterally diffused metal-oxide-semiconductor field-effect transistor (Reduced Surface Field Laterally Diffused MOSFET, referred to as RESURF LDMOS) according to the present invention. schematic diagram of the process. As shown in FIG. 1 , a substrate 10 is provided, and a first well region 12 and a second well region 20 are formed in the substrate 10 by, for example, doping. It is worth noting that the substrate 10 is, for example, a silicon substrate (single crystal silicon), and the first well region 12 is located on the substrate 10 and includes a first conductivity type (such as N type, and the first well region 12 may include a barrier layer 14 and a drift region 16, both of which are connected to each other and have the same conductivity type (for example, N type). The second well region 20 includes a second conductivity type (for example, P type) complementary to the first conductivity type. In this embodiment, the substrate 10 is, for example, a P-type substrate.

值得注意的是，如第1圖所示，有一部分的第二井區20橫向深入第一井區12之內，且部分第二井區20的上下兩面被第一井區12所包圍，形成第一井區12與第二井區20相互交錯的結構。換句話說，一部分第二井區20的延伸部，位於第一井區12的阻障層14以及漂移區16之間。在實際製作過程中，可以先在基底10上形成阻障層14，然後形成第二井區20之後，再於一部分的第二井區20中摻雜離子而形成漂移區16。 It is worth noting that, as shown in Figure 1, part of the second well area 20 penetrates laterally into the first well area 12, and the upper and lower sides of part of the second well area 20 are surrounded by the first well area 12, forming A structure in which the first well area 12 and the second well area 20 are interlaced. In other words, a part of the extension of the second well region 20 is located between the barrier layer 14 and the drift region 16 of the first well region 12 . In the actual manufacturing process, the barrier layer 14 may be formed on the substrate 10 first, and then the second well region 20 is formed, and then a part of the second well region 20 is doped with ions to form the drift region 16 .

後續步驟中，將這種井區的分佈結構製成LDMOS元件時，有利於在N-P介面處形成空乏區阻擋電流通過，讓LDMOS在關閉狀態時可承受較大的電壓差，此種結構比起一般的LDMOS所需要的面積更小，因此上述LDMOS也可簡稱為降低表面場的橫向擴散金屬氧化物半導體場效應電晶體(Reduced Surface Field Laterally Diffused MOSFET，簡稱為RESURF LDMOS)。關於RESURF LDMOS的其他介紹，已經揭露於部分先前技術中(例如美國專利證書號US 9484454)，因此在此不多加贅述。 In the subsequent steps, when the distribution structure of this well region is made into LDMOS elements, it is beneficial to form a depletion region at the N-P interface to block the passage of current, so that the LDMOS can withstand a large voltage difference when it is off. The area required by the LDMOS is smaller, so the above LDMOS can also be referred to as a Reduced Surface Field Laterally Diffused MOSFET (Resurf LDMOS for short). Other introductions about RESURF LDMOS have already been disclosed in some prior art (such as US Patent No. US 9484454), so details will not be repeated here.

本發明在RESURF LDMOS的架構下進行改進，以達到減少元件面積以及增加元件品質的效果。如第2圖所示，形成一圖案化的絕緣層22位於第一井區12以及第二井區20的表面，絕緣層22例如為氧化矽或是氮化矽，但不限於此。然後以絕緣層22為遮罩，在第一井區12中形成一凹槽24，凹槽24例如可以用圖案化與蝕刻等方式形成，但不限於此。另外本實施例中，凹槽24的寬度較佳小於0.5微米，深度大於8微米，但不限於此。本實施例中，凹槽24的寬度約為0.3微米，而深度較佳大於阻障層14與第二井區20的交界面。 The present invention is improved under the structure of RESURF LDMOS, so as to achieve the effect of reducing the element area and increasing the element quality. As shown in FIG. 2 , a patterned insulating layer 22 is formed on the surfaces of the first well region 12 and the second well region 20 . The insulating layer 22 is, for example, silicon oxide or silicon nitride, but not limited thereto. Then, using the insulating layer 22 as a mask, a groove 24 is formed in the first well region 12 . The groove 24 can be formed by, for example, patterning and etching, but is not limited thereto. In addition, in this embodiment, the width of the groove 24 is preferably less than 0.5 microns, and the depth is greater than 8 microns, but it is not limited thereto. In this embodiment, the width of the groove 24 is about 0.3 microns, and the depth is preferably larger than the interface between the barrier layer 14 and the second well region 20 .

接著如第3圖所示，形成一多晶矽層26填滿凹槽24，其中多晶矽層26例如為具有高摻雜濃度的多晶矽層，可以藉由原位(in-situ)摻雜製程形成，其具有第一導電型態(例如N型)。本實施例中，多晶矽層26的濃度較佳大於1E18cm³上述濃度較習知步驟中，以離子佈植與加熱步驟等方式所形成的摻雜區濃度更高。 Next, as shown in FIG. 3, a polysilicon layer 26 is formed to fill the groove 24, wherein the polysilicon layer 26 is, for example, a polysilicon layer with a high doping concentration, which can be formed by an in-situ doping process. It has a first conductivity type (such as N type). In this embodiment, the concentration of the polysilicon layer 26 is preferably greater than 1E18 cm ³ . The above concentration is higher than that of the doped region formed by ion implantation and heating steps in conventional steps.

接著如第4圖所示，以回蝕刻或是化學機械研磨等方式，移除多餘的多晶矽層26與絕緣層22，以曝露出第一井區12與第二井區20的表面。此處剩餘在凹槽24內的多晶矽層26，又可以被定義為深汲極摻雜區27，其作用將會在下面段落繼續描述。 Next, as shown in FIG. 4 , the redundant polysilicon layer 26 and the insulating layer 22 are removed by etching back or chemical mechanical polishing to expose the surfaces of the first well region 12 and the second well region 20 . Here, the remaining polysilicon layer 26 in the groove 24 can be defined as a deep drain doped region 27 , and its function will be described in the following paragraphs.

如第5圖所示，形成一閘極結構28於第一井區12以及第二井區20上，其中閘極結構28包含有閘極介電層29以及閘極導電層30，其中閘極介電層29在漂移區16上方的厚度較厚，而在第一井區12以及第二井區20在表面的交界處附近則具有較薄的厚度。上述閘極結構28屬於RESURF LDMOS的習知技術，其餘特徵不多加贅述。 As shown in FIG. 5, a gate structure 28 is formed on the first well region 12 and the second well region 20, wherein the gate structure 28 includes a gate dielectric layer 29 and a gate conductive layer 30, wherein the gate The dielectric layer 29 has a thicker thickness above the drift region 16 and a thinner thickness near the junction of the first well region 12 and the second well region 20 on the surface. The above-mentioned gate structure 28 belongs to the known technology of RESURF LDMOS, and the rest The characteristics are not repeated.

繼續參考第6圖，在閘極結構28完成後，以離子摻雜與加熱步驟等方式分別在第一井區12以及第二井區14內至少形成源極(source)摻雜區32以及淺汲極(drain)摻雜區34。其中源極摻雜區32與淺汲極摻雜區34都包含有第一導電型態(例如N型)，且淺汲極摻雜區34與上述深汲極摻雜區27連接。值得注意的是，由於源極摻雜區32與淺汲極摻雜區34都是以離子摻雜以及加熱的步驟形成於單晶矽成分的井區之中，因此其材質也是單晶矽，且材質不同於深汲極摻雜區27。另外，本實施例中，源極摻雜區32以及淺汲極摻雜區34的離子摻雜濃度例如為大於1E20cm³。除此之外，在一些實施例中，可以在源極摻雜區32旁另外形成有基體區(body)36，其中基體區36例如為包含有第二導電型態(例如P型)的摻雜區。 Continuing to refer to FIG. 6, after the gate structure 28 is completed, at least a source (source) doped region 32 and a shallow well region 32 are formed in the first well region 12 and the second well region 14 by means of ion doping and heating steps, etc. Drain doped region 34 . The source doped region 32 and the shallow drain doped region 34 both contain the first conductivity type (for example, N type), and the shallow drain doped region 34 is connected to the above-mentioned deep drain doped region 27 . It is worth noting that since the source doped region 32 and the shallow drain doped region 34 are formed in the well region composed of single crystal silicon through the steps of ion doping and heating, their material is also single crystal silicon. And the material is different from the deep-drain doped region 27 . In addition, in this embodiment, the ion doping concentrations of the source doped region 32 and the shallow drain doped region 34 are, for example, greater than 1E20 cm ³ . In addition, in some embodiments, a body region (body) 36 may be additionally formed beside the source doped region 32, where the body region 36 is, for example, doped with a second conductivity type (such as P type). Miscellaneous area.

如第7圖所示，可以選擇性地在閘極結構28、第一井區12與第二井區20的表面形成金屬矽化物層40。接著形成一介電層42覆蓋於上述元件後，在介電層42中形成接觸結構44，接觸結構連接到源極摻雜區32與淺汲極摻雜區34。其中在一些實施例中，金屬矽化物層40可以省略不形成，或是在介電層42完成後，將金屬矽化物層40形成於接觸結構44底下。介電層42例如為氧化矽或氮化矽，而接觸結構44可能包含有襯墊層45，其材質例如為鈦/氮化鈦，以及導電層46，其材質例如為鎢(W)。上述元件的其他細節與製作方法，屬於本領域的習知技術，在此不多贅述。至此已完成本發明所述的RESURF LDMOS結構1。由於本實施例中RESURF LDMOS結構1的第一井區12為N型，因此本實施例的RESURF LDMOS結構1又可定義為N型RESURF LDMOS結構。 As shown in FIG. 7 , the metal silicide layer 40 can be selectively formed on the surfaces of the gate structure 28 , the first well region 12 and the second well region 20 . Then a dielectric layer 42 is formed to cover the above components, and a contact structure 44 is formed in the dielectric layer 42 , the contact structure is connected to the source doped region 32 and the shallow drain doped region 34 . In some embodiments, the metal silicide layer 40 may be omitted, or the metal silicide layer 40 may be formed under the contact structure 44 after the dielectric layer 42 is completed. The dielectric layer 42 is, for example, silicon oxide or silicon nitride, and the contact structure 44 may include a liner layer 45 made of, for example, titanium/titanium nitride, and a conductive layer 46, made of, for example, tungsten (W). Other details and manufacturing methods of the above-mentioned components belong to the known technology in the art, and will not be repeated here. So far, the RESURF LDMOS structure 1 described in the present invention has been completed. Since the first well region 12 of the RESURF LDMOS structure 1 in this embodiment is N-type, the RESURF LDMOS structure 1 in this embodiment can be defined as an N-type RESURF LDMOS structure.

本發明的RESURF LDMOS結構1，在閘極結構28關閉時，源極端與汲極端仍具有電位差，例如在汲極端上方的接觸結構44導入高電壓(例如100V)，而源極端維持0電位，此時由於深汲極摻雜區27的摻雜濃度高且導電性佳，因此傳導至下方的電壓僅有少量降低。電壓會使得第一井區12維持高電位，而第二井區20保持低電位，使得位於RESURF LDMOS結構1中央部分的N-P交界面產生空乏區。例如第7圖中的區域A、B、C，皆是可能產生空乏區的區域。也就是說，當RESURF LDMOS結構1的閘極結構28關閉時，除了通道區關閉可以造成隔絕之外，中央產生的空乏區也能進一步隔絕電流，讓RESURF LDMOS結構1可以承受高電壓的運作模式。 In the RESURF LDMOS structure 1 of the present invention, when the gate structure 28 is closed, the source terminal and The drain terminal still has a potential difference. For example, the contact structure 44 above the drain terminal introduces a high voltage (for example, 100V), while the source terminal maintains a potential of 0. At this time, due to the high doping concentration and good conductivity of the deep drain doped region 27, Therefore the voltage conducted to the bottom is only slightly reduced. The voltage will make the first well region 12 maintain a high potential, and the second well region 20 maintain a low potential, so that the N-P interface located at the central part of the RESURF LDMOS structure 1 generates a depletion region. For example, regions A, B, and C in FIG. 7 are all regions where depletion regions may be generated. That is to say, when the gate structure 28 of the RESURF LDMOS structure 1 is turned off, in addition to the isolation caused by the closing of the channel region, the depletion region generated in the center can also further isolate the current, so that the RESURF LDMOS structure 1 can withstand high voltage operation mode .

為了讓上述空乏區可以順利形成，習知技術中較佳將深汲極摻雜區的深度製作得更深，以讓電壓可以順利傳導至下方靠近阻障層14的部分，並且順利產生空乏區。第8圖繪示一以離子佈植與加熱步驟形成深汲極摻雜區的RESURF LDMOS的結構示意圖。習知技術中，以離子佈植與加熱步驟來增加深汲極摻雜區的深度，然而，離子在加熱的同時也會朝向橫向擴散，因此習知技術中深汲極摻雜區的寬度較大(如第8圖中的離子摻雜區34A)，如此一來將會導致元件的面積過大，不利於元件的微小化。舉例來說，習知技術中離子摻雜區34A的深度若要達到8微米，則其寬度約會擴散到12微米左右。此外，離子摻雜區34A的摻雜濃度不如本發明的深汲極摻雜區27，故導電性也不如深汲極摻雜區27。當從離子摻雜區34A上方導入高電壓(例如100V)時，傳導至離子摻雜區34A下方的電壓將會下降得更多，如此不利於空乏區的形成。 In order to smoothly form the above-mentioned depletion region, it is preferable to make the depth of the deep-drain doped region deeper in the prior art, so that the voltage can be smoothly transmitted to the lower part close to the barrier layer 14 and the depletion region can be smoothly generated. FIG. 8 shows a schematic structure diagram of a RESURF LDMOS in which a deep drain doped region is formed by ion implantation and heating steps. In the conventional technology, the depth of the deep-drain doped region is increased by ion implantation and heating steps. However, the ions also diffuse toward the lateral direction while being heated, so the width of the deep-drain doped region in the conventional technology is relatively large. Large (such as the ion-doped region 34A in FIG. 8), this will lead to an excessively large area of the device, which is not conducive to the miniaturization of the device. For example, in the prior art, if the depth of the ion-doped region 34A is to reach 8 micrometers, its width will be diffused to about 12 micrometers. In addition, the doping concentration of the ion-doped region 34A is lower than that of the deep-drain doped region 27 of the present invention, so the conductivity is also lower than that of the deep-drain doped region 27 . When a high voltage (for example, 100V) is introduced from above the ion-doped region 34A, the voltage transmitted to the lower part of the ion-doped region 34A will drop even more, which is not conducive to the formation of a depletion region.

本發明的RESURF LDMOS結構1與習知技術中的RESURF LDMOS結構的主要不同處在於形成深汲極摻雜區27取代部份的離子摻雜區，上述深汲極摻雜區27以蝕刻凹槽24與回填多晶矽層26的方式所形成。其中，凹槽24的寬度可以遠小於上述習知技術中離子摻雜區34A的寬度，另一個特徵是在凹槽24中填入更高摻雜濃度且導電性更好的多晶矽層26，不但可以大幅度減少元件面積(因為深汲極摻雜區27的寬度較小)，且深汲極摻雜區27的導電效果更佳，使得來自上方接觸結構44的高電壓，可以順利地傳導至深汲極摻雜區27的下方，進一步再傳導到第一井區12內，讓空乏區可以順利形成。總之，本發明具有減少元件面積、提高元件品質以及與現有製程相容等優點。 The main difference between the RESURF LDMOS structure 1 of the present invention and the RESURF LDMOS structure in the prior art is that a deep drain doped region 27 is formed to replace part of the ion doped region, and the deep drain doped region 27 is used to etch the groove 24 is formed by backfilling the polysilicon layer 26 . Among them, the width of the groove 24 The width can be much smaller than the width of the ion-doped region 34A in the above-mentioned conventional technology. Another feature is that the polysilicon layer 26 with higher doping concentration and better conductivity is filled in the groove 24, which can not only greatly reduce the device area (Because the width of the deep drain doped region 27 is small), and the conduction effect of the deep drain doped region 27 is better, so that the high voltage from the upper contact structure 44 can be successfully conducted to the deep drain doped region 27, it is further conducted into the first well area 12, so that the depletion area can be formed smoothly. In a word, the present invention has the advantages of reducing device area, improving device quality, and being compatible with existing manufacturing processes.

在上述實施例中(第1圖到第7圖)，以製作N型RESURF LDMOS結構為例，也就是第一井區12以及深汲極摻雜區27為N型、第二井區20為P型。但在本發明的其他實施例中，也可以製作P型RESURF LDMOS結構。如第9圖所示，第9圖繪示一P型RESURF LDMOS的結構示意圖。其中，多數元件的結構、材質與製作方法與上述第一較佳實施例相同而不多贅述，與上述實施例不同之處在於，本實施例中基底10、第一井區12、深汲極摻雜區27、源極摻雜區32與淺汲極摻雜區34為P型，而第二井區20與基體區36則是N型。值得注意的是，本實施例中深汲極摻雜區27並不接觸第二井區20，且深汲極摻雜區27以及第二井區20之間維持有一間距G，以避免在汲極端導入高電位時，具有較高摻雜濃度的深汲極摻雜區27與具有較低摻雜濃度的第二井區20之間產生電流擊穿(punch through)而引起元件崩潰(breakdown)。 In the above-mentioned embodiments (Fig. 1 to Fig. 7), the N-type RESURF LDMOS structure is taken as an example, that is, the first well region 12 and the deep drain doped region 27 are N-type, and the second well region 20 is N-type. Type P. However, in other embodiments of the present invention, a P-type RESURF LDMOS structure can also be fabricated. As shown in FIG. 9, FIG. 9 shows a schematic structure diagram of a P-type RESURF LDMOS. Among them, the structures, materials and manufacturing methods of most components are the same as those of the above-mentioned first preferred embodiment and will not be described in detail. The doped region 27 , the source doped region 32 and the shallow drain doped region 34 are P-type, while the second well region 20 and the base region 36 are N-type. It should be noted that in this embodiment, the deep drain doped region 27 does not contact the second well region 20, and a distance G is maintained between the deep drain doped region 27 and the second well region 20 to avoid When an extremely high potential is introduced, a current punch through occurs between the deep drain doped region 27 with a higher doping concentration and the second well region 20 with a lower doping concentration, causing breakdown of the device. .

同樣地，在本發明的其他實施例中，為了避免橫向的電流擊穿，可以在深汲極摻雜區27旁邊或是下方設置絕緣層。請參考第10-11圖，第10-11圖分別繪示根據本發明另兩個實施例的RESURF LDMOS的結構示意圖。如第10圖所示，本實施例中額外形成一絕緣層50在深汲極摻雜區27旁邊，絕緣層50例如為氧化矽、或是外圍被氧化矽所包圍的多晶矽層。絕緣層50的深度可以比深汲極摻雜區27的深度更深，且絕緣層50設置在第一井區12旁的基底10內，在一些實施例中，深溝渠隔離(deep trench isolation，DTI)可以當作此處的絕緣層50。絕緣層50具有防止深汲極摻雜區27擊穿第一井區12而影響其他相鄰元件的功能。 Likewise, in other embodiments of the present invention, in order to avoid lateral current breakdown, an insulating layer may be disposed beside or below the deep drain doped region 27 . Please refer to FIGS. 10-11. FIGS. 10-11 respectively illustrate the structural schematic diagrams of RESURF LDMOS according to two other embodiments of the present invention. As shown in FIG. 10 , in this embodiment, an insulating layer 50 is additionally formed beside the deep drain doped region 27 . The insulating layer 50 is, for example, silicon oxide or a polysilicon layer surrounded by silicon oxide. The depth of insulating layer 50 can be deeper than the drain The depth of the doped region 27 is deeper, and the insulating layer 50 is disposed in the substrate 10 next to the first well region 12. In some embodiments, deep trench isolation (DTI) can be used as the insulating layer 50 here. . The insulating layer 50 has the function of preventing the deep drain doped region 27 from breaking through the first well region 12 and affecting other adjacent components.

在另一實施例中，如第11圖所示，除了設置上述的絕緣層50以外，本實施例中將部分的阻障層14以另一絕緣層60取代。絕緣層60例如為氧化矽。在一些實施例中，可以用矽覆絕緣層(silicon on substrate，SOI)基底來代替原本的矽基底，以達到如第11圖所示的結構。在本實施例中，絕緣層60同樣可以防止縱向方向的電流擊穿。 In another embodiment, as shown in FIG. 11 , in addition to the above-mentioned insulating layer 50 , part of the barrier layer 14 is replaced by another insulating layer 60 in this embodiment. The insulating layer 60 is, for example, silicon oxide. In some embodiments, a silicon on substrate (SOI) substrate may be used to replace the original silicon substrate to achieve the structure shown in FIG. 11 . In this embodiment, the insulating layer 60 can also prevent current breakdown in the longitudinal direction.

在本發明的其他實施例中，也可以在同一基底上形成不同的LDMOS。舉例來說，可以將N型RESURF LDMOS(第7圖所示的結構)與P型RESURF LDMOS(第9圖所示的結構)一起形成在同一基底的不同區域上。此結構也屬於本發明的涵蓋範圍內。 In other embodiments of the present invention, different LDMOSs can also be formed on the same substrate. For example, N-type RESURF LDMOS (structure shown in FIG. 7 ) and P-type RESURF LDMOS (structure shown in FIG. 9 ) can be formed together on different regions of the same substrate. This structure also falls within the scope of the present invention.

在以上的實施例中，在凹槽24中填入高摻雜濃度的多晶矽層26，藉以形成寬度較窄的多晶矽深汲極摻雜區27。另外在本發明的其他實施例中，也可以藉由在凹槽24內以摻雜或是電漿佈植等其他方式，在第一井區12內形成寬度較窄且深度足夠的深汲極摻雜區，詳細如下第12圖至第14圖所示。 In the above embodiments, the polysilicon layer 26 with high doping concentration is filled in the groove 24 to form a polysilicon deep drain doped region 27 with a narrow width. In addition, in other embodiments of the present invention, a deep drain with a narrow width and sufficient depth can also be formed in the first well region 12 by doping or plasma implantation in the groove 24. The details of the doped region are shown in Figure 12 to Figure 14 below.

如第12圖所示，在本實施例中，形成凹槽24之後(接續第一實施例的第1圖與第2圖的步驟)，先形成一光阻層25覆蓋部分的第一井區12與第二井區20，並且同時曝露出部分的第一井區12與第二井區20，其中被曝露的區域包含有凹槽24、以及第二井區20中預定要形成源極摻雜區32的位置。接下來，進行一摻雜步驟P1，對未被光阻層25覆蓋的區域進行摻雜，在本實施例中，以摻雜高濃度的N型離子為例，但本發明的其他實施例中，也可能摻雜高濃度的P型離子，本發明不以此為限制。此外，凹槽24、源極摻雜區32、閘極結構28也可以分別用不同光罩進行個別獨立的摻雜，本發明不以此為限制。 As shown in Figure 12, in this embodiment, after forming the groove 24 (continuing the steps in Figure 1 and Figure 2 of the first embodiment), a photoresist layer 25 is first formed to cover the first well region 12 and the second well region 20, and expose part of the first well region 12 and the second well region 20 at the same time, wherein the exposed region contains the groove 24, and the second well region 20 is intended to form source doping The location of the impurity region 32 . Next, proceed to A doping step P1 is to dope the area not covered by the photoresist layer 25. In this embodiment, the doping of high-concentration N-type ions is taken as an example, but in other embodiments of the present invention, it is also possible to dope High concentration of P-type ions, the present invention is not limited thereto. In addition, the groove 24 , the source doped region 32 , and the gate structure 28 can also be individually and independently doped with different masks, and the present invention is not limited thereto.

值得注意的是，本實施例中離子摻雜步驟P1過程中可以調整其摻雜角度，例如以斜向方向進行摻雜，因此所摻雜的離子，可以深入至凹槽24的底面以及側壁，在凹槽24的底面與側壁形成深汲極摻雜區27A。與前述實施例所提及的深汲極摻雜區27不同的是，本實施例中的深汲極摻雜區27A因為以離子摻雜的方式形成在第一井區12的凹槽24外圍，因此具有U型的剖面輪廓，且深汲極摻雜區27A的材質與第一井區12相同，兩者均為單晶矽。此外，本實施例中在形成深汲極摻雜區27A的同時，也同時可在第二井區20內形成源極摻雜區32，因此可以達到節省步驟的功效。此外凹槽24亦可以使用電漿摻雜(plasma doping)方式進行摻雜，本發明不以此為限制。 It is worth noting that the doping angle can be adjusted during the ion doping step P1 in this embodiment, for example, doping in an oblique direction, so that the doped ions can penetrate deep into the bottom surface and sidewall of the groove 24, A deep drain doped region 27A is formed on the bottom and sidewalls of the groove 24 . Different from the deep drain doped region 27 mentioned in the previous embodiments, the deep drain doped region 27A in this embodiment is formed on the periphery of the groove 24 of the first well region 12 by means of ion doping. , so it has a U-shaped cross-sectional profile, and the material of the deep drain doped region 27A is the same as that of the first well region 12, both of which are single crystal silicon. In addition, in this embodiment, while forming the deep drain doped region 27A, the source doped region 32 can also be formed in the second well region 20 at the same time, so the effect of saving steps can be achieved. In addition, the groove 24 can also be doped by plasma doping, and the present invention is not limited thereto.

接著，如第13圖所示，移除光阻層25，之後在源極摻雜區32旁邊形成基體區36，此處的基體區36例如是以摻雜的方式形成的一P型摻雜區。然後再形成金屬矽化物層40，其中金屬矽化物層40覆蓋在閘極結構28、第一井區12、第二井區20與凹槽24(即深汲極摻雜區27A)的表面。此外本發明亦可以不用形成金屬矽化物層、或選擇性的形成金屬矽化物層於基底，或閘極結構，或凹槽內表面，本發明不以此為限制。 Next, as shown in FIG. 13, the photoresist layer 25 is removed, and then a base region 36 is formed next to the source doped region 32, where the base region 36 is, for example, a P-type doped doped region formed by doping. district. Then a metal silicide layer 40 is formed, wherein the metal silicide layer 40 covers the surfaces of the gate structure 28 , the first well region 12 , the second well region 20 and the groove 24 (ie, the deep drain doped region 27A). In addition, the present invention may not form the metal silicide layer, or selectively form the metal silicide layer on the substrate, or the gate structure, or the inner surface of the groove, and the present invention is not limited thereto.

然後如第14圖所示，形成介電層42以及接觸結構44以及接觸結構44A。其中介電層42例如為氧化矽或氮化矽，而接觸結構44與接觸結構44A可能包含有襯墊層45，其材質例如為鈦/氮化鈦，以及導電層46，其材質例如為鎢(W)。此處關於形成基體區36、金屬矽化物層40與接觸結構44、44A的步驟與上述實施例相似(可參考第6圖與第7圖的描述)相似，在此不多加贅述。值得注意的是，本實施例中的接觸結構44A形成在凹槽24內，也就是形成在深汲極摻雜區27A上。接觸結構44A深入第一井區12內，也就是接觸結構44A的底面低於第一井區12的頂面，因此可以有效地將來自上方其他元件的電流傳導至下方。 Then, as shown in FIG. 14 , a dielectric layer 42 and a contact structure 44 and a contact structure 44A are formed. The dielectric layer 42 is, for example, silicon oxide or silicon nitride, and the contact structure 44 and the contact structure 44A may It includes a liner layer 45 whose material is, for example, titanium/titanium nitride, and a conductive layer 46, whose material is, for example, tungsten (W). The steps of forming the base region 36 , the metal silicide layer 40 and the contact structures 44 , 44A are similar to those of the above-mentioned embodiments (refer to the description in FIG. 6 and FIG. 7 ), and will not be repeated here. It should be noted that the contact structure 44A in this embodiment is formed in the groove 24 , that is, formed on the deep drain doped region 27A. The contact structure 44A goes deep into the first well region 12 , that is, the bottom surface of the contact structure 44A is lower than the top surface of the first well region 12 , so it can effectively conduct current from other components above to below.

綜合以上第12圖至第14圖，本實施例以另一種方式形成深汲極摻雜區27A，其在凹槽中藉由摻雜或是離子佈植等方式形成深汲極摻雜區。其中深汲極摻雜區的深度足夠將來自上方的電流傳導至下方。在另一實施例中，深汲極摻雜區的寬度也小於0.5微米，同樣具有節省空間的功效。此外本實施例也與現有的製程相容。此外，本實施例中以製作N型RESURF LDMOS結構為例，但可以調整摻雜離子的種類，而製作P型的RESURF LDMOS結構。也就是將本實施例中在凹槽內摻雜離子的方法，應用於第9圖的實施例中，也屬於本發明的涵蓋範圍。 Based on the above-mentioned FIG. 12 to FIG. 14 , this embodiment forms the deep-drain doped region 27A in another way, which forms the deep-drain doped region in the groove by doping or ion implantation. The depth of the deep drain doped region is sufficient to conduct current from above to below. In another embodiment, the width of the deep drain doped region is also less than 0.5 micron, which also has the effect of saving space. In addition, this embodiment is also compatible with existing manufacturing processes. In addition, in this embodiment, an N-type RESURF LDMOS structure is fabricated as an example, but the type of dopant ions can be adjusted to fabricate a P-type RESURF LDMOS structure. That is, applying the method of doping ions in the grooves in this embodiment to the embodiment shown in FIG. 9 also falls within the scope of the present invention.

綜合以上說明書與圖式，本發明提供一種半導體結構，包含一基底10，一橫向擴散金氧半導體(laterally diffused metal-oxide-semiconductor，LDMOS)元件位於該基底10上，其中該LDMOS元件包含：一第一井區12，位於該基底10上，該第一井區12有一第一導電型態，一第二井區20，位於該第一井區12之內，且其中一部分的該第二井區20的上下兩面被該第一井區12所包圍，其中該第二井區20具有一第二導電型態，其中該第二導電型態與該第一導電型態互補，一源極摻雜區32，位於該第二井區20之內，該源極摻雜區32具有該第一導電型態，以及一深汲極摻雜區(27或27A)，位於第一井區12之內，深汲極摻雜區(27或27A)具有第一導電型態。在另一實施例中，其深汲極摻雜區(27或27A)的一寬度小於0.5微米。 Based on the above description and drawings, the present invention provides a semiconductor structure, including a substrate 10, and a laterally diffused metal-oxide-semiconductor (LDMOS) device is located on the substrate 10, wherein the LDMOS device includes: a The first well area 12 is located on the substrate 10, the first well area 12 has a first conductivity type, a second well area 20 is located in the first well area 12, and a part of the second well area The upper and lower sides of the region 20 are surrounded by the first well region 12, wherein the second well region 20 has a second conductivity type, wherein the second conductivity type is complementary to the first conductivity type, and a source doped impurity region 32, located in the second well region 20, the source doped region 32 has the first conductivity type, and a deep drain doped region (27 or 27A), located in the first well region 12 inside, deeply drawn The impurity region (27 or 27A) has the first conductivity type. In another embodiment, a width of the deep drain doped region ( 27 or 27A) is less than 0.5 microns.

本發明另提供一種半導體結構的形成方法，包含提供一基底10，形成一橫向擴散金氧半導體(laterally diffused metal-oxide-semiconductor，LDMOS)元件位於基底上，其中形成LDMOS元件的步驟包含：形成一第一井區12於基底10上，第一井區12有一第一導電型態，形成一第二井區20於第一井區12之內，且其中一部分的第二井區20的上下兩面被第一井區12所包圍，其中第二井區20具有一第二導電型態，其中第二導電型態與第一導電型態互補，形成一源極摻雜區32，位於第二井區20之內，源極摻雜區32具有第一導電型態，以及在第一井區12中形成一凹槽24，並且在凹槽24中形成一深汲極摻雜區(27或27A)於第一井區12之內，深汲極摻雜區(27或27A)具有第一導電型態。在另一實施例中，其深汲極摻雜區(27或27A)的一寬度小於0.5微米。 The present invention further provides a method for forming a semiconductor structure, including providing a substrate 10, forming a laterally diffused metal-oxide-semiconductor (LDMOS) element on the substrate, wherein the step of forming the LDMOS element includes: forming a The first well area 12 is on the substrate 10, the first well area 12 has a first conductivity type, a second well area 20 is formed in the first well area 12, and the upper and lower sides of a part of the second well area 20 Surrounded by the first well region 12, the second well region 20 has a second conductivity type, wherein the second conductivity type is complementary to the first conductivity type, forming a source doped region 32, located in the second well Within the region 20, the source doped region 32 has a first conductivity type, and a groove 24 is formed in the first well region 12, and a deep drain doped region (27 or 27A) is formed in the groove 24. ) within the first well region 12, the deep drain doped region (27 or 27A) has the first conductivity type. In another embodiment, a width of the deep drain doped region ( 27 or 27A) is less than 0.5 microns.

在一些實施例中，其中第一井區12與第二井區20的材質均包含單晶矽，而深汲極摻雜區27的材質包含多晶矽，且深汲極摻雜區27的形狀包含一柱狀體。 In some embodiments, the materials of the first well region 12 and the second well region 20 both include monocrystalline silicon, and the material of the deep drain doped region 27 includes polysilicon, and the shape of the deep drain doped region 27 includes A columnar body.

在一些實施例中，其中第一井區12、第二井區20與深汲極摻雜區27A的材質均包含單晶矽，深汲極摻雜區27A具有一U型剖面輪廓 In some embodiments, the materials of the first well region 12, the second well region 20, and the deep-drain doped region 27A all include single crystal silicon, and the deep-drain doped region 27A has a U-shaped profile.

在一些實施例中，其中更包含有一接觸結構44A，位於第一井區12上，並且與深汲極摻雜區27A電性連接，其中接觸結構44A的一底面低於該第一井區12的一頂面。 In some embodiments, it further includes a contact structure 44A located on the first well region 12 and electrically connected to the deep drain doped region 27A, wherein a bottom surface of the contact structure 44A is lower than the first well region 12 a top surface of the .

在一些實施例中，其中深汲極摻雜區27的一摻雜濃度高於1E18cm³。 In some embodiments, a doping concentration of the deep-drain doped region 27 is higher than 1E18 cm ³ .

在一些實施例中，更包含有一淺汲極摻雜區34，位於第一井區12之內，並且連接深汲極摻雜區27。 In some embodiments, it further includes a shallow drain doped region 34 located in the first well region 12 and connected to the deep drain doped region 27 .

在一些實施例中，其中第一井區12包含有一阻障層14以及一漂移區16相互連接，且部分第二井區20位元於阻障層14與漂移區16之間。 In some embodiments, the first well region 12 includes a barrier layer 14 and a drift region 16 connected to each other, and part of the second well region 20 is located between the barrier layer 14 and the drift region 16 .

在一些實施例中，更包含有至少一絕緣結構50，位於深汲極摻雜區27旁邊。 In some embodiments, at least one insulating structure 50 is further included, located beside the deep drain doped region 27 .

在一些實施例中，其中第一導電型態包含N型，第二導電型態包含P型。 In some embodiments, the first conductivity type includes N type, and the second conductivity type includes P type.

在一些實施例中，其中第一導電型態包含P型，第二導電型態包含N型。 In some embodiments, the first conductivity type includes P type, and the second conductivity type includes N type.

本發明的特徵在於，提供一種降低表面場的橫向擴散金屬氧化物半導體場效應電晶體(Reduced Surface Field Laterally Diffused MOSFET，簡稱為RESURF LDMOS)。該RESURF LDMOS的形成過程中，在一第一井區中形成一凹槽，接著在該凹槽中填入高摻雜濃度的多晶矽材質，或是以摻雜方式形成U型剖面的離子摻雜區，以在第一井區中形成一深汲極摻雜區。有別於習知方式在第一井區中以離子佈植與加熱擴散的方式形成深汲極摻雜區，本案的深汲極摻雜區所需面積大幅減少，因此也可減少元件的總面積，達到微型化的效果。此外深汲極摻雜區具有高摻雜濃度，較不容易產生壓降，也因此可以提高產品的品質。 The present invention is characterized in that it provides a reduced surface field laterally diffused metal oxide semiconductor field effect transistor (Reduced Surface Field Laterally Diffused MOSFET, referred to as RESURF LDMOS). In the formation process of the RESURF LDMOS, a groove is formed in a first well region, and then polysilicon material with a high doping concentration is filled in the groove, or ion doping to form a U-shaped profile by doping region to form a deep drain doped region in the first well region. Different from the conventional method in which the deep drain doped region is formed by ion implantation and heating diffusion in the first well area, the deep drain doped region in this case The required area of the miscellaneous area is greatly reduced, so the total area of the components can also be reduced to achieve the effect of miniaturization. In addition, the deep-drain doped region has a high doping concentration, which is less prone to voltage drop, and thus can improve product quality.

以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

10:基底 10: Base

12:第一井區 12: The first well area

20:第二井區 20: Second well area

27:深汲極摻雜區 27: Deep drain doped region

28:閘極結構 28:Gate structure

32:源極摻雜區 32: Source doped region

34:深汲極摻雜區 34: Deep drain doped region

36:基體區 36: Matrix area

40:金屬矽化物層 40: metal silicide layer

42:介電層 42: Dielectric layer

44:接觸結構 44: Contact structure

45:襯墊層 45: Cushion layer

46:導電層 46: Conductive layer

A:區域 A: area

B:區域 B: area

C:區域 C: area

Claims

一種半導體結構，包含：一基底；一橫向擴散金氧半導體(laterally diffused metal-oxide-semiconductor，LDMOS)元件位於該基底上，其中該橫向擴散金氧半導體元件包含：一第一井區，位於該基底上，該第一井區有一第一導電型態；一第二井區，位於該第一井區之內，且其中一部分的該第二井區的上下兩面被該第一井區所包圍，其中該第二井區具有一第二導電型態，其中該第二導電型態與該第一導電型態互補；一源極摻雜區，位於該第二井區之內，該源極摻雜區具有該第一導電型態；以及一深汲極摻雜區，位於該第一井區之內，該深汲極摻雜區具有該第一導電型態，且該深汲極摻雜區的一底面低於該第二井區的一底面，其中該第一井區與該第二井區的材質均包含單晶矽，而該深汲極摻雜區的材質包含多晶矽，且該深汲極摻雜區的形狀包含一柱狀體。 A semiconductor structure comprising: a substrate; a laterally diffused metal-oxide-semiconductor (LDMOS) element located on the substrate, wherein the laterally diffused metal-oxide-semiconductor element comprises: a first well region located on the substrate On the substrate, the first well area has a first conductivity type; a second well area is located within the first well area, and a part of the second well area is surrounded by the first well area on the upper and lower sides , wherein the second well region has a second conductivity type, wherein the second conductivity type is complementary to the first conductivity type; a source doped region is located in the second well region, and the source The doped region has the first conductivity type; and a deep drain doped region is located in the first well region, the deep drain doped region has the first conductivity type, and the deep drain doped region A bottom surface of the impurity region is lower than a bottom surface of the second well region, wherein the materials of the first well region and the second well region both include monocrystalline silicon, and the material of the deep drain doped region includes polysilicon, and The shape of the deep-drain doped region includes a columnar body.

如申請專利範圍第1項所述的半導體結構，其中該第一井區、該第二井區與該深汲極摻雜區的材質均包含單晶矽，該深汲極摻雜區具有一U型剖面輪廓。 The semiconductor structure described in item 1 of the scope of the patent application, wherein the materials of the first well region, the second well region and the deep drain doped region all include single crystal silicon, and the deep drain doped region has a U-shaped profile.

如申請專利範圍第2項所述的半導體結構，更包含有一接觸結構，位於該第一井區上，並且與該深汲極摻雜區電性連接，其中該接觸結構的一底面低於該第一井區的一頂面。 The semiconductor structure described in item 2 of the scope of the patent application further includes a contact structure located on the first well region and electrically connected to the deep drain doped region, wherein a bottom surface of the contact structure is lower than the A top surface of the first well area.

如申請專利範圍第1項所述的半導體結構，其中該深汲極摻雜區的一摻雜濃度高於1E18cm³。 The semiconductor structure as described in claim 1, wherein a doping concentration of the deep drain doped region is higher than 1E18cm ³ .

如申請專利範圍第1項所述的半導體結構，更包含有一淺汲極摻雜區，位於該第一井區之內，並且連接該深汲極摻雜區。 The semiconductor structure described in claim 1 further includes a shallow drain doped region located in the first well region and connected to the deep drain doped region.

如申請專利範圍第1項所述的半導體結構，其中該第一井區包含有一阻障層以及一漂移區相互連接，且部分該第二井區位於該阻障層與該漂移區之間。 The semiconductor structure described in claim 1, wherein the first well region includes a barrier layer and a drift region connected to each other, and part of the second well region is located between the barrier layer and the drift region.

如申請專利範圍第1項所述的半導體結構，更包含有至少一絕緣結構，位於該深汲極摻雜區旁邊。 The semiconductor structure described in claim 1 further includes at least one insulating structure located beside the deep drain doped region.

如申請專利範圍第1項所述的半導體結構，其中該第一導電型態包含N型，該第二導電型態包含P型，或是該第一導電型態包含P型，該第二導電型態包含N型。 The semiconductor structure described in item 1 of the scope of the patent application, wherein the first conductivity type includes N type, the second conductivity type includes P type, or the first conductivity type includes P type, and the second conductivity type Type includes N type.

如申請專利範圍第1項所述的半導體結構，其中該深汲極摻雜區的一寬度小於0.5微米。 The semiconductor structure according to claim 1, wherein a width of the deep drain doped region is less than 0.5 microns.

一種半導體結構的形成方法，包含：提供一基底；形成一橫向擴散金氧半導體(laterally diffused metal-oxide-semiconductor，LDMOS)元件位於該基底上，其中形成該橫向擴散金氧半導體元件的步驟包含：形成一第一井區於該基底上，該第一井區有一第一導電型態；形成一第二井區於該第一井區之內，且其中一部分的該第二井區的上下兩面被該第一井區所包圍，其中該第二井區具有一第二導電型態，其中該第二導電型態與該第一導電型態互補；形成一源極摻雜區，位於該第二井區之內，該源極摻雜區具有該第一導電型態；在該第一井區中形成一凹槽；以及在該凹槽中形成一深汲極摻雜區於該第一井區之內，該深汲極摻雜區具有該第一導電型態。 A method for forming a semiconductor structure, comprising: providing a substrate; forming a laterally diffused metal-oxide-semiconductor (LDMOS) element on the substrate, wherein the step of forming the laterally diffused metal-oxide-semiconductor element includes: Forming a first well area on the substrate, the first well area has a first conductivity type; forming a second well area within the first well area, and part of the upper and lower sides of the second well area Surrounded by the first well region, wherein the second well region has a second conductivity type, wherein the second conductivity type is complementary to the first conductivity type; forming a source doped region, located at the first In the second well region, the source doped region has the first conductivity type; a groove is formed in the first well region; and a deep drain doped region is formed in the groove in the first well region Within the well region, the deep drain doped region has the first conductivity type.

如申請專利範圍第10項所述的方法，其中該深汲極摻雜區係由在該凹槽內填入一摻雜的多晶矽層所形成，其中該第一井區與該第二井區的材質均包含單晶矽，而該深汲極摻雜區的材質包含多晶矽，並且該深汲極摻雜區的形狀包含一柱狀體。 The method described in claim 10 of the patent application, wherein the deep drain doped region is formed by filling a doped polysilicon layer in the groove, wherein the first well region and the second well region The material of the deep drain doped region includes polysilicon, and the shape of the deep drain doped region includes a columnar body.

如申請專利範圍第10項所述的方法，其中該深汲極摻雜區係由在該凹槽內進行一摻雜步驟所形成，其中該第一井區、該第二井區與該深汲極摻雜區的材質均包含單晶矽，該深汲極摻雜區具有一U型剖面輪廓。 The method described in item 10 of the scope of patent application, wherein the deep drain doped region is formed by performing a doping step in the groove, wherein the first well region, the second well region and the deep The material of the drain doped region includes single crystal silicon, and the deep drain doped region has a U-shaped profile.

如申請專利範圍第12項所述的方法，更包含形成一接觸結構，位於該第一井區上，並且與該深汲極摻雜區電性連接，其中該接觸結構的一底面低於該第一井區的一頂面。 The method described in claim 12 further includes forming a contact structure located on the first well region and electrically connected to the deep drain doped region, wherein a bottom surface of the contact structure is lower than the A top surface of the first well area.

如申請專利範圍第10項所述的方法，其中該深汲極摻雜區的一摻雜濃度高於1E18cm³。 The method according to claim 10, wherein a doping concentration of the deep-drain doped region is higher than 1E18cm ³ .

如申請專利範圍第10項所述的方法，更包含形成有一淺汲極摻雜區，位於該第一井區之內，並且連接該深汲極摻雜區。 The method described in claim 10 further includes forming a shallow drain doped region located within the first well region and connected to the deep drain doped region.

如申請專利範圍第10項所述的方法，其中該第一井區包含有一阻障層以及一漂移區相互連接，且部分該第二井區位於該阻障層與該漂移區之間。 The method described in claim 10, wherein the first well region includes a barrier layer and a drift region connected to each other, and part of the second well region is located between the barrier layer and the drift region.

如申請專利範圍第10項所述的方法，更包含形成有至少一絕緣結構，位於該深汲極摻雜區旁邊。 The method described in claim 10 further includes forming at least one insulating structure next to the deep drain doped region.

如申請專利範圍第10項所述的方法，其中該第一導電型態包含N型，該第二導電型態包含P型，或是該第一導電型態包含P型，該第二導電型態包含N型。 The method described in item 10 of the scope of the patent application, wherein the first conductivity type includes N type, the second conductivity type includes P type, or the first conductivity type includes P type, and the second conductivity type States include N-type.

如申請專利範圍第10項所述的方法，其中該該深汲極摻雜區的一寬度小於0.5微米。 The method according to claim 10, wherein a width of the deep-drain doped region is less than 0.5 microns.