TWI467765B - Semiconductor device and fabricating method thereof - Google Patents
Semiconductor device and fabricating method thereof Download PDFInfo
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本發明係有關於一種半導體裝置,特別係有關於一種具有超接面(super junction)結構之半導體裝置及其製造方法。The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a super junction structure and a method of fabricating the same.
半導體裝置,例如高壓元件,通常可分為垂直式擴散金氧半場效電晶體(vertical double-diffused MOSFET,VDMOSFET)與水平式擴散金氧半場效電晶體(laterally diffused MOSFET,LDMOSFET)。而為了上述高壓元件的耐壓(withstand voltage),通常會降低深井區(或稱為漂移區(drift region))的摻雜濃度、增加漂移區的深度或是增加閘極下方隔離結構(或稱為場氧化層(field oxide))的長度。Semiconductor devices, such as high voltage components, are generally classified into vertical diffused double-diffused MOSFETs (VDMOSFETs) and horizontally diffused MOSFETs (LDMOSFETs). For the above-mentioned high voltage component withstand voltage, it usually reduces the doping concentration of the deep well region (or called the drift region), increases the depth of the drift region, or increases the isolation structure under the gate (or It is the length of the field oxide.
第1圖係繪示出習知的N型水平式擴散金氧半場效電晶體(LDMOSFET)剖面示意圖。N型水平式擴散金氧半場效電晶體10包括:一P型半導體基底100及位於其上的一P型磊晶層102。P型磊晶層102上具有閘極結構116及場氧化層114。再者,閘極結構116兩側的P型磊晶層102內分別為一P型基體(body)區106及一N型漂移區104,其中漂移區104進一步延伸於下方的P型半導體基底100內。基體區106內具有P型接觸區108及相鄰的N型接觸區110(二者或稱為源極區),而漂移區104內具有N型接觸區112(或稱為汲極區)。再者,一源極電極117電性連接於P型接觸區108及N型接觸區110;一汲極電極119電性 連接於N型接觸區112;及一閘極電極121電性連接於閘極結構116。FIG. 1 is a schematic cross-sectional view showing a conventional N-type horizontal diffusion gold-oxygen half field effect transistor (LDMOSFET). The N-type horizontal diffusion gold-oxygen field effect transistor 10 includes a P-type semiconductor substrate 100 and a P-type epitaxial layer 102 thereon. The P-type epitaxial layer 102 has a gate structure 116 and a field oxide layer 114 thereon. Furthermore, the P-type epitaxial layer 102 on both sides of the gate structure 116 is a P-type body region 106 and an N-type drift region 104, wherein the drift region 104 further extends to the underlying P-type semiconductor substrate 100. Inside. The base region 106 has a P-type contact region 108 and an adjacent N-type contact region 110 (both referred to as a source region), and the drift region 104 has an N-type contact region 112 (also referred to as a drain region). Furthermore, a source electrode 117 is electrically connected to the P-type contact region 108 and the N-type contact region 110; a drain electrode 119 is electrically connected. Connected to the N-type contact region 112; and a gate electrode 121 is electrically connected to the gate structure 116.
如以上所述,為了提升上述電晶體10的耐壓(withstand voltage),必須降低漂移區104的摻雜濃度及/或增加閘極結構116下方場氧化層114的長度。然而,以上述方式來提升耐壓時,同時也會增加上述電晶體10的導通電阻(Ron)或增加電晶體10的尺寸。As described above, in order to increase the withstand voltage of the above-described transistor 10, it is necessary to reduce the doping concentration of the drift region 104 and/or increase the length of the field oxide layer 114 under the gate structure 116. However, when the withstand voltage is raised in the above manner, the on-resistance (Ron) of the above-described transistor 10 is also increased or the size of the transistor 10 is increased.
因此,有必要尋求一種半導體裝置,其能夠增加耐壓,同時可避免增加上述裝置的導通電阻。Therefore, it is necessary to find a semiconductor device capable of increasing withstand voltage while avoiding an increase in on-resistance of the above device.
本發明一實施例提供一種半導體裝置,包括:一半導體基底,具有一第一導電型;一井區,具有一第二導電型,形成於半導體基底內;一汲極區及一源極區,分別形成於半導體基底的井區內與井區外側;至少一組第一及第二重摻雜區,形成於汲極區與源極區之間的井區內,其中第一及第二重摻雜區由下而上垂直堆疊,分別具有第一導電型及第二導電型,且摻雜濃度大於井區的摻雜濃度;以及一閘極結構,設置於半導體基底上。An embodiment of the present invention provides a semiconductor device including: a semiconductor substrate having a first conductivity type; a well region having a second conductivity type formed in the semiconductor substrate; a drain region and a source region; Formed in the well region of the semiconductor substrate and outside the well region; at least one set of the first and second heavily doped regions are formed in the well region between the drain region and the source region, wherein the first and second weights The doped regions are vertically stacked from bottom to top, respectively having a first conductivity type and a second conductivity type, and a doping concentration greater than a doping concentration of the well region; and a gate structure disposed on the semiconductor substrate.
本發明另一實施例提供一種半導體裝置之製造方法,包括:提供一半導體基底,其具有一第一導電型;在半導體基底內形成一井區,其中井區具有一第二導電型;在井區內形成至少一組第一及第二重摻雜區,其中第一及第二重摻雜區由下而上垂直堆疊,分別具有第一導電型及第二導電型,且摻雜濃度大於井區的摻雜濃度;在半導體基底 的井區內與井區外側分別形成一汲極區及一源極區,使該組第一及第二重摻雜區位於汲極區與源極區之間的井區內;以及在半導體基底上形成一閘極結構。Another embodiment of the present invention provides a method of fabricating a semiconductor device, comprising: providing a semiconductor substrate having a first conductivity type; forming a well region in the semiconductor substrate, wherein the well region has a second conductivity type; Forming at least one set of first and second heavily doped regions, wherein the first and second heavily doped regions are vertically stacked from bottom to top, respectively having a first conductivity type and a second conductivity type, and the doping concentration is greater than Doping concentration of the well region; at the semiconductor substrate a drain region and a source region are respectively formed in the well region and the outside of the well region, so that the first and second heavily doped regions of the group are located in the well region between the drain region and the source region; and in the semiconductor A gate structure is formed on the substrate.
以下說明本發明實施例之半導體裝置及其製造方法。然而,可輕易了解本發明所提供的實施例僅用於說明以特定方法製作及使用本發明,並非用以侷限本發明的範圍。Hereinafter, a semiconductor device and a method of manufacturing the same according to embodiments of the present invention will be described. However, the present invention is to be understood as being limited to the details of the present invention.
請參照第2D圖,其繪示出根據本發明一實施例之半導體裝置20剖面示意圖。在本實施例中,半導體裝置20可為具有超接面(super junction)結構的一水平式擴散金氧半場效電晶體(LDMOSFET)。再者,半導體裝置20包括一半導體基底200,例如矽基底或絕緣層上覆矽(silicon on insulator,SOI)基底或其他適當的半導體基底,其具有一第一導電型。Referring to FIG. 2D, a cross-sectional view of a semiconductor device 20 in accordance with an embodiment of the present invention is shown. In the present embodiment, the semiconductor device 20 may be a horizontal diffusion metal oxide half field effect transistor (LDMOSFET) having a super junction structure. Furthermore, the semiconductor device 20 includes a semiconductor substrate 200, such as a germanium or silicon on insulator (SOI) substrate or other suitable semiconductor substrate, having a first conductivity type.
一井區204、一源極區218、汲極區220以及一基體區212形成於半導體基底200內。舉例來說,井區204具有相反於第一導電型的一第二導電型,且自半導體基底200的上表面延伸進入半導體基底200內。再者,井區204對應於半導體基底200的一主動區A(由部分的隔離結構(例如,場氧化層214)所定義而成),以作為LDMOSFET的一漂移區。A well region 204, a source region 218, a drain region 220, and a substrate region 212 are formed in the semiconductor substrate 200. For example, well region 204 has a second conductivity type opposite to the first conductivity type and extends into the semiconductor substrate 200 from the upper surface of semiconductor substrate 200. Moreover, the well region 204 corresponds to an active region A of the semiconductor substrate 200 (defined by a portion of the isolation structure (eg, field oxide layer 214)) as a drift region of the LDMOSFET.
源極區218由具有第二導電型的摻雜區218a及具有第一導電型的摻雜區218b所構成。源極區218形成於半導體基底200的井區204外側,且對應於主動區A。再者,基 體區212,具有第一導電型,且形成於半導體基底200的井區204外側,使源極區218位於基體區212內。汲極區220僅由具有第二導電型的摻雜區所構成。汲極區220形成於井區204內,且對應於主動區A。The source region 218 is composed of a doped region 218a having a second conductivity type and a doped region 218b having a first conductivity type. The source region 218 is formed outside the well region 204 of the semiconductor substrate 200 and corresponds to the active region A. Again, base The body region 212 has a first conductivity type and is formed outside the well region 204 of the semiconductor substrate 200 such that the source region 218 is located within the body region 212. The drain region 220 is composed only of a doped region having a second conductivity type. The drain region 220 is formed within the well region 204 and corresponds to the active region A.
至少一組第一重摻雜區201及第二重摻雜區203形成於汲極區220與源極區218之間的井區204內,其中第一重摻雜區201及第二重摻雜區203由下而上垂直堆疊,且第一重摻雜區201為電性浮接(floating)。第一及第二重摻雜區201及203分別具有第一導電型及第二導電型,且摻雜濃度大於井區204的摻雜濃度,以在半導體基底200的井區204內形成一超接面結構。在本實施例中,第一導電類型為P型,且第二導電類型為N型。然而,在其他實施例中,第一導電類型也可為N型,且第二導電類型為P型。At least one first heavily doped region 201 and a second heavily doped region 203 are formed in the well region 204 between the drain region 220 and the source region 218, wherein the first heavily doped region 201 and the second heavily doped region The miscellaneous regions 203 are vertically stacked from bottom to top, and the first heavily doped regions 201 are electrically floating. The first and second heavily doped regions 201 and 203 have a first conductivity type and a second conductivity type, respectively, and the doping concentration is greater than the doping concentration of the well region 204 to form an ultra in the well region 204 of the semiconductor substrate 200. Joint structure. In this embodiment, the first conductivity type is a P type, and the second conductivity type is an N type. However, in other embodiments, the first conductivity type may also be N-type and the second conductivity type is P-type.
在其他實施例中,半導體裝置20可包括複數組第一及第二重摻雜區201及203,垂直堆疊於半導體基底200的井區204內,以在半導體基底200內構成複數個超接面結構。In other embodiments, the semiconductor device 20 can include a plurality of first and second heavily doped regions 201 and 203 stacked vertically within the well region 204 of the semiconductor substrate 200 to form a plurality of super junctions within the semiconductor substrate 200. structure.
閘極結構216係設置於半導體基底200上,且位於源極區218及汲極區220之間。閘極結構216通常包括一閘極(例如,由複晶矽所構成)、位於下方的閘極介電層以及位於閘極介電層下方的場氧化層214。The gate structure 216 is disposed on the semiconductor substrate 200 and between the source region 218 and the drain region 220. Gate structure 216 typically includes a gate (e.g., comprised of a germanium), a gate dielectric layer located below, and a field oxide layer 214 underlying the gate dielectric layer.
半導體裝置20更包括一內層介電層(interlayer dielectric,ILD)226及位於其中的複數個內連結構221、223及225。在本實施例中,內連結構221電性連接於源極區218,以作為一源極電極;內連結構223電性連接於閘極結 構216,以作為一閘極電極;以及內連結構225電性連接於汲極區220,以作為一汲極電極。The semiconductor device 20 further includes an inner dielectric layer (ILD) 226 and a plurality of interconnect structures 221, 223 and 225 located therein. In this embodiment, the interconnect structure 221 is electrically connected to the source region 218 as a source electrode; the interconnect structure 223 is electrically connected to the gate junction. The structure 216 is used as a gate electrode; and the interconnect structure 225 is electrically connected to the drain region 220 to serve as a drain electrode.
在上述實施例中,超接面結構中具有第一導電型且電性浮接的重摻雜區有助於在井區204(即,漂移區)內形成空乏區,進而提升半導體裝置20中LDMOSFET的耐壓。再者,超接面結構中具有第二導電型的重摻雜區則在井區204(即,漂移區)內提供額外的電流路徑,以降低源極區與汲極區之間的導通電阻。In the above embodiment, the heavily doped region having the first conductivity type and electrically floating in the super junction structure helps to form a depletion region in the well region 204 (ie, the drift region), thereby enhancing the semiconductor device 20 The withstand voltage of the LDMOSFET. Furthermore, the heavily doped region having the second conductivity type in the super junction structure provides an additional current path in the well region 204 (ie, the drift region) to reduce the on-resistance between the source region and the drain region. .
第2A至2D圖係繪示出根據本發明一實施例之半導體裝置20之製造方法剖面示意圖。請參照第2A圖,提供一半導體基底200,例如矽基底或絕緣層上覆矽(silicon on insulator,SOI)基底或其他適當的半導體基底,其具有一第一導電型。接著,可依序藉由摻雜製程(例如,離子佈值)及熱擴散等製程,在半導體基底200的一既定區域(即,主動區A)內形成一井區204,其中井區204具有不同於第一導電類型的一第二導電型,以作為後續形成的LDMOSFET的一漂移區。2A through 2D are cross-sectional views showing a method of fabricating a semiconductor device 20 in accordance with an embodiment of the present invention. Referring to FIG. 2A, a semiconductor substrate 200 is provided, such as a germanium substrate or a silicon on insulator (SOI) substrate or other suitable semiconductor substrate having a first conductivity type. Then, a well region 204 may be formed in a predetermined region (ie, active region A) of the semiconductor substrate 200 by a doping process (eg, ion cloth value) and thermal diffusion processes, wherein the well region 204 has A second conductivity type different from the first conductivity type serves as a drift region of the subsequently formed LDMOSFET.
在本實施例中,可在井區204內形成一組第一及第二重摻雜區201及203,其中第一及第二重摻雜區201及203由下而上垂直堆疊。第一及第二重摻雜區201及203分別具有第一導電型及第二導電型,且摻雜濃度大於井區204的摻雜濃度,以在半導體基底200的井區204內形成一超接面結構。In the present embodiment, a set of first and second heavily doped regions 201 and 203 may be formed in the well region 204, wherein the first and second heavily doped regions 201 and 203 are vertically stacked from bottom to top. The first and second heavily doped regions 201 and 203 have a first conductivity type and a second conductivity type, respectively, and the doping concentration is greater than the doping concentration of the well region 204 to form an ultra in the well region 204 of the semiconductor substrate 200. Joint structure.
在其他實施例中,可在半導體基底200的井區204內形成複數組第一及第二重摻雜區201及203。上述複數組 第一及第二重摻雜區201及203大體上彼此垂直對準,以在半導體基底200的井區204內構成複數個超接面結構。In other embodiments, a plurality of first and second heavily doped regions 201 and 203 may be formed in well region 204 of semiconductor substrate 200. The above complex array The first and second heavily doped regions 201 and 203 are generally vertically aligned with each other to form a plurality of super junction structures within the well region 204 of the semiconductor substrate 200.
在上述實施例中,第一及第二重摻雜區201及203係位於後續形成的汲極區220與源極區218(標示於第2C圖中)之間,其中第一重摻雜區201為電性浮接。在本實施例中,第一導電類型為P型,且第二導電類型為N型。然而,在其他實施例中,第一導電類型也可為N型,且第二導電類型為P型。In the above embodiment, the first and second heavily doped regions 201 and 203 are located between the subsequently formed drain region 220 and the source region 218 (indicated in FIG. 2C), wherein the first heavily doped region 201 is an electrical floating connection. In this embodiment, the first conductivity type is a P type, and the second conductivity type is an N type. However, in other embodiments, the first conductivity type may also be N-type and the second conductivity type is P-type.
請參照第2B及2C圖,可透過習知MOS製程,在半導體基底200上形成複數個隔離結構(例如,場氧化層214),其中部分的場氧化層214定義出主動區A,而其他部分的場氧化層214則在井區204內定義出待形成汲極區D。之後,在半導體基底200上形成一閘極結構216,以在主動區A內的井區204外側定義出待形成源極區S,如第2B圖所示。Referring to FIGS. 2B and 2C, a plurality of isolation structures (eg, field oxide layer 214) may be formed on the semiconductor substrate 200 by a conventional MOS process, in which a portion of the field oxide layer 214 defines the active region A, and other portions. The field oxide layer 214 defines a drain region D to be formed in the well region 204. Thereafter, a gate structure 216 is formed over the semiconductor substrate 200 to define a source region S to be formed outside the well region 204 in the active region A, as shown in FIG. 2B.
接著,可依序藉由摻雜製程(例如,離子佈值)及熱擴散等製程,在半導體基底200的井區204外側選擇性形成具有第一導電型的一基體區212,使後續形成的源極區218位於基體區212內。接著,可藉由摻雜製程(例如,離子佈值),在待形成源極區S(標示於第2B圖)形成具有第二導電型的摻雜區218a,且在待形成汲極區D(標示於第2B圖)形成具有第二導電型的摻雜區(即,汲極區220)。之後,在待形成源極區S(標示於第2B圖)形成具有第一導電型的摻雜區218b,使其相鄰於摻雜區218a,並與摻雜區218a構成源極區218,如第2C圖所示。Then, a substrate region 212 having a first conductivity type is selectively formed on the outside of the well region 204 of the semiconductor substrate 200 by a process such as a doping process (for example, ion cloth value) and thermal diffusion, so as to be subsequently formed. Source region 218 is located within substrate region 212. Then, a doping region 218a having a second conductivity type is formed in the source region S to be formed (indicated in FIG. 2B) by a doping process (for example, an ion cloth value), and the drain region D to be formed is formed. (labeled in Figure 2B) forms a doped region having a second conductivity type (i.e., drain region 220). Thereafter, a doped region 218b having a first conductivity type is formed adjacent to the doped region 218a and a source region 218 is formed with the doped region 218a in the source region S to be formed (indicated in FIG. 2B). As shown in Figure 2C.
在其他實施例中,摻雜區218b可在形成摻雜區218a與汲極區220之前形成。在本實施例中,源極區218、閘極結構216、汲極區220以及具有超接面結構的井區204係構成一LDFETMOS。In other embodiments, doped regions 218b may be formed prior to forming doped regions 218a and drain regions 220. In the present embodiment, the source region 218, the gate structure 216, the drain region 220, and the well region 204 having the super junction structure constitute an LDFETMOS.
請參照第2D圖,可透過習知金屬化製程,在半導體基底200上形成一內層介電層(ILD)226及位於其中的複數個內連結構221、223及225。內連結構221電性連接於源極區218,以作為一源極電極;內連結構223電性連接於閘極結構216,以作為一閘極電極;以及內連結構225電性連接於汲極區220,以作為一汲極電極。如此一來,便完成半導體裝置20的製作。Referring to FIG. 2D, an inner dielectric layer (ILD) 226 and a plurality of interconnect structures 221, 223 and 225 located therein may be formed on the semiconductor substrate 200 by a conventional metallization process. The interconnect structure 221 is electrically connected to the source region 218 as a source electrode; the interconnect structure 223 is electrically connected to the gate structure 216 as a gate electrode; and the interconnect structure 225 is electrically connected to the gate electrode 225. The pole region 220 serves as a drain electrode. In this way, the fabrication of the semiconductor device 20 is completed.
根據上述實施例,由於超接面結構中具有第一導電型且電性浮接的重摻雜區可在漂移區內形成空乏區,因此可提升半導體裝置中LDMOSFET的耐壓。再者,由於超接面結構中具有第二導電型的重摻雜區在漂移區內提供額外的電流路徑,因此可降低LDMOSFET的導通電阻。另外,根據上述實施例,可藉由控制在漂移區內垂直堆疊的超接面結構的數量,以進一步提升LDMOSFET的耐壓,同時避免增加LDMOSFET的導通電阻。According to the above embodiment, since the heavily doped region having the first conductivity type and electrically floating in the super junction structure can form a depletion region in the drift region, the withstand voltage of the LDMOSFET in the semiconductor device can be improved. Furthermore, since the heavily doped region having the second conductivity type in the super junction structure provides an additional current path in the drift region, the on-resistance of the LDMOSFET can be lowered. In addition, according to the above embodiment, the withstand voltage of the LDMOSFET can be further improved by controlling the number of super junction structures vertically stacked in the drift region while avoiding an increase in the on-resistance of the LDMOSFET.
雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can be modified and retouched without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.
10‧‧‧N型水平式擴散金氧半場效電晶體10‧‧‧N type horizontal diffusion gold oxide half field effect transistor
100‧‧‧P型半導體基底100‧‧‧P type semiconductor substrate
102‧‧‧P型磊晶層102‧‧‧P type epitaxial layer
104‧‧‧N型漂移區104‧‧‧N type drift zone
106‧‧‧P型基體區106‧‧‧P type base area
108‧‧‧P型接觸區108‧‧‧P type contact area
110、112‧‧‧N型接觸區110, 112‧‧‧N type contact area
114‧‧‧場氧化層114‧‧‧Field oxide layer
116‧‧‧閘極結構116‧‧‧ gate structure
117‧‧‧源極電極117‧‧‧ source electrode
119‧‧‧汲極電極119‧‧‧汲electrode
121‧‧‧閘極電極121‧‧‧gate electrode
20‧‧‧半導體裝置20‧‧‧Semiconductor device
200‧‧‧半導體基底200‧‧‧Semiconductor substrate
201‧‧‧第一重摻雜區201‧‧‧First heavily doped area
203‧‧‧第二重摻雜區203‧‧‧Second heavily doped area
204‧‧‧井區204‧‧‧ Well Area
212‧‧‧基體區212‧‧‧basal area
214‧‧‧場氧化層214‧‧ ‧ field oxide layer
216‧‧‧閘極結構216‧‧‧ gate structure
218‧‧‧源極區218‧‧‧ source area
218a、218b‧‧‧摻雜區218a, 218b‧‧‧ doped area
220‧‧‧汲極區220‧‧‧Bungee Area
221、223、225‧‧‧內連結構221, 223, 225‧‧‧ interconnected structure
226‧‧‧內層介電層226‧‧‧ Inner dielectric layer
A‧‧‧主動區A‧‧‧active area
D‧‧‧待形成汲極區D‧‧‧To be formed into the bungee area
S‧‧‧待形成源極區S‧‧‧The source area to be formed
第1圖係繪示出習知的N型水平式擴散金氧半場效電晶體剖面示意圖。Fig. 1 is a schematic cross-sectional view showing a conventional N-type horizontal diffusion gold-oxygen half field effect transistor.
第2A至2D圖係繪示出根據本發明一實施例之半導體裝置之製造方法剖面示意圖。2A to 2D are cross-sectional views showing a method of fabricating a semiconductor device in accordance with an embodiment of the present invention.
20‧‧‧半導體裝置20‧‧‧Semiconductor device
200‧‧‧半導體基底200‧‧‧Semiconductor substrate
201‧‧‧第一摻雜區201‧‧‧First doped area
203‧‧‧第二摻雜區203‧‧‧Second doped area
204‧‧‧井區204‧‧‧ Well Area
212‧‧‧基體區212‧‧‧basal area
214‧‧‧場氧化層214‧‧ ‧ field oxide layer
216‧‧‧閘極結構216‧‧‧ gate structure
218‧‧‧源極區218‧‧‧ source area
218a、218b‧‧‧摻雜區218a, 218b‧‧‧ doped area
220‧‧‧汲極區220‧‧‧Bungee Area
221、223、225‧‧‧內連結構221, 223, 225‧‧‧ interconnected structure
226‧‧‧內層介電層226‧‧‧ Inner dielectric layer
A‧‧‧主動區A‧‧‧active area
Claims (12)
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US20120187481A1 (en) * | 2009-12-02 | 2012-07-26 | Alpha & Omega Semiconductor, Inc. | Vertical Trench LDMOS Transistor |
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EP1286399A2 (en) * | 2001-08-23 | 2003-02-26 | Micrel Incorporated | LDMOS field-effect transistors |
US20120187481A1 (en) * | 2009-12-02 | 2012-07-26 | Alpha & Omega Semiconductor, Inc. | Vertical Trench LDMOS Transistor |
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