WO2023245604A1 - 薄膜晶体管及其制备方法、显示装置 - Google Patents

薄膜晶体管及其制备方法、显示装置 Download PDF

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WO2023245604A1
WO2023245604A1 PCT/CN2022/101047 CN2022101047W WO2023245604A1 WO 2023245604 A1 WO2023245604 A1 WO 2023245604A1 CN 2022101047 W CN2022101047 W CN 2022101047W WO 2023245604 A1 WO2023245604 A1 WO 2023245604A1
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Prior art keywords
active layer
thin film
film transistor
gate electrode
substrate
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PCT/CN2022/101047
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English (en)
French (fr)
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WO2023245604A9 (zh
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宋泳锡
李禹奉
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京东方科技集团股份有限公司
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Priority to CN202280001926.5A priority Critical patent/CN117642875A/zh
Priority to PCT/CN2022/101047 priority patent/WO2023245604A1/zh
Publication of WO2023245604A1 publication Critical patent/WO2023245604A1/zh
Publication of WO2023245604A9 publication Critical patent/WO2023245604A9/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a thin film transistor, a preparation method thereof, and a display device.
  • TFT Thin Film Transistor
  • the technical problem to be solved by this disclosure is to provide a thin film transistor, a preparation method thereof, and a display device, which can increase the on-state current of the thin film transistor and reduce the area of the thin film transistor.
  • a thin film transistor including a gate electrode extending along a first direction and a first active layer provided on a substrate, the first active layer having an arch structure, and the gate electrode passing through the In the arch structure, the orthographic projection of the first active layer on the substrate covers the orthographic projection of the gate electrode on the substrate.
  • the thin film transistor further includes a first gate insulating layer
  • the gate electrode is located on the substrate and extends along the first direction
  • the first gate insulating layer covers the gate electrode, and the first gate insulating layer includes two first slots;
  • the first active layer is located on a side of the first gate insulating layer away from the gate electrode, extends along the first direction, and fills the two first grooves to form the arch structure. Two arch side surfaces surround the gate electrode.
  • the thin film transistor further includes:
  • the source electrode and the drain electrode located on the side of the first active layer away from the substrate are respectively connected to the first active layer.
  • the thin film transistor further includes:
  • the second active layer is located on the side of the gate electrode away from the first active layer.
  • the second active layer is respectively connected to the two arch side surfaces to form a channel surrounding the gate electrode.
  • the first active layer further includes a first connection portion connected to the side surface of the arch, the first connection portion is located outside the arch structure and is parallel or substantially parallel to the base;
  • the second active layer includes a second connection portion corresponding to the first connection portion.
  • the second connection portion is located outside the arch structure and is parallel or substantially parallel to the substrate.
  • the second connection portion In direct contact with the corresponding first connecting portion, the orthographic projection of the second connecting portion on the substrate at least partially overlaps with the orthographic projection of the corresponding first connecting portion on the substrate.
  • the second connection portion is conductorized; and/or
  • the first connecting portion is conductorized.
  • the thin film transistor further includes:
  • a second gate insulating layer located between the gate electrode and the second active layer, the second gate insulating layer including two second grooves, the first groove and the second groove Through, the two arch side surfaces are connected to the second active layer through the second slot.
  • the thin film transistor further includes:
  • the extension direction of the first connection part is a second direction, the second direction is parallel or substantially parallel to the base and perpendicular to the first direction, and the first active layer passes through the first
  • the connection part is connected to the source electrode
  • the extension direction of the second connection part is the second direction, and the first active layer is connected to the drain electrode through the second connection part.
  • the thin film transistor further includes:
  • An interlayer insulating layer located between the first active layer and the source and drain electrodes.
  • the first active layer is connected to the source electrode through a first via hole penetrating the interlayer insulating layer.
  • An embodiment of the present disclosure also provides a display device including the thin film transistor as described above.
  • the gate electrode and the gate line of the display device have an integral structure.
  • the orthographic projection of the first via hole on the substrate falls within the orthographic projection of the gate line on the substrate;
  • the orthographic projection of the second via hole on the substrate falls within the orthographic projection of the gate line on the substrate.
  • Embodiments of the present disclosure also provide a method for manufacturing a thin film transistor, including:
  • a gate electrode extending along a first direction and a first active layer are formed on the substrate, the first active layer is an arch structure, the gate electrode is disposed in the arch structure, and the first active layer
  • the orthographic projection on the substrate covers the orthographic projection of the gate electrode on the substrate.
  • the preparation method further includes:
  • first gate insulating layer covering the gate electrode, the first gate insulating layer including two first slots;
  • the first active layer is located on a side of the first gate insulating layer away from the gate electrode, extends along the first direction, and fills the two first grooves to form the arch structure. Two arch side surfaces surround the gate electrode.
  • the preparation method further includes:
  • a second active layer is formed on the side of the gate electrode away from the first active layer.
  • the second active layer is connected to the two arch side surfaces respectively to form a channel surrounding the gate electrode. .
  • the structure in which the three-dimensional channel surrounds the gate electrode can increase the channel width of the thin film transistor, improve the width-to-length ratio of the channel of the thin film transistor, and thereby increase the on-state capability of the thin film transistor.
  • the three-dimensional channel surrounds the gate electrode.
  • the structure of the electrode strengthens the gate electrode's control over the conductivity of the channel, effectively improving the driving capability and operating stability of the thin film transistor.
  • the structure of the three-dimensional channel surrounding the gate electrode effectively reduces the area of the thin film transistor. It is beneficial to improve the aperture ratio of the display device, meet the high resolution requirements, and effectively solve the problem that it is difficult to improve the resolution by reducing the area of the thin film transistor in the existing structure.
  • FIGS. 1-5 are schematic diagrams of manufacturing a thin film transistor according to an embodiment of the present disclosure
  • Figure 6 is a schematic diagram of the on-state current direction of an existing thin film transistor
  • Figure 7 is a schematic diagram of the on-state current direction of a thin film transistor according to an embodiment of the present disclosure.
  • FIGS. 8-13 are schematic diagrams of manufacturing a thin film transistor according to another embodiment of the present disclosure.
  • Figure 14 is a schematic plan view of a conventional display device
  • Figure 15 is a schematic plan view of a display device according to an embodiment of the present disclosure.
  • Figure 16 is a three-dimensional schematic diagram of a thin film transistor according to an embodiment of the present disclosure.
  • Figure 17 is a schematic plan view of a display device according to another embodiment of the present disclosure.
  • Figure 18 is a three-dimensional schematic diagram of a thin film transistor according to another embodiment of the present disclosure.
  • Figure 19 is a schematic plan view of a display device according to another embodiment of the present disclosure.
  • Figure 20 is a three-dimensional schematic diagram of a thin film transistor according to another embodiment of the present disclosure.
  • Embodiments of the present disclosure provide a thin film transistor, a preparation method thereof, and a display device, which can increase the on-state current of the thin film transistor and reduce the area of the thin film transistor.
  • Embodiments of the present disclosure provide a thin film transistor, including a gate electrode extending along a first direction and a first active layer provided on a substrate, the first active layer having an arch structure, and the gate electrode passing through In the arch structure, the orthographic projection of the first active layer on the substrate covers the orthographic projection of the gate electrode on the substrate.
  • the structure in which the gate electrode is surrounded by a three-dimensional channel can increase the channel width of the thin film transistor, improve the width-to-length ratio of the channel of the thin film transistor, and thereby increase the on-state capability of the thin film transistor.
  • the three-dimensional channel surrounds the gate electrode.
  • the structure of the gate electrode strengthens the gate electrode's control over the channel's conductivity, effectively improving the driving capability and operating stability of the thin film transistor.
  • the structure of the three-dimensional channel surrounding the gate electrode effectively reduces the area of the thin film transistor. , which is conducive to improving the aperture ratio of the display device, meeting the high resolution requirements, and effectively solving the problem that the existing structure is difficult to improve the resolution by reducing the area of the thin film transistor.
  • the thin film transistor of this embodiment includes a substrate 01, a buffer layer 02 provided on the substrate 01, a gate electrode 05 located on the buffer layer 02, and a gate electrode 05 covering the gate electrode 05.
  • a source layer 08 surrounds the gate electrode 05 .
  • the gate electrode 05 extends along the first direction
  • the first gate insulating layer 06 covers the gate electrode 05, and the first gate insulating layer 06 includes two first grooves;
  • the first active layer 08 is located on the side of the first gate insulating layer 06 away from the gate electrode 05 , extends along the first direction, and fills the two first grooves to form the first active layer 08 .
  • Two arch side surfaces 088 of the arch structure surround the gate electrode 05 .
  • the thin film transistor also includes: an interlayer insulating layer 09 located on the side of the first active layer 08 away from the substrate 01 , and a source electrode and a drain electrode located on the side of the interlayer insulating layer 09 away from the substrate 01 .
  • Layer 08 is connected to the source electrode through a first via hole 101 penetrating the interlayer insulating layer, and is connected to the drain electrode through a second via hole 102 penetrating the interlayer insulating layer.
  • the annular arch structure of the first active layer 08 is similar to an inverted U shape, and the U-shaped opening faces the direction of the substrate.
  • the annular arch structure has three surfaces toward the base, an arch upper surface 087 located at the top of the arch and two arch side surfaces 088 located on both sides of the arch upper surface 087, the arch side surface 088, the arch upper surface 087 and the arch side surfaces. 088 forms an annular shape that is not closed on three sides, and the gate electrode 05 is surrounded by this annular shape that is not closed on three sides.
  • the thin film transistor may further include:
  • the second active layer 03 is located on the side of the gate electrode 05 away from the first active layer 08.
  • the second active layer 03 is connected to the two side surfaces of the arches to form a structure surrounding the gate electrode. 05 channel.
  • the second active layer 03 can be connected to the first active layer 08 to form a closed ring surrounding the gate electrode 05.
  • the first active layer 08 and the second active layer 03 form a ring surrounding the gate electrode 05.
  • the three-dimensional channel can increase the channel width of the thin film transistor through the structure of the three-dimensional channel surrounding the gate electrode, improve the width-to-length ratio of the thin film transistor channel, and thereby increase the on-state current of the thin film transistor.
  • the three-dimensional channel surrounds the gate electrode.
  • the structure of the electrode strengthens the gate electrode's control over the conductivity of the channel, effectively improving the driving capability and operating stability of the thin film transistor.
  • the structure of the three-dimensional channel surrounding the gate electrode effectively reduces the area of the thin film transistor. It is beneficial to improve the aperture ratio of the display device, meet the high resolution requirements, and effectively solve the problem that it is difficult to improve the resolution by reducing the area of the thin film transistor in the existing structure.
  • the thin film transistor further includes: a second gate insulating layer 04 located between the gate electrode 05 and the second active layer 03 , and the second gate insulating layer 04 includes two The second groove, the first groove and the second groove are connected through each other, and the two arch side surfaces 088 are connected to the second active layer 03 through the second groove.
  • the first active layer 08 in addition to an arch structure, also includes a side surface 088 connected to the arch.
  • the connected first connection part 081 is located outside the arch structure and is parallel or substantially parallel to the substrate 01;
  • the second active layer 03 includes a connection part corresponding to the first connection part 081
  • the second connection part 031 is located outside the arch structure and is parallel or substantially parallel to the base 01.
  • the second connection part 031 is in direct contact with the corresponding first connection part 081 , the orthographic projection of the second connecting portion 031 on the substrate at least partially overlaps the orthographic projection of the corresponding first connecting portion 081 on the substrate.
  • the second connection part 031 may undergo conductorization processing; and/or the first connection part 081 may pass through a conductor. chemical treatment. Only the first connection part 081 may be conductorized, only the second connection part 031 may be conductorized, or both the first connection part 081 and the second connection part 031 may be conductorized, wherein, in When the first connection part 081 is subjected to conductorization treatment, part or all of the first connection part 081 may be conductorized; when the second connection part 031 is subjected to conductorization treatment, part of the second connection part 031 may be conductorized. Or all conductive treatment.
  • the technical solution of this embodiment will be further described below through the preparation process of the thin film transistor of this embodiment.
  • the "patterning process” mentioned in this embodiment includes processes such as deposition of film layers, coating of photoresist, mask exposure, development, etching, and stripping of photoresist, and is a mature preparation process in related technologies.
  • Deposition can use known processes such as sputtering, evaporation, chemical vapor deposition, etc.
  • coating can use known coating processes, and etching can use known methods, which are not specifically limited here.
  • thin film refers to a thin film produced by depositing or coating a certain material on a substrate.
  • the "thin film” does not require patterning or photolithography processes during the entire production process, the “thin film” can also be called a “layer.” If the "thin film” requires a patterning process or photolithography process during the entire production process, it will be called a “thin film” before the patterning process, and it will be called a “layer” after the patterning process. The "layer” after the patterning process or photolithography process contains at least one "pattern".
  • a gate electrode extending along a first direction and a first active layer are formed on the substrate, the first active layer is an arch structure, the gate electrode is disposed in the arch structure, and the first active layer
  • the orthographic projection on the substrate covers the orthographic projection of the gate electrode on the substrate.
  • the preparation method further includes:
  • first gate insulating layer covering the gate electrode, the first gate insulating layer including two first grooves;
  • the first active layer is located on a side of the first gate insulating layer away from the gate electrode, extends along the first direction, and fills the two first grooves to form the arch structure. Two arch side surfaces surround the gate electrode.
  • the preparation method further includes:
  • a second active layer is formed on the side of the gate electrode away from the first active layer.
  • the second active layer is connected to the two arch side surfaces respectively to form a channel surrounding the gate electrode. .
  • the preparation method of this embodiment includes the following steps:
  • a buffer layer 02 and a second active layer 03 are formed on a substrate 01 .
  • the buffer layer 02 can be made of silicon oxide SiOx, silicon nitride SiNx, silicon oxynitride SiON, etc., or it can be made of high k materials, such as aluminum oxide AlOx, hafnium oxide HfOx, tantalum oxide TaOx, etc. It can be a single layer, multi-layer or Composite layer.
  • the buffer layer 02 is mainly used to prevent impurities contained in the substrate 01 from diffusing into the second active layer 03 to prevent effects on the threshold voltage, leakage current and other characteristics of the thin film transistor.
  • Form an active layer film on the buffer layer 02 Apply a layer of photoresist on the active layer film, use a single-tone mask to expose and develop the photoresist, and form an unexposed area at the active layer pattern position. , the photoresist is retained, and a fully exposed area is formed in other positions. The photoresist is removed, and the active layer film in the fully exposed area is etched and the remaining photoresist is peeled off to form the pattern of the second active layer 03 .
  • the second active layer 03 can be made of amorphous silicon a-Si, polycrystalline silicon p-Si, amorphous indium gallium zinc oxide material a-IGZO, zinc oxynitride ZnON, indium zinc tin oxide IZTO, hexathiophene, polythiophene, etc.
  • This material means that the embodiments of the present disclosure are applicable to thin film transistors manufactured based on amorphous silicon technology, polycrystalline silicon technology, oxide Oxide technology, and organic technology. They can be N-type thin film transistors or P-type thin film transistors.
  • the second active layer 03 in this embodiment is made of polysilicon to form a low temperature polysilicon (Low Temperature Poly Silicon, LTPS) thin film transistor.
  • a second gate insulating layer 04 is formed.
  • the second gate insulating layer 04 can be made of silicon oxide SiOx, silicon nitride SiNx, silicon oxynitride SiON, etc., or it can also be made of high k material, such as aluminum oxide AlOx, Hafnium oxide HfOx, tantalum oxide TaOx, etc. can be single layer, multi-layer or composite layer.
  • forming the gate electrode 05 includes: forming a metal film, and patterning the metal film to form the gate electrode 05 .
  • the metal film can be made of metal materials, such as silver Ag, copper Cu, aluminum Al, molybdenum Mo, etc., or alloy materials of the above metals, such as aluminum neodymium alloy AlNd, molybdenum niobium alloy MoNb, etc. It can be a multi-layer metal, such as Mo/Cu /Mo, etc., or it can be a stack structure formed of metal and transparent conductive materials, such as ITO/Ag/ITO, etc.
  • a first gate insulating layer 06 is formed.
  • the first gate insulating layer 06 can be made of silicon oxide SiOx, silicon nitride SiNx, silicon oxynitride SiON, etc., or it can also be made of high k materials, such as aluminum oxide AlOx, Hafnium oxide HfOx, tantalum oxide TaOx, etc. can be single layer, multi-layer or composite layer.
  • the first gate insulating layer 06 may be prepared using an atomic layer deposition ALD process.
  • the first gate insulating layer 06 is etched using the pattern of the photoresist 07 as a mask to form a groove penetrating the first gate insulating layer 06 , as shown in the rectangular dotted line frame.
  • the second active layer 03 is conductive through a groove penetrating the first gate insulating layer 06 to form the second connection portion 031 and improve the conductivity of the second connection portion 031.
  • the second active layer 03 can be conductive through a doping process.
  • the second active layer 03 is subjected to a conductorization process. The doping and doping process are well known to those skilled in the art and will not be described again here. Then remove the pattern of photoresist 07.
  • the first active layer 08 is formed. Specifically, an active layer film is formed, a layer of photoresist is coated on the active layer film, and a single-tone mask is used to expose the photoresist and Developing, forming an unexposed area at the active layer pattern position, retaining the photoresist, forming a fully exposed area at other positions, the photoresist is removed, etching the active layer film in the fully exposed area and stripping off the remaining light Resist to form the pattern of the first active layer 08 .
  • the first active layer 08 can be made of amorphous silicon a-Si, polycrystalline silicon p-Si, amorphous indium gallium zinc oxide material a-IGZO, zinc oxynitride ZnON, indium zinc tin oxide IZTO, hexathiophene, polythiophene, etc.
  • This material means that the embodiments of the present disclosure are applicable to thin film transistors manufactured based on amorphous silicon technology, polycrystalline silicon technology, oxide Oxide technology, and organic technology. They can be N-type thin film transistors or P-type thin film transistors.
  • the first active layer 08 in this embodiment is made of polysilicon to form a low temperature polysilicon (Low Temperature Poly Silicon, LTPS) thin film transistor.
  • the first active layer 08 is connected to the second active layer 03 through a groove that penetrates the first gate insulating layer 06 and the second gate insulating layer 04 .
  • the first active layer 08 and the second active layer 03 form a surrounding gate electrode.
  • 05's ring structure forms a three-dimensional structure channel.
  • the interlayer insulating layer 09 is formed.
  • the interlayer insulating layer 09 can be made of silicon oxide SiOx, silicon nitride SiNx, silicon oxynitride SiON, etc., or high k materials, such as aluminum oxide AlOx, hafnium oxide HfOx, tantalum oxide TaOx, etc. , can be a single layer, multi-layer or composite layer.
  • the interlayer insulating layer 09 includes a first via hole 101 and a second via hole 102.
  • the source electrode can be connected to the first active layer 08 through the first via hole 101.
  • the drain electrode It can be connected to the first active layer 08 through the second via hole 102 .
  • the second active layer 03 can be doped through the first via hole 101 and the second via hole 102.
  • the relevant doping and doping processing processes are well known to those skilled in the art and will not be discussed here. Again.
  • FIG. 6 is a schematic diagram of the on-state current direction of the existing thin film transistor, in which 11 is the active layer, 122 is the source electrode, 121 is the drain electrode, and 05 is the gate electrode;
  • Figure 7 is the on-state current of the thin film transistor according to the embodiment of the present disclosure.
  • the shortest distance between the drain electrode and the source electrode is the length of the channel of the thin film transistor; the length of the active layer 11 surrounding the gate electrode 05 (Perimeter) is the channel width of the thin film transistor, so the width-to-length ratio of the channel of the thin film transistor can be increased.
  • the gate electrode and channel are both horizontal structures. Since the shorter the channel length, the greater the leakage current and the serious short channel effect, it is difficult to further reduce the channel length of this structure. It is difficult to increase the width-to-length ratio of the channel of the transistor, and it is difficult to further reduce the area of the thin film transistor.
  • Embodiments of the present disclosure actually form a three-dimensional channel through a structure in which an annular channel surrounds the gate electrode, which increases the width-to-length ratio of the channel of the thin film transistor and can ensure the performance of the thin film transistor.
  • the area of the thin film transistor of this embodiment is much smaller than that of the existing quasi-planar structure thin film transistor.
  • the projected area of the channel region of the thin film transistor of this embodiment can be reduced by 50% to 60% compared with the projected area of the channel region of the existing quasi-planar structure thin film transistor, effectively reducing the The area of the thin film transistor is reduced.
  • the embodiment of the present disclosure uses a structure in which an annular channel surrounds the gate electrode, the channel width and length can be effectively increased. Compared with W/L, it speeds up the channel opening speed, increases electron mobility, reduces threshold voltage drift, effectively improves the driving capability and operating stability of thin film transistors, and can also speed up channel closing by providing stable negative voltage. speed, further reducing leakage current and reducing power consumption.
  • the preparation of thin film transistors according to the embodiments of the present disclosure does not require changing the existing process flow or the existing process equipment. It has good compatibility with existing processes, high process achievability, strong practicability, and good application prospects. .
  • the thin film transistor of this embodiment includes a substrate 01, a buffer layer 02 provided on the substrate 01, a gate electrode 05 located on the buffer layer 02, and covering the gate electrode 05.
  • the gate electrode 05 extends along the first direction
  • the first gate insulating layer 06 covers the gate electrode 05, and the first gate insulating layer 06 includes two first grooves;
  • the first active layer 08 is located on the side of the first gate insulating layer 06 away from the gate electrode 05 , extends along the first direction, and fills the two first grooves to form the first active layer 08 .
  • Two arch side surfaces of the arch structure surround the gate electrode 05 .
  • the thin film transistor also includes: an interlayer insulating layer 09 located on the side of the first active layer 08 away from the substrate 01, and a source-drain metal layer 12 located on the side of the inter-layer insulating layer 09 away from the substrate 01.
  • the source-drain metal layer 12 passes through The via hole 10 penetrating the interlayer insulating layer 09 is connected to the first active layer 08 , and the source and drain metal layer 12 includes a source electrode and/or a drain electrode.
  • the annular arch structure of the first active layer 08 is similar to an inverted U shape, and the U-shaped opening faces the direction of the substrate.
  • the annular arch structure has three surfaces toward the base, an upper surface of the arch located at the top of the arch and two side surfaces of the arch located on both sides of the upper surface of the arch.
  • the side surfaces of the arch, the upper surface of the arch and the side surfaces of the arch form a three-sided non-closed
  • the gate electrode 05 is annular, and the gate electrode 05 is surrounded by the three-sided non-closed annular shape.
  • the thin film transistor may further include:
  • the second active layer 03 is located on the side of the gate electrode 05 away from the first active layer 08.
  • the second active layer 03 is connected to the two side surfaces of the arches to form a structure surrounding the gate electrode. 05 channel.
  • the second active layer 03 can be connected to the first active layer 08 to form a closed ring surrounding the gate electrode 05.
  • the first active layer 08 and the second active layer 03 form a ring surrounding the gate electrode 05.
  • the three-dimensional channel can increase the channel width of the thin film transistor through the structure of the three-dimensional channel surrounding the gate electrode, improve the width-to-length ratio of the thin film transistor channel, and thereby increase the on-state current of the thin film transistor.
  • the three-dimensional channel surrounds the gate electrode.
  • the structure of the electrode strengthens the gate electrode's control over the channel conductivity, effectively improving the driving capability and operating stability of the thin film transistor; in addition, the structure of the three-dimensional channel surrounding the gate electrode effectively reduces the area of the thin film transistor. It is beneficial to improve the aperture ratio of the display device, meet the high resolution requirements, and effectively solve the problem that it is difficult to improve the resolution by reducing the area of the thin film transistor in the existing structure.
  • the thin film transistor further includes: a second gate insulating layer 04 located between the gate electrode 05 and the second active layer 03 .
  • the second gate insulating layer 04 includes two The second groove, the first groove and the second groove penetrate, and the two arch side surfaces are connected to the second active layer 03 through the second groove.
  • the first active layer 08 can be conductive through the via hole 10 to form the conductive portion 082 .
  • the preparation method of the thin film transistor in this embodiment includes:
  • a gate electrode extending along a first direction and a first active layer are formed on the substrate, the first active layer is an arch structure, the gate electrode is disposed in the arch structure, and the first active layer
  • the orthographic projection on the substrate covers the orthographic projection of the gate electrode on the substrate.
  • the preparation method further includes:
  • first gate insulating layer covering the gate electrode, the first gate insulating layer including two first grooves;
  • the first active layer is located on a side of the first gate insulating layer away from the gate electrode, extends along the first direction, and fills the two first grooves to form the arch structure. Two arch side surfaces surround the gate electrode.
  • the preparation method further includes:
  • a second active layer is formed on the side of the gate electrode away from the first active layer.
  • the second active layer is connected to the two arch side surfaces respectively to form a channel surrounding the gate electrode. .
  • the preparation method of the thin film transistor of this embodiment includes the following steps:
  • the buffer layer 02 can be made of silicon oxide SiOx, silicon nitride SiNx, silicon oxynitride SiON, etc., or it can be made of high k materials, such as aluminum oxide AlOx, hafnium oxide HfOx, tantalum oxide TaOx, etc., and can be a single layer, multi-layer or Composite layer.
  • the buffer layer 02 is mainly used to prevent impurities contained in the substrate 01 from diffusing into the second active layer 03 to prevent effects on the threshold voltage, leakage current and other characteristics of the thin film transistor.
  • Form an active layer film on the buffer layer 02 Apply a layer of photoresist on the active layer film, use a single-tone mask to expose and develop the photoresist, and form an unexposed area at the active layer pattern position. , the photoresist is retained, and a fully exposed area is formed in other positions. The photoresist is removed, and the active layer film in the fully exposed area is etched and the remaining photoresist is peeled off to form the pattern of the second active layer 03 .
  • the second active layer 03 can be made of amorphous silicon a-Si, polycrystalline silicon p-Si, amorphous indium gallium zinc oxide material a-IGZO, zinc oxynitride ZnON, indium zinc tin oxide IZTO, hexathiophene, polythiophene, etc.
  • This material means that the embodiments of the present disclosure are applicable to thin film transistors manufactured based on amorphous silicon technology, polycrystalline silicon technology, oxide Oxide technology, and organic technology. They can be N-type thin film transistors or P-type thin film transistors.
  • the second active layer 03 in this embodiment is made of polysilicon to form a low temperature polysilicon (Low Temperature Poly Silicon, LTPS) thin film transistor.
  • a second gate insulating layer 04 is formed.
  • the second gate insulating layer 04 can be made of silicon oxide SiOx, silicon nitride SiNx, silicon oxynitride SiON, etc., or it can also be made of high k materials, such as aluminum oxide AlOx, Hafnium oxide HfOx, tantalum oxide TaOx, etc. can be single layer, multi-layer or composite layer.
  • forming the gate electrode 05 includes: forming a metal film, and patterning the metal film to form the gate electrode 05 .
  • the metal film can be made of metal materials, such as silver Ag, copper Cu, aluminum Al, molybdenum Mo, etc., or alloy materials of the above metals, such as aluminum neodymium alloy AlNd, molybdenum niobium alloy MoNb, etc. It can be a multi-layer metal, such as Mo/Cu /Mo, etc., or it can be a stack structure formed of metal and transparent conductive materials, such as ITO/Ag/ITO, etc.
  • a first gate insulating layer 06 is formed.
  • the first gate insulating layer 06 can be made of silicon oxide SiOx, silicon nitride SiNx, silicon oxynitride SiON, etc., or it can also be made of high k material, such as aluminum oxide AlOx, Hafnium oxide HfOx, tantalum oxide TaOx, etc. can be single layer, multi-layer or composite layer.
  • the first gate insulating layer 06 may be prepared using an atomic layer deposition ALD process.
  • the grooves of the first gate insulating layer 06 and the grooves of the second gate insulating layer 04 penetrate through each other, forming a groove structure shown in the dotted line frame.
  • the first active layer 08 is formed. Specifically, an active layer film is formed, a layer of photoresist is coated on the active layer film, and a single-tone mask is used to expose the photoresist and Developing, forming an unexposed area at the active layer pattern position, retaining the photoresist, forming a fully exposed area at other positions, the photoresist is removed, etching the active layer film in the fully exposed area and stripping off the remaining light Resist to form the pattern of the first active layer 08 .
  • the first active layer 08 can be made of amorphous silicon a-Si, polycrystalline silicon p-Si, amorphous indium gallium zinc oxide material a-IGZO, zinc oxynitride ZnON, indium zinc tin oxide IZTO, hexathiophene, polythiophene, etc.
  • This material means that the embodiments of the present disclosure are applicable to thin film transistors manufactured based on amorphous silicon technology, polycrystalline silicon technology, oxide Oxide technology, and organic technology. They can be N-type thin film transistors or P-type thin film transistors.
  • the first active layer 08 in this embodiment is made of polysilicon to form a low temperature polysilicon (Low Temperature Poly Silicon, LTPS) thin film transistor.
  • the first active layer 08 is connected to the second active layer 03 through a groove that penetrates the first gate insulating layer 06 and the second gate insulating layer 04 .
  • the first active layer 08 and the second active layer 03 form a surrounding gate electrode.
  • 05's ring structure forms a three-dimensional structure channel.
  • the first active layer 08 is etched to remove the portion of the first active layer 08 located outside the arched structure.
  • an interlayer insulating layer 09 is formed.
  • the interlayer insulating layer 09 can be made of silicon oxide SiOx, silicon nitride SiNx, silicon oxynitride SiON, etc., or it can also be made of high k materials, such as aluminum oxide AlOx, hafnium oxide HfOx, tantalum oxide TaOx, etc., can be a single layer, multi-layer or composite layer.
  • the interlayer insulating layer 09 includes a via hole 10, and the source electrode and/or the drain electrode can be connected to the first active layer 08 through the via hole 10.
  • the first active layer 08 can be doped through the via hole 10 to form a conductive portion 082 .
  • the doping and doping treatment processes are well known to those skilled in the art and will not be described again here.
  • forming the pattern of the source-drain metal layer 12 includes forming a metal film, and patterning the metal film to form the pattern of the source-drain metal layer 12 , including a source electrode and a drain electrode.
  • the metal film can be made of metal materials, such as silver Ag, copper Cu, aluminum Al, molybdenum Mo, etc., or alloy materials of the above metals, such as aluminum neodymium alloy AlNd, molybdenum niobium alloy MoNb, etc. It can be a multi-layer metal, such as Mo/Cu /Mo, etc., or it can be a stack structure formed of metal and transparent conductive materials, such as ITO/Ag/ITO, etc.
  • FIG. 6 is a schematic diagram of the on-state current direction of the existing thin film transistor, in which 11 is the active layer, 122 is the source electrode, and 121 is the drain electrode;
  • Figure 7 is a schematic diagram of the on-state current direction of the thin film transistor according to the embodiment of the present disclosure.
  • the shortest distance between the drain electrode and the source electrode is the length of the channel of the thin film transistor; the length (circumference) of the active layer 11 surrounding the gate electrode 05 is The channel width of the thin film transistor can therefore increase the width-to-length ratio of the channel of the thin film transistor.
  • the gate electrode and channel are both horizontal structures. Since the shorter the channel length, the greater the leakage current and the serious short channel effect, it is difficult to further reduce the channel length of this structure. It is difficult to increase the width-to-length ratio of the channel of the transistor, and it is difficult to further reduce the area of the thin film transistor.
  • Embodiments of the present disclosure actually form a three-dimensional channel through a structure in which an annular channel surrounds the gate electrode, which increases the width-to-length ratio of the channel of the thin film transistor and can ensure the performance of the thin film transistor.
  • the area of the thin film transistor of this embodiment is much smaller than that of the existing quasi-planar structure thin film transistor.
  • the projected area of the channel region of the thin film transistor of this embodiment can be reduced by 50% to 60% compared with the projected area of the channel region of the existing quasi-planar structure thin film transistor, effectively reducing the The area of the thin film transistor is reduced.
  • the embodiment of the present disclosure uses a structure in which an annular channel surrounds the gate electrode, the channel width and length can be effectively increased. Compared with W/L, it speeds up the channel opening speed, increases electron mobility, reduces threshold voltage drift, effectively improves the driving capability and operating stability of thin film transistors, and can also speed up channel closing by providing stable negative voltage. speed, further reducing leakage current and reducing power consumption.
  • the preparation of thin film transistors according to the embodiments of the present disclosure does not require changing the existing process flow or the existing process equipment. It has good compatibility with existing processes, high process achievability, strong practicability, and good application prospects. .
  • An embodiment of the present disclosure also provides a display device including the thin film transistor as described above.
  • Figure 14 is a schematic plan view of an existing display device, in which 13 is a data line, 14 is a gate line, and the oval solid line box is a thin film transistor. It can be seen that the area of the existing thin film transistor is relatively large, resulting in the display device The opening area (shown in the dotted frame) is relatively small, resulting in a small opening ratio of the display device.
  • FIG. 15 is a schematic plan view of a display device according to a specific embodiment of the present disclosure.
  • FIG. 16 is a schematic three-dimensional view of a thin film transistor in this embodiment.
  • the gate electrode 05 and the gate line 14 are an integral structure.
  • the thin film transistor also includes : the first connecting portion 083 and the second connecting portion 084 extending from the first active layer 08; wherein the extending direction of the first connecting portion 083 is a second direction, and the second direction is consistent with the The base is parallel or substantially parallel and perpendicular to the first direction.
  • the first active layer 08 can be connected to the source electrode through the first connection part 083; the extending direction of the second connection part 084 is the In two directions, the first active layer 08 can be connected to the drain electrode through the second connection portion 084 .
  • first connection portion 083 can extend from the first active layer 08
  • second connection portion 084 can extend from the first active layer 08
  • first connection portion 084 can extend from the first active layer 08
  • the first connection part 083 and/or the second connection part 084 can pass through a via hole penetrating the interlayer insulating layer. Connected to the source electrode and/or drain electrode formed by the source and drain metal layer.
  • this embodiment can reduce the area of the thin film transistor and increase the area of the opening area (shown in the dotted box) of the display device, thereby increasing the aperture ratio of the display device.
  • FIG. 17 is a schematic plan view of a display device according to another specific embodiment of the present disclosure.
  • FIG. 18 is a schematic three-dimensional view of a thin film transistor in this embodiment.
  • the gate electrode 05 and the gate line 14 are an integral structure, and the thin film transistor also has an integrated structure. It includes: a first connecting portion 083 extending from the first active layer 08; wherein the extending direction of the first connecting portion 083 is a second direction, and the second direction is parallel or substantially parallel to the substrate.
  • the first active layer 08 can be connected to the source electrode through the first connection portion 083; the first active layer 08 also includes a conductive portion 085, and the conductive portion 085 is the part where the orthographic projection of the first via hole 101 on the first active layer 08 is located.
  • the orthographic projection of the first via hole on the substrate falls into the orthogonal projection of the gate line on the substrate.
  • the orthographic projection of the conductive part 085 on the substrate falls within the orthographic projection of the gate line 14 on the substrate, which can further reduce the area of the thin film transistor and increase the opening area of the display device. (shown in the dotted box) area, thereby improving the aperture ratio of the display device.
  • Figure 19 is a schematic plan view of a display device according to another specific embodiment of the present disclosure.
  • Figure 18 is a three-dimensional schematic view of a thin film transistor in this embodiment.
  • the gate electrode 05 and the gate line 14 are an integral structure, and the first active layer 08 also includes conductive parts 085 and 086.
  • the conductive part 085 is the part where the orthographic projection of the first via hole 101 is on the first active layer 08, and the conductive part 086 is where the second via hole 102 is on the first active layer.
  • the part where the orthographic projection is located on 08.
  • the orthographic projection of the first via hole on the substrate falls within the orthographic projection of the gate line on the substrate, that is, the orthographic projection of the conductive part 085 on the substrate falls within the orthographic projection of the conductive part 085 on the substrate.
  • the orthographic projection of the gate line on the substrate, and the orthographic projection of the second via hole on the substrate fall into the orthographic projection of the gate line on the substrate, that is, the conductive portion 086 is on the substrate.
  • the orthographic projection on the substrate falls within the orthographic projection of the gate line on the substrate, which can further reduce the area of the thin film transistor and increase the area of the opening area (shown in the dotted box) of the display device, thereby improving the display The opening ratio of the device.
  • the display device in this embodiment includes but is not limited to: a radio frequency unit, a network module, an audio output unit, an input unit, a sensor, a display unit, a user input unit, an interface unit, a memory, a processor, a power supply, and other components.
  • a radio frequency unit for example, a radio frequency unit
  • a network module for example, a radio frequency unit
  • an audio output unit for example, a speaker
  • an input unit a sensor
  • a display unit a user input unit
  • an interface unit a memory
  • a processor a power supply
  • display devices include but are not limited to monitors, mobile phones, tablet computers, televisions, wearable electronic devices, navigation display devices, and the like.
  • the display device may be any product or component with a display function such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc.
  • the display device further includes a flexible circuit board, a printed circuit board and a backplane.

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Abstract

本公开提供了一种薄膜晶体管及其制备方法、显示装置，属于显示技术领域。其中，薄膜晶体管包括设置在基底上的沿第一方向延伸的栅电极和第一有源层，所述第一有源层为拱门结构，所述栅电极穿设在所述拱门结构内，所述第一有源层在所述基底上的正投影覆盖所述栅电极在所述基底上的正投影。本公开的技术方案能够提高薄膜晶体管的开态电流，减小薄膜晶体管的面积。

Description

薄膜晶体管及其制备方法、显示装置 技术领域
本公开涉及显示技术领域，具体涉及一种薄膜晶体管及其制备方法、显示装置。
背景技术
薄膜晶体管(Thin Film Transistor，TFT)作为开关部件和驱动部件，是显示技术领域非常重要的元件，普遍应用于各种显示装置中。
随着显示技术的发展，需要提高薄膜晶体管的开态电流以改善显示装置的性能；另外为了满足高分辨率要求，也需要减小薄膜晶体管的面积来提高显示装置的开口率。
发明内容
本公开要解决的技术问题是提供一种薄膜晶体管及其制备方法、显示装置，能够提高薄膜晶体管的开态电流，减小薄膜晶体管的面积。
为解决上述技术问题，本公开的实施例提供技术方案如下：
一方面，提供一种薄膜晶体管，包括设置在基底上的沿第一方向延伸的栅电极和第一有源层，所述第一有源层为拱门结构，所述栅电极穿设在所述拱门结构内，所述第一有源层在所述基底上的正投影覆盖所述栅电极在所述基底上的正投影。
一些实施例中，所述薄膜晶体管还包括第一栅绝缘层，
所述栅电极位于所述基底上，沿第一方向延伸；
所述第一栅绝缘层覆盖所述栅电极，所述第一栅绝缘层包括两个第一开槽；
所述第一有源层位于所述第一栅绝缘层远离所述栅电极的一侧，沿所述第一方向延伸，并填充于两个所述第一开槽内形成所述拱门结构的两个拱门侧表面，两个所述拱门侧表面包围所述栅电极。
一些实施例中，所述薄膜晶体管还包括：
位于所述第一有源层远离所述基底一侧的源电极和漏电极，分别与所述第一有源层连接。
一些实施例中，所述薄膜晶体管还包括：
位于所述栅电极远离所述第一有源层一侧的第二有源层，所述第二有源层分别与两个所述拱门侧表面连接，形成包围所述栅电极的沟道。
一些实施例中，所述第一有源层还包括与所述拱门侧表面连接的第一连接部分，所述第一连接部分位于所述拱门结构外，与所述基底平行或大致平行；
所述第二有源层包括与所述第一连接部分对应的第二连接部分，所述第二连接部分位于所述拱门结构外，与所述基底平行或大致平行，所述第二连接部分与对应的所述第一连接部分直接接触，所述第二连接部分在所述基底上的正投影与对应的第一连接部分在所述基底上的正投影至少部分重叠。
一些实施例中，所述第二连接部分经过导体化处理；和/或
所述第一连接部分经过导体化处理。
一些实施例中，所述薄膜晶体管还包括：
位于所述栅电极和所述第二有源层之间的第二栅绝缘层，所述第二栅绝缘层包括两个第二开槽，所述第一开槽与所述第二开槽贯通，所述两个拱门侧表面通过所述第二开槽与所述第二有源层连接。
一些实施例中，所述薄膜晶体管还包括：
由所述第一有源层延伸出的第一连接部和/或第二连接部；
其中，所述第一连接部的延伸方向为第二方向，所述第二方向与所述基底平行或大致平行且与所述第一方向垂直，所述第一有源层通过所述第一连接部与所述源电极连接；
所述第二连接部的延伸方向为第二方向，所述第一有源层通过所述第二连接部与所述漏电极连接。
一些实施例中，所述薄膜晶体管还包括：
位于所述第一有源层与所述源电极和漏电极之间的层间绝缘层，所述第 一有源层通过贯穿所述层间绝缘层的第一过孔与所述源电极连接，通过贯穿所述层间绝缘层的第二过孔与所述漏电极连接。
本公开的实施例还提供了一种显示装置，包括如上所述的薄膜晶体管。
一些实施例中，所述栅电极与所述显示装置的栅线为一体结构。
一些实施例中，所述第一过孔在所述基底上的正投影落入所述栅线在所述基底上的正投影内；和/或
所述第二过孔在所述基底上的正投影落入所述栅线在所述基底上的正投影内。
本公开的实施例还提供了一种薄膜晶体管的制备方法，包括：
在基底上形成沿第一方向延伸的栅电极和第一有源层，所述第一有源层为拱门结构，所述栅电极穿设在所述拱门结构内，所述第一有源层在所述基底上的正投影覆盖所述栅电极在所述基底上的正投影。
一些实施例中，所述制备方法还包括：
形成覆盖所述栅电极的第一栅绝缘层，所述第一栅绝缘层包括两个第一开槽；
所述第一有源层位于所述第一栅绝缘层远离所述栅电极的一侧，沿所述第一方向延伸，并填充于两个所述第一开槽内形成所述拱门结构的两个拱门侧表面，两个所述拱门侧表面包围所述栅电极。
一些实施例中，所述制备方法还包括：
在所述栅电极远离所述第一有源层的一侧形成第二有源层，所述第二有源层分别与两个所述拱门侧表面连接，形成包围所述栅电极的沟道。
本公开的实施例具有以下有益效果：
上述方案中，通过立体沟道包围栅电极的结构，能够增加薄膜晶体管的沟道宽度，提高薄膜晶体管沟道的宽长比，进而增加薄膜晶体管的开态能力，同时，通过立体沟道包围栅电极的结构，加强了栅电极对沟道导电能力的控制，有效提高了薄膜晶体管的驱动能力和工作稳定性；另外，通过立体沟道包围栅电极的结构，有效减小了薄膜晶体管的面积，有利于提高显示装置的开口率，满足高分辨率要求，有效解决了现有结构难以通过减小薄膜晶体管 的面积来提高分辨率的问题。
当然，实施本公开的任一产品或方法并不一定需要同时达到以上所述的所有优点。本公开的其它特征和优点将在随后的说明书实施例中阐述，并且，部分地从说明书实施例中变得显而易见，或者通过实施本公开而了解。本公开实施例的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本申请的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。附图中各部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1-图5为本公开一实施例制作薄膜晶体管的示意图；
图6为现有薄膜晶体管的开态电流方向示意图；
图7为本公开实施例薄膜晶体管的开态电流方向示意图；
图8-图13为本公开另一实施例制作薄膜晶体管的示意图；
图14为现有显示装置的平面示意图；
图15为本公开一实施例显示装置的平面示意图；
图16为本公开一实施例薄膜晶体管的立体示意图；
图17为本公开另一实施例显示装置的平面示意图；
图18为本公开另一实施例薄膜晶体管的立体示意图；
图19为本公开又一实施例显示装置的平面示意图；
图20为本公开又一实施例薄膜晶体管的立体示意图；。
附图标记
01基底
02缓冲层
03第二有源层
031第二连接部分
04第二栅绝缘层
05栅电极
06第一栅绝缘层
07光刻胶
08第一有源层
081第一连接部分
082、085、086导体化部分
083第一连接部
084第二连接部
087拱门上表面
088拱门侧表面
09层间绝缘层
10过孔
101第一过孔
102第二过孔
11有源层
12源漏金属层
121漏电极
122源电极
13数据线
14栅线
具体实施方式
为使本公开的实施例要解决的技术问题、技术方案和优点更加清楚，下面将结合附图及具体实施例进行详细描述。
本公开的实施例提供一种薄膜晶体管及其制备方法、显示装置，能够提高薄膜晶体管的开态电流，减小薄膜晶体管的面积。
本公开的实施例提供一种薄膜晶体管，包括设置在基底上的沿第一方向延伸的栅电极和第一有源层，所述第一有源层为拱门结构，所述栅电极穿设 在所述拱门结构内，所述第一有源层在所述基底上的正投影覆盖所述栅电极在所述基底上的正投影。
本实施例中，通过立体沟道包围栅电极的结构，能够增加薄膜晶体管的沟道宽度，提高薄膜晶体管沟道的宽长比，进而增加薄膜晶体管的开态能力，同时，通过立体沟道包围栅电极的结构，加强了栅电极对沟道导电能力的控制，有效提高了薄膜晶体管的驱动能力和工作稳定性；另外，通过立体沟道包围栅电极的结构，有效减小了薄膜晶体管的面积，有利于提高显示装置的开口率，满足高分辨率要求，有效解决了现有结构难以通过减小薄膜晶体管的面积来提高分辨率的问题。
一具体实施例中，如图1-图5所示，本实施例的薄膜晶体管包括基底01，设置在基底01上的缓冲层02，位于缓冲层02上的栅电极05，覆盖栅电极05的第一栅绝缘层06，位于第一栅绝缘层06上的第一有源层08，其中，第一有源层08为拱门结构，栅电极05穿设在所述拱门结构内，第一有源层08包围所述栅电极05。
其中，如图15和图16所示，栅电极05沿第一方向延伸；
所述第一栅绝缘层06覆盖所述栅电极05，所述第一栅绝缘层06包括两个第一开槽；
所述第一有源层08位于所述第一栅绝缘层06远离所述栅电极05的一侧，沿所述第一方向延伸，并填充于两个所述第一开槽内形成所述拱门结构的两个拱门侧表面088，两个所述拱门侧表面088包围所述栅电极05。
薄膜晶体管还包括：位于所述第一有源层08远离基底01一侧的层间绝缘层09，位于层间绝缘层09远离基底01一侧的源电极和漏电极，所述第一有源层08通过贯穿所述层间绝缘层的第一过孔101与所述源电极连接，通过贯穿所述层间绝缘层的第二过孔102与所述漏电极连接。
其中，第一有源层08环形的拱门结构类似倒U形状，U形开口朝向基底方向。环形的拱门结构朝向基底方向具有三个表面，一个位于拱门顶部的拱门上表面087和位于拱门上表面087两侧的两个拱门侧表面088，拱门侧表面088、拱门上表面087和拱门侧表面088形成三面非闭合的环形，栅电极 05被该三面非闭合的环形包围。
本实施例中，所述薄膜晶体管还可以包括：
位于所述栅电极05远离所述第一有源层08一侧的第二有源层03，所述第二有源层03分别与两个所述拱门侧表面连接，形成包围所述栅电极05的沟道。本实施例中，第二有源层03能够与第一有源层08连接，形成闭合的环形包围栅电极05，通过第一有源层08和第二有源层03组成包围栅电极05的立体沟道，通过立体沟道包围栅电极的结构，能够增加薄膜晶体管的沟道宽度，提高薄膜晶体管沟道的宽长比，进而增加薄膜晶体管的开态电流，同时，通过立体沟道包围栅电极的结构，加强了栅电极对沟道导电能力的控制，有效提高了薄膜晶体管的驱动能力和工作稳定性；另外，通过立体沟道包围栅电极的结构，有效减小了薄膜晶体管的面积，有利于提高显示装置的开口率，满足高分辨率要求，有效解决了现有结构难以通过减小薄膜晶体管的面积来提高分辨率的问题。
如图1-图5所示，薄膜晶体管还包括：位于所述栅电极05和所述第二有源层03之间的第二栅绝缘层04，所述第二栅绝缘层04包括两个第二开槽，所述第一开槽与所述第二开槽贯通，所述两个拱门侧表面088通过所述第二开槽与所述第二有源层03连接。
本实施例中，为了保证第二有源层03和第一有源层08之间连接的可靠性，所述第一有源层08除包括拱门结构外，还包括与所述拱门侧表面088连接的第一连接部分081，所述第一连接部分081位于所述拱门结构外，与所述基底01平行或大致平行；所述第二有源层03包括与所述第一连接部分081对应的第二连接部分031，所述第二连接部分031位于所述拱门结构外，与所述基底01平行或大致平行，所述第二连接部分031与对应的所述第一连接部分081直接接触，所述第二连接部分031在所述基底上的正投影与对应的第一连接部分081在所述基底上的正投影至少部分重叠。
为了进一步提高第二有源层03和第一有源层08之间连接的可靠性，所述第二连接部分031可以经过导体化处理；和/或，所述第一连接部分081可以经过导体化处理。可以仅对第一连接部分081进行导体化处理，也可以仅 对第二连接部分031进行导体化处理，或者，对第一连接部分081和第二连接部分031均进行导体化处理，其中，在对第一连接部分081进行导体化处理时，可以对第一连接部分081的部分或全部进行导体化处理；在对第二连接部分031进行导体化处理时，可以对第二连接部分031的部分或全部进行导体化处理。
下面通过本实施例薄膜晶体管的制备过程进一步说明本实施例的技术方案。本实施例中所说的“构图工艺”包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，是相关技术中成熟的制备工艺。沉积可采用溅射、蒸镀、化学气相沉积等已知工艺，涂覆可采用已知的涂覆工艺，刻蚀可采用已知的方法，在此不做具体的限定。在本实施例的描述中，需要理解的是，“薄膜”是指将某一种材料在基底上利用沉积或涂覆工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需构图工艺或光刻工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”还需构图工艺或光刻工艺，则在构图工艺前称为“薄膜”，构图工艺后称为“层”。经过构图工艺或光刻工艺后的“层”中包含至少一个“图案”。
本实施例的薄膜晶体管的制备方法，包括：
在基底上形成沿第一方向延伸的栅电极和第一有源层，所述第一有源层为拱门结构，所述栅电极穿设在所述拱门结构内，所述第一有源层在所述基底上的正投影覆盖所述栅电极在所述基底上的正投影。
一些实施例中，所述制备方法还包括：
形成覆盖所述栅电极的第一栅绝缘层，所述第一栅绝缘层包括两个第一开槽；
所述第一有源层位于所述第一栅绝缘层远离所述栅电极的一侧，沿所述第一方向延伸，并填充于两个所述第一开槽内形成所述拱门结构的两个拱门侧表面，两个所述拱门侧表面包围所述栅电极。
一些实施例中，所述制备方法还包括：
在所述栅电极远离所述第一有源层的一侧形成第二有源层，所述第二有源层分别与两个所述拱门侧表面连接，形成包围所述栅电极的沟道。
具体地，本实施例的制备方法包括以下步骤：
如图1所示，在基底01上形成缓冲层02和第二有源层03。缓冲层02可以采用硅氧化物SiOx、硅氮化物SiNx、氮氧化硅SiON等，也可以采用High k材料，如氧化铝AlOx、氧化铪HfOx、氧化钽TaOx等，可以是单层、多层或复合层。缓冲层02，主要用于阻挡基底01中所含的杂质扩散进入第二有源层03，防止对薄膜晶体管的阈值电压和漏电流等特性产生影响。在缓冲层02上形成有源层薄膜，在有源层薄膜上涂覆一层光刻胶，采用单色调掩膜版对光刻胶进行曝光并显影，在有源层图案位置形成未曝光区域，保留有光刻胶，在其它位置形成完全曝光区域，光刻胶被去除，对完全曝光区域的有源层薄膜进行刻蚀并剥离剩余的光刻胶，形成第二有源层03的图形。第二有源层03可以采用非晶硅a-Si、多晶硅p-Si、非晶态氧化铟镓锌材料a-IGZO、氮氧化锌ZnON、氧化铟锌锡IZTO、六噻吩、聚噻吩等各种材料，即本公开实施例同时适用于基于非晶硅技术、多晶硅技术、氧化物Oxide技术以及有机物技术制造的薄膜晶体管，可以是N型薄膜晶体管，也可以是P型薄膜晶体管。优选地，本实施例第二有源层03采用多晶硅，形成低温多晶硅(Low Temperature Poly Silicon，LTPS)薄膜晶体管。
如图1所示，形成第二栅绝缘层04，第二栅绝缘层04可以采用硅氧化物SiOx、硅氮化物SiNx、氮氧化硅SiON等，也可以采用High k材料，如氧化铝AlOx、氧化铪HfOx、氧化钽TaOx等，可以是单层、多层或复合层。
如图1所示，形成栅电极05，形成栅电极05包括：形成金属薄膜，对金属薄膜进行构图形成栅电极05。金属薄膜可以采用金属材料，如银Ag、铜Cu、铝Al、钼Mo等，或上述金属的合金材料，如铝钕合金AlNd、钼铌合金MoNb等，可以是多层金属，如Mo/Cu/Mo等，也可以是金属和透明导电材料形成的堆栈结构，如ITO/Ag/ITO等。
如图2所示，形成第一栅绝缘层06，第一栅绝缘层06可以采用硅氧化物SiOx、硅氮化物SiNx、氮氧化硅SiON等，也可以采用High k材料，如氧化铝AlOx、氧化铪HfOx、氧化钽TaOx等，可以是单层、多层或复合层。为了实现均一的第一栅绝缘层06厚度，第一栅绝缘层06可以使用原子层沉积 ALD工艺进行制备。
如图3所示，形成光刻胶07的图形。
如图4所示，以光刻胶07的图形为掩膜对第一栅绝缘层06进行刻蚀，形成贯穿第一栅绝缘层06的开槽，如矩形虚线框内所示。通过贯穿第一栅绝缘层06的开槽对第二有源层03进行导体化处理，形成第二连接部分031，提高第二连接部分031的导电性，具体地，可以通过掺杂处理对第二有源层03进行导体化处理，有关掺杂以及掺杂处理过程为本领域技术人员所熟知，这里不再赘述。之后去除光刻胶07的图形。
如图5所示，形成第一有源层08，具体地，形成有源层薄膜，在有源层薄膜上涂覆一层光刻胶，采用单色调掩膜版对光刻胶进行曝光并显影，在有源层图案位置形成未曝光区域，保留有光刻胶，在其它位置形成完全曝光区域，光刻胶被去除，对完全曝光区域的有源层薄膜进行刻蚀并剥离剩余的光刻胶，形成第一有源层08的图形。第一有源层08可以采用非晶硅a-Si、多晶硅p-Si、非晶态氧化铟镓锌材料a-IGZO、氮氧化锌ZnON、氧化铟锌锡IZTO、六噻吩、聚噻吩等各种材料，即本公开实施例同时适用于基于非晶硅技术、多晶硅技术、氧化物Oxide技术以及有机物技术制造的薄膜晶体管，可以是N型薄膜晶体管，也可以是P型薄膜晶体管。优选地，本实施例第一有源层08采用多晶硅，形成低温多晶硅(Low Temperature Poly Silicon，LTPS)薄膜晶体管。第一有源层08通过贯穿第一栅绝缘层06和第二栅绝缘层04的开槽与第二有源层03连接，第一有源层08与第二有源层03形成包围栅电极05的环形结构，形成立体结构的沟道。
形成层间绝缘层09，层间绝缘层09可以采用硅氧化物SiOx、硅氮化物SiNx、氮氧化硅SiON等，也可以采用High k材料，如氧化铝AlOx、氧化铪HfOx、氧化钽TaOx等，可以是单层、多层或复合层，层间绝缘层09包括第一过孔101和第二过孔102，源电极可以通过第一过孔101与第一有源层08连接，漏电极可以通过第二过孔102与第一有源层08连接。为了提高薄膜晶体管的性能，可以通过第一过孔101和第二过孔102对第二有源层03进行掺杂处理，有关掺杂以及掺杂处理过程为本领域技术人员所熟知，这里不再赘 述。
通过本公开实施例薄膜晶体管的结构以及制备过程可以看出，本实施例提出了一种立体结构的薄膜晶体管，通过环形的有源层包围栅电极的结构，可以增加薄膜晶体管的沟道的宽长比。图6为现有薄膜晶体管的开态电流方向示意图，其中，11为有源层，122为源电极，121为漏电极，05为栅电极；图7为本公开实施例薄膜晶体管的开态电流方向示意图，在采用本实施例的立体沟道后，与现有技术不同，漏电极与源电极之间的最短距离为薄膜晶体管的沟道的长度；围绕栅电极05的有源层11的长度(周长)为薄膜晶体管的沟道宽度，因此可以增加薄膜晶体管的沟道的宽长比。
现有准平面结构的薄膜晶体管，栅电极和沟道均为水平结构，由于沟道长度越短漏电流越大，短沟道效应严重，因此该结构形式的沟道长度难以进一步减小，薄膜晶体管的沟道的宽长比难以提高，并且薄膜晶体管的面积难以进一步减小。本公开实施例通过环形沟道包围栅电极的结构，实际上形成了立体沟道，增加了薄膜晶体管的沟道的宽长比，能够保证薄膜晶体管的性能。此外，即使本实施例薄膜晶体管的沟道宽长比与现有准平面结构薄膜晶体管的沟道宽长比相同，本实施例薄膜晶体管的面积也远小于现有准平面结构薄膜晶体管的面积。在相同沟道长度和沟道宽长比的情况下，本实施例薄膜晶体管沟道区域的投影面积较现有准平面结构薄膜晶体管沟道区域的投影面积可以减少50％～60％，有效减小了薄膜晶体管的面积。
此外，在本公开实施例薄膜晶体管的面积与现有准平面结构薄膜晶体管的面积相同的情况下，由于本公开实施例采用环形沟道包围栅电极的结构，因而可以有效增大沟道宽长比W/L，加快了沟道开启速度，增加了电子迁移率，减小了阈值电压漂移，有效提升了薄膜晶体管的驱动能力和工作稳定性，还可以通过提供稳定的负压加快沟道关闭速度，进一步降低漏电流，较少功耗。
进一步地，本公开实施例制备薄膜晶体管不需要改变现有工艺流程，不需改变现有工艺设备，与现有工艺互相兼容性好，工艺可实现性高，实用性强，具有良好的应用前景。
另一具体实施例中，如图8-图13所示，本实施例的薄膜晶体管包括基底01，设置在基底01上的缓冲层02，位于缓冲层02上的栅电极05，覆盖栅电极05的第一栅绝缘层06，位于第一栅绝缘层06上的第一有源层08，其中，第一有源层08为拱门结构，栅电极05穿设在所述拱门结构内，第一有源层08包围所述栅电极05。
其中，栅电极05沿第一方向延伸；
所述第一栅绝缘层06覆盖所述栅电极05，所述第一栅绝缘层06包括两个第一开槽；
所述第一有源层08位于所述第一栅绝缘层06远离所述栅电极05的一侧，沿所述第一方向延伸，并填充于两个所述第一开槽内形成所述拱门结构的两个拱门侧表面，两个所述拱门侧表面包围所述栅电极05。
薄膜晶体管还包括：位于所述第一有源层08远离基底01一侧的层间绝缘层09，位于层间绝缘层09远离基底01一侧的源漏金属层12，源漏金属层12通过贯穿所述层间绝缘层09的过孔10与第一有源层08连接，源漏金属层12包括源电极和/或漏电极。
其中，第一有源层08环形的拱门结构类似倒U形状，U形开口朝向基底方向。环形的拱门结构朝向基底方向具有三个表面，一个位于拱门顶部的拱门上表面和位于拱门上表面两侧的两个拱门侧表面，拱门侧表面、拱门上表面和拱门侧表面形成三面非闭合的环形，栅电极05被该三面非闭合的环形包围。
本实施例中，所述薄膜晶体管还可以包括：
位于所述栅电极05远离所述第一有源层08一侧的第二有源层03，所述第二有源层03分别与两个所述拱门侧表面连接，形成包围所述栅电极05的沟道。本实施例中，第二有源层03能够与第一有源层08连接，形成闭合的环形包围栅电极05，通过第一有源层08和第二有源层03组成包围栅电极05的立体沟道，通过立体沟道包围栅电极的结构，能够增加薄膜晶体管的沟道宽度，提高薄膜晶体管沟道的宽长比，进而增加薄膜晶体管的开态电流，同时，通过立体沟道包围栅电极的结构，加强了栅电极对沟道导电能力的控制， 有效提高了薄膜晶体管的驱动能力和工作稳定性；另外，通过立体沟道包围栅电极的结构，有效减小了薄膜晶体管的面积，有利于提高显示装置的开口率，满足高分辨率要求，有效解决了现有结构难以通过减小薄膜晶体管的面积来提高分辨率的问题。
如图8-图13所示，薄膜晶体管还包括：位于所述栅电极05和所述第二有源层03之间的第二栅绝缘层04，所述第二栅绝缘层04包括两个第二开槽，所述第一开槽与所述第二开槽贯通，所述两个拱门侧表面通过所述第二开槽与所述第二有源层03连接。
为了提高源漏金属层12与第一有源层08之间电连接的可靠性，可以通过过孔10对第一有源层08进行导体化处理，形成导体化部分082。
下面通过本实施例薄膜晶体管的制备过程进一步说明本实施例的技术方案。本实施例的薄膜晶体管的制备方法，包括：
在基底上形成沿第一方向延伸的栅电极和第一有源层，所述第一有源层为拱门结构，所述栅电极穿设在所述拱门结构内，所述第一有源层在所述基底上的正投影覆盖所述栅电极在所述基底上的正投影。
一些实施例中，所述制备方法还包括：
形成覆盖所述栅电极的第一栅绝缘层，所述第一栅绝缘层包括两个第一开槽；
所述第一有源层位于所述第一栅绝缘层远离所述栅电极的一侧，沿所述第一方向延伸，并填充于两个所述第一开槽内形成所述拱门结构的两个拱门侧表面，两个所述拱门侧表面包围所述栅电极。
一些实施例中，所述制备方法还包括：
在所述栅电极远离所述第一有源层的一侧形成第二有源层，所述第二有源层分别与两个所述拱门侧表面连接，形成包围所述栅电极的沟道。
具体地，本实施例的薄膜晶体管的制备方法包括以下步骤：
如图8所示，在基底01上形成缓冲层02和第二有源层03。缓冲层02可以采用硅氧化物SiOx、硅氮化物SiNx、氮氧化硅SiON等，也可以采用High k材料，如氧化铝AlOx、氧化铪HfOx、氧化钽TaOx等，可以是单层、 多层或复合层。缓冲层02，主要用于阻挡基底01中所含的杂质扩散进入第二有源层03，防止对薄膜晶体管的阈值电压和漏电流等特性产生影响。在缓冲层02上形成有源层薄膜，在有源层薄膜上涂覆一层光刻胶，采用单色调掩膜版对光刻胶进行曝光并显影，在有源层图案位置形成未曝光区域，保留有光刻胶，在其它位置形成完全曝光区域，光刻胶被去除，对完全曝光区域的有源层薄膜进行刻蚀并剥离剩余的光刻胶，形成第二有源层03的图形。第二有源层03可以采用非晶硅a-Si、多晶硅p-Si、非晶态氧化铟镓锌材料a-IGZO、氮氧化锌ZnON、氧化铟锌锡IZTO、六噻吩、聚噻吩等各种材料，即本公开实施例同时适用于基于非晶硅技术、多晶硅技术、氧化物Oxide技术以及有机物技术制造的薄膜晶体管，可以是N型薄膜晶体管，也可以是P型薄膜晶体管。优选地，本实施例第二有源层03采用多晶硅，形成低温多晶硅(Low Temperature Poly Silicon，LTPS)薄膜晶体管。
如图8所示，形成第二栅绝缘层04，第二栅绝缘层04可以采用硅氧化物SiOx、硅氮化物SiNx、氮氧化硅SiON等，也可以采用High k材料，如氧化铝AlOx、氧化铪HfOx、氧化钽TaOx等，可以是单层、多层或复合层。
如图8所示，形成栅电极05，形成栅电极05包括：形成金属薄膜，对金属薄膜进行构图形成栅电极05。金属薄膜可以采用金属材料，如银Ag、铜Cu、铝Al、钼Mo等，或上述金属的合金材料，如铝钕合金AlNd、钼铌合金MoNb等，可以是多层金属，如Mo/Cu/Mo等，也可以是金属和透明导电材料形成的堆栈结构，如ITO/Ag/ITO等。
如图8所示，形成第一栅绝缘层06，第一栅绝缘层06可以采用硅氧化物SiOx、硅氮化物SiNx、氮氧化硅SiON等，也可以采用High k材料，如氧化铝AlOx、氧化铪HfOx、氧化钽TaOx等，可以是单层、多层或复合层。为了实现均一的第一栅绝缘层06厚度，第一栅绝缘层06可以使用原子层沉积ALD工艺进行制备。第一栅绝缘层06的开槽与第二栅绝缘层04的开槽贯通，形成虚线框内所示的开槽结构。
如图9所示，形成第一有源层08，具体地，形成有源层薄膜，在有源层薄膜上涂覆一层光刻胶，采用单色调掩膜版对光刻胶进行曝光并显影，在有 源层图案位置形成未曝光区域，保留有光刻胶，在其它位置形成完全曝光区域，光刻胶被去除，对完全曝光区域的有源层薄膜进行刻蚀并剥离剩余的光刻胶，形成第一有源层08的图形。第一有源层08可以采用非晶硅a-Si、多晶硅p-Si、非晶态氧化铟镓锌材料a-IGZO、氮氧化锌ZnON、氧化铟锌锡IZTO、六噻吩、聚噻吩等各种材料，即本公开实施例同时适用于基于非晶硅技术、多晶硅技术、氧化物Oxide技术以及有机物技术制造的薄膜晶体管，可以是N型薄膜晶体管，也可以是P型薄膜晶体管。优选地，本实施例第一有源层08采用多晶硅，形成低温多晶硅(Low Temperature Poly Silicon，LTPS)薄膜晶体管。第一有源层08通过贯穿第一栅绝缘层06和第二栅绝缘层04的开槽与第二有源层03连接，第一有源层08与第二有源层03形成包围栅电极05的环形结构，形成立体结构的沟道。
如图10所示，形成光刻胶07的图形。
如图11所示，以光刻胶07的图形为掩膜，对第一有源层08进行刻蚀，去除位于拱形结构之外的第一有源层08的部分。
如图12所示，形成层间绝缘层09，层间绝缘层09可以采用硅氧化物SiOx、硅氮化物SiNx、氮氧化硅SiON等，也可以采用High k材料，如氧化铝AlOx、氧化铪HfOx、氧化钽TaOx等，可以是单层、多层或复合层，层间绝缘层09包括过孔10，源电极和/或漏电极可以通过过孔10与第一有源层08连接。为了提高薄膜晶体管的性能，可以通过过孔10对第一有源层08进行掺杂处理，形成导体化部分082。有关掺杂以及掺杂处理过程为本领域技术人员所熟知，这里不再赘述。
如图13所示，形成源漏金属层12的图形，形成源漏金属层12包括：形成金属薄膜，对金属薄膜进行构图形成源漏金属层12的图形，包括源电极和漏电极。金属薄膜可以采用金属材料，如银Ag、铜Cu、铝Al、钼Mo等，或上述金属的合金材料，如铝钕合金AlNd、钼铌合金MoNb等，可以是多层金属，如Mo/Cu/Mo等，也可以是金属和透明导电材料形成的堆栈结构，如ITO/Ag/ITO等。
通过本公开实施例薄膜晶体管的结构以及制备过程可以看出，本实施例 提出了一种立体结构的薄膜晶体管，通过环形的有源层包围栅电极的结构，可以增加薄膜晶体管的沟道的宽长比。图6为现有薄膜晶体管的开态电流方向示意图，其中，11为有源层，122为源电极，121为漏电极；图7为本公开实施例薄膜晶体管的开态电流方向示意图，在采用本实施例的立体沟道后，与现有技术不同，漏电极与源电极之间的最短距离为薄膜晶体管的沟道的长度；围绕栅电极05的有源层11的长度(周长)为薄膜晶体管的沟道宽度，因此可以增加薄膜晶体管的沟道的宽长比。
现有准平面结构的薄膜晶体管，栅电极和沟道均为水平结构，由于沟道长度越短漏电流越大，短沟道效应严重，因此该结构形式的沟道长度难以进一步减小，薄膜晶体管的沟道的宽长比难以提高，并且薄膜晶体管的面积难以进一步减小。本公开实施例通过环形沟道包围栅电极的结构，实际上形成了立体沟道，增加了薄膜晶体管的沟道的宽长比，能够保证薄膜晶体管的性能。此外，即使本实施例薄膜晶体管的沟道宽长比与现有准平面结构薄膜晶体管的沟道宽长比相同，本实施例薄膜晶体管的面积也远小于现有准平面结构薄膜晶体管的面积。在相同沟道长度和沟道宽长比的情况下，本实施例薄膜晶体管沟道区域的投影面积较现有准平面结构薄膜晶体管沟道区域的投影面积可以减少50％～60％，有效减小了薄膜晶体管的面积。
此外，在本公开实施例薄膜晶体管的面积与现有准平面结构薄膜晶体管的面积相同的情况下，由于本公开实施例采用环形沟道包围栅电极的结构，因而可以有效增大沟道宽长比W/L，加快了沟道开启速度，增加了电子迁移率，减小了阈值电压漂移，有效提升了薄膜晶体管的驱动能力和工作稳定性，还可以通过提供稳定的负压加快沟道关闭速度，进一步降低漏电流，较少功耗。
进一步地，本公开实施例制备薄膜晶体管不需要改变现有工艺流程，不需改变现有工艺设备，与现有工艺互相兼容性好，工艺可实现性高，实用性强，具有良好的应用前景。
本公开的实施例还提供了一种显示装置，包括如上所述的薄膜晶体管。
图14为现有显示装置的平面示意图，其中，13为数据线，14为栅线， 椭圆形实线框内为薄膜晶体管，可以看出，现有薄膜晶体管的面积比较大，导致显示装置的开口区域(虚线框内所示)比较小，导致显示装置的开口率较小。
图15为本公开一具体实施例显示装置的平面示意图，图16为该实施例中薄膜晶体管的立体示意图，该显示装置中，栅电极05与栅线14为一体结构，所述薄膜晶体管还包括：由所述第一有源层08延伸出的第一连接部083和第二连接部084；其中，所述第一连接部083的延伸方向为第二方向，所述第二方向与所述基底平行或大致平行且与所述第一方向垂直，所述第一有源层08可以通过所述第一连接部083与所述源电极连接；所述第二连接部084的延伸方向为第二方向，所述第一有源层08可以通过所述第二连接部084与所述漏电极连接。
其中，从第一有源层08可以仅延伸出第一连接部083，或者，从第一有源层08可以仅延伸出第二连接部084，或者，从第一有源层08可以延伸出第一连接部083和第二连接部084。第一连接部083和/或第二连接部084与源漏金属层之间间隔有层间绝缘层，第一连接部083和/或第二连接部084可以通过贯穿层间绝缘层的过孔与源漏金属层形成的源电极和/或漏电极连接。
可以看出，本实施例通过采用立体结构的沟道，可以减小薄膜晶体管的面积，提高显示装置的开口区域(虚线框内所示)的面积，进而提高显示装置的开口率。
图17为本公开另一具体实施例显示装置的平面示意图，图18为该实施例中薄膜晶体管的立体示意图，该显示装置中，栅电极05与栅线14为一体结构，所述薄膜晶体管还包括：由所述第一有源层08延伸出的第一连接部083；其中，所述第一连接部083的延伸方向为第二方向，所述第二方向与所述基底平行或大致平行且与所述第一方向垂直，所述第一有源层08可以通过所述第一连接部083与所述源电极连接；第一有源层08还包括导体化部分085，导体化部分085为第一过孔101在第一有源层08上的正投影所在部分，本实施例中，第一过孔在所述基底上的正投影落入所述栅线在所述基底上的正投影内，也即导体化部分085在所述基底上的正投影落入所述栅线14在所 述基底上的正投影内，这样可以进一步减小薄膜晶体管的面积，提高显示装置的开口区域(虚线框内所示)的面积，进而提高显示装置的开口率。
图19为本公开又一具体实施例显示装置的平面示意图，图18为该实施例中薄膜晶体管的立体示意图，该显示装置中，栅电极05与栅线14为一体结构，第一有源层08还包括导体化部分085和086，导体化部分085为第一过孔101在第一有源层08上的正投影所在部分，导体化部分086为第二过孔102在第一有源层08上的正投影所在部分。本实施例中，第一过孔在所述基底上的正投影落入所述栅线在所述基底上的正投影内，也即导体化部分085在所述基底上的正投影落入所述栅线在所述基底上的正投影内，第二过孔在所述基底上的正投影落入所述栅线在所述基底上的正投影内，也即导体化部分086在所述基底上的正投影落入所述栅线在所述基底上的正投影内，这样可以进一步减小薄膜晶体管的面积，提高显示装置的开口区域(虚线框内所示)的面积，进而提高显示装置的开口率。
本实施例的显示装置包括但不限于：射频单元、网络模块、音频输出单元、输入单元、传感器、显示单元、用户输入单元、接口单元、存储器、处理器、以及电源等部件。本领域技术人员可以理解，上述显示装置的结构并不构成对显示装置的限定，显示装置可以包括上述更多或更少的部件，或者组合某些部件，或者不同的部件布置。在本公开实施例中，显示装置包括但不限于显示器、手机、平板电脑、电视机、可穿戴电子设备、导航显示设备等。
所述显示装置可以为：电视、显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件，其中，所述显示装置还包括柔性电路板、印刷电路板和背板。
需要说明，本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于实施例而言，由于其基本相似于产品实施例，所以描述得比较简单，相关之处参见产品实施例的部分说明即可。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属 领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (15)

  1. 一种薄膜晶体管，其特征在于，包括设置在基底上的沿第一方向延伸的栅电极和第一有源层，所述第一有源层为拱门结构，所述栅电极穿设在所述拱门结构内，所述第一有源层在所述基底上的正投影覆盖所述栅电极在所述基底上的正投影。
  2. 根据权利要求1所述的薄膜晶体管，其特征在于，所述薄膜晶体管还包括第一栅绝缘层，
    所述第一栅绝缘层覆盖所述栅电极，所述第一栅绝缘层包括两个第一开槽；
    所述第一有源层位于所述第一栅绝缘层远离所述栅电极的一侧，并填充于两个所述第一开槽内形成所述拱门结构的两个拱门侧表面，两个所述拱门侧表面包围所述栅电极。
  3. 根据权利要求2所述的薄膜晶体管，其特征在于，所述薄膜晶体管还包括：
    位于所述第一有源层远离所述基底一侧的源电极和漏电极，分别与所述第一有源层连接。
  4. 根据权利要求2所述的薄膜晶体管，其特征在于，所述薄膜晶体管还包括：
    位于所述栅电极远离所述第一有源层一侧的第二有源层，所述第二有源层分别与两个所述拱门侧表面连接，形成包围所述栅电极的沟道。
  5. 根据权利要求4所述的薄膜晶体管，其特征在于，所述第一有源层还包括与所述拱门侧表面连接的第一连接部分，所述第一连接部分位于所述拱门结构外，与所述基底平行或大致平行；
    所述第二有源层包括与所述第一连接部分对应的第二连接部分，所述第二连接部分位于所述拱门结构外，与所述基底平行或大致平行，所述第二连接部分与对应的所述第一连接部分直接接触，所述第二连接部分在所述基底上的正投影与对应的第一连接部分在所述基底上的正投影至少部分重叠。
  6. 根据权利要求5所述的薄膜晶体管，其特征在于，所述第二连接部分经过导体化处理；和/或
    所述第一连接部分经过导体化处理。
  7. 根据权利要求4所述的薄膜晶体管，其特征在于，所述薄膜晶体管还包括：
    位于所述栅电极和所述第二有源层之间的第二栅绝缘层，所述第二栅绝缘层包括两个第二开槽，所述第一开槽与所述第二开槽贯通，所述两个拱门侧表面通过所述第二开槽与所述第二有源层连接。
  8. 根据权利要求3所述的薄膜晶体管，其特征在于，所述薄膜晶体管还包括：
    由所述第一有源层延伸出的第一连接部和/或第二连接部；
    其中，所述第一连接部的延伸方向为第二方向，所述第二方向与所述基底平行或大致平行且与所述第一方向垂直，所述第一有源层通过所述第一连接部与所述源电极连接；
    所述第二连接部的延伸方向为第二方向，所述第一有源层通过所述第二连接部与所述漏电极连接。
  9. 根据权利要求3所述的薄膜晶体管，其特征在于，所述薄膜晶体管还包括：
    位于所述第一有源层与所述源电极和漏电极之间的层间绝缘层，所述第一有源层通过贯穿所述层间绝缘层的第一过孔与所述源电极连接，通过贯穿所述层间绝缘层的第二过孔与所述漏电极连接。
  10. 一种显示装置，其特征在于，包括如权利要求1-9中任一项所述的薄膜晶体管。
  11. 根据权利要求10所述的显示装置，其特征在于，所述栅电极与所述显示装置的栅线为一体结构。
  12. 根据权利要求11所述的显示装置，其特征在于，包括如权利要求9所述的薄膜晶体管，
    所述第一过孔在所述基底上的正投影落入所述栅线在所述基底上的正投 影内；和/或
    所述第二过孔在所述基底上的正投影落入所述栅线在所述基底上的正投影内。
  13. 一种薄膜晶体管的制备方法，其特征在于，包括：
    在基底上形成沿第一方向延伸的栅电极和第一有源层，所述第一有源层为拱门结构，所述栅电极穿设在所述拱门结构内，所述第一有源层在所述基底上的正投影覆盖所述栅电极在所述基底上的正投影。
  14. 根据权利要求13所述的薄膜晶体管的制备方法，其特征在于，所述制备方法还包括：
    形成覆盖所述栅电极的第一栅绝缘层，所述第一栅绝缘层包括两个第一开槽；
    所述第一有源层位于所述第一栅绝缘层远离所述栅电极的一侧，沿所述第一方向延伸，并填充于两个所述第一开槽内形成所述拱门结构的两个拱门侧表面，两个所述拱门侧表面包围所述栅电极。
  15. 根据权利要求14所述的薄膜晶体管的制备方法，其特征在于，所述制备方法还包括：
    在所述栅电极远离所述第一有源层的一侧形成第二有源层，所述第二有源层分别与两个所述拱门侧表面连接，形成包围所述栅电极的沟道。
PCT/CN2022/101047 2022-06-24 2022-06-24 薄膜晶体管及其制备方法、显示装置 WO2023245604A1 (zh)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102437178A (zh) * 2011-11-29 2012-05-02 中国科学院宁波材料技术与工程研究所 一种薄膜晶体管及其制作方法
CN102945807A (zh) * 2012-11-15 2013-02-27 京东方科技集团股份有限公司 一种薄膜晶体管的制备方法及薄膜晶体管
CN106960881A (zh) * 2017-05-17 2017-07-18 京东方科技集团股份有限公司 薄膜晶体管及其制备方法
CN114628527A (zh) * 2020-12-09 2022-06-14 深圳市柔宇科技股份有限公司 一种薄膜晶体管及其制备方法、阵列基板和显示装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102437178A (zh) * 2011-11-29 2012-05-02 中国科学院宁波材料技术与工程研究所 一种薄膜晶体管及其制作方法
CN102945807A (zh) * 2012-11-15 2013-02-27 京东方科技集团股份有限公司 一种薄膜晶体管的制备方法及薄膜晶体管
CN106960881A (zh) * 2017-05-17 2017-07-18 京东方科技集团股份有限公司 薄膜晶体管及其制备方法
CN114628527A (zh) * 2020-12-09 2022-06-14 深圳市柔宇科技股份有限公司 一种薄膜晶体管及其制备方法、阵列基板和显示装置

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