WO2016188052A1 - 一种薄膜晶体管及其制造方法、阵列基板、显示装置 - Google Patents

一种薄膜晶体管及其制造方法、阵列基板、显示装置 Download PDF

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WO2016188052A1
WO2016188052A1 PCT/CN2015/094391 CN2015094391W WO2016188052A1 WO 2016188052 A1 WO2016188052 A1 WO 2016188052A1 CN 2015094391 W CN2015094391 W CN 2015094391W WO 2016188052 A1 WO2016188052 A1 WO 2016188052A1
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gate
drain
layer
film transistor
thin film
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PCT/CN2015/094391
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English (en)
French (fr)
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孔祥永
朱夏明
刘晓娣
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京东方科技集团股份有限公司
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Priority to US15/329,180 priority Critical patent/US10340389B2/en
Publication of WO2016188052A1 publication Critical patent/WO2016188052A1/zh

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    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
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Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular, to a thin film transistor, a method of fabricating the same, an array substrate, and a display device.
  • thin film transistors have been widely used in displays to meet the needs of thinning and miniaturization of displays.
  • the thin film transistor is easily irradiated with light, and when the light is irradiated to its active layer, it causes an increase in the off-state leakage current, thereby deteriorating the characteristics of the thin film transistor.
  • a conventional thin film transistor including a gate electrode, a gate insulating layer formed on the gate electrode, an active layer formed on the gate insulating layer, and a source formed on the active layer and spaced apart from each other And the drain.
  • the gate is located below the active layer, and light irradiated from below the active layer can be blocked, and light irradiated from above the active layer is not blocked and can be irradiated from between the source and the drain On the active layer, the characteristics of the thin film transistor are further deteriorated.
  • Embodiments of the present disclosure provide a thin film transistor and a method of fabricating the same, an array substrate, and a display device that can prevent an active layer from being irradiated with light, thereby improving characteristics of the thin film transistor.
  • the technical solution is as follows:
  • an embodiment of the present disclosure provides a thin film transistor including: a substrate, and An active layer, a source, a gate, and a drain formed on the substrate. Both ends of the active layer are respectively connected to the source and the drain.
  • the gate includes a top gate and a bottom gate, the top gate including a top gate top and a top gate side connected to the top of the top gate, the top gate side extending from the top of the top gate toward the substrate .
  • the active layer is interposed between the top of the top gate and the bottom gate, and sidewalls of the active layer are at least partially surrounded by the top side of the top gate.
  • the gate, the source and the drain are both made of a non-transparent conductive material.
  • the drain includes a drain underlayer, the drain underlayer, the bottom gate and the source are equally formed on the substrate, and the bottom gate is located at the source and drain bottom layers between.
  • the thin film transistor further includes a gate insulating layer formed on the substrate and covering the drain underlayer, the bottom gate and the source, and the gate insulating a first via hole is formed in the layer corresponding to the drain bottom layer and the source, and the active layer is formed on the gate insulating layer, and the active layer passes through the first via hole respectively Connected to the drain bottom layer and the source.
  • the thin film transistor further includes a passivation layer formed on the gate insulating layer and covering the active layer, in the passivation layer and the gate insulating layer Corresponding to the substrate, a second via is formed, and a drain via is formed corresponding to the drain via, the drain further includes a drain top layer, and the drain top layer passes through the third via Connected to the drain underlayer, the top gate side portion extends from the passivation layer to at least the gate insulating layer through the second via hole, the third via hole and the second via hole Interposed, the third via and the second via together surround a sidewall of the active layer.
  • the cross section of the third via and the cross section of the second via together form a rectangular frame structure.
  • a fourth via is formed in the passivation layer and the gate insulating layer, and the top gate and the bottom gate are connected through the fourth via.
  • the active layer has a rectangular structure, and the top gate side surrounds three sides of the rectangular structure.
  • the active layer has a rectangular structure, and the top gate side surrounds the The two sides of the rectangular structure.
  • the thin film transistor further includes a gate insulating layer covering the gate electrode and an insulating layer formed on the gate insulating layer, and wherein the drain electrode is formed on the gate insulating layer a drain bottom layer and a drain top layer formed on the insulating layer.
  • the active layer is an oxide semiconductor layer.
  • the material of the oxide semiconductor layer includes IGZO, ITZO or ZnON.
  • the oxide semiconductor layer has a thickness of 10 to 150 nm.
  • the gate, the source and the drain are both made of opaque metal.
  • an embodiment of the present disclosure provides a method of fabricating a thin film transistor, including:
  • An active layer, a source, a gate, and a drain are formed on the substrate, and two ends of the active layer are respectively connected to the source and the source, wherein the gate includes a top gate and a bottom gate including a top gate top and a top gate side connected to the top of the top gate, the top gate top and the bottom gate being oppositely disposed in a direction perpendicular to the substrate, the top a gate side extending from the top of the top gate toward the substrate, and wherein the active layer is sandwiched between the top of the top gate and the bottom gate, the sidewall of the active layer being at least partially Surrounded by the side of the top grid.
  • the gate, the source and the drain are both made of a non-transparent conductive material.
  • an active layer, a source, a gate, and a drain on the substrate including:
  • the bottom gate, the source and the drain underlayer on a substrate Forming the bottom gate, the source and the drain underlayer on a substrate, the drain underlayer, the bottom gate and the source are formed on the substrate at intervals, and the bottom gate Located between the source and the bottom layer of the drain;
  • the drain top layer is connected to the drain bottom layer through the third via hole, and the top gate side portion passes the second layer A via extends from the passivation layer to at least the gate insulating layer.
  • an embodiment of the present disclosure provides an array substrate, the foregoing thin film transistor.
  • the array substrate includes a substrate substrate, wherein the substrate substrate is provided with a gate line, a data line, a pixel electrode layer, and the thin film transistor, and a drain of the thin film transistor and the pixel electrode A layer is connected, a gate of the thin film transistor is connected to the gate line, and a source of the thin film transistor is connected to the data line.
  • an embodiment of the present disclosure further provides a display device including the foregoing array substrate.
  • the bottom gate under the active layer may block light irradiated from under the oxide semiconductor layer, and the side of the top gate surrounding the sidewall of the active layer may block light irradiated from the sidewall of the active layer,
  • the top of the top gate above the active layer can block the light irradiated from above the active layer, so that the light of the active layer can be reduced, and the characteristics of the thin film transistor can be prevented from deteriorating due to illumination.
  • FIG. 1 is a schematic cross-sectional view of a thin film transistor according to an embodiment of the present disclosure
  • FIG. 2 is a schematic top plan view of a thin film transistor according to an embodiment of the present disclosure after removing a top gate and a portion of a drain;
  • FIG. 3 is a flow chart of a method of fabricating a thin film transistor according to an embodiment of the present disclosure
  • FIGS. 4a-4d are diagrams showing a process of preparing a thin film transistor according to an embodiment of the present disclosure
  • FIG. 5 is a schematic cross-sectional view of another thin film transistor according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic cross-sectional view showing another structure of the thin film transistor shown in FIG. 5;
  • FIG. 7 is a flowchart of a method of manufacturing another thin film transistor according to an embodiment of the present disclosure.
  • Embodiments of the present disclosure provide a thin film transistor including: a substrate, and an active layer, a source, a gate, and a drain formed on the substrate. Both ends of the active layer are respectively connected to the source and the drain.
  • the gate includes a top gate and a bottom gate, the top gate including a top gate top and a top gate side connected to the top of the top gate, the top gate top and the bottom gate being perpendicular to the substrate Oppositely disposed in a direction, the top gate side extends from the top of the top gate toward the substrate.
  • the active layer is interposed between the top of the top gate and the bottom gate, and sidewalls of the active layer are at least partially surrounded by the top side of the top gate.
  • the gate, the source and the drain are both made of a non-transparent conductive material.
  • the non-transparent conductive material may be a conductive material that is not completely transparent.
  • the conductive material that is not completely transparent may be a conductive material having a transmittance of 15% or less, preferably A conductive material having a rate of 5% or less.
  • the non-transparent conductive material is an opaque conductive material such as an opaque metal. Therefore, in the embodiments of the present disclosure, the opaque metal will be described as an example.
  • the active layer may have a rectangular structure
  • the top gate side portion may surround three sides of the rectangular structure (as shown in the embodiment of FIG. 1), or the top gate side portion may also surround the rectangle Knot The two sides of the structure (as shown in the embodiment of Figure 5).
  • the active layer includes a top surface, a bottom surface, and sidewalls connecting the top surface and the bottom surface.
  • the top surface of the active layer is opposite the top of the top gate, and the bottom surface of the active layer is opposite to the bottom gate.
  • the sidewall of the active layer is at least partially surrounded by the top gate side, meaning that the top gate side extends from the top of the top gate toward the substrate until it blocks the sidewall of the active layer, ie, at least extends to the gate insulating layer.
  • the bottom gate under the active layer may block light irradiated from under the oxide semiconductor layer, and the side of the top gate surrounding the sidewall of the active layer may block light irradiated from the sidewall of the active layer,
  • the top of the top gate above the active layer can block the light irradiated from above the active layer, so that the light of the active layer can be reduced, and the characteristics of the thin film transistor can be prevented from deteriorating due to illumination.
  • FIG. 1 shows a specific structure of a thin film transistor provided by an embodiment of the present disclosure.
  • FIG. 1 is a schematic cross-sectional view of a thin film transistor according to an embodiment of the present disclosure.
  • the thin film transistor includes a substrate 11, and an active layer 12, a source 13, and a drain 14 and a gate formed on the substrate 11. Both ends of the active layer 12 are connected to the source 13 and the drain 14, respectively.
  • the gate includes a top gate 15 including a top gate top 15a and a top gate side portion 15b connected to the top gate top 15a, the top gate top 15a and the bottom gate 16 being opposite in a direction perpendicular to the substrate 11. It is provided that the top gate side portion 15b extends from the top gate top portion 15a toward the substrate 11.
  • the active layer 12 is sandwiched between the top gate top 15a and the bottom gate 16, and the sidewalls of the active layer 12 are at least partially surrounded by the top gate side portion 15b.
  • the substrate 11 may be a glass substrate, a transparent plastic substrate, or the like, which is not limited in the present disclosure.
  • the material of the active layer 12 may be an oxide semiconductor, polysilicon, amorphous silicon or the like. Embodiments of the present disclosure are particularly applicable to oxide semiconductor thin film transistors because oxide semiconductors are more sensitive to light. Therefore, in the present embodiment, the active layer 12 is an oxide semiconductor layer. Materials of the oxide semiconductor layer of the embodiments of the present disclosure include, but are not limited to, IGZO (Indium Gallium Zinc Oxide), ITZO (Indium Tin Zinc Oxide), or ZnON (zinc oxynitride). ). In one embodiment, the oxide semiconductor layer may have a thickness of 10 to 150 nm.
  • the drain 14 includes a drain underlayer 141. Drain bottom layer 141, bottom gate 16 The same level as the source 13 is formed on the substrate 11, and the bottom gate 16 is located between the source 14 and the drain underlayer 141.
  • the bottom gate 16, the source 13 and the drain underlayer 141 are disposed in the same layer.
  • the bottom gate, source and drain underlayers are preferably made of the same material, so that the bottom gate, source and drain underlayers can be formed on the substrate by one patterning process, thereby reducing the number of times the mask is used.
  • the simplification of the preparation process of the thin film transistor can further reduce the preparation cost thereof.
  • the bottom gate 16, the source 13 and the drain underlayer 141 are each made of an opaque metal.
  • a single layer film formed of one of molybdenum (Mo), molybdenum-niobium alloy (MoNb), aluminum (Al), aluminum-niobium alloy (AlNd), titanium (Ti), and copper (Cu) may be used or
  • the bottom gate, source and drain underlayers may have a thickness of from 100 nm to 500 nm.
  • the thin film transistor further includes a gate insulating layer 17.
  • a gate insulating layer 17 is formed on the substrate 11 and covers the drain underlayer 141, the bottom gate 16 and the source 13 such that the drain underlayer 141, the bottom gate 16 and the source 13 are insulated from each other.
  • a first via hole 171 is provided in the gate insulating layer 17 corresponding to the drain underlayer 141 and the source electrode 13 (see FIG. 4b).
  • the active layer 12 is formed on the gate insulating layer 17, and the active layer 12 is connected to the drain underlayer 141 and the source 13 through the first via 171, respectively.
  • the gate insulating layer 17 may be one of silicon oxide (SiOx), silicon nitride (SiNx), germanium oxide (HfOx), silicon oxynitride (SiON), AlOx, or the like.
  • SiOx silicon oxide
  • SiNx silicon nitride
  • HfOx germanium oxide
  • SiON silicon oxynitride
  • AlOx aluminum oxide
  • the thickness of the gate insulating layer 17 may be 100 to 600 nm.
  • the thin film transistor also includes a passivation layer 18.
  • a passivation layer 18 is formed on the gate insulating layer 17 and covers the active layer 12.
  • a second via hole 181 (see FIG. 4d) is formed in the passivation layer 18 and the gate insulating layer 17 corresponding to the substrate, and a third via hole 182 is formed corresponding to the drain bottom layer 141.
  • the drain 14 further includes a drain top layer 142, and the drain top layer 142 passes through the third via 182 and the drain bottom layer 141 connection.
  • the top gate 15 is connected to the substrate 11 through the second via 181 (i.e., the top gate side portion 15b is connected to the substrate 11).
  • the third via 182 and the second via 181 are spaced apart, and the third via 182 and the second via 181 together surround the sidewall of the active layer 12.
  • Embodiments of the present disclosure surround the sidewalls of the active layer 12 by surrounding the third via 182 and the second via 181 so that the top gate side and the drain top layer may surround the sidewall of the active layer, the gate,
  • the drain and the source form a substantially closed space, and the active layer is in a state of being substantially not irradiated with light, so that the characteristics of the thin film transistor can be further prevented from being deteriorated by illumination.
  • a drain top layer is formed on the passivation layer.
  • the pixel electrode layer can be directly patterned on the passivation layer to facilitate connection with the pixel electrode layer.
  • the second via hole 181 extends from the passivation layer 18 to the surface of the substrate 11, so that the active layer can be more closely blocked from being illuminated; In the mode, the second via hole 181 may also extend from the passivation layer 18 into the gate insulating layer 17 without reaching the surface of the substrate 11, as long as the light irradiated from the sidewall of the active layer can be blocked. That is, in the embodiment of the present disclosure, the top gate side portion extends from the passivation layer to at least the gate insulating layer through the second via hole.
  • FIG. 2 is a schematic top plan view of a thin film transistor according to an embodiment of the present disclosure after the top gate and a portion of the drain are removed.
  • the cross-sectional shape of the second via hole 181 is a rectangular frame with one side open (including a bottom edge 181a and two side edges 181b perpendicularly connected at both ends of the bottom edge 181a), and the third The cross-sectional shape of the via hole 182 is linear, and the cross-sectional shapes of the second via hole 181 and the third via hole 182 together constitute a rectangular frame-like structure.
  • the cross-sectional shape of the second via 181 and the cross-sectional shape of the third via 182 may also be circular arc shapes, and the cross section of the second via 181 and the cross-sectional shape of the third via 182 together constitute a similar
  • the cross-sectional shapes of the second via 181 and the third via 182 may also form a polygonal frame or the like as long as it can surround the periphery of the active layer. The disclosure does not limit this.
  • the sidewalls of the vias in the embodiments of the present disclosure are generally not perpendicular to the plane of the substrate, but have a certain slope angle.
  • the slope angle is usually 30° to 70°.
  • the top gate 15 is made of an opaque metal.
  • the top gate 15 may be a single layer film formed of one of Mo, MoNb, Al, AlNd, Ti, Cu or a multilayer composite film formed of a plurality of materials, preferably Mo, Al or Mo, Al.
  • the top gate formed on the passivation layer may have a thickness of 200 to 900 nm. It is easy to know that the top grid 15 and the bottom grid 16 can be made of the same material or different materials.
  • the passivation layer 18 may be made of one of silicon oxide (SiOx), silicon nitride (SiNx), germanium oxide (HfOx), silicon oxynitride (SiON), AlOx, or the like.
  • SiOx silicon oxide
  • SiNx silicon nitride
  • HfOx germanium oxide
  • SiON silicon oxynitride
  • AlOx aluminum oxide
  • the passivation layer may have a thickness of 100 to 600 nm.
  • a fourth via 183 that is in communication is formed in the passivation layer 18 and the gate insulating layer 17.
  • the top gate 15 and the bottom gate 16 are connected by a fourth via 183 to electrically connect the top gate and the bottom gate such that the two gates operate simultaneously.
  • the two gates provide a stable negative voltage, which speeds up the turn-off of the channel of the thin film transistor, and at the same time increases the resistance of the thin film transistor to prevent charge leakage, thereby reducing the leakage current of the thin film transistor, thereby reducing power consumption.
  • the top gate and the bottom gate are connected through the fourth via hole, so that when the thin film transistor of the embodiment of the present disclosure is applied to the array substrate, the top gate and the bottom gate wiring are not separately used, and the trace of the array substrate can be reduced. It is easy to know that in other embodiments, the fourth via hole may not be provided, and the top gate and the bottom gate are connected by external wiring.
  • the fourth via 183 can be formed in the same process step as the second via 181.
  • FIG. 3 shows a method of fabricating a thin film transistor according to an embodiment of the present disclosure. As shown in FIG. 3, the method for fabricating the thin film transistor includes:
  • Step 301 Providing a substrate.
  • Step 302 Form an active layer, a source, a gate, and a drain on the substrate.
  • the gate comprises a top gate and a bottom gate
  • the top gate comprises a top gate top and a top gate side connected to the top of the top gate, a top gate top and the bottom gate are oppositely disposed in a direction perpendicular to the substrate, the top gate side portion extending from the top of the top gate toward the substrate; the active layer being interposed on the top gate Between the top and the bottom gate, sidewalls of the active layer are at least partially surrounded by the top gate sides.
  • the gate, the source and the drain are both made of a non-transparent conductive material.
  • the step 302 may include the following steps:
  • Step 1 Form the bottom gate 16, the source 13 and the drain underlayer 141 on the substrate 11. As shown in FIG. 4a, the drain underlayer 141, the bottom gate 16 and the source 13 are formed on the substrate 11 in the same layer, and the bottom gate 16 is located between the source 13 and the drain underlayer 141.
  • Step 2 forming a gate insulating layer 17 on the substrate 11 in the form of covering the bottom gate 16, the source 13 and the drain underlayer 141, and forming corresponding to the source 13 and the drain underlayer 141 in the gate insulating layer 17, respectively.
  • the first via 171 is as shown in Figure 4b.
  • the gate insulating layer 17 can be fabricated by PECVD (Plasma Enhanced Chemical Vapor Deposition), and the hydrogen content of the film layer needs to be controlled at a low level during the fabrication process.
  • Step 3 An active layer 12 is formed on the gate insulating layer 17. As shown in FIG. 4c, both ends of the active layer 12 are connected to the source 13 and the drain underlayer 141 through the first via 171. Specifically, the active layer can be prepared by sputtering deposition.
  • Step 4 forming a passivation layer 18 on the gate insulating layer 17 in such a manner as to cover the active layer 12, and forming a third via hole in the passivation layer 18 and the gate insulating layer 17 corresponding to the drain underlayer 141.
  • 182 and corresponding to the substrate 11 form a second via 181 that is in communication, as shown in FIG. 4d.
  • the passivation layer 18 can be fabricated by PECVD, and the hydrogen content of the film layer needs to be controlled at a lower level during the fabrication process.
  • Step 5 Form a top gate 15 and a drain top layer 142 on the passivation layer 18.
  • the drain top layer 142 is connected to the drain bottom layer 141 through the third via 182.
  • the top gate side portion 15b passes through the second via hole 181
  • the passivation layer 18 is extended to the surface of the substrate 11, thereby obtaining a thin film transistor as shown in FIG.
  • top gate side portion 15b extends to the surface of the substrate 11 to obtain a better light blocking effect, while in other implementations, the top gate side portion 15b may also extend only to the gate insulating layer, and may also serve a certain degree. The effect of light illuminating from the side walls of the active layer is blocked.
  • the manufacturing method of the thin film transistor shown in FIG. 1-2 uses only five patterning processes, the process steps are simple, and the manufacturing cost is low.
  • the thin film transistor includes a substrate 21, and an active layer 22, a source 23, a drain 24, and a gate formed on the substrate 21. Both ends of the active layer 22 are connected to the source 23 and the drain 24, respectively.
  • the gate includes a top gate 25 including a top gate top 25a and a top gate side 25b connected to the top gate top 25a, the top gate top 25a and the bottom gate 26 being opposite in a direction perpendicular to the substrate 21. It is provided that the top gate side portion 25b extends from the top gate top portion 25a toward the substrate 21.
  • the active layer 22 is sandwiched between the top gate top 25a and the bottom gate 26, and the sidewalls of the active layer 22 are at least partially surrounded by the top gate side portion 25b.
  • the active layer 22 has a rectangular structure, and the opposite ends of the rectangular structure are respectively provided with a source 23 and a drain 24, and the top gate side 25b surrounds the active layer 22.
  • the two sides of the source 23 and the drain 24 are not formed.
  • the bottom gate 26 is formed on the substrate 21.
  • the thin film transistor further includes a gate insulating layer 27 formed on the substrate 21 and covering the gate electrode 26.
  • the active layer 22 is formed on the gate insulating layer 27 and formed over the bottom gate 26.
  • a source 23 and a drain 24 are formed at both ends of the active layer 22.
  • the thin film transistor of the present embodiment further includes a passivation layer 28 formed on the gate insulating layer 27 and covering the source 23, the drain 24, and the active layer 22.
  • a top gate 25 is formed on the passivation layer 28.
  • Connected vias 281 are formed in the passivation layer 28 and the gate insulating layer 27, and the vias 281 may be disposed on opposite sides of the active layer 22 where the source 23 and the drain 24 are not formed.
  • the top gate side portion 25b surrounds the periphery of the active layer 22 together with the source 23 and the drain 24 through the via 281.
  • vias on one of the opposite sides of the active layer 22 where the source 23 and the drain 24 are not formed may extend from the passivation layer 28 to the substrate 21, while the active layer 22 Unshaped
  • the vias on the other of the opposite sides of the source 23 and the drain 24 extend from the passivation layer 28 to the bottom gate 26.
  • vias on the opposite sides of the active layer 22 where the source 23 and the drain 24 are not formed extend from the passivation layer 28 to the substrate 21, or both extend from the passivation layer 28 to Bottom grid.
  • the top gate only surrounds both sides of the active layer, and the top gate substantially surrounds the active layer together with the source and the drain, while in other embodiments, the via 281 may also The active layer 22, the source 23, and the drain 24 are disposed, and at this time, the top gate 25 may surround the periphery of the active layer 22.
  • the drain 24 of the embodiment of the present disclosure may also include a drain underlayer 241 and a drain top layer 242, wherein the drain underlayer 241 is formed on the gate insulating layer 27 and connected to the active layer 22, and the drain top layer 242 is formed on the passivation layer 28, and the drain top layer 242 and the drain bottom layer 241 are connected by via holes.
  • the materials of the source, the drain and the gate in this embodiment may be the same as those of the source, the drain and the gate in the embodiment shown in FIG. 1, and details are not described herein again.
  • FIG. 7 shows a method of fabricating the thin film transistor shown in FIG. 5. As shown in FIG. 7, the method of manufacturing the thin film transistor includes:
  • Step 601 Providing a substrate.
  • Step 602 Form a bottom gate on the substrate.
  • Step 603 forming a gate insulating layer formed on the substrate and covering the bottom gate.
  • Step 604 forming an active layer on the gate insulating layer, the active layer being formed over the bottom gate.
  • Step 605 forming a source and a drain, the source and the drain being located on opposite sides of the active layer.
  • Step 606 forming a passivation layer and forming via holes in the passivation layer and the gate insulating layer, the passivation layer being formed on the gate insulating layer and covering the source, the drain and the active layer.
  • the holes are disposed on opposite sides of the active layer where the source and drain are not formed.
  • the vias can also be placed around the active layer, the source and the drain.
  • Step 607 forming a top gate on the insulating layer, the top gate extending through the via formed in step 606 to around the sidewall of the active layer, so that the top gate surrounds the active layer together with the source and the drain through the via.
  • an embodiment of the present disclosure further provides an array substrate comprising the thin film transistor provided by any of the foregoing embodiments.
  • the array substrate includes a base substrate on which a gate line, a data line, a pixel electrode layer and the thin film transistor are disposed, a drain of the thin film transistor is connected to the pixel electrode layer, and a gate and a gate of the thin film transistor are The line is connected, and the source of the thin film transistor is connected to the data line.
  • the pixel electrode layer may be a transparent conductive metal oxide layer such as ITO (Indium Tin Oxides), IZO (Indium Zinc Oxides), or the like.
  • ITO Indium Tin Oxides
  • IZO Indium Zinc Oxides
  • an embodiment of the present disclosure further provides a display device including the array substrate provided by the foregoing embodiments.
  • the display device may be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.

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Abstract

提供一种薄膜晶体管及其制造方法、阵列基板、显示装置。该薄膜晶体管包括：基板（11）、以及形成于基板（11）上的有源层（12）、源极（13）、栅极和漏极（14）。有源层（12）两端分别与所述源极（13）和所述漏极（14）连接，栅极包括顶栅（15）和底栅（16），顶栅（15）包括顶栅顶部（15a）和与顶栅顶部（15a）连接的顶栅侧部（15b），顶栅顶部（15a）和底栅（16）在垂直于基板（11）的方向上相对设置，顶栅侧部（15b）从顶栅顶部（15a）朝向基板（11）延伸。有源层（12）夹设于顶栅顶部（15a）和底栅（16）之间，有源层（12）的侧壁至少部分地被顶栅侧部（15b）围绕。栅极、源极（13）和漏极（14）均采用非透明的导电材料制成。

Description

一种薄膜晶体管及其制造方法、阵列基板、显示装置
相关申请的交叉引用
本申请要求于2015年05月28日递交的中国专利申请第201510282237.8号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开涉及半导体技术领域，特别涉及一种薄膜晶体管及其制造方法、阵列基板、显示装置。
背景技术
随着工艺技术的进步，薄膜晶体管已被大量应用在显示器之中，以适应显示器的薄型化和小型化等需求。在显示器的工作过程中，薄膜晶体管很容易被光照射到，而当光照射到其有源层时，会导致其关态漏电流增加，从而造成薄膜晶体管特性的劣化。
现有一种常见的薄膜晶体管，其包括栅极、形成在栅极上的栅极绝缘层、形成在栅极绝缘层上的有源层、以及形成在有源层上并相互隔开的源极和漏极。在该结构中，栅极位于有源层的下方，从有源层下方照射的光能够被阻挡，而从有源层上方照射的光没有被阻挡且可以从源极和漏极之间照射到有源层上，进而导致薄膜晶体管的特性劣化。
发明内容
本公开实施例提供了一种薄膜晶体管及其制造方法、阵列基板、显示装置，其可以防止有源层被光照射，进而提高薄膜晶体管的特性。所述技术方案如下：
第一方面，本公开实施例提供了一种薄膜晶体管，包括：基板、以及 形成于所述基板上的有源层、源极、栅极和漏极。所述有源层的两端分别与所述源极和所述漏极连接。所述栅极包括顶栅和底栅，所述顶栅包括顶栅顶部和与所述顶栅顶部连接的顶栅侧部，所述顶栅侧部从所述顶栅顶部朝向所述基板延伸。所述有源层夹设于所述顶栅顶部和所述底栅之间，所述有源层的侧壁至少部分地被所述顶栅侧部围绕。
可选地，所述栅极、所述源极和所述漏极均采用非透明的导电材料制成。
可选地，所述漏极包括漏极底层，所述漏极底层、底栅和所述源极同层间隔形成在所述基板上，且所述底栅位于所述源极和漏极底层之间。
进一步地，所述薄膜晶体管还包括栅极绝缘层，所述栅极绝缘层形成在所述基板上且覆盖所述漏极底层、所述底栅和所述源极，在所述栅极绝缘层中对应于所述漏极底层和所述源极分别形成有第一过孔，所述有源层形成在所述栅极绝缘层上，所述有源层通过所述第一过孔分别与所述漏极底层和所述源极连接。
可选地，所述薄膜晶体管还包括钝化层，所述钝化层形成在所述栅极绝缘层上且覆盖所述有源层，在所述钝化层和所述栅极绝缘层中对应于所述基板形成有连通的第二过孔，而对应所述漏极底层形成有连通的第三过孔，所述漏极还包括漏极顶层，所述漏极顶层通过第三过孔与所述漏极底层连接，所述顶栅侧部通过所述第二过孔从所述钝化层至少延伸到所述栅极绝缘层，所述第三过孔和所述第二过孔间隔设置，所述第三过孔和所述第二过孔一起围绕在所述有源层的侧壁周围。
在一种实施方式中，所述第三过孔的横截面和所述第二过孔的横截面一起形成矩形框状结构。
可选地，所述钝化层和所述栅极绝缘层内还形成有连通的第四过孔，所述顶栅和所述底栅通过所述第四过孔连接。
在一种实施方式中，所述有源层呈矩形结构，所述顶栅侧部包围所述矩形结构的三个侧边。
在一种实施方式中，所述有源层呈矩形结构，所述顶栅侧部包围所述 矩形结构的两个侧边。
可选地，所述薄膜晶体管还包括覆盖所述栅极的栅极绝缘层以及形成在所述栅极绝缘层上的绝缘层，并且其中，所述漏极包括形成在所述栅极绝缘层上的漏极底层和形成在所述绝缘层上的漏极顶层。
可选地，所述有源层为氧化物半导体层。
可选地，所述氧化物半导体层的材料包括IGZO、ITZO或ZnON。
可选地，所述氧化物半导体层的厚度为10-150nm。
可选地，所述栅极、所述源极和所述漏极均采用不透明的金属制成。
第二方面，本公开实施例提供了一种薄膜晶体管的制造方法，包括：
提供基板；
在所述基板上形成有源层、源极、栅极和漏极，所述有源层的两端分别与所述源极和所述源极连接，其中，所述栅极包括顶栅和底栅，所述顶栅包括顶栅顶部和与所述顶栅顶部连接的顶栅侧部，所述顶栅顶部和所述底栅在垂直于所述基板的方向上相对设置，所述顶栅侧部从所述顶栅顶部朝向所述基板延伸，并且其中，所述有源层夹设于所述顶栅顶部和所述底栅之间，所述有源层的侧壁至少部分地被所述顶栅侧部围绕。
可选地，所述栅极、所述源极和所述漏极均采用非透明的导电材料制成。
可选地，在所述基板上形成有源层、源极、栅极和漏极，包括：
在基板上形成所述底栅、所述源极和所述漏极底层，所述漏极底层、所述底栅和所述源极同层间隔形成在所述基板上，且所述底栅位于所述源极和所述漏极底层之间；
在所述基板上以覆盖所述底栅、源极和漏极底层的形式形成所述栅极绝缘层，并在所述栅极绝缘层中对应于所述源极和所述漏极底层分别形成第一过孔；
在栅极绝缘层上形成所述有源层；
以覆盖所述有源层的方式在所述栅极绝缘层上形成所述钝化层，并在所述钝化层和所述栅极绝缘层中对应于所述基板形成连通的第二过孔并对 应所述漏极底层形成连通的第三过孔；
在所述钝化层上形成所述顶栅和所述漏极顶层，所述漏极顶层通过所述第三过孔与所述漏极底层连接，所述顶栅侧部通过所述第二过孔从所述钝化层至少延伸到所述栅极绝缘层。
第三方面，本公开实施例提供了一种阵列基板，前述薄膜晶体管。可选地，所述阵列基板包括衬底基板，其中，所述衬底基板上设有栅线、数据线、像素电极层和所述薄膜晶体管，所述薄膜晶体管的漏极与所述像素电极层连接，所述薄膜晶体管的栅极与所述栅线连接，所述薄膜晶体管的源极与所述数据线连接。
第四方面，本公开实施例还提供了一种显示装置，包括前述阵列基板。
本公开实施例提供的技术方案带来的有益效果是：
在本公开实施例中，有源层下方的底栅可以阻挡从氧化物半导体层下方照射的光，围绕在有源层侧壁的顶栅侧部可以阻挡从有源层侧壁照射的光，而位于有源层上方的顶栅顶部可以阻挡从有源层上方照射的光，从而可以减少有源层被光照射的情况，进而可以避免薄膜晶体管的特性由于光照而劣化。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开实施例提供的一种薄膜晶体管的截面结构示意图；
图2是本公开实施例提供的薄膜晶体管去掉顶栅和部分漏极后的俯视结构示意图；
图3是本公开实施例提供的一种薄膜晶体管的制造方法的流程图；
图4a-4d是本公开实施例提供的薄膜晶体管的制备工艺图；
图5是本公开实施例提供的又一薄膜晶体管的截面结构示意图；
图6是图5所示薄膜晶体管的又一截面结构示意图；
图7是本公开实施例提供的又一薄膜晶体管的制造方法的流程图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。附图中各层薄膜的厚度和形状不反映阵列基板的真实比例，目的只是示意说明本公开内容。
在本公开的描述中，需要说明的是，术语“上”、“下”、“顶”、“底”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
此外，在本公开的描述中，除非另有说明，“多种”的含义是两种或两种以上。
本公开实施例提供了一种薄膜晶体管，包括：基板、以及形成于所述基板上的有源层、源极、栅极和漏极。所述有源层的两端分别与所述源极和所述漏极连接。所述栅极包括顶栅和底栅，所述顶栅包括顶栅顶部和与所述顶栅顶部连接的顶栅侧部，所述顶栅顶部和所述底栅在垂直于所述基板的方向上相对设置，所述顶栅侧部从所述顶栅顶部朝向所述基板延伸。所述有源层夹设于所述顶栅顶部和所述底栅之间，所述有源层的侧壁至少部分地被所述顶栅侧部围绕。所述栅极、所述源极和所述漏极均采用非透明的导电材料制成。
在本实施例的一种实现方式中，非透明的导电材料可以为不完全透明的导电材料，其中，不完全透明的导电材料可以为透过率为15％以下的导电材料，优选为透过率为5％以下的导电材料，在本实施例的一种优选的实现方式中，非透明的导电材料为不透明的导电材料，例如不透明的金属。故此，在本公开实施例中，将均以不透明的金属为例进行说明。
可选地，有源层可以呈矩形结构，所述顶栅侧部可以包围所述矩形结构的三个侧边(如图1所示实施例，)，或者，顶栅侧部也可以包围矩形结 构的两个侧边(如图5所示实施例)。
需要说明的是，在本公开实施例中，有源层包括顶面、底面和连接顶面和底面的侧壁。有源层的顶面与顶栅顶部相对，有源层的底面与底栅相对。有源层的侧壁至少部分地被顶栅侧部围绕，是指顶栅侧部会从顶栅顶部朝向基板方向延伸直至挡住有源层的侧壁，即至少延伸到栅极绝缘层。
在本公开实施例中，有源层下方的底栅可以阻挡从氧化物半导体层下方照射的光，围绕在有源层侧壁的顶栅侧部可以阻挡从有源层侧壁照射的光，而位于有源层上方的顶栅顶部可以阻挡从有源层上方照射的光，从而可以减少有源层被光照射的情况，进而可以避免薄膜晶体管的特性由于光照而劣化。
图1显示了本公开实施例提供的一薄膜晶体管的具体结构。图1是本公开实施例提供的一种薄膜晶体管的截面示意图。如图1所示，该薄膜晶体管包括：基板11、以及形成于基板11上的有源层12、源极13、和漏极14和栅极。有源层12的两端分别与源极13和漏极14连接。栅极包括顶栅15和底栅16，顶栅15包括顶栅顶部15a和与顶栅顶部15a连接的顶栅侧部15b，顶栅顶部15a和底栅16在垂直于基板11的方向上相对设置，顶栅侧部15b从顶栅顶部15a朝向基板11延伸。有源层12夹设于顶栅顶部15a和底栅16之间，且有源层12的侧壁至少部分地被顶栅侧部15b围绕。
其中，基板11可为玻璃基板、透明塑料基板等，本公开对此不作限制。
有源层12的材料可以为氧化物半导体、多晶硅、非晶硅等。由于氧化物半导体对光照更为敏感，所以本公开实施例尤其适用于氧化物半导体薄膜晶体管。故在本实施例中，有源层12为氧化物半导体层。本公开实施例的氧化物半导体层的材料包括但不限于IGZO(Indium Gallium Zinc Oxide，铟镓锌氧化物)、ITZO(Indium Tin Zinc Oxide，铟锡锌氧化物)或ZnON(锌的氮氧化物)。在一个实施例中，氧化物半导体层的厚度可以为10-150nm。
在本实施例中，漏极14包括漏极底层141。漏极底层141、底栅16 和源极13同层间隔形成在基板11上，且底栅16位于源极14和漏极底层141之间。
在本公开实施例中，底栅16、源极13和漏极底层141同层设置。为了节省制作工序，底栅、源极和漏极底层优选采用相同的材料制备，这样，底栅、源极和漏极底层可以通过一次构图工艺形成在基板上，从而减少了掩模板的使用次数，简化了该薄膜晶体管的制备工艺，进而可以降低其制备成本。
如前所述，在本实施例中，底栅16、源极13和漏极底层141均采用不透明的金属制成。具体地，可以采用由钼(Mo)、钼铌合金(MoNb)、铝(Al)、铝钕合金(AlNd)、钛(Ti)和铜(Cu)中的一种材料形成的单层膜或多种材料形成的多层复合膜；优选采用Mo、Al或含Mo、Al的合金组成的单层或多层复合膜，例如Mo/Al/Mo三层复合膜。由于Al的电阻较小而Mo的抗氧化能力较强，所以采用这种复合膜结构能够保证信号传输速度并提高使用寿命。在一个实施例中，底栅、源极和漏极底层的厚度可以为100nm～500nm。
该薄膜晶体管还包括栅极绝缘层17。栅极绝缘层17形成在基板11上，且覆盖漏极底层141、底栅16和源极13，从而使得漏极底层141、底栅16和源极13彼此绝缘。在栅极绝缘层17中对应于漏极底层141和源极13分别设有第一过孔171(参见图4b)。有源层12形成在栅极绝缘层17上，有源层12通过第一过孔171分别与漏极底层141和源极13连接。
其中，栅极绝缘层17可以为由硅的氧化物(SiOx)、硅的氮化物(SiNx)、铪的氧化物(HfOx)、硅的氮氧化物(SiON)、AlOx等中的一种材料形成的单层膜或两种材料组成的多层复合膜。优选为SiNx/SiOx的叠层结构或者SiNx/SiON/SiOx的叠层结构。栅极绝缘层17的厚度可以为100～600nm。
薄膜晶体管还包括钝化层18。钝化层18形成在栅极绝缘层17上且覆盖有源层12。在钝化层18和栅极绝缘层17中对应于基板形成有连通的第二过孔181(参见图4d)，对应于漏极底层141形成有连通的第三过孔182。漏极14还包括漏极顶层142，漏极顶层142通过第三过孔182与漏极底层 141连接。顶栅15通过第二过孔181与基板11连接(即顶栅侧部15b与基板11连接)。第三过孔182和第二过孔181间隔设置，第三过孔182和第二过孔181一起围绕在有源层12的侧壁周围。
本公开实施例通过使第三过孔182和第二过孔181一起围绕在有源层12的侧壁周围，从而顶栅侧部和漏极顶层可以包围有源层的侧壁，栅极、漏极、源极形成一个基本封闭的空间，进而有源层处于基本上不会被光照射到的状态，这样可以进一步防止薄膜晶体管的特性因光照而劣化。同时，在钝化层上形成有漏极顶层。当该薄膜晶体管应用于阵列基板时，像素电极层可以直接在钝化层上形成图案，便于与像素电极层连接。
需要说明的是，在图1所示实施例中，第二过孔181从钝化层18延伸至基板11表面，从而可以更严密地遮挡有源层，防止其被光照到；而在其他实现方式中，第二过孔181也可以从钝化层18延伸到栅极绝缘层17内而不到达基板11表面，只要能够遮挡从有源层侧壁照射的光即可。也就是说，在本公开实施例中，顶栅侧部通过第二过孔从钝化层至少延伸到栅极绝缘层。
结合图2，图2是本公开实施例提供的薄膜晶体管去掉顶栅和部分漏极后的俯视结构示意图。如图2所示，在本实施例中，第二过孔181的横截面形状为一边开口的矩形框(包括底边181a和垂直连接在底边181a两端的两侧边181b)，而第三过孔182的横截面形状呈直线形，第二过孔181和第三过孔182的横截面形状一起构成类似于矩形框状结构。容易知道，第二过孔181的横截面形状和第三过孔182的横截面形状也可以是圆弧形，第二过孔181的横截面和第三过孔182的横截面形状一起构成类似于圆形框状结构，或者，在其他实现方式中，第二过孔181和第三过孔182的横截面形状一起还可以构成多边形框等形状，只要能够围绕有源层的四周即可，本公开对此不做限制。
需要说明的是，本公开实施例中的过孔(包括第一过孔、第二过孔、第三过孔等)的侧壁通常并非垂直于基板的板面，而是呈一定的坡度角，坡度角通常为30°～70°。
同样地，在本实施例中，顶栅15采用不透明的金属制成。具体地，顶栅15可以为Mo、MoNb、Al、AlNd、Ti、Cu中的一种材料形成的单层膜或多种材料形成的多层复合膜，优选为Mo、Al或含Mo、Al的合金组成的单层或多层复合膜，例如Mo/Al/Mo三层复合膜。由于Al的电阻较小而Mo的抗氧化能力较强，所以采用这种复合膜结构能够保证信号传输速度并提高使用寿命。具体实施时，形成在钝化层上的顶栅的厚度可以为200～900nm。容易知道，顶栅15和底栅16可以采用相同的材料制成，也可以采用不同的材料制成。
钝化层18可以为由硅的氧化物(SiOx)、硅的氮化物(SiNx)、铪的氧化物(HfOx)、硅的氮氧化物(SiON)、AlOx等中的一种材料制成的单层膜或两种组成的多层复合膜。其优选为SiNx/SiOx的叠层结构或SiNx/SiON/SiOx的叠层结构。在一个实施例中，钝化层的厚度可以为100～600nm。
如图2所示，在本公开实施例中，在钝化层18和栅极绝缘层17中还形成有连通的第四过孔183。顶栅15和底栅16通过第四过孔183连接，将顶栅和底栅电连接，使得该两个栅极同时工作。这加快了薄膜晶体管内的电荷的沟道的开启的速度，同时给予电荷更好的引导能力，以提高其导电能力，从而提高响应速度；并且，在停止该薄膜晶体管工作时，向薄膜晶体管的两个栅极提供稳定的负电压，加快薄膜晶体管的沟道的关断的速度，同时提高了薄膜晶体管的阻止电荷移动能力，以降低薄膜晶体管的漏电流，从而降低功耗。并且，顶栅和底栅通过第四过孔连接，从而当本公开实施例的薄膜晶体管应用于阵列基板时，不用分别为顶栅和底栅布线，可以减少阵列基板的走线。容易知道，在其他实施例中，也可以不设置第四过孔，顶栅和底栅采用外部走线的方式连接。
容易知道，第四过孔183可以与第二过孔181在同一工艺步骤中形成。
图3显示了本公开实施例提供的薄膜晶体管的制造方法，如图3所示，该薄膜晶体管的制造方法包括：
步骤301：提供基板。
步骤302：在基板上形成有源层、源极、栅极和漏极。其中，有源层的两端分别与源极和源极连接；栅极包括顶栅和底栅，所述顶栅包括顶栅顶部和与所述顶栅顶部连接的顶栅侧部，所述顶栅顶部和所述底栅在垂直于所述基板的方向上相对设置，所述顶栅侧部从所述顶栅顶部朝向所述基板延伸；所述有源层夹设于所述顶栅顶部和所述底栅之间，所述有源层的侧壁至少部分地被所述顶栅侧部围绕。所述栅极、所述源极和所述漏极均采用非透明的导电材料制成。
具体地，当本公开实施例的制造方法用于制备图1-2所示的薄膜晶体管时，该步骤302可以包括以下步骤：
步骤一、在基板11上形成底栅16、源极13和漏极底层141。如图4a所示，漏极底层141、底栅16和源极13同层间隔形成在基板11上，且底栅16位于源极13和漏极底层141之间。
步骤二、在基板11上以覆盖底栅16、源极13和漏极底层141的形式形成栅极绝缘层17，并在栅极绝缘层17中对应于源极13和漏极底层141分别形成第一过孔171，如图4b所示。具体地，栅极绝缘层17可以采用PECVD(Plasma Enhanced Chemical Vapor Deposition，等离子体增强化学气相沉积法)制作，且在制作过程中，需控制膜层的氢含量在较低的水平。
步骤三、在栅极绝缘层17上形成有源层12，如图4c所示，该有源层12的两端通过第一过孔171与源极13和漏极底层141连接。具体地，有源层可以采用溅射沉积的方式制备。
步骤四、以覆盖有源层12的方式在栅极绝缘层17上形成钝化层18，并在钝化层18和栅极绝缘层17中对应于漏极底层141形成连通的第三过孔182并对应于基板11形成连通的第二过孔181，如图4d所示。具体地，钝化层18可以采用PECVD制作，且在制作过程中，需控制膜层的氢含量在较低的水平。
步骤五、在钝化层18上形成顶栅15和漏极顶层142。漏极顶层142通过第三过孔182与漏极底层141连接。顶栅侧部15b通过第二过孔181 从钝化层18延伸到基板11表面，从而得到如图1所示的薄膜晶体管。
容易知道，顶栅侧部15b延伸到基板11表面可以获得更好地挡光效果，而在其他实现方式中，顶栅侧部15b也可以只延伸到栅极绝缘层，同样可以起到一定的遮挡从有源层侧壁照射的光的作用。
从前述步骤可以看出，图1-2所示的薄膜晶体管的制造方法仅采用了5次构图工艺，工艺步骤简单，制造成本低。
图5和图6显示了本公开实施例提供的又一薄膜晶体管的结构。图5和图6所示截面相互垂直。如图5和图6所示，该薄膜晶体管包括基板21、以及形成于基板21上的有源层22、源极23、漏极24和栅极。有源层22的两端分别与所述源极23和所述漏极24连接。栅极包括顶栅25和底栅26，顶栅25包括顶栅顶部25a和与顶栅顶部25a连接的顶栅侧部25b，顶栅顶部25a和底栅26在垂直于基板21的方向上相对设置，顶栅侧部25b从顶栅顶部25a朝向基板21延伸。有源层22夹设于顶栅顶部25a和底栅26之间，，有源层22的侧壁至少部分地被顶栅侧部25b围绕。
进一步地，在图5所示实施例中，有源层22呈矩形结构，矩形结构的相对的两端分别设有源极23和漏极24，而顶栅侧部25b围绕有源层22的未形成源极23和漏极24的两个侧边。
在图5所示的薄膜晶体管中，底栅26形成在基板21上。该薄膜晶体管还包括栅极绝缘层27，该栅极绝缘层27形成在基板21上且覆盖栅极26。有源层22形成在栅极绝缘层27上且形成在底栅26上方。源极23和漏极24形成在有源层22的两端。
本实施例的薄膜晶体管还包括钝化层28，钝化层28形成在栅极绝缘层27上，且覆盖源极23、漏极24和有源层22。顶栅25形成在钝化层28上。在钝化层28和栅极绝缘层27中形成有连通的过孔281，该过孔281可以设置在有源层22的未形成源极23和漏极24的相对两侧。顶栅侧部25b通过该过孔281与源极23、漏极24一起包围有源层22的四周。
在一种实施方式中，在有源层22的未形成源极23和漏极24的相对两侧中的一侧的过孔可以从钝化层28延伸至基板21，而在有源层22的未形 成源极23和漏极24的相对两侧中的另一侧的过孔从钝化层28延伸至底栅26。
在另一种实施方式中，在有源层22的未形成源极23和漏极24的相对两侧的过孔均从钝化层28延伸至基板21、或者均从钝化层28延伸至底栅。
容易知道，在前述两种实施方式中，顶栅仅围绕有源层的两侧，顶栅与源极和漏极一起基本上包围有源层，而在其他实施方式中，过孔281也可以围绕有源层22、源极23和漏极24设置，此时，顶栅25可以包围有源层22的四周。
可选地，本公开实施例的漏极24也可以包括漏极底层241和漏极顶层242，其中漏极底层241形成在栅极绝缘层27上且与有源层22连接，而漏极顶层242形成在钝化层28上，漏极顶层242和漏极底层241通过过孔连接。
本实施例中的源极、漏极和栅极的材料可以与图1所示实施例中的源极、漏极和栅极的材料相同，在此不再赘述。
图7显示了图5所示薄膜晶体管的制备方法，如图7所示，该薄膜晶体管的制造方法包括：
步骤601：提供基板。
步骤602：在基板上形成底栅。
步骤603：形成栅极绝缘层，栅极绝缘层形成在基板上且覆盖底栅。
步骤604：在栅极绝缘层上形成有源层，该有源层形成在底栅上方。
步骤605：形成源极和漏极，源极和漏极位于有源层的相对两侧。
步骤606：形成钝化层并在钝化层和栅极绝缘层中形成连通的过孔，该钝化层形成在栅极绝缘层上，且覆盖源极、漏极和有源层，该过孔设置在有源层的未形成源极和漏极的相对两侧。
如前所述，该过孔也可以围绕有源层、源极和漏极设置。
步骤607：在绝缘层上形成顶栅，顶栅通过步骤606中形成的过孔延伸至有源层的侧壁周围，从而顶栅通过该过孔与源极、漏极一起围绕有源层。
本公开实施例还提供了一种阵列基板，该阵列基板包括前述任一实施例提供的薄膜晶体管。具体地，该阵列基板包括衬底基板，衬底基板上设有栅线、数据线、像素电极层和前述薄膜晶体管，该薄膜晶体管的漏极与像素电极层连接，薄膜晶体管的栅极与栅线连接，薄膜晶体管的源极与数据线连接。
其中，像素电极层可以为透明的导电金属氧化物层，例如ITO(Indium Tin Oxides，氧化铟锡)、IZO(Indium Zinc Oxides，氧化铟锌)等。
基于相同的发明构思，本公开实施例还提供了一种显示装置，该显示装置包括前述实施例提供的阵列基板。
在具体实施时，本公开实施例提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述仅为本公开的较佳实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (20)

  1. 一种薄膜晶体管，包括：基板、以及形成于所述基板上的有源层、源极、栅极和漏极，所述有源层的两端分别与所述源极和所述漏极连接，其中，
    所述栅极包括顶栅和底栅，所述顶栅包括顶栅顶部和与所述顶栅顶部连接的顶栅侧部，所述顶栅顶部和所述底栅在垂直于所述基板的方向上相对设置，所述顶栅侧部从所述顶栅顶部朝向所述基板延伸；
    所述有源层夹设于所述顶栅顶部和所述底栅之间，所述有源层的侧壁至少部分地被所述顶栅侧部围绕。
  2. 根据权利要求1所述的薄膜晶体管，其中，所述栅极、所述源极和所述漏极均采用非透明的导电材料制成。3、根据权利要求1或2所述的薄膜晶体管，其中，所述漏极包括漏极底层，所述漏极底层、所述底栅和所述源极同层间隔形成在所述基板上，且所述底栅位于所述源极和漏极底层之间。
  3. 根据权利要求3所述的薄膜晶体管，其中，所述薄膜晶体管还包括栅极绝缘层，所述栅极绝缘层形成在所述基板上且覆盖所述漏极底层、所述底栅和所述源极，在所述栅极绝缘层中对应于所述漏极底层和所述源极分别形成有第一过孔，所述有源层形成在所述栅极绝缘层上，所述有源层通过所述第一过孔分别与所述漏极底层和所述源极连接。
  4. 根据权利要求4所述的薄膜晶体管，其中，所述薄膜晶体管还包括钝化层，所述钝化层形成在所述栅极绝缘层上且覆盖所述有源层，在所述钝化层和所述栅极绝缘层中对应于所述基板形成有连通的第二过孔，而对应于所述漏极底层形成有连通的第三过孔，所述漏极还包括漏极顶层，所述漏极顶层通过所述第三过孔与所述漏极底层连接，所述顶栅侧部通过所述第二过孔从所述钝化层至少延伸到所述栅极绝缘层，所述第三过孔和所述第二过孔间隔设置，所述第三过孔和所述第二过孔一起围绕在所述有源层的侧壁周围。
  5. 根据权利要求5所述的薄膜晶体管，其中，所述第三过孔的横截面和所述第二过孔的横截面一起形成矩形框状结构。
  6. 根据权利要求5或6所述的薄膜晶体管，其中，在所述钝化层和所述栅极绝缘层内还形成有连通的第四过孔，所述顶栅和所述底栅通过所述第四过孔连接。
  7. 根据权利要求1所述的薄膜晶体管，其特征在于，所述有源层呈矩形结构。
  8. 根据权利要求8所述的薄膜晶体管，其中，所述顶栅侧部包围所述矩形结构的三个侧边。
  9. 根据权利要求8所述的薄膜晶体管，其中，所述顶栅侧部包围所述矩形结构的两个侧边。
  10. 根据权利要求10所述的薄膜晶体管，还包括覆盖所述栅极的栅极绝缘层以及形成在所述栅极绝缘层上的钝化层，并且其中，所述漏极包括形成在所述栅极绝缘层上的漏极底层和形成在所述钝化层上的漏极顶层。
  11. 根据上述任一项权利要求所述的薄膜晶体管，其中，所述有源层为氧化物半导体层。
  12. 根据权利要求12所述的薄膜晶体管，其中，所述氧化物半导体层的材料包括IGZO、ITZO或ZnON。
  13. 根据权利要求12所述的薄膜晶体管，其中，所述氧化物半导体层的厚度为10-150nm。
  14. 根据上述权利要求中的任一项所述的薄膜晶体管，其中，所述栅极、所述源极和所述漏极均采用不透明的金属制成。
  15. 一种薄膜晶体管的制造方法，包括：
    提供基板；
    在所述基板上形成有源层、源极、栅极和漏极，所述有源层的两端分别与所述源极和所述源极连接，其中，所述栅极包括顶栅和底栅，所述顶栅包括顶栅顶部和与所述顶栅顶部连接的顶栅侧部，所述顶栅顶部和所述底栅在垂直于所述基板的方向上相对设置，所述顶栅侧部从所述顶栅顶部 朝向所述基板延伸，并且其中，所述有源层夹设于所述顶栅顶部和所述底栅之间，所述有源层的侧壁至少部分地被所述顶栅侧部围绕。
  16. 根据权利要求16所述的制造方法，其中，所述栅极、所述源极和所述漏极均采用非透明的导电材料制成。
  17. 根据权利要求16或17所述的制造方法，其中，在所述基板上形成有源层、源极、栅极和漏极，包括：
    在基板上形成所述底栅、所述源极和所述漏极底层，所述漏极底层、所述底栅和所述源极同层间隔形成在所述基板上，且所述底栅位于所述源极和所述漏极底层之间；
    在所述基板上以覆盖所述底栅、所述源极和所述漏极底层的形式形成所述栅极绝缘层，并在所述栅极绝缘层中对应于所述源极和所述漏极底层分别形成第一过孔；
    在栅极绝缘层上形成所述有源层；
    以覆盖所述有源层的方式在所述栅极绝缘层上形成所述钝化层，并在所述钝化层和所述栅极绝缘层中对应于所述基板形成连通的第二过孔并对应于所述漏极底层形成连通的第三过孔；
    在所述钝化层上形成所述顶栅和所述漏极顶层，所述漏极顶层通过所述第三过孔与所述漏极底层连接，所述顶栅侧部通过所述第二过孔从所述钝化层至少延伸到所述栅极绝缘层。
  18. 一种阵列基板，包括如权利要求1-15中的任一项所述的薄膜晶体管。
  19. 根据权利要求19所述的阵列基板，包括衬底基板，其中，所述衬底基板上设有栅线、数据线、像素电极层和所述薄膜晶体管，所述薄膜晶体管的漏极与所述像素电极层连接，所述薄膜晶体管的栅极与所述栅线连接，所述薄膜晶体管的源极与所述数据线连接。
  20. 一种显示装置，包括如权利要求19或20所述的阵列基板。
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Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6671155B2 (ja) * 2015-11-26 2020-03-25 三菱電機株式会社 薄膜トランジスタ基板
CN105789119B (zh) * 2016-05-20 2019-01-22 武汉华星光电技术有限公司 阵列基板及其制作方法
CN110690228B (zh) * 2019-09-06 2022-03-08 深圳市华星光电半导体显示技术有限公司 阵列基板及显示面板
CN111628003A (zh) * 2020-04-16 2020-09-04 福建华佳彩有限公司 一种晶体管结构及制作方法
CN111725240B (zh) * 2020-06-10 2023-04-18 武汉华星光电半导体显示技术有限公司 薄膜晶体管电极及其制造方法、显示装置
CN112071268B (zh) * 2020-08-12 2022-02-22 武汉华星光电半导体显示技术有限公司 显示面板和显示装置
CN112397579B (zh) * 2020-10-22 2022-12-06 云谷（固安）科技有限公司 显示面板
CN112530978B (zh) * 2020-12-01 2024-02-13 京东方科技集团股份有限公司 开关器件结构及其制备方法、薄膜晶体管膜层、显示面板
CN116544151B (zh) * 2023-07-05 2023-09-19 砺铸智能设备(天津)有限公司 一种用于芯片的检测、封装设备

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101140911A (zh) * 2007-10-16 2008-03-12 友达光电股份有限公司 一种薄膜晶体管及其形成方法
CN102315278A (zh) * 2010-07-07 2012-01-11 三星移动显示器株式会社 双栅薄膜晶体管及包括双栅薄膜晶体管的oled显示装置
CN102956649A (zh) * 2012-11-26 2013-03-06 京东方科技集团股份有限公司 阵列基板、阵列基板制作方法及显示装置
CN102983135A (zh) * 2012-12-13 2013-03-20 京东方科技集团股份有限公司 一种阵列基板、显示装置及阵列基板的制备方法
US20150062475A1 (en) * 2013-09-05 2015-03-05 Samsung Electronics Co., Ltd. Thin film transistor and method of driving same

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001177100A (ja) * 1999-12-17 2001-06-29 Matsushita Electronics Industry Corp 薄膜トランジスタとそれを用いた液晶表示素子およびその製造方法
JP4554180B2 (ja) * 2003-09-17 2010-09-29 ソニー株式会社 薄膜半導体デバイスの製造方法
JP5275739B2 (ja) * 2008-10-03 2013-08-28 株式会社ジャパンディスプレイウェスト センサ素子およびその駆動方法
CN104244988A (zh) * 2012-03-05 2014-12-24 雷蒙特亚特特拉维夫大学有限公司 结合治疗活性剂的聚合物、其制备方法以及其用途
KR101614398B1 (ko) 2012-08-13 2016-05-02 엘지디스플레이 주식회사 박막 트랜지스터 기판과 그 제조방법 및 그를 이용한 유기 발광장치
JP6570825B2 (ja) * 2013-12-12 2019-09-04 株式会社半導体エネルギー研究所 電子機器
KR102132181B1 (ko) * 2013-12-31 2020-07-10 엘지디스플레이 주식회사 유기 발광 디스플레이 장치와 이의 제조 방법
CN104393051A (zh) * 2014-10-31 2015-03-04 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、阵列基板

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101140911A (zh) * 2007-10-16 2008-03-12 友达光电股份有限公司 一种薄膜晶体管及其形成方法
CN102315278A (zh) * 2010-07-07 2012-01-11 三星移动显示器株式会社 双栅薄膜晶体管及包括双栅薄膜晶体管的oled显示装置
CN102956649A (zh) * 2012-11-26 2013-03-06 京东方科技集团股份有限公司 阵列基板、阵列基板制作方法及显示装置
CN102983135A (zh) * 2012-12-13 2013-03-20 京东方科技集团股份有限公司 一种阵列基板、显示装置及阵列基板的制备方法
US20150062475A1 (en) * 2013-09-05 2015-03-05 Samsung Electronics Co., Ltd. Thin film transistor and method of driving same

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