WO2023207216A1 - 移位寄存器、栅极驱动电路、显示面板及电子设备 - Google Patents

移位寄存器、栅极驱动电路、显示面板及电子设备 Download PDF

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Publication number
WO2023207216A1
WO2023207216A1 PCT/CN2023/070297 CN2023070297W WO2023207216A1 WO 2023207216 A1 WO2023207216 A1 WO 2023207216A1 CN 2023070297 W CN2023070297 W CN 2023070297W WO 2023207216 A1 WO2023207216 A1 WO 2023207216A1
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Prior art keywords
transistor
node
signal
electrically connected
terminal
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PCT/CN2023/070297
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English (en)
French (fr)
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WO2023207216A9 (zh
Inventor
韩林宏
吴婉铭
耿玓
李泠
田正
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荣耀终端有限公司
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Priority to EP23735958.3A priority Critical patent/EP4297005A1/en
Publication of WO2023207216A1 publication Critical patent/WO2023207216A1/zh
Publication of WO2023207216A9 publication Critical patent/WO2023207216A9/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0281—Arrangement of scan or data electrode driver circuits at the periphery of a panel not inherent to a split matrix structure
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes

Definitions

  • the present application relates to the field of display technology, and in particular to a shift register, a gate drive circuit, a display panel and electronic equipment.
  • the main component of electronic equipment that implements the display function is the display panel.
  • the driving circuit in the display panel outputs a driving signal to the pixel circuit in the pixel array according to the clock signal sent by the clock signal line to control the pixel array to display the image.
  • each drive signal is generated by its own drive circuit, and each drive circuit corresponds to its own clock signal line, more clock signal lines will be needed and the display driver chip will need to provide more clocks for the clock signal lines.
  • Signal clock control module As the design cost of driving the display chip.
  • the drive circuit is generally composed of multiple transistors. Deviations in the stability of the transistors often lead to errors in the circuit logic and ultimately lead to drive abnormalities. Therefore, a circuit architecture with simple structure and high stability is needed.
  • this application provides a shift register, a gate drive circuit, a display panel and an electronic device.
  • embodiments of the present application provide a shift register, which includes a node control module, a first level signal receiving end, a second level signal receiving end, a first clock signal end, a second clock
  • the signal terminal, the first node and the second node are electrically connected;
  • the input module is electrically connected with the second clock signal terminal, the trigger signal input terminal and the second node;
  • the voltage stabilizing module is electrically connected with the second node, the second clock signal terminal and the second node.
  • the three nodes are electrically connected; the output module is electrically connected to the first level signal receiving end, the second level signal receiving end, the first node, the third node and the drive signal output end; the input module is used to receive input from the trigger signal input end signal, and control the signal of the second node in response to the second clock signal received by the second clock signal terminal; the node control module is used to receive the first level signal and the second level signal received by the first level signal receiving terminal.
  • the output module is used to receive the second level signal received by the second level signal receiving end, and in response to the signal of the first node, control the signal output by the driving signal output end; alternatively, the output module is used to receive the first level signal The first level signal at the receiving end, and in response to the signal at the third node, controls the signal output by the driving signal output end;
  • the voltage stabilizing module is used to receive the signal at the second node, and respond to the second signal received at the second clock signal end.
  • the clock signal controls the signal of the third node; among them, the first level signal is a low level signal, and the second level signal is a high level signal; when the signal output by the driving signal output terminal is a low level signal, the third level signal is a low level signal.
  • the potential of the signals at the three nodes is less than the potential of the first level signal received by the first level signal receiving end;
  • the node control module includes at least one transistor whose active layer is an oxide semiconductor; in the input module, the voltage stabilizing module and the output module At least one of the transistors includes at least one active layer of silicon.
  • the signal of the third node is controlled by the voltage stabilizing module, so that when the signal output by the driving signal output terminal is low level, the potential of the signal of the third node is lower than the low level potential received by the first level signal receiving terminal, and then Make the signal output by the drive signal output terminal be the low level received by the first level signal receiving end, to avoid when the signal of the third node is higher, the output module receives the first level signal from the first level signal receiving end, It cannot be transmitted to the control drive signal output end, thereby affecting the signal output and ensuring the display effect of the display panel.
  • the node control module includes oxide semiconductor transistors, compared to all low-temperature polysilicon transistors, the leakage of the first node can be improved, making the signal of the first node stable, stabilizing the output signal, and improving the display of the display panel. effect; and because the shift register combines oxide semiconductor transistors and low-temperature polysilicon transistors, the shift register can have strong driving capabilities and low power consumption. In addition, it has been verified that the shift register can effectively avoid the shortcomings of leakage of low-temperature polysilicon transistors; and when the threshold voltage offset of the low-temperature polysilicon transistor is large (threshold voltage offset ), the drive signal output end can still output a relatively stable waveform, providing a certain tolerance error for the process.
  • the gate drive circuit using the shift register has two functions: it can provide a light-emitting control signal to control the turning on or off of the light-emitting control transistor on the light-emitting branch, and it can also provide a control scanning signal. That is, the gate drive circuit can be either a light emission control drive circuit or a scan drive circuit. When both the light emission control drive circuit and the scan drive circuit are the gate drive circuits, the structures of the light emission control drive circuit and the scan drive circuit are: Similarly, by changing the input signal of the first-stage circuit, two different driving signals (light-emitting control signals or scanning signals) for the pixel circuit can be generated without changing the clock signal.
  • the clock signal lines can be reused, which can reduce the number of clock signal lines and facilitate the narrow-frame design of the display panel. , and can reduce the number of clock control modules in the display driver chip that provide clock signals for the clock signal line, and reduce the design cost of the display driver chip.
  • the node control module includes: a first control unit electrically connected to the first level signal receiving end, the first clock signal end, the second clock signal end, the first node and the second node. ;
  • the second control unit is electrically connected to the second level signal receiving end, the first node and the second node; the first control unit is used to receive the first level signal from the first level signal receiving end, and respond to the second The signal of the node, the first clock signal received by the first clock signal terminal and the second clock signal received by the second clock signal terminal control the signal of the first node; or, the second control unit is used to receive the second level signal.
  • the terminal receives the second level signal, and responds to the signal of the second node to control the signal of the first node.
  • the first node is controlled through an independent unit.
  • the first level signal is transmitted to the first node through the first control unit;
  • the first node needs a second level signal When the signal is flat, the second level signal is transmitted to the first node through the second control unit, thereby avoiding signal interference and making the signal of the first node more stable.
  • the first control unit includes at least one transistor whose active layer is an oxide semiconductor, such as a transistor with IGZO as the active layer.
  • the IGZO transistor has the advantage of small leakage current. Therefore, when the first control unit provides a low level to the first node, the signal of the first node can be ensured to be stable, thereby ensuring that the output signal of the driving signal output terminal is relatively stable.
  • the light-emitting control transistor in the pixel circuit When the signal output by the drive signal output terminal is a light-emitting control signal, the light-emitting control transistor in the pixel circuit is turned on when receiving a low level, and the display unit displays; when it is turned off when receiving a high level, the display unit does not display, that is, It is said that when the luminescence control signal output by the drive signal output terminal is at a high level, the luminescence control transistor is turned off and the display unit does not display; when the signal output by the drive signal output terminal is at a low level, the luminescence control transistor is turned on and the display unit displays; and because When the first control unit provides a low level to the first node, the luminescence control signal output by the drive signal output terminal is a high-level signal. Therefore, when the high-level signal output by the drive signal output terminal is stable, the luminescence in the pixel circuit can be guaranteed.
  • the control transistor can be completely cut off to avoid a bright screen.
  • the shift register further includes: a protection module located between the second node and the third node, and between the second node and the voltage stabilizing module, and receiving the first level signal. Terminal electrical connection; the protection module is used to prevent the signal from the third node from being transmitted to the second node to prevent the input module from being subject to high Vds bias.
  • the input module includes a first transistor; a gate of the first transistor is electrically connected to the second clock signal terminal, a first pole of the first transistor is electrically connected to the trigger signal input terminal, and a third terminal of the first transistor is electrically connected to the trigger signal input terminal.
  • the two poles are electrically connected to the second node.
  • the specific structure of the input module is not limited to this. Those skilled in the art can set it according to the actual situation, as long as the normal input of the input signal is ensured. When the input module includes only one transistor, the structure is simple.
  • the first control unit includes at least one transistor whose active layer is an oxide semiconductor
  • the first control unit includes a second transistor, a third transistor and a fourth transistor; the second transistor The gate of the second transistor is electrically connected to the first clock signal terminal, the first terminal of the second transistor is electrically connected to the first level signal receiving terminal, the second terminal of the second transistor, the gate of the fourth transistor and the third terminal of the third transistor are electrically connected.
  • the two poles are coupled to the fourth node; the gate of the third transistor is electrically connected to the second node; the first pole of the third transistor is electrically connected to the second clock signal terminal; the first pole of the fourth transistor is electrically connected to the first level signal The receiving end is electrically connected, and the second pole of the fourth transistor is electrically connected to the first node.
  • the specific structure of the input module is not limited to this, and those skilled in the art can set it according to actual conditions.
  • the third transistor and the fourth transistor is an oxide semiconductor.
  • transistor when the first control unit provides a low level to the first node, it can further ensure that the signal of the first node is stable, thereby ensuring that the light-emitting control signal output by the drive signal output terminal is relatively stable, avoiding The screen will turn on.
  • the second control unit includes at least one transistor whose active layer is an oxide semiconductor
  • the second control unit includes a fifth transistor; the gate of the fifth transistor is connected to the second node voltage. connection, the first pole of the fifth transistor is electrically connected to the second level signal receiving end, and the second pole of the fifth transistor is electrically connected to the first node.
  • the specific structure of the second control unit is not limited to this, and those skilled in the art can set it according to actual conditions. When the second control unit only includes one transistor, the structure is simple.
  • the protection module includes a sixth transistor; the first electrode of the sixth transistor is electrically connected to the second node, and the gate electrode of the sixth transistor is electrically connected to the first node.
  • the level signal receiving end is electrically connected, and the second pole of the sixth transistor is electrically connected to the third node and the voltage stabilizing module respectively.
  • the specific structure of the protection module is not limited to this, and those skilled in the art can set it according to actual conditions. When the protection module only includes one transistor, the structure is simple.
  • the voltage stabilizing module includes a seventh transistor and a first capacitor; the gate of the seventh transistor is electrically connected to the third node, the first pole of the seventh transistor is electrically connected to the first clock signal terminal, and the gate of the seventh transistor is electrically connected to the third node.
  • the second pole of the seven transistors is electrically connected to the second pole of the first capacitor, and the first pole of the first capacitor is electrically connected to the third node and the second pole of the sixth transistor respectively.
  • the seventh transistor and the first capacitor form a capacitive coupling pull-down structure, so that when the signal output by the driving signal output terminal is low level, the potential of the signal at the third node is lower than the low level potential received by the first level signal receiving terminal. , thereby causing the signal output by the driving signal output terminal to be the low level received by the first level signal receiving terminal.
  • the output module includes a second capacitor, an eighth transistor, and a ninth transistor; the gate of the eighth transistor and the first electrode of the second capacitor are both electrically connected to the first node, and the gate of the eighth transistor is electrically connected to the first node.
  • One pole and the second pole of the second capacitor are both electrically connected to the second level signal receiving terminal.
  • the second pole of the eighth transistor and the second pole of the ninth transistor are both electrically connected to the drive signal output terminal.
  • the ninth transistor is electrically connected to the driving signal output terminal.
  • the gate is electrically connected to the third node, and the first electrode of the ninth transistor is electrically connected to the first level signal receiving end.
  • the transistor whose active layer is an oxide semiconductor is an N-type transistor; the transistor whose active layer is silicon is a P-type transistor.
  • the combination of N-type transistors and P-type transistors will effectively reduce the number of shift registers.
  • the required number of thin film transistors makes the structure of the shift register simpler.
  • embodiments of the present application further provide a gate driving circuit, including N shift registers described in the first aspect cascaded with each other, N ⁇ 2.
  • the gate drive circuit has two functions: it can provide a light-emitting control signal to control the turning on or off of the light-emitting control transistor on the light-emitting branch, and it can also provide a control scanning signal. That is, the gate drive circuit can be either a light emission control drive circuit or a scan drive circuit. When both the light emission control drive circuit and the scan drive circuit are the gate drive circuits, the structures of the light emission control drive circuit and the scan drive circuit are: Similarly, by changing the input signal of the first-stage circuit, two different driving signals (light-emitting control signals or scanning signals) for the pixel circuit can be generated without changing the clock signal.
  • the clock signal lines can be reused, which can reduce the number of clock signal lines and facilitate the narrow-frame design of the display panel. , and can reduce the number of clock control modules in the display driver chip that provide clock signals for the clock signal line, and reduce the design cost of the display driver chip.
  • embodiments of the present application further provide a display panel, including at least one gate driving circuit described in the second aspect, which has all the effects of the gate driving circuit in the second aspect.
  • At least two gate drive circuits are included, one of which is a lighting control driving circuit, and the other gate driving circuit is a scanning driving circuit; a clock signal line electrically connected to the lighting control driving circuit Multiplexed as a clock signal line for the scan driver circuit.
  • embodiments of the present application further provide an electronic device, including the display panel as described in the third aspect, having all the effects of the gate driving circuit in the third aspect.
  • Figure 1 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • Figure 2 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • Figure 3 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present application.
  • Figure 4 is a schematic structural diagram of another display panel provided by an embodiment of the present application.
  • Figure 5 is a schematic structural diagram of a shift register provided by an embodiment of the present application.
  • Figure 6 is a schematic structural diagram of another shift register provided by an embodiment of the present application.
  • Figure 7 is a schematic structural diagram of another shift register provided by an embodiment of the present application.
  • Figure 8 is a schematic structural diagram of another shift register provided by an embodiment of the present application.
  • Figure 9 is a timing diagram of a shift register provided by an embodiment of the present application.
  • Figure 10 is a working process diagram of a shift register provided by an embodiment of the present application.
  • Figure 11 is a working process diagram of yet another shift register provided by an embodiment of the present application.
  • Figure 12 is a working process diagram of yet another shift register provided by an embodiment of the present application.
  • Figure 13 is a working process diagram of yet another shift register provided by an embodiment of the present application.
  • Figure 14 is a working process diagram of yet another shift register provided by an embodiment of the present application.
  • Figure 15 is a working process diagram of yet another shift register provided by an embodiment of the present application.
  • Figure 16 is a simulation comparison diagram between related technology and embodiments of the present application.
  • Figure 17 is another simulation comparison diagram between the related technology and the embodiment of the present application.
  • Figure 18 is a timing diagram of another shift register provided by an embodiment of the present application.
  • Figure 19 is a timing diagram of another shift register provided by an embodiment of the present application.
  • Figure 20 is another simulation comparison diagram between the related technology and the embodiment of the present application.
  • a and/or B can mean: A exists alone, A and B exist simultaneously, and they exist alone. B these three situations.
  • first and second in the description and claims of the embodiments of this application are used to distinguish different objects, rather than to describe a specific order of objects.
  • first target object, the second target object, etc. are used to distinguish different target objects, rather than to describe a specific order of the target objects.
  • multiple processing units refer to two or more processing units; multiple systems refer to two or more systems.
  • Embodiments of the present application provide an electronic device.
  • the electronic device provided by the embodiment of the present application may be a mobile phone, a tablet computer, a notebook computer, a personal digital assistant (PDA for short), a vehicle-mounted computer, a smart wearable device, or a smart home.
  • Equipment, etc. include electronic equipment such as display panels.
  • the embodiments of this application do not limit the specific form of the above-mentioned electronic equipment.
  • the electronic device is a mobile phone as an example.
  • a mobile phone 100 includes a display panel 10 , a rear case 20 and a middle frame 30 .
  • the display panel 10, the rear case 20 and the middle frame 30 may enclose a receiving cavity.
  • Structures such as a motherboard, batteries, and functional devices (not shown in the figure) are arranged in the accommodation cavity.
  • Functional devices include, for example, display driver chips and processors.
  • the processor sends corresponding signals to the display driver chip, so that the display driver chip drives the display panel 10 to display.
  • the material of the back shell 20 may include, for example, opaque materials such as plastic, plain leather, and fiberglass; it may also include light-transmitting materials such as glass.
  • the embodiment of the present application does not limit the material of the rear case 20 .
  • the display panel 10 includes, for example, a Liquid Crystal Display (LCD) panel, an Organic Light Emitting Diode (OLED) display panel, an LED display panel, etc.
  • the LED display panel includes, for example, a Micro-LED display panel, a Mini-LED display panel, and the like. LED display panel, etc.
  • the embodiment of the present application does not limit the type of the display panel 10 .
  • the following description takes the display panel 10 as an OLED display panel as an example.
  • the display panel 10 includes a display area AA and a non-display area NAA.
  • the non-display area NAA is, for example, arranged around the display area AA.
  • the display area AA of the display panel 10 is provided with a plurality of pixels 11 arranged in an array, a plurality of scan line groups 12 and a plurality of data lines 13 .
  • Each pixel 11 includes a pixel circuit 111 and a display unit 112 .
  • the plurality of data lines 13 correspond to the pixel circuits 111 in the plurality of columns of pixels 11 one-to-one, that is, the pixel circuits 111 in one column of pixels 11 correspond to one data line 13.
  • the plurality of scan line groups 12 correspond to the pixel circuits 111 of multiple rows of pixels 11 in a one-to-one manner, that is, the pixel circuits 111 in one row of pixels 11 correspond to one scan line group 12 .
  • the pixel circuit 111 includes, for example, 7T1C (7 transistors and 1 storage capacitor), that is, the pixel circuit 111 may include a driving transistor M1, a data writing transistor M2, a threshold compensation transistor M3, reset transistors M4 and M5, and a light emitting transistor. Control transistors M6 and M7, and storage capacitor Cst.
  • the specific structure of the pixel circuit 111 includes but is not limited to the above examples.
  • the pixel circuit 111 can also be arranged in other ways, as long as the display unit 112 can be driven to emit light.
  • the above-mentioned reset transistor M4 and threshold compensation transistor M3 are made of oxide semiconductor materials, such as indium gallium zinc oxide (IGZO), as active layer transistors; the driving transistor M1, the data writing transistor M2, and the reset transistor M5, light emission control transistors M6 and M7 are made of silicon, optionally polysilicon, such as low temperature polysilicon (Low Temperature Poly-Silicon, LTPS) material, as the active layer transistor, that is, the LTPS transistor and IGZO transistor are integrated on one substrate , forming a low temperature polycrystalline oxide (LTPO, Low Temperature Polycrystalline Oxide) display panel 10.
  • IGZO indium gallium zinc oxide
  • Low-temperature polysilicon transistors have the advantages of high carrier mobility, fast response, and low power consumption.
  • Oxide semiconductor transistors have the advantages of small leakage current. Therefore, when the pixel circuit 111 includes both LTPS material as an active layer transistor and IGZO When the material is used as a transistor in the active layer, it can ensure that the pixel circuit 111 has better performance.
  • the pixel circuit 111 also includes an initialization signal terminal Vref, a first power terminal PVDD, a second power terminal PVEE, a data signal terminal Data, a first scanning signal terminal Scan1, a second scanning signal terminal Scan2, a third scanning signal terminal Scan3, The fourth scanning signal terminal Scan4 and the lighting control signal terminal Emit.
  • the first pole of the light emitting control transistor M6 is electrically connected to the first power supply terminal PVDD
  • the first pole of the data writing transistor M2 is electrically connected to the data signal terminal Data
  • the gate of the data writing transistor M2 is electrically connected to the fourth scanning signal terminal Scan4.
  • the gate of the threshold compensation transistor M3 is electrically connected to the third scan signal terminal Scan3, and the first poles of the reset transistors M4 and M5 are electrically connected to the initialization signal terminal Vref respectively (the corresponding initialization signal terminals of the two can be the same or different ), the gate of the reset transistor M4 may be electrically connected to the first scan signal terminal Scan1, the gate of the reset transistor M5 may be electrically connected to the second scan signal terminal Scan2, and the gates of the light emitting control transistors M6 and M7 may be connected to the light emitting control transistors M6 and M7 respectively.
  • the signal terminal Emit is electrically connected, the light-emitting control transistor M7 is electrically connected to the anode of the first light-emitting element 112, and the cathode of the first light-emitting element 112 is electrically connected to the second power terminal PVEE.
  • each scan line group 12 includes a first scan signal line 121 , a second scan signal line 122 and a light emission control signal line 123 .
  • the pixel circuit 111 in a column of pixels 11 corresponds to one data line 13 , that is, the data signal terminal Data in the pixel circuit 111 of each pixel 11 in the same column is electrically connected to the same data line 13 .
  • the pixel circuit 111 in a row of pixels 11 corresponds to one scan line group 12, that is, the first scan signal terminal Scan1 in the pixel circuit 111 of each pixel 11 in the same row is electrically connected to the first scan signal line 121 corresponding to the row.
  • the same row The second scanning signal terminal Scan2 in the pixel circuit 111 of each pixel 11 is electrically connected to the second scanning signal line 122 corresponding to the row, and the third scanning signal terminal Scan3 in the pixel circuit 111 of each pixel 11 in the same row is electrically connected to other
  • the first scanning signal line 121 corresponding to the row (specific rows can be set by those skilled in the art according to the actual situation) is electrically connected, and the fourth scanning signal terminal Scan4 in the pixel circuit 111 of each pixel 11 in the same row is connected to other rows (specific rows).
  • FIG. 2 does not show that the third scanning signal terminal Scan3 in the pixel circuit 111 of each pixel 11 in the same row is electrically connected to the corresponding first scanning signal line 121 of other rows.
  • the fourth scanning signal terminal Scan4 in the pixel circuit 111 of each pixel 11 in the same row is electrically connected to the corresponding second scanning signal line 122 in other rows.
  • the pixel circuit 111 using the LTPO process usually requires three gate control signals.
  • One is the light-emitting control signal transmitted by the light-emitting control signal line 123, that is, the light-emitting control signal transmitted by the light-emitting control signal line 123 can control the light-emitting branch.
  • the lighting control transistors M6 and M7 are turned on or off; the second is the first scanning signal transmitted by the first scanning signal line 121, that is, the first scanning signal transmitted by the first scanning signal line 121 can control the reset transistor whose active layer is IGZO.
  • the M4 and the threshold compensation transistor M3 are turned on or off, that is, the first scanning signal transmitted by the first scanning signal line 121 corresponding to the row of the reset transistor M4 can control the turning on or off of the reset transistor M4, through the corresponding first scanning signal line 121 of other rows.
  • the first scanning signal transmitted by the scanning signal line 121 controls the turning on or off of the threshold compensation transistor M3;
  • the third is the second scanning signal transmitted by the second scanning signal line 122, that is, the second scanning signal transmitted by the second scanning signal line 122.
  • the reset transistor M5 and the data writing transistor M2 whose active layer is LTPS can be controlled to be turned on or off, that is, the second scan signal transmitted by the second scan signal line 122 corresponding to the row of the reset transistor M5 can control the reset transistor M5. Turning on or off, the second scanning signal transmitted through the second scanning signal line 122 corresponding to other rows controls the turning on or off of the data writing transistor M2.
  • the principle by which the pixel circuit 111 drives the display unit 112 to emit light based on the light emission control signal, the first scan signal, the second scan signal, etc. is similar to the principle of the 7T1C pixel circuit in the prior art that drives the display unit to emit light, and will not be described again here.
  • a drive circuit 14 is provided in the non-display area NAA of the display panel 10 , where the drive circuit 14 may include, for example, a first scan drive circuit, a second scan drive circuit and a light emission control drive circuit.
  • the first scan driving circuit includes a plurality of first scanning signal output terminals
  • the second scanning driving circuit includes a plurality of second scanning signal output terminals
  • the lighting control driving circuit includes a plurality of lighting control signal output terminals.
  • the plurality of first scanning signal output terminals of the first scan driving circuit are electrically connected to the plurality of first scanning signal lines 121 of the display area AA in a one-to-one correspondence, and the plurality of second scanning signal output terminals of the second scanning driving circuit are connected to the display area AA in a one-to-one correspondence.
  • the plurality of second scanning signal lines 122 of AA are electrically connected in a one-to-one correspondence, and the plurality of lighting control signal output terminals of the lighting control driving circuit are electrically connected in a one-to-one correspondence to the lighting control signal lines 123 of the display area AA.
  • the first scan driver circuit transmits the first scan signal to the first scan signal line 121 through the first scan signal output terminal
  • the second scan driver circuit transmits the second scan signal to the second scan signal line 122 through the second scan signal output terminal
  • the light-emitting control driving circuit transmits the light-emitting control signal to the light-emitting control signal line 123 through the light-emitting control signal output terminal.
  • the gate drive circuit has two functions. It can control the turning on or off of the light-emitting control transistors M6 and M7 on the light-emitting branch.
  • the light emission control signal can also provide a first scanning signal that controls the on or off of the reset transistor M4 and the threshold compensation transistor M3. That is, the gate drive circuit can be either a light emission control drive circuit or a first scan drive circuit.
  • the light emission control drive circuit and the first scan drive circuit are the gate drive circuit, the light emission control drive circuit and the first scan drive circuit A scan drive circuit has the same structure.
  • two different drive signals (light emitting control signal or first scan signal) for the pixel circuit can be generated without changing the clock signal.
  • the clock signal lines can be multiplexed. In this way, the number of clock signal lines can be reduced, which is beneficial to the narrow display panel.
  • the frame design can reduce the number of clock control modules in the display driver chip that provide clock signals for the clock signal line, and reduce the design cost of the display driver chip.
  • the gate drive circuit 141 includes N cascaded shift registers ASG.
  • N cascaded shift registers ASG.
  • it may include N shift registers ASG1 to ASGn, N ⁇ 2, and the specific value of N is Those skilled in the art can set it according to the actual situation, and there is no limitation here.
  • Each stage of the shift register ASG includes a first clock signal terminal CK1, a second clock signal terminal CK2, a trigger signal input terminal IN and a drive signal output terminal OUT. Except for the last stage shift register ASGn, the remaining shift registers ASG of each stage The drive signal output terminal OUT is electrically connected to the trigger signal input terminal IN of the adjacent next-stage shift register ASG, and the trigger signal input terminal IN of the first-stage shift register ASG1 receives the trigger signal line (not shown in Figure 4 out) trigger signal STV.
  • the shift register ASG controls the light emission through the drive signal output terminal OUT according to the first clock signal input from the first clock signal terminal CK1, the second clock signal input from the second clock signal terminal CK2 and the trigger signal STV input from the trigger signal input terminal IN.
  • the signal line 123 sends a light emission control signal or a first scanning signal to the first scanning signal line 121 .
  • the display panel 10 also includes a first clock signal line CKL1 and a second clock signal line CKL2 located in the non-display area NAA.
  • the first clock signal terminal CK1 of the odd-numbered stage shift register ASG is electrically connected to the first clock signal line CKL1
  • the second clock signal terminal CK2 of the odd-numbered stage shift register ASG is electrically connected to the second clock signal line CKL2
  • the first clock signal terminal CK1 of the register ASG is electrically connected to the second clock signal line CKL2
  • the second clock signal terminal CK2 of the even-stage shift register ASG is electrically connected to the first clock signal line CKL1.
  • the first clock signal terminal CK1 of the first-stage shift register ASG1 and the third-stage shift register ASG3 is electrically connected to the first clock signal line CKL1.
  • the second clock signal terminal CK2 of the bit register ASG3 is electrically connected to the second clock signal line CKL2, and the first clock signal terminal CK1 of the second-stage shift register ASG2 and the fourth-stage shift register ASG4 is electrically connected to the second clock signal line CKL2.
  • the second clock signal terminal CK2 of the second-stage shift register ASG2 and the fourth-stage shift register ASG4 is electrically connected to the first clock signal line CKL1.
  • each stage of the shift register ASG also includes: a first level signal receiving end VGL, a second level signal receiving end VGH, a node control module 142, an input module 143, a voltage stabilizing module 144 and an output module 145.
  • the node control module 142 is electrically connected to the first level signal receiving terminal VGL, the second level signal receiving terminal VGH, the first clock signal terminal CK1, the second clock signal terminal CK2, the first node N1 and the second node N2.
  • the input module 143 is electrically connected to the second clock signal terminal CK2, the trigger signal input terminal IN and the second node N2.
  • the voltage stabilizing module 144 is electrically connected to the second node N2, the second clock signal terminal CK2 and the third node N3.
  • the output module 145 is electrically connected to the first level signal receiving terminal VGL, the second level signal receiving terminal VGH, the first node N1, the third node N3 and the driving signal output terminal OUT.
  • the input module 143 is configured to receive the input signal STV from the trigger signal input terminal IN, and to control the signal of the second node N2 in response to the second clock signal CKV2 received by the second clock signal terminal CK2.
  • the node control module 142 is used to receive the first level signal from the first level signal receiving terminal VGL and the second level signal received from the second level signal receiving terminal VGH, and respond to the signal of the second node N2, the first level signal
  • the first clock signal CKV1 received by the clock signal terminal CK1 and the second clock signal CKV2 received by the second clock signal terminal CK2 control the signal of the first node N1.
  • the output module 145 is used to receive the second level signal received by the second level signal receiving terminal VGH, and in response to the signal of the first node N1, control the driving signal output terminal OUT to output the lighting control signal or the first scanning signal; or, The output module 145 is configured to receive the first level signal from the first level signal receiving terminal VGL, and in response to the signal of the third node N3, control the driving signal output terminal OUT to output the lighting control signal or the first scanning signal.
  • the voltage stabilizing module 144 is used to receive the signal of the second node N2 and control the signal of the third node N3 in response to the second clock signal CKV2 received by the second clock signal terminal CK2; wherein the first level signal is low level. signal, the second level signal is a high level signal; when the signal output by the driving signal output terminal OUT is a low level signal, the potential of the signal at the third node N3 is smaller than the first level signal received by the first level signal receiving terminal VGL. The potential of the level signal.
  • the node control module 142 includes at least one transistor, which is a transistor using an oxide semiconductor material, such as IGZO, as an active layer.
  • At least one of the input module 143, the voltage stabilizing module 144 and the output module 145 includes at least one transistor, which is a transistor with silicon, optionally polysilicon, such as LTPS, as the active layer.
  • the input signal STV is received through the input module 143 and the signal of the second node N2 is controlled in response to the second clock signal CKV2.
  • the first level signal and the second level signal are received through the node control module 142, and the signal of the second node N2 is controlled in response to the second clock signal CKV2.
  • the signal of the second node N2, the first clock signal CKV1 and the second clock signal CKV2 control the signal of the first node N1, receive the second level signal through the output module 145, and control the output in response to the signal of the first node N1 signal; or, receive the first level signal through the output module 145, and control the output signal in response to the signal of the third node N3.
  • the signal of the third node N3 is controlled through the voltage stabilizing module 144 so that when the signal output by the driving signal output terminal OUT is low level, the potential of the signal of the third node N3 is low.
  • the low-level potential received by the first-level signal receiving terminal VGL causes the signal output by the driving signal output terminal OUT to be the low-level received by the first-level signal receiving terminal VGL, thus preventing the output module 145 from including a transistor. Due to the threshold loss of the transistor, the first level signal received by the output module 145 from the first level signal receiving terminal VGL cannot be transmitted to the control driving signal output terminal OUT, thereby affecting the output of the signal.
  • the node control module 142 includes IGZO transistors, compared with all LTPS transistors, the leakage of the first node N1 can be improved, so that the signal of the first node N1 is stable, and the output signal is stabilized; and because the shift register ASG Combining IGZO transistors and LTPS transistors, the shift register ASG can have strong driving capabilities and low power consumption.
  • the IGZO transistor included in the node control module 142 is an N-type IGZO transistor
  • the LTPS transistor included in at least one of the input module 143, the voltage stabilizing module 144 and the output module 145 is a P-type LTPS transistor.
  • the combination of N-type transistors and P-type transistors will effectively reduce the number of thin-film transistors required for the shift register ASG, making the structure of the shift register ASG simpler and conducive to realizing a narrower frame panel design.
  • each stage of the shift register ASG also includes: a protection module 146 located between the second node N2 and the third node N3, and located between the second node N2 and the voltage stabilizing module 144 between them, and is electrically connected to the first level signal receiving terminal VGL.
  • the protection module 146 is used to prevent the signal of the third node N3 from being transmitted to the second node N2, that is, to act as a pinch-off to prevent the input module 143 from being biased by high Vds.
  • the node control module 142 includes a first control unit 1421 and a second control unit 1422 .
  • the first control unit 1421 is electrically connected to the first level signal receiving terminal VGL, the first clock signal terminal CK1, the second clock signal terminal CK2, the first node N1 and the second node N2.
  • the second control unit 1422 is electrically connected to the second level signal receiving terminal VGH, the first node N1 and the second node N2.
  • the first control unit 1421 is used to receive the first level signal from the first level signal receiving terminal VGL, and respond to the signal of the second node N2, the first clock signal CKV1 and the second clock received by the first clock signal terminal CK1.
  • the second clock signal CKV2 received by the signal terminal CK2 controls the signal of the first node N1.
  • the second control unit 1422 is configured to receive the second level signal received by the second level signal receiving terminal VGH, and in response to the signal of the second node N2, control the signal of the first node N1. That is to say, the first level signal may be provided to the first node N1 through the first control unit 1421, and the second level signal may be provided to the first node N1 through the second control unit 1422.
  • the first level signal is transmitted to the first node N1 through the first control unit 1421; when the first node N1 needs a second level signal, the first level signal is transmitted to the first node N1 through the first control unit 1421.
  • the second control unit 1422 transmits the second level signal to the first node N1.
  • the output module 145 outputs the second level signal received by the second level signal receiving terminal VGH through the driving signal output terminal OUT; when the first node N1 is the second level signal, When the signal is flat, the output module 145 cannot output the second level signal received by the second level signal receiving terminal VGH through the driving signal output terminal OUT.
  • the first control unit 1421 includes at least one transistor, which is a transistor using an oxide semiconductor material, such as IGZO, as an active layer. Since the IGZO transistor has the advantage of small leakage current, when the first control unit 1421 provides a low level to the first node N1, the signal of the first node N1 can be ensured to be stable, thereby ensuring that the output signal of the driving signal output terminal OUT is relatively stable.
  • IGZO oxide semiconductor material
  • the display Unit 112 displays; when receiving a high level, it is cut off, and the display unit 112 does not display. That is to say, when the lighting control signal output by the driving signal output terminal OUT is a high level, the lighting control transistors M6 and M7 are cut off, and the display unit 112 does not display.
  • the driving signal output terminal OUT When the signal output by the driving signal output terminal OUT is low level, the light-emitting control transistors M6 and M7 are turned on, and the display unit 112 displays; and because the first control unit 1421 provides a low level to the first node N1, the driving signal output terminal OUT
  • the output light-emitting control signal is a high-level signal. Therefore, when the high-level signal output by the driving signal output terminal OUT is stable, it can ensure that the light-emitting control transistors M6 and M7 in the pixel circuit 111 can be completely cut off, avoiding the problem of bright screen. occur.
  • the input module 143 includes a first transistor T1 , the gate of the first transistor T1 is electrically connected to the second clock signal terminal CK2 , and the first pole of the first transistor T1 is connected to the trigger signal input.
  • the terminal IN is electrically connected, and the second pole of the first transistor T1 is electrically connected to the second node N2.
  • the first transistor T1 is made of silicon, for example, polysilicon, for example, LTPS, as a transistor of the active layer.
  • first electrode of the first transistor T1 may be the source electrode of the first transistor T1, and the second electrode of the first transistor T1 may be the drain electrode of the first transistor T1; or, the first electrode of the first transistor T1 may be the drain electrode of the first transistor T1.
  • the first electrode of the first transistor T1 may be the drain electrode of the first transistor T1, and the second electrode of the first transistor T1 may be the source electrode of the first transistor T1.
  • the first control unit 1421 includes a second transistor T2, a third transistor T3, and a fourth transistor T4.
  • the gate of the second transistor T2 is electrically connected to the first clock signal terminal CK1
  • the first electrode of the second transistor T2 is electrically connected to the first level signal receiving terminal VGL
  • the gate electrode of the third transistor T3 and the second electrode of the third transistor T3 are coupled to the fourth node N4.
  • the gate electrode of the third transistor T3 is electrically connected to the second node N2, and the first electrode of the third transistor T3 is electrically connected to the second clock signal terminal CK2.
  • the first electrode of the fourth transistor T4 is electrically connected to the first level signal receiving terminal VGL, and the second electrode of the fourth transistor T4 is electrically connected to the first node N1.
  • the second transistor T2, the third transistor T3, and the fourth transistor T4 are, for example, transistors using an oxide semiconductor material, such as IGZO, as the active layer.
  • the second control unit 1422 includes a fifth transistor T5.
  • the gate of the fifth transistor T5 is electrically connected to the second node N2, the first electrode of the fifth transistor T5 is electrically connected to the second level signal receiving terminal VGH, and the second electrode of the fifth transistor T5 is electrically connected to the first node N1. .
  • the protection module 146 includes a sixth transistor T6.
  • the first electrode of the sixth transistor T6 is electrically connected to the second node N2, the gate electrode of the sixth transistor T6 is electrically connected to the first level signal receiving terminal VGL, and the second electrode of the sixth transistor T6 is respectively connected to the third node N3 and the third node N2.
  • the voltage stabilizing module 144 is electrically connected.
  • the sixth transistor T6 is made of silicon, for example, polysilicon, for example, LTPS, as an active layer transistor.
  • the voltage stabilizing module 144 includes a seventh transistor T7 and a first capacitor C1.
  • the gate of the seventh transistor T7 is electrically connected to the third node N3, the first pole of the seventh transistor T7 is electrically connected to the first clock signal terminal CK1, and the second pole of the seventh transistor T7 is electrically connected to the second pole of the first capacitor C1. Electrically connected, the first pole of the first capacitor C1 is electrically connected to the third node N3 and the second pole of the sixth transistor T6 respectively.
  • the seventh transistor T7 is made of silicon, for example, polysilicon, for example, LTPS, as an active layer transistor.
  • the output module 145 includes a second capacitor C2, an eighth transistor T8, and a ninth transistor T9.
  • the gate electrode of the eighth transistor T8 and the first electrode of the second capacitor C2 are both electrically connected to the first node N1.
  • the first electrode of the eighth transistor T8 and the second electrode of the second capacitor C2 are both connected to the second level signal.
  • terminal VGH is electrically connected
  • the second pole of the eighth transistor T8 and the second pole of the ninth transistor T9 are both electrically connected to the drive signal output terminal OUT
  • the gate of the ninth transistor T9 is electrically connected to the third node N3, and the ninth transistor T9 is electrically connected to the third node N3.
  • the first pole of T9 is electrically connected to the first level signal receiving terminal VGL.
  • the eighth transistor T8 and the ninth transistor T9 are both made of silicon, for example, polysilicon, such as LTPS, as active layer transistors.
  • the structure of the gate driving circuit is introduced in detail above.
  • the working process when the gate driving circuit is a light emission control driving circuit and the working process when the gate driving circuit is a first scan driving circuit are described below. introduce.
  • FIG. 9 shows a timing diagram of each signal in the shift register when the gate drive circuit is a light emission control drive circuit.
  • the following describes the working process of the shift register shown in Figure 8 in conjunction with the timing diagram of each signal in the shift register when the gate drive circuit is a light-emitting control drive circuit.
  • the timing of signals in shift registers with other structures is the same as This is basically the same and will not be repeated here.
  • the second transistor T2, the third transistor T3 and the fourth transistor T4 are N-type IGZO transistors, and the first transistor T1, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8 and the ninth transistor are
  • the transistor T9 is a P-type LTPS transistor, and the first level signal received by the first level signal receiving terminal VGL is -7V, and the second level signal received by the second level signal receiving terminal VGH is 7V, for example.
  • the CKV1 received by the first clock signal terminal CK1 changes from low level to high level
  • the CKV2 received by the second clock signal terminal CK2 changes from high level.
  • the first transistor T1 is turned on
  • the sixth transistor T6 is turned on
  • the high level of the input signal STV received by the trigger signal input terminal IN is written into the third node N3.
  • the third node N3 is pulled high, and the ninth transistor T9 is closed.
  • the fifth transistor T5 is turned off, the third transistor T3 is turned on, and the first node N1 cannot be set high through the fifth transistor T5.
  • the high level of CKV1 turns on the second transistor T2, and the third transistor T3 transmits the low level of CKV2 to the fourth node N4. Then the fourth node N4 is in a low level state at this time, and the fourth transistor T4 is turned off.
  • the first node N1 still maintains a high level. Due to the holding effect of the second capacitor C2, the lighting control signal output by the driving signal output terminal OUT is still at a low level at this time.
  • the CKV1 received by the first clock signal terminal CK1 changes from high level to low level
  • the CKV2 received by the second clock signal terminal CK2 changes from high level to low level.
  • the low level becomes high level
  • the first transistor T1 and the second transistor T2 are turned off.
  • the third transistor T3 transmits the high level of CKV2 received by the second clock signal terminal CK2 to the fourth node N4.
  • the fourth transistor T4 is turned on, the first node N1 is pulled low, the eighth transistor T8 is turned on, and the driving signal output terminal The lighting control signal output by OUT is high level.
  • the third node N3 still maintains a high level
  • the ninth transistor T9 is turned off.
  • the CKV1 received by the first clock signal terminal CK1 changes from low level to high level
  • the CKV2 received by the second clock signal terminal CK2 changes from high level. becomes low level
  • the first transistor T1 is turned on
  • the sixth transistor T6 is turned on
  • the high level of the input signal STV received by the trigger signal input terminal IN is written into the third node N3.
  • the third node N3 is pulled high, and the ninth transistor T9 is turned off.
  • the fifth transistor T5 is turned off, the third transistor T3 is turned on, and the first node N1 cannot be set high through the fifth transistor T5.
  • the high level of CKV1 turns on the second transistor T2, and the third transistor T3 transmits the low level of CKV2 to the fourth node N4. Then the fourth node N4 is in a low level state at this time, and the fourth transistor T4 is turned off. Due to the holding effect of the second capacitor C2, the first node N1 still maintains a low level, the eighth transistor T8 is turned on, and the light-emitting control signal output by the driving signal output terminal OUT maintains a high level.
  • the CKV1 received by the first clock signal terminal CK1 changes from high level to low level
  • the CKV1 received by the second clock signal terminal CK2 changes from high level to low level
  • CKV2 changes from low level to high level
  • the first transistor T1 and the second transistor T2 are turned off.
  • the third transistor T3 transmits the high level of CKV2 received by the second clock signal terminal CK2 to the fourth node N4.
  • the fourth transistor T4 is turned on, the first node N1 is pulled low, the eighth transistor T8 is turned on, and the driving signal output terminal The lighting control signal output by OUT is high level.
  • the third node N3 still maintains a high level
  • the ninth transistor T9 is turned off.
  • the CKV1 received by the first clock signal terminal CK1 changes from low level to high level
  • the CKV2 received by the second clock signal terminal CK2 changes from high level.
  • low level the first transistor T1 is turned on
  • the sixth transistor T6 is turned on
  • the low level of the input signal STV received by the trigger signal input terminal IN is written into the third node N3, the third node N3 is pulled low, and the ninth transistor T9 be opened.
  • the third transistor T3 is turned off, the second transistor T2 is turned on, the fourth node N4 is low level, and the fourth transistor T4 is turned off.
  • the low level of the second node N2 turns on the fifth transistor T5, the first node N1 is pulled high, the eighth transistor T8 is turned off, and the lighting control signal output by the driving signal output terminal OUT is low level.
  • the CKV1 received by the first clock signal terminal CK1 changes from high level to low level
  • the CKV2 received by the second clock signal terminal CK2 changes from low level to high level.
  • the first transistor T1 and the second transistor T2 are turned off.
  • the third node N3 remains low
  • the seventh transistor T7 is turned on. Due to the threshold loss of the ninth transistor T9, the ninth transistor T9 cannot completely output the lowest level.
  • the seventh transistor T7 and the first capacitor C1 pull the third node N3 to a level lower than the first level signal receiving terminal VGL.
  • the ninth transistor T9 can output the low level received by the first-level signal receiving terminal VGL, that is, ensuring that the light-emitting control signal output by the driving signal output terminal OUT is the first-level signal receiving terminal VGL. Received low level.
  • the signal of the third node N3 is controlled by the seventh transistor T7 and the first capacitor C1, so that when the lighting control signal output by the driving signal output terminal OUT is low level, the potential of the signal of the third node N3 is lower than the first level signal.
  • the low-level potential received by the receiving terminal VGL causes the lighting control signal output by the driving signal output terminal OUT to be the low-level signal received by the first-level signal receiving terminal VGL, thus preventing the third node N3 from causing the The low level received by the nine-transistor T9 from the first level signal receiving terminal VGL cannot be transmitted to the control driving signal output terminal OUT, thereby affecting the output of the lighting control signal.
  • the first node N1 is provided with the first control unit 1421.
  • the signal of the first node N1 can be ensured to be stable, thereby ensuring that the lighting control signal output by the driving signal output terminal OUT is relatively stable, thus avoiding the occurrence of a bright screen.
  • the shift register ASG since the shift register ASG combines N-type transistors and P-type transistors, the number of thin film transistors required for the shift register ASG is effectively reduced, that is, the shift register ASG only includes 9 transistors and 2 capacitors, and the structural unit , the number of components is small, which is conducive to realizing panel design with narrower borders.
  • the shift register ASG since the shift register ASG combines IGZO transistors and LTPS transistors, the shift register ASG can have strong driving capabilities and low power consumption. And it has been proven that this gate drive circuit can effectively avoid the shortcomings of leakage of LTPS transistors.
  • the threshold voltage of the LTPS transistor is easily affected by the external electric field, the threshold voltage shifts, thereby affecting the signal output of the drive signal output terminal OUT. It has been verified that the gate drive circuit including the IGZO transistor provided by the embodiment of the present application has a large threshold voltage offset of the LTPS transistor (threshold voltage offset ), the drive signal output terminal OUT can still output a relatively stable waveform, providing a certain tolerance error for the process.
  • Figures 16 and 17 both show comparative simulation diagrams between the related technology and the embodiments of the present application, in which the abscissa is time and the ordinate is the signal output by the driving signal output terminal OUT during simulation.
  • the four simulation results in Figure 16 are as follows from top to bottom: when the threshold voltage of the LTPS transistor of the related technology deviates from 0V, the signal at the driving signal output terminal OUT; when the threshold voltage of the LTPS transistor of the related technology deviates from -2.5V , the signal of the driving signal output terminal OUT; when the threshold voltage of the LTPS transistor in the embodiment of the present application deviates from 0V, the signal of the driving signal output terminal OUT; when the threshold voltage of the LTPS transistor in the embodiment of the present application deviates from -2.5V, The signal driving the signal output terminal OUT.
  • the four simulation results in Figure 17 are as follows from top to bottom: when the threshold voltage of the LTPS transistor of the related technology deviates from 0V, the signal at the driving signal output terminal OUT; when the threshold voltage of the LTPS transistor of the related technology deviates from 2.5V, The signal at the driving signal output terminal OUT; when the threshold voltage of the LTPS transistor in the embodiment of the present application deviates from 0V, the signal at the driving signal output terminal OUT; when the threshold voltage of the LTPS transistor in the embodiment of the present application deviates from 2.5V, the driving signal The signal of the output terminal OUT.
  • the gate drive circuit including the IGZO transistor provided by the embodiment of the present application has an offset of LTPS threshold voltage. At this time, the circuit can still output a relatively stable waveform as a light-emitting control drive circuit, providing a certain tolerance error for the process.
  • the shift register ASG of the light emission control drive circuit supports pulse width modulation.
  • the STV signal pulse width is 3.5 clock cycles
  • the light-emitting control signal output by the driving signal output terminal OUT is also 3.5 clock cycles.
  • FIG. 19 shows a timing diagram of each signal in the shift register when the gate driving circuit is the first scan driving circuit.
  • the pulse width of the input signal STV is only half the period of the second clock signal CKV2.
  • the following describes the working process of the shift register shown in Figure 8 in conjunction with the timing diagram of each signal in the shift register when the gate drive circuit is the first scan drive circuit.
  • the timing of signals in shift registers with other structures is explained below. This is basically the same and will not be repeated here.
  • the second transistor T2 the third transistor T3 and the fourth transistor T4 are N-type IGZO transistors
  • the first transistor T1 the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8 and the ninth transistor
  • the transistor T9 is a P-type LTPS transistor, and the first level signal received by the first level signal receiving terminal VGL is -7V, and the second level signal received by the second level signal receiving terminal VGH is 7V, for example.
  • the CKV1 received by the first clock signal terminal CK1 changes from low level to high level
  • the CKV2 received by the second clock signal terminal CK2 changes from high level.
  • the first transistor T1 is turned on
  • the sixth transistor T6 is turned on
  • the high level of the input signal STV received by the trigger signal input terminal IN is written into the third node N3.
  • the third node N3 is pulled high, and the ninth transistor T9 is closed.
  • the fifth transistor T5 is turned off, the third transistor T3 is turned on, and the first node N1 cannot be set high through the fifth transistor T5.
  • the high level of CKV1 turns on the second transistor T2, and the third transistor T3 transmits the low level of CKV2 to the fourth node N4. Then the fourth node N4 is in a low level state at this time, and the fourth transistor T4 is turned off.
  • the first node N1 still maintains a high level. Due to the holding effect of the second capacitor C2, the lighting control signal output by the driving signal output terminal OUT is still at a low level at this time.
  • the CKV1 received by the first clock signal terminal CK1 changes from high level to low level
  • the CKV2 received by the second clock signal terminal CK2 changes from high level to low level.
  • the low level becomes high level
  • the first transistor T1 and the second transistor T2 are turned off.
  • the third transistor T3 transmits the high level of CKV2 received by the second clock signal terminal CK2 to the fourth node N4.
  • the fourth transistor T4 is turned on, the first node N1 is pulled low, the eighth transistor T8 is turned on, and the driving signal output terminal The lighting control signal output by OUT is high level.
  • the third node N3 still maintains a high level
  • the ninth transistor T9 is turned off.
  • the CKV1 received by the first clock signal terminal CK1 changes from low level to high level
  • the CKV2 received by the second clock signal terminal CK2 changes from high level.
  • low level the first transistor T1 is turned on
  • the sixth transistor T6 is turned on
  • the low level of the input signal STV received by the trigger signal input terminal IN is written into the third node N3, the third node N3 is pulled low, and the ninth transistor T9 be opened.
  • the third transistor T3 is turned off, the second transistor T2 is turned on, the fourth node N4 is low level, and the fourth transistor T4 is turned off.
  • the low level of the second node N2 turns on the fifth transistor T5, the first node N1 is pulled high, the eighth transistor T8 is turned off, and the lighting control signal output by the driving signal output terminal OUT is low level.
  • the CKV1 received by the first clock signal terminal CK1 changes from high level to low level
  • the CKV2 received by the second clock signal terminal CK2 changes from low level to high level.
  • the first transistor T1 and the second transistor T2 are turned off.
  • the third node N3 remains low
  • the seventh transistor T7 is turned on. Due to the threshold loss of the ninth transistor T9, the ninth transistor T9 cannot completely output the lowest level.
  • the seventh transistor T7 and the first capacitor C1 pull the third node N3 to a level lower than the first level signal receiving terminal VGL.
  • the ninth transistor T9 can output the low level received by the first-level signal receiving terminal VGL, that is, ensuring that the light-emitting control signal output by the driving signal output terminal OUT is the first-level signal receiving terminal VGL. Received low level.
  • the signal of the third node N3 is controlled by the seventh transistor T7 and the first capacitor C1, so that when the first scanning signal output by the driving signal output terminal OUT is low level, the potential of the signal of the third node N3 is lower than the first level.
  • the low-level potential received by the signal receiving terminal VGL causes the first scan signal output by the driving signal output terminal OUT to be the low-level received by the first-level signal receiving terminal VGL, thus preventing the signal from being generated when the third node N3 is high.
  • the low level received by the ninth transistor T9 from the first level signal receiving terminal VGL cannot be transmitted to the control driving signal output terminal OUT, thereby affecting the output of the first scanning signal.
  • the first node N1 is provided with the first control unit 1421.
  • the signal of the first node N1 can be ensured to be stable, thereby ensuring that the first scanning signal output by the driving signal output terminal OUT is relatively stable, and ensuring the normal operation of the pixel circuit 111.
  • the shift register ASG since the shift register ASG combines N-type transistors and P-type transistors, the number of thin film transistors required for the shift register ASG is effectively reduced, that is, the shift register ASG only includes 9 transistors and 2 capacitors, and the structural unit , the number of components is small, which is conducive to realizing panel design with narrower borders.
  • the shift register ASG since the shift register ASG combines IGZO transistors and LTPS transistors, the shift register ASG can have strong driving capabilities and low power consumption. And it has been proven that this gate drive circuit can effectively avoid the shortcomings of leakage of LTPS transistors.
  • the threshold voltage of the LTPS transistor is easily affected by the external electric field, the threshold voltage shifts, thereby affecting the signal output of the drive signal output terminal OUT. It has been verified that the gate drive circuit including the IGZO transistor provided by the embodiment of the present application has a large threshold voltage offset of the LTPS transistor (threshold voltage offset ), the drive signal output terminal OUT can still output a relatively stable waveform, providing a certain tolerance error for the process.
  • Figure 20 shows a comparative simulation diagram between the related technology and the embodiment of the present application, in which the abscissa is time and the ordinate is the signal output by the driving signal output terminal OUT during simulation.
  • the four simulation results in Figure 20 are as follows from top to bottom: when the threshold voltage of the LTPS transistor of the related technology deviates from 0V, the signal at the driving signal output terminal OUT; when the threshold voltage of the LTPS transistor of the related technology deviates from -2.5V , the signal of the driving signal output terminal OUT; when the threshold voltage of the LTPS transistor in the embodiment of the present application deviates from 0V, the signal of the driving signal output terminal OUT; when the threshold voltage of the LTPS transistor in the embodiment of the present application deviates from -2.5V, The signal driving the signal output terminal OUT.
  • the gate drive circuit including the IGZO transistor provided by the embodiment of the present application has an offset of LTPS threshold voltage.
  • the circuit as the first scan driving circuit can still output a relatively stable waveform, providing a certain tolerance error for the process.
  • the shift register ASG of the first scan driving circuit supports pulse width modulation.

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Abstract

移位寄存器（ASG）、栅极驱动电路（141）、显示面板（10）及电子设备。移位寄存器（ASG）包括节点控制模块（142），与接收低电平的第一电平信号接收端（VGL）、接收高电平的第二电平信号接收端（VGH）、第一时钟信号端（CK1）、第二时钟信号端（CK2）、第一节点（N1）、第二节点（N2）电连接；输入模块（143），与第二时钟信号端（CK2）、触发信号输入端（IN）和第二节点（N2）电连接；稳压模块（144），与第二节点（N2）、第三节点（N3）、第一时钟信号端（CK1）电连接；输出模块（145），与第一电平信号接收端（VGL）、第二电平信号接收端（VGH）、驱动信号输出端（OUT）和第一节点（N1）、第三节点（N3）电连接；当驱动信号输出端（OUT）输出的信号为低电平时，第三节点（N3）的信号的电位小于第一电平信号接收端（VGL）接收的低电平的电位；节点控制模块（142）包括至少一个有源层为氧化物半导体的晶体管；输入模块（143）、稳压模块（144）和输出模块（145）中的至少一者中包括至少一个有源层为硅的晶体管。

Description

移位寄存器、栅极驱动电路、显示面板及电子设备
本申请要求于2022年04月27日提交中国国家知识产权局、申请号为202210449955.X、申请名称为“移位寄存器、栅极驱动电路、显示面板及电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种移位寄存器、栅极驱动电路、显示面板及电子设备。
背景技术
随着显示技术的不断发展，越来越多具有显示功能的电子设备被广泛应用于人们的日常生活及工作当中，为人们的日常生活及工作带来了巨大的便利。
电子设备实现显示功能的主要部件是显示面板。显示面板中的驱动电路根据时钟信号线发送的时钟信号输出驱动信号至像素阵列中的像素电路，控制像素阵列进行画面显示。
随着显示精度的不断提升，对像素电路的阈值补偿提出了更高的要求，一个像素电路中通常需要多个不同的驱动信号。由于每个驱动信号由各自的驱动电路产生，而每个驱动电路都会对应各自的时钟信号线，这样，就会需要较多的时钟信号线以及显示驱动芯片需要较多的为时钟信号线提供时钟信号的时钟控制模块。然而，较多的时钟信号线不利于显示面板的窄边框设计，较多的时钟控制模块增加驱动显示芯片的设计成本。此外，驱动电路一般由多个晶体管组成，晶体管的稳定性出现偏差经常会导致电路逻辑出现错误，最终导致驱动异常。所以，需要一种结构简单、且稳定性较高的电路架构。
发明内容
为了解决上述技术问题，本申请提供一种移位寄存器、栅极驱动电路、显示面板及电子设备。
第一方面，本申请实施例提供一种移位寄存器，该移位寄存器包括节点控制模块，与第一电平信号接收端、第二电平信号接收端、第一时钟信号端、第二时钟信号端、第一节点和第二节点电连接；输入模块，与第二时钟信号端、触发信号输入端和第二节点电连接；稳压模块，与第二节点、第二时钟信号端和第三节点电连接；输出模块，与第一电平信号接收端、第二电平信号接收端、第一节点、第三节点和驱动信号输出端电连接；输入模块用于接收触发信号输入端的输入信号，并响应于第二时钟信号端接收的第二时钟信号而控制第二节点的信号；节点控制模块用于接收第一电平信号接收端接收的第一电平信号和第二电平信号接收端接收的第二电平信号，并响应于第二节点的信号、第一时钟信号端接收的第一时钟信号和第二时钟信号端接收的第二时钟信号，控制第一 节点的信号；输出模块用于接收第二电平信号接收端接收的第二电平信号，并响应于第一节点的信号，控制驱动信号输出端输出的信号；或者，输出模块用于接收第一电平信号接收端的第一电平信号，并响应于第三节点的信号，控制驱动信号输出端输出的信号；稳压模块用于接收第二节点的信号，并响应于第二时钟信号端接收的第二时钟信号，控制第三节点的信号；其中，第一电平信号为低电平信号，第二电平信号为高电平信号；当驱动信号输出端输出的信号为低电平信号时，第三节点的信号的电位小于第一电平信号接收端接收的第一电平信号的电位；节点控制模块包括至少一个有源层为氧化物半导体的晶体管；输入模块、稳压模块和输出模块中的至少一者中包括至少一个有源层为硅的晶体管。
通过稳压模块控制第三节点的信号，使得当驱动信号输出端输出的信号为低电平时，第三节点的信号的电位低于第一电平信号接收端接收的低电平的电位，进而使得驱动信号输出端输出的信号为第一电平信号接收端接收的低电平，避免当第三节点的信号较高，输出模块从第一电平信号接收端接收的第一电平信号，无法传输至控制驱动信号输出端，进而影响信号的输出，保证显示面板的显示效果。此外，由于节点控制模块包括氧化物半导体的晶体管，相比于全部为低温多晶硅晶体管，可以改善第一节点的漏电，使得第一节点的信号稳定，进行使得输出的信号稳定，提高显示面板的显示效果；且由于移位寄存器结合了氧化物半导体的晶体管和低温多晶硅晶体管，因此，可以使得移位寄存器具有较强的驱动能力和低功耗等特点。此外，经验证，该移位寄存器可以有效规避低温多晶硅晶体管漏电的缺点；且当低温多晶硅晶体管的阈值电压偏移量较大(阈值电压偏移
Figure PCTCN2023070297-appb-000001
)时，驱动信号输出端仍旧可以输出比较稳定的波形，为工艺提供一定的容限误差。此外，采用该移位寄存器的栅极驱动电路具有两种功能，既可以提供控制发光支路上的发光控制晶体管的开启或关断的发光控制信号，又可以提供控制扫描信号。即，该栅极驱动电路既可以为发光控制驱动电路，也可以为扫描驱动电路，当发光控制驱动电路和扫描驱动电路均为该栅极驱动电路时，发光控制驱动电路和扫描驱动电路的结构相同，通过改变首级电路的输入信号，在不改变时钟信号的前提下，即能够产生两种不同的像素电路的驱动信号(发光控制信号或扫描信号)。且由于发光控制驱动电路和扫描驱动电路的结构相同，需要的时钟信号也相同，因此，可以复用时钟信号线，这样一来，可以减少时钟信号线的数量，有利于显示面板的窄边框设计，且可以减少显示驱动芯片内为时钟信号线提供时钟信号的时钟控制模块的数量，降低显示驱动芯片的设计成本。
在一些可能实现的方式中，节点控制模块包括：第一控制单元，与第一电平信号接收端、第一时钟信号端、第二时钟信号端、第一节点和所述第二节点电连接；第二控制单元，与第二电平信号接收端、第一节点和第二节点电连接；第一控制单元用于接收第一电平信号接收端的第一电平信号，并响应于第二节点的信号、第一时钟信号端接收的第一时钟信号和第二时钟信号端接收的第二时钟信号，控制第一节点的信号；或者，第二控制单元用于接收第二电平信号接收端接收的第二电平信号，并响应于第二节点的信号，控制第一节点的信号。即分别通过独立的单元对第一节点进行控制，当第一节点需 要第一电平信号时，则通过第一控制单元向第一节点传输第一电平信号；当第一节点需要第二电平信号时，则通过第二控制单元向第一节点传输第二电平信号，避免了信号的干扰，使得第一节点的信号更加的稳定。
在一些可能实现的方式中，在上述节点控制模块包括第一控制单元的基础上，第一控制单元包括至少一个有源层为氧化物半导体的晶体管，例如以IGZO作为有源层的晶体管，由于IGZO晶体管具有漏电流小的优点，所以，通过第一控制单元向第一节点提供低电平时，可以保证第一节点的信号稳定，进而保证驱动信号输出端输出信号较稳定。当驱动信号输出端输出的信号为发光控制信号时，由于像素电路中的发光控制晶体管在接收到低电平时导通，显示单元显示；在接收到高电平时截止，显示单元不显示，也就是说，驱动信号输出端输出的发光控制信号为高电平时，发光控制晶体管截止，显示单元不显示；驱动信号输出端输出的信号为低电平时，发光控制晶体管导通，显示单元显示；又由于第一控制单元向第一节点提供低电平时，驱动信号输出端输出的发光控制信号为高电平信号，因此，当驱动信号输出端输出的高电平信号稳定，可以保证像素电路中的发光控制晶体管可以彻底的截止，避免了亮屏的发生。
在一些可能实现的方式中，移位寄存器还包括：保护模块，位于第二节点和所述第三节点之间，以及位于第二节点与稳压模块之间，且与第一电平信号接收端电连接；保护模块用于阻止第三节点的信号传输至第二节点，避免输入模块受到高的Vds偏置。
在一些可能实现的方式中，输入模块包括第一晶体管；第一晶体管的栅极与第二时钟信号端电连接，第一晶体管的第一极与触发信号输入端电连接，第一晶体管的第二极与第二节点电连接。当然，输入模块具体结构并不限于此，本领域技术人员可以根据实际情况进行设置，只要保证输入信号的正常输入即可。当输入模块仅包括一个晶体管时，结构简单。
在一些可能实现的方式中，在上述第一控制单元包括至少一个有源层为氧化物半导体的晶体管的基础上，第一控制单元包括第二晶体管、第三晶体管和第四晶体管；第二晶体管的栅极与第一时钟信号端电连接，第二晶体管的第一极与第一电平信号接收端电连接，第二晶体管的第二极、第四晶体管的栅极以及第三晶体管的第二极耦合于第四节点；第三晶体管的栅极与第二节点电连接，第三晶体管的第一极与第二时钟信号端电连接；第四晶体管的第一极与第一电平信号接收端电连接，第四晶体管的第二极与第一节点电连接。当然，输入模块具体结构并不限于此，本领域技术人员可以根据实际情况进行设置。
在一些可能实现的方式中，在上述第一控制单元包括第二晶体管、第三晶体管和第四晶体管的基础上，第二晶体管、第三晶体管和第四晶体管均为有源层为氧化物半导体的晶体管(具有漏电流小的优点)，当第一控制单元向第一节点提供低电平时，进一步 可以保证第一节点的信号稳定，进而保证驱动信号输出端输出的发光控制信号较稳定，避免了亮屏的发生。
在一些可能实现的方式中，在上述第二控制单元包括至少一个有源层为氧化物半导体的晶体管的基础上，第二控制单元包括第五晶体管；第五晶体管的栅极与第二节点电连接，第五晶体管的第一极与第二电平信号接收端电连接，第五晶体管的第二极与第一节点电连接。当然，第二控制单元具体结构并不限于此，本领域技术人员可以根据实际情况进行设置。当第二控制单元仅包括一个晶体管时，结构简单。
在一些可能实现的方式中，在上述移位寄存器包括保护模块的基础上，保护模块包括第六晶体管；第六晶体管的第一极与第二节点电连接，第六晶体管的栅极与第一电平信号接收端电连接，第六晶体管的第二极分别与第三节点和稳压模块电连接。当然，保护模块的具体结构并不限于此，本领域技术人员可以根据实际情况进行设置。当保护模块仅包括一个晶体管时，结构简单。
在一些可能实现的方式中，稳压模块包括第七晶体管和第一电容；第七晶体管的栅极与第三节点电连接，第七晶体管的第一极与第一时钟信号端电连接，第七晶体管的第二极与第一电容的第二极电连接，第一电容的第一极分别与第三节点和所述第六晶体管的第二极电连接。第七晶体管和第一电容构成电容耦合下拉结构，使得当驱动信号输出端输出的信号为低电平时，第三节点的信号的电位低于第一电平信号接收端接收的低电平的电位，进而使得驱动信号输出端输出的信号为第一电平信号接收端接收的低电平。
在一些可能实现的方式中，输出模块包括第二电容、第八晶体管和第九晶体管；第八晶体管的栅极、第二电容的第一极均与第一节点电连接，第八晶体管的第一极、第二电容的第二极均与第二电平信号接收端电连接，第八晶体管的第二极、第九晶体管的第二极均与驱动信号输出端电连接，第九晶体管的栅极与第三节点电连接，第九晶体管的第一极与第一电平信号接收端电连接，结构简单，且保证驱动信号输出端输出信号的稳定性。
在一些可能实现的方式中，有源层为氧化物半导体的晶体管为N型晶体管；有源层为硅的晶体管为P型晶体管，N型晶体管和P型晶体管的结合，将有效减少移位寄存器所需的薄膜晶体管个数，使得移位寄存器的结构更加的简单，当该移位寄存器应用于显示面板时，有利于实现更窄边框的面板设计。
第二方面，本申请实施例还提供一种栅极驱动电路，包括相互级联的N个第一方面所述的移位寄存器，N≥2。
该栅极驱动电路具有两种功能，既可以提供控制发光支路上的发光控制晶体管的开启或关断的发光控制信号，又可以提供控制扫描信号。即，该栅极驱动电路既可以为发 光控制驱动电路，也可以为扫描驱动电路，当发光控制驱动电路和扫描驱动电路均为该栅极驱动电路时，发光控制驱动电路和扫描驱动电路的结构相同，通过改变首级电路的输入信号，在不改变时钟信号的前提下，即能够产生两种不同的像素电路的驱动信号(发光控制信号或扫描信号)。且由于发光控制驱动电路和扫描驱动电路的结构相同，需要的时钟信号也相同，因此，可以复用时钟信号线，这样一来，可以减少时钟信号线的数量，有利于显示面板的窄边框设计，且可以减少显示驱动芯片内为时钟信号线提供时钟信号的时钟控制模块的数量，降低显示驱动芯片的设计成本。
第三方面，本申请实施例还提供一种显示面板，包括至少一个第二方面所述的栅极驱动电路，具有第二方面的栅极驱动电路的所有效果。
在一些可能实现的方式中，包括至少两个栅极驱动电路，其中一个栅极驱动电路为发光控制驱动电路，另一个栅极驱动电路为扫描驱动电路；发光控制驱动电路电连接的时钟信号线复用为扫描驱动电路的时钟信号线。
第四方面，本申请实施例还提供一种电子设备，包括如第三方面所述的显示面板，具有第三方面的栅极驱动电路的所有效果。
附图说明
图1为本申请实施例提供的一种电子设备的结构示意图；
图2为本申请实施例提供的一种显示面板的结构示意图；
图3为本申请实施例提供的一种像素电路的结构示意图；
图4为本申请实施例提供的又一种显示面板的结构示意图；
图5为本申请实施例提供的一种移位寄存器的结构示意图；
图6为本申请实施例提供的又一种移位寄存器的结构示意图；
图7为本申请实施例提供的又一种移位寄存器的结构示意图；
图8为本申请实施例提供的又一种移位寄存器的结构示意图；
图9为本申请实施例提供的一种移位寄存器的时序示意图；
图10为本申请实施例提供的一种移位寄存器的工作过程图；
图11为本申请实施例提供的又一种移位寄存器的工作过程图；
图12为本申请实施例提供的又一种移位寄存器的工作过程图；
图13为本申请实施例提供的又一种移位寄存器的工作过程图；
图14为本申请实施例提供的又一种移位寄存器的工作过程图；
图15为本申请实施例提供的又一种移位寄存器的工作过程图；
图16为相关技术与本申请实施例的一种仿真对比图；
图17为相关技术与本申请实施例的又一种仿真对比图；
图18为本申请实施例提供的又一种移位寄存器的时序示意图；
图19为本申请实施例提供的又一种移位寄存器的时序示意图；
图20为相关技术与本申请实施例的又一种仿真对比图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本文中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。
本申请实施例的说明书和权利要求书中的术语“第一”和“第二”等是用于区别不同的对象，而不是用于描述对象的特定顺序。例如，第一目标对象和第二目标对象等是用于区别不同的目标对象，而不是用于描述目标对象的特定顺序。
在本申请实施例中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请实施例中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
在本申请实施例的描述中，除非另有说明，“多个”的含义是指两个或两个以上。例如，多个处理单元是指两个或两个以上的处理单元；多个***是指两个或两个以上的***。
本申请实施例提供一种电子设备，本申请实施例提供的电子设备可以是手机、平板电脑、笔记本电脑、个人数字助理(personal digital assistant，简称PDA)、车载电脑、智能穿戴式设备、智能家居设备等包括显示面板的电子设备，本申请实施例对上述电子设备的具体形式不作限定。如图1所示，以下为了方便说明，以电子设备是手机为例进行说明。
如图1所示，手机100包括显示面板10、后壳20和中框30。显示面板10、后壳20和中框30可以围成容纳腔体。容纳腔体内设置有主板、电池和功能器件(图中未示出)等结构。功能器件例如包括显示驱动芯片和处理器等。处理器向显示驱动芯片发送相应的信号，以使显示驱动芯片驱动显示面板10进行显示。
后壳20的材料例如可以包括塑料、素皮、玻璃纤维等不透光材料；也可以包括玻璃等透光材料。本申请实施例对后壳20的材料不进行限定。
显示面板10例如包括液晶显示(Liquid Crystal Display，LCD)面板、有机发光二极管(Organic Light Emitting Diode，OLED)显示面板和LED显示面板等，其中，LED显示面板例如包括Micro-LED显示面板、Mini-LED显示面板等。本申请实施例对显示面板10的类型不进行限定。下面以显示面板10为OLED显示面板为例进行说明。
如图2所示，显示面板10包括显示区AA和非显示区NAA，非显示区NAA例如环绕显示区AA设置。显示面板10的显示区AA中设置有阵列排布的多个像素11、多个扫描线组12和多条数据线13。每个像素11包括像素电路111和显示单元112。多条 数据线13与多列像素11中像素电路111一一对应，即一列像素11中的像素电路111对应一条数据线13。多个扫描线组12与多行像素11的像素电路111一一对应，即一行像素11中的像素电路111对应一个扫描线组12。
结合图3，像素电路111例如包括7T1C(7个晶体管和1个存储电容)，即该像素电路111可以包括驱动晶体管M1、数据写入晶体管M2、阈值补偿晶体管M3、复位晶体管M4和M5、发光控制晶体管M6和M7、以及存储电容Cst。
可以理解的是，像素电路111的具体结构包括但不限于上述示例，在其他可选的实施例中，像素电路111还可以是其他设置方式，只要可以驱动显示单元112发光即可。
上述复位晶体管M4和阈值补偿晶体管M3是以氧化物半导体材料，例如铟镓锌氧化物(indium gallium zinc oxide，IGZO)，作为有源层的晶体管；驱动晶体管M1、数据写入晶体管M2、复位晶体管M5、发光控制晶体管M6和M7是以硅，可选为多晶硅，例如为低温多晶硅(Low Temperature Poly-Silicon，LTPS)材料，作为有源层的晶体管，即将LTPS晶体管和IGZO晶体管集成在一个基板上，形成低温多晶氧化物(LTPO，Low Temperature Polycrystalline Oxide)显示面板10。
低温多晶硅晶体管具有载流子迁移率高、响应快、和功耗小等的优点，氧化物半导体晶体管具有漏流小的优点，所以当像素电路111同时包括LTPS材料作为有源层的晶体管以及IGZO材料作为有源层的晶体管时，可以保证像素电路111具有较佳的性能。
此外，像素电路111还包括初始化信号端Vref、第一电源端PVDD、第二电源端PVEE、数据信号端Data、第一扫描信号端Scan1、第二扫描信号端Scan2、第三扫描信号端Scan3、第四扫描信号端Scan4和发光控制信号端Emit。发光控制晶体管M6的第一极与第一电源端PVDD电连接，数据写入晶体管M2的第一极与数据信号端Data电连接，数据写入晶体管M2的栅极与第四扫描信号端Scan4电连接，阈值补偿晶体管M3的栅极与第三扫描信号端Scan3电连接，复位晶体管M4和M5的第一极分别与初始化信号端Vref电连接(两者对应的初始化信号端可以相同，也可以不同)，复位晶体管M4的栅极可以与第一扫描信号端Scan1电连接，复位晶体管M5的栅极可以与第二扫描信号端Scan2电连接，发光控制晶体管M6和M7的栅极可以分别与发光控制信号端Emit电连接，发光控制晶体管M7与第一发光元件112的阳极电连接，第一发光元件112的阴极与第二电源端PVEE电连接。
相应的，继续参见图2，每个扫描线组12包括第一扫描信号线121、第二扫描信号线122和发光控制信号线123。
相应的，一列像素11中的像素电路111对应一条数据线13即为同一列的各像素11的像素电路111中的数据信号端Data与同一条数据线13电连接。一行像素11中的像素电路111对应一个扫描线组12即为同一行的各像素11的像素电路111中的第一扫描信号端Scan1与该行对应的第一扫描信号线121电连接，同一行的各像素11的像素电路111中的第二扫描信号端Scan2与该行对应的第二扫描信号线122电连接，同一行的各像素11的像素电路111中的第三扫描信号端Scan3与其它行(具体行本领域技术人员可以根据实际情况设置)对应的第一扫描信号线121电连接，同一行的各像素11的像素电路111中的第四扫描信号端Scan4与其它行(具体行本领域技术人员可以根据实际情 况设置)对应的第二扫描信号线122电连接，同一行的各像素11的像素电路111中的发光控制信号端Emit与同一条发光控制信号线123电连接。
需要说明的是，为了保证电路的简洁清楚，图2中并未示出同一行的各像素11的像素电路111中的第三扫描信号端Scan3与其它行对应的第一扫描信号线121电连接，同一行的各像素11的像素电路111中的第四扫描信号端Scan4与其它行对应的第二扫描信号线122电连接。
也就是说，运用LTPO工艺的像素电路111通常需要三种栅极控制信号，一是发光控制信号线123传输的发光控制信号，即发光控制信号线123传输的发光控制信号可以控制发光支路上的发光控制晶体管M6和M7的开启或关断；二是第一扫描信号线121传输的第一扫描信号，即第一扫描信号线121传输的第一扫描信号可以控制有源层为IGZO的复位晶体管M4和阈值补偿晶体管M3的开启或关断，亦即复位晶体管M4所在行对应的第一扫描信号线121传输的第一扫描信号可以控制复位晶体管M4的开启或关断，通过其它行对应的第一扫描信号线121传输的第一扫描信号控制阈值补偿晶体管M3的开启或关断；三是第二扫描信号线122传输的第二扫描信号，即第二扫描信号线122传输的第二扫描信号可以控制有源层为LTPS的复位晶体管M5和数据写入晶体管M2的开启或关断，亦即复位晶体管M5所在行对应的第二扫描信号线122传输的第二扫描信号可以控制复位晶体管M5的开启或关断，通过其它行对应的第二扫描信号线122传输的第二扫描信号控制数据写入晶体管M2的开启或关断。
像素电路111基于发光控制信号、第一扫描信号、第二扫描信号等驱动显示单元112发光的原理与现有技术中的7T1C的像素电路驱动显示单元发光的原理类似，在此不再赘述。
继续参见图2，显示面板10的非显示区NAA中设置有驱动电路14，其中，驱动电路14例如可以包括第一扫描驱动电路、第二扫描驱动电路和发光控制驱动电路。第一扫描驱动电路包括多个第一扫描信号输出端，第二扫描驱动电路包括多个第二扫描信号输出端，发光控制驱动电路包括多个发光控制信号输出端。第一扫描驱动电路的多个第一扫描信号输出端与显示区AA的多条第一扫描信号线121一一对应电连接，第二扫描驱动电路的多个第二扫描信号输出端与显示区AA的多条第二扫描信号线122一一对应电连接，以及，发光控制驱动电路的多个发光控制信号输出端与显示区AA的发光控制信号线123一一对应电连接。第一扫描驱动电路通过第一扫描信号输出端向第一扫描信号线121传输第一扫描信号，第二扫描驱动电路通过第二扫描信号输出端向第二扫描信号线122传输第二扫描信号，发光控制驱动电路通过发光控制信号输出端向发光控制信号线123传输发光控制信号。
为了解决背景技术中的问题，本申请实施例提供一种栅极驱动电路，该栅极驱动电路具有两种功能，既可以提供控制发光支路上的发光控制晶体管M6和M7的开启或关断的发光控制信号，又可以提供控制复位晶体管M4和阈值补偿晶体管M3的开启或关断的第一扫描信号。即，该栅极驱动电路既可以为发光控制驱动电路，也可以为第一扫描驱动电路，当发光控制驱动电路和第一扫描驱动电路均为该栅极驱动电路时，发光控制驱动电路和第一扫描驱动电路的结构相同，通过改变首级电路的输入信号，在不改变 时钟信号的前提下，即能够产生两种不同的像素电路的驱动信号(发光控制信号或第一扫描信号)。且由于发光控制驱动电路和第一扫描驱动电路的结构相同，需要的时钟信号也相同，因此，可以复用时钟信号线，这样一来，可以减少时钟信号线的数量，有利于显示面板的窄边框设计，且可以减少显示驱动芯片内为时钟信号线提供时钟信号的时钟控制模块的数量，降低显示驱动芯片的设计成本。
下面对本申请实施例提供的栅极驱动电路的具体结构进行介绍。
如图4所示，本申请实施例中，栅极驱动电路141包括N个级联的移位寄存器ASG，例如可以包括N个移位寄存器ASG1～ASGn，N≥2，N的具体取值本领域技术人员可根据实际情况设置，此处不作限定。
每级移位寄存器ASG包括第一时钟信号端CK1、第二时钟信号端CK2、触发信号输入端IN和驱动信号输出端OUT，除最后一级移位寄存器ASGn外，其余每级移位寄存器ASG的驱动信号输出端OUT与其相邻的下一级的移位寄存器ASG的触发信号输入端IN电连接，第一级移位寄存器ASG1的触发信号输入端IN接收触发信号线(图4中未示出)发出的触发信号STV。移位寄存器ASG根据第一时钟信号端CK1输入的第一时钟信号、第二时钟信号端CK2输入的第二时钟信号和触发信号输入端IN输入的触发信号STV通过驱动信号输出端OUT向发光控制信号线123发送发光控制信号或向第一扫描信号线121发送第一扫描信号。
显示面板10还包括位于非显示区NAA的第一时钟信号线CKL1和第二时钟信号线CKL2。奇数级移位寄存器ASG的第一时钟信号端CK1与第一时钟信号线CKL1电连接，奇数级移位寄存器ASG的第二时钟信号端CK2与第二时钟信号线CKL2电连接；偶数级移位寄存器ASG的第一时钟信号端CK1与第二时钟信号线CKL2电连接，偶数级移位寄存器ASG的第二时钟信号端CK2与第一时钟信号线CKL1电连接。如图4所示，第一级移位寄存器ASG1和第三级移位寄存器ASG3的第一时钟信号端CK1与第一时钟信号线CKL1电连接，第一级移位寄存器ASG1和第三级移位寄存器ASG3的第二时钟信号端CK2与第二时钟信号线CKL2电连接，第二级移位寄存器ASG2和第四级移位寄存器ASG4的第一时钟信号端CK1与第二时钟信号线CKL2电连接，第二级移位寄存器ASG2和第四级移位寄存器ASG4的第二时钟信号端CK2与第一时钟信号线CKL1电连接。
结合图5，每级移位寄存器ASG还包括：第一电平信号接收端VGL、第二电平信号接收端VGH、节点控制模块142、输入模块143、稳压模块144和输出模块145。
节点控制模块142，与第一电平信号接收端VGL、第二电平信号接收端VGH、第一时钟信号端CK1、第二时钟信号端CK2、第一节点N1和第二节点N2电连接。输入模块143，与第二时钟信号端CK2、触发信号输入端IN和第二节点N2电连接。稳压模块144，与第二节点N2、第二时钟信号端CK2和第三节点N3电连接。输出模块145，与第一电平信号接收端VGL、第二电平信号接收端VGH、第一节点N1、第三节点N3和驱动信号输出端OUT电连接。
输入模块143用于接收触发信号输入端IN的输入信号STV，并响应于第二时钟信号端CK2接收的第二时钟信号CKV2而控制第二节点N2的信号。
节点控制模块142用于接收第一电平信号接收端VGL的第一电平信号和第二电平信号接收端VGH接收的第二电平信号，并响应于第二节点N2的信号、第一时钟信号端CK1接收的第一时钟信号CKV1和第二时钟信号端CK2接收的第二时钟信号CKV2，控制第一节点N1的信号。
输出模块145用于接收第二电平信号接收端VGH接收的第二电平信号，并响应于第一节点N1的信号，控制驱动信号输出端OUT输出发光控制信号或第一扫描信号；或者，输出模块145用于接收第一电平信号接收端VGL的第一电平信号，并响应于第三节点N3的信号，控制驱动信号输出端OUT输出发光控制信号或第一扫描信号。
稳压模块144用于接收第二节点N2的信号，并响应于第二时钟信号端CK2接收的第二时钟信号CKV2，控制第三节点N3的信号；其中，第一电平信号为低电平信号，第二电平信号为高电平信号；当驱动信号输出端OUT输出的信号为低电平信号时，第三节点N3的信号的电位小于第一电平信号接收端VGL接收的第一电平信号的电位。
此外，节点控制模块142包括至少一个晶体管，该晶体管是以氧化物半导体材料，例如IGZO，作为有源层的晶体管。输入模块143、稳压模块144和输出模块145中的至少一者中包括至少一个晶体管，该晶体管是以硅，可选为多晶硅，例如为LTPS，作为有源层的晶体管。
本申请实施例中，通过输入模块143接收输入信号STV并响应于第二时钟信号CKV2控制第二节点N2的信号，通过节点控制模块142接收第一电平信号和第二电平信号，并响应于第二节点N2的信号、第一时钟信号CKV1和第二时钟信号CKV2控制第一节点N1的信号，通过输出模块145接收第二电平信号，并响应于第一节点N1的信号，控制输出信号；或者，通过输出模块145接收第一电平信号，并响应于第三节点N3的信号，控制输出信号。由于第三节点N3的电位会影响输出信号，所以通过稳压模块144控制第三节点N3的信号，使得当驱动信号输出端OUT输出的信号为低电平时，第三节点N3的信号的电位低于第一电平信号接收端VGL接收的低电平的电位，进而使得驱动信号输出端OUT输出的信号为第一电平信号接收端VGL接收的低电平，避免输出模块145包括晶体管时，由于晶体管的阈值损耗，输出模块145从第一电平信号接收端VGL接收的第一电平信号，无法传输至控制驱动信号输出端OUT，进而影响信号的输出。此外，由于节点控制模块142包括IGZO晶体管，相比于全部为LTPS晶体管，可以改善第一节点N1的漏电，使得第一节点N1的信号稳定，进行使得输出的信号稳定；且由于移位寄存器ASG结合了IGZO晶体管和LTPS晶体管，因此，可以使得移位寄存器ASG具有较强的驱动能力和低功耗等特点。
可选的，节点控制模块142包括的IGZO晶体管为N型IGZO晶体管，输入模块143、稳压模块144和输出模块145中的至少一者中包括的LTPS晶体管为P型LTPS晶体管。N型晶体管和P型晶体管的结合，将有效减少移位寄存器ASG所需的薄膜晶体管个数，使得移位寄存器ASG的结构更加的简单，有利于实现更窄边框的面板设计。
在一些可能的实施例中，参见图6，每级移位寄存器ASG还包括：保护模块146，位于第二节点N2和第三节点N3之间，以及，位于第二节点N2和稳压模块144之间，且与第一电平信号接收端VGL电连接。保护模块146用于阻止第三节点N3的信号传输 至第二节点N2，即起到夹断作用，避免输入模块143受到高的Vds偏置。
在一些可能的实施例中，参见图7，节点控制模块142包括第一控制单元1421和第二控制单元1422。第一控制单元1421，与第一电平信号接收端VGL、第一时钟信号端CK1、第二时钟信号端CK2、第一节点N1和第二节点N2电连接。第二控制单元1422，与第二电平信号接收端VGH、第一节点N1和第二节点N2电连接。
第一控制单元1421用于接收第一电平信号接收端VGL的第一电平信号，并响应于第二节点N2的信号、第一时钟信号端CK1接收的第一时钟信号CKV1和第二时钟信号端CK2接收的第二时钟信号CKV2，控制第一节点N1的信号。或者，第二控制单元1422，用于接收第二电平信号接收端VGH接收的第二电平信号，并响应于第二节点N2的信号，控制第一节点N1的信号。也就是说，可以通过第一控制单元1421向第一节点N1提供第一电平信号，通过第二控制单元1422向第一节点N1提供第二电平信号。换言之，当第一节点N1需要第一电平信号时，则通过第一控制单元1421向第一节点N1传输第一电平信号；当第一节点N1需要第二电平信号时，则通过第二控制单元1422向第一节点N1传输第二电平信号。且当第一节点N1为第一电平信号时，输出模块145将第二电平信号接收端VGH接收的第二电平信号通过驱动信号输出端OUT输出；当第一节点N1为第二电平信号时，输出模块145无法将第二电平信号接收端VGH接收的第二电平信号通过驱动信号输出端OUT输出。
此外，第一控制单元1421包括至少一个晶体管，该晶体管是以氧化物半导体材料，例如IGZO，作为有源层的晶体管。由于IGZO晶体管具有漏电流小的优点，所以，通过第一控制单元1421向第一节点N1提供低电平时，可以保证第一节点N1的信号稳定，进而保证驱动信号输出端OUT输出信号较稳定。当驱动信号输出端OUT输出的信号为发光控制信号(即该栅极驱动电路为发光控制驱动电路)时，由于像素电路111中的发光控制晶体管M6和M7在接收到低电平时导通，显示单元112显示；在接收到高电平时截止，显示单元112不显示，也就是说，驱动信号输出端OUT输出的发光控制信号为高电平时，发光控制晶体管M6和M7截止，显示单元112不显示；驱动信号输出端OUT输出的信号为低电平时，发光控制晶体管M6和M7导通，显示单元112显示；又由于第一控制单元1421向第一节点N1提供低电平时，驱动信号输出端OUT输出的发光控制信号为高电平信号，因此，当驱动信号输出端OUT输出的高电平信号稳定，可以保证像素电路111中的发光控制晶体管M6和M7可以彻底的截止，避免了亮屏的发生。
在一些可能的实施例中，参见图8，输入模块143包括第一晶体管T1，第一晶体管T1的栅极与第二时钟信号端CK2电连接，第一晶体管T1的第一极与触发信号输入端IN电连接，第一晶体管T1的第二极与第二节点N2电连接。第一晶体管T1例如是以硅，可选为多晶硅，例如为LTPS，作为有源层的晶体管。
需要说明的是，第一晶体管T1的第一极可以为第一晶体管T1的源电极，第一晶体管T1的第二极可以为第一晶体管T1的漏电极；或者，第一晶体管T1的第一极可以为第一晶体管T1的漏电极，第一晶体管T1的第二极可以为第一晶体管T1的源电极。下述实施例中的晶体管相同，下述实施例不再赘述。
在一些可能的实施例中，参见图8，第一控制单元1421包括第二晶体管T2、第三晶体管T3和第四晶体管T4。第二晶体管T2的栅极与第一时钟信号端CK1电连接，第二晶体管T2的第一极与第一电平信号接收端VGL电连接，第二晶体管T2的第二极、第四晶体管T4的栅极以及第三晶体管T3的第二极耦合于第四节点N4。第三晶体管T3的栅极与第二节点N2电连接，第三晶体管T3的第一极与第二时钟信号端CK2电连接。第四晶体管T4的第一极与第一电平信号接收端VGL电连接，第四晶体管T4的第二极与第一节点N1电连接。第二晶体管T2、第三晶体管T3和第四晶体管T4例如均为以氧化物半导体材料，例如IGZO，作为有源层的晶体管。
在一些可能的实施例中，参见图8，第二控制单元1422包括第五晶体管T5。第五晶体管T5的栅极与第二节点N2电连接，第五晶体管T5的第一极与第二电平信号接收端VGH电连接，第五晶体管T5的第二极与第一节点N1电连接。
在一些可能的实施例中，参见图8，保护模块146包括第六晶体管T6。第六晶体管T6的第一极与第二节点N2电连接，第六晶体管T6的栅极与第一电平信号接收端VGL电连接，第六晶体管T6的第二极分别与第三节点N3和稳压模块144电连接。第六晶体管T6例如是以硅，可选为多晶硅，例如为LTPS，作为有源层的晶体管。
在一些可能的实施例中，参见图8，稳压模块144包括第七晶体管T7和第一电容C1。第七晶体管T7的栅极与第三节点N3电连接，第七晶体管T7的第一极与第一时钟信号端CK1电连接，第七晶体管T7的第二极与第一电容C1的第二极电连接，第一电容C1的第一极分别与第三节点N3和第六晶体管T6的第二极电连接。第七晶体管T7例如是以硅，可选为多晶硅，例如为LTPS，作为有源层的晶体管。
在一些可能的实施例中，参见图8，输出模块145包括第二电容C2、第八晶体管T8和第九晶体管T9。第八晶体管T8的栅极、第二电容C2的第一极均与第一节点N1电连接，第八晶体管T8的第一极、第二电容C2的第二极均与第二电平信号接收端VGH电连接，第八晶体管T8的第二极、第九晶体管T9的第二极均与驱动信号输出端OUT电连接，第九晶体管T9的栅极与第三节点N3电连接，第九晶体管T9的第一极与第一电平信号接收端VGL电连接。第八晶体管T8和第九晶体管T9例如均是以硅，可选为多晶硅，例如为LTPS，作为有源层的晶体管。
以上对栅极驱动电路的结构进行了具体介绍，下面对当栅极驱动电路为发光控制驱动电路时的工作过程，以及，当栅极驱动电路为第一扫描驱动电路时的工作过程分别进行介绍。
首先，对当栅极驱动电路为发光控制驱动电路时的工作过程进行介绍。
图9示出了当栅极驱动电路为发光控制驱动电路时的移位寄存器中各信号的时序图。下面结合当栅极驱动电路为发光控制驱动电路时的移位寄存器中各信号的时序图，对图8所示的移位寄存器的工作过程进行说明，其他结构移位寄存器中的信号的时序与此基本相同，在此不再赘述。其中，以第二晶体管T2、第三晶体管T3和第四晶体管T4为N型IGZO晶体管，第一晶体管T1、第五晶体管T5、第六晶体管T6、第七晶体管T7、第八晶体管T8和第九晶体管T9为P型LTPS晶体管，且第一电平信号接收端VGL接收的第一电平信号为-7V，第二电平信号接收端VGH接收的第二电平信号为7V 为例。
在第一阶段t1，即STV高电平输入阶段：结合图10，第一时钟信号端CK1接收的CKV1由低电平变高电平，第二时钟信号端CK2接收的CKV2由高电平变低电平，第一晶体管T1打开，第六晶体管T6打开，将触发信号输入端IN接收的输入信号STV的高电平写入第三节点N3，第三节点N3被拉高，第九晶体管T9被关闭。同时第五晶体管T5被关闭，第三晶体管T3打开，第一节点N1无法通过第五晶体管T5被置高。此外，CKV1的高电平打开第二晶体管T2，第三晶体管T3将CKV2的低电平传至第四节点N4，则第四节点N4此时处于低电平状态，第四晶体管T4被关闭，第一节点N1仍旧维持高电平。由于第二电容C2的保持作用，驱动信号输出端OUT输出的发光控制信号此时仍旧为低电平。
在第二阶段t2，即驱动信号输出端OUT输出高电平阶段：结合图11，第一时钟信号端CK1接收的CKV1由高电平变低电平，第二时钟信号端CK2接收的CKV2由低电平变高电平，第一晶体管T1和第二晶体管T2关闭。第三晶体管T3将第二时钟信号端CK2接收的CKV2的高电平传至第四节点N4，第四晶体管T4打开，第一节点N1被拉低，第八晶体管T8被打开，驱动信号输出端OUT输出的发光控制信号为高电平。同时，第三节点N3仍旧维持高电平，第九晶体管T9被关闭。
在第三阶段t3，即STV高电平再输入阶段：结合图12，第一时钟信号端CK1接收的CKV1由低电平变高电平，第二时钟信号端CK2接收的CKV2由高电平变低电平，第一晶体管T1打开，第六晶体管T6打开，将触发信号输入端IN接收的输入信号STV的高电平写入第三节点N3，第三节点N3被拉高，第九晶体管T9被关闭。同时第五晶体管T5被关闭，第三晶体管T3打开，第一节点N1无法通过第五晶体管T5被置高。此外，CKV1的高电平打开第二晶体管T2，第三晶体管T3将CKV2的低电平传至第四节点N4，则第四节点N4此时处于低电平状态，第四晶体管T4被关闭，由于第二电容C2的保持作用，第一节点N1仍旧维持低电平，第八晶体管T8被打开，驱动信号输出端OUT输出的发光控制信号维持高电平。
在第四阶段t4，即驱动信号输出端OUT输出的高电平保持阶段：结合图13，第一时钟信号端CK1接收的CKV1由高电平变低电平，第二时钟信号端CK2接收的CKV2由低电平变高电平，第一晶体管T1和第二晶体管T2关闭。第三晶体管T3将第二时钟信号端CK2接收的CKV2的高电平传至第四节点N4，第四晶体管T4打开，第一节点N1被拉低，第八晶体管T8被打开，驱动信号输出端OUT输出的发光控制信号为高电平。同时，第三节点N3仍旧维持高电平，第九晶体管T9被关闭。
在第五阶段t5，即STV低电平输入阶段：结合图14，第一时钟信号端CK1接收的CKV1由低电平变高电平，第二时钟信号端CK2接收的CKV2由高电平变低电平，第一晶体管T1打开，第六晶体管T6打开，将触发信号输入端IN接收的输入信号STV的低电平写入第三节点N3，第三节点N3被拉低，第九晶体管T9被打开。同时第三晶体管T3被关闭，第二晶体管T2打开，第四节点N4为低电平，第四晶体管T4关闭。第二节点N2的低电平将第五晶体管T5打开，第一节点N1被拉高，第八晶体管T8被关闭，驱动信号输出端OUT输出的发光控制信号为低电平。
在第六阶段t6，即电容耦合阶段：结合图15，第一时钟信号端CK1接收的CKV1由高电平变低电平，第二时钟信号端CK2接收的CKV2由低电平变高电平，第一晶体管T1和第二晶体管T2关闭。第三节点N3保持低电平，第七晶体管T7导通。由于第九晶体管T9的阈值损耗，第九晶体管T9不能完全输出最低电平。当第一时钟信号端CK1接收的CKV1由高电平向低电平跳变时，第七晶体管T7和第一电容C1将第三节点N3拉至一个低于第一电平信号接收端VGL接收的低电平的电位，这样，第九晶体管T9能够输出第一电平信号接收端VGL接收的低电平，即保证驱动信号输出端OUT输出的发光控制信号为第一电平信号接收端VGL接收的低电平。
通过第七晶体管T7和第一电容C1控制第三节点N3的信号，使得当驱动信号输出端OUT输出的发光控制信号为低电平时，第三节点N3的信号的电位低于第一电平信号接收端VGL接收的低电平的电位，使得驱动信号输出端OUT输出的发光控制信号为第一电平信号接收端VGL接收的低电平，避免当第三节点N3的信号较高，使得第九晶体管T9从第一电平信号接收端VGL接收的低电平无法传输至控制驱动信号输出端OUT，进而影响发光控制信号的输出。此外，由于第一控制单元1421的第二晶体管T2、第三晶体管T3以及第四晶体管T4均为IGZO晶体管(具有漏电流小的优点)，所以，通过第一控制单元1421向第一节点N1提供低电平时，可以保证第一节点N1的信号稳定，进而保证驱动信号输出端OUT输出的发光控制信号较稳定，避免了亮屏的发生。此外，由于移位寄存器ASG结合了N型晶体管和P型晶体管的结合，有效减少移位寄存器ASG所需的薄膜晶体管个数，即移位寄存器ASG仅包括9个晶体管和2个电容，结构单元，器件数量少，有利于实现更窄边框的面板设计。此外，由于移位寄存器ASG结合了IGZO晶体管和LTPS晶体管，因此，可以使得移位寄存器ASG具有较强的驱动能力和低功耗等特点。且经验证，该栅极驱动电路可以有效规避LTPS晶体管漏电的缺点。
此外，由于LTPS晶体管的阈值电压容易受到外界电场的影响，发生阈值电压的偏移，进而影响驱动信号输出端OUT的信号输出。经验证，本申请实施例提供的包括IGZO晶体管的栅极驱动电路，即便LTPS晶体管的阈值电压偏移量较大(阈值电压偏移
Figure PCTCN2023070297-appb-000002
)，驱动信号输出端OUT仍旧可以输出比较稳定的波形，为工艺提供一定的容限误差。
为详细说明该有益效果，下面通过与相关技术进行对比来说明。
图16和图17均示出了相关技术与本申请实施例的对比仿真图，其中，横坐标为时间，纵坐标为仿真时驱动信号输出端OUT输出的信号。
图16中的四个仿真结果由上到下依次为：相关技术的LTPS晶体管的阈值电压偏移0V时，驱动信号输出端OUT的信号；相关技术的LTPS晶体管的阈值电压偏移-2.5V时，驱动信号输出端OUT的信号；本申请实施例的LTPS晶体管的阈值电压偏移0V时，驱动信号输出端OUT的信号；本申请实施例的的LTPS晶体管的阈值电压偏移-2.5V时，驱动信号输出端OUT的信号。由图16可知，当相关技术和本申请实施例的LTPS晶体管的阈值电压均偏移0V时，相关技术和本申请实施例驱动信号输出端的输出的信号均正常，但是，当相关技术和本申请实施例的LTPS晶体管的阈值电压均偏移- 2.5V时，相关技术输出的信号异常，即相关技术的移位寄存器失效，而本申请实施例输出的信号仍然正常。
图17中的四个仿真结果由上到下依次为：相关技术的LTPS晶体管的阈值电压偏移0V时，驱动信号输出端OUT的信号；相关技术的LTPS晶体管的阈值电压偏移2.5V时，驱动信号输出端OUT的信号；本申请实施例的LTPS晶体管的阈值电压偏移0V时，驱动信号输出端OUT的信号；本申请实施例的的LTPS晶体管的阈值电压偏移2.5V时，驱动信号输出端OUT的信号。由图17可知，当相关技术和本申请实施例的LTPS晶体管的阈值电压均偏移0V时，相关技术和本申请实施例驱动信号输出端的输出的信号均正常，但是，当相关技术和本申请实施例的LTPS晶体管的阈值电压均偏移2.5V时，相关技术输出的信号异常，即相关技术的移位寄存器失效，而本申请实施例输出的信号仍然较正常。
由此可见，本申请实施例提供的包括IGZO晶体管的栅极驱动电路在LTPS阈值电压偏移
Figure PCTCN2023070297-appb-000003
时，电路作为发光控制驱动电路仍旧可以输出比较稳定的波形，为工艺提供一定的容限误差。
以上是以某批次的晶体管特性为例说明，旨在表述本提案可以容忍的阈值电压偏移范围更强，留给工艺窗口的容忍度更高。实际可容忍的偏移值不局限于此。
此外，当栅极驱动电路为发光控制驱动电路时，发光控制驱动电路的移位寄存器ASG支撑脉宽调制。示例性的，参见图18，当STV信号脉宽为3.5个时钟周期时，驱动信号输出端OUT输出的发光控制信号也为3.5个时钟周期。
其次，对当栅极驱动电路为第一扫描驱动电路时的工作过程进行介绍。
图19示出了当栅极驱动电路为第一扫描驱动电路时的移位寄存器中各信号的时序图。与图9相比，输入信号STV的脉宽仅有半个第二时钟信号CKV2周期。下面结合当栅极驱动电路为第一扫描驱动电路时的移位寄存器中各信号的时序图，对图8所示的移位寄存器的工作过程进行说明，其他结构移位寄存器中的信号的时序与此基本相同，在此不再赘述。同样，以第二晶体管T2、第三晶体管T3和第四晶体管T4为N型IGZO晶体管，第一晶体管T1、第五晶体管T5、第六晶体管T6、第七晶体管T7、第八晶体管T8和第九晶体管T9为P型LTPS晶体管，且第一电平信号接收端VGL接收的第一电平信号为-7V，第二电平信号接收端VGH接收的第二电平信号为7V为例。
在第一阶段t1，即STV高电平输入阶段：结合图10，第一时钟信号端CK1接收的CKV1由低电平变高电平，第二时钟信号端CK2接收的CKV2由高电平变低电平，第一晶体管T1打开，第六晶体管T6打开，将触发信号输入端IN接收的输入信号STV的高电平写入第三节点N3，第三节点N3被拉高，第九晶体管T9被关闭。同时第五晶体管T5被关闭，第三晶体管T3打开，第一节点N1无法通过第五晶体管T5被置高。此外，CKV1的高电平打开第二晶体管T2，第三晶体管T3将CKV2的低电平传至第四节点N4，则第四节点N4此时处于低电平状态，第四晶体管T4被关闭，第一节点N1仍旧维持高电平。由于第二电容C2的保持作用，驱动信号输出端OUT输出的发光控制信号此时仍旧为低电平。
在第二阶段t2，即驱动信号输出端OUT输出高电平阶段：结合图11，第一时钟信 号端CK1接收的CKV1由高电平变低电平，第二时钟信号端CK2接收的CKV2由低电平变高电平，第一晶体管T1和第二晶体管T2关闭。第三晶体管T3将第二时钟信号端CK2接收的CKV2的高电平传至第四节点N4，第四晶体管T4打开，第一节点N1被拉低，第八晶体管T8被打开，驱动信号输出端OUT输出的发光控制信号为高电平。同时，第三节点N3仍旧维持高电平，第九晶体管T9被关闭。
在第三阶段t3，即STV低电平输入阶段：结合图14，第一时钟信号端CK1接收的CKV1由低电平变高电平，第二时钟信号端CK2接收的CKV2由高电平变低电平，第一晶体管T1打开，第六晶体管T6打开，将触发信号输入端IN接收的输入信号STV的低电平写入第三节点N3，第三节点N3被拉低，第九晶体管T9被打开。同时第三晶体管T3被关闭，第二晶体管T2打开，第四节点N4为低电平，第四晶体管T4关闭。第二节点N2的低电平将第五晶体管T5打开，第一节点N1被拉高，第八晶体管T8被关闭，驱动信号输出端OUT输出的发光控制信号为低电平。
在第六阶段t6，即电容耦合阶段：结合图15，第一时钟信号端CK1接收的CKV1由高电平变低电平，第二时钟信号端CK2接收的CKV2由低电平变高电平，第一晶体管T1和第二晶体管T2关闭。第三节点N3保持低电平，第七晶体管T7导通。由于第九晶体管T9的阈值损耗，第九晶体管T9不能完全输出最低电平。当第一时钟信号端CK1接收的CKV1由高电平向低电平跳变时，第七晶体管T7和第一电容C1将第三节点N3拉至一个低于第一电平信号接收端VGL接收的低电平的电位，这样，第九晶体管T9能够输出第一电平信号接收端VGL接收的低电平，即保证驱动信号输出端OUT输出的发光控制信号为第一电平信号接收端VGL接收的低电平。
通过第七晶体管T7和第一电容C1控制第三节点N3的信号，使得当驱动信号输出端OUT输出的第一扫描信号为低电平时，第三节点N3的信号的电位低于第一电平信号接收端VGL接收的低电平的电位，使得驱动信号输出端OUT输出的第一扫描信号为第一电平信号接收端VGL接收的低电平，避免当第三节点N3的信号较高，使得第九晶体管T9从第一电平信号接收端VGL接收的低电平无法传输至控制驱动信号输出端OUT，进而影响第一扫描信号的输出。此外，由于第一控制单元1421的第二晶体管T2、第三晶体管T3以及第四晶体管T4均为IGZO晶体管(具有漏电流小的优点)，所以，通过第一控制单元1421向第一节点N1提供低电平时，可以保证第一节点N1的信号稳定，进而保证驱动信号输出端OUT输出的第一扫描信号较稳定，保证像素电路111的正常工作。此外，由于移位寄存器ASG结合了N型晶体管和P型晶体管的结合，有效减少移位寄存器ASG所需的薄膜晶体管个数，即移位寄存器ASG仅包括9个晶体管和2个电容，结构单元，器件数量少，有利于实现更窄边框的面板设计。此外，由于移位寄存器ASG结合了IGZO晶体管和LTPS晶体管，因此，可以使得移位寄存器ASG具有较强的驱动能力和低功耗等特点。且经验证，该栅极驱动电路可以有效规避LTPS晶体管漏电的缺点。
此外，由于LTPS晶体管的阈值电压容易受到外界电场的影响，发生阈值电压的偏移，进而影响驱动信号输出端OUT的信号输出。经验证，本申请实施例提供的包括IGZO晶体管的栅极驱动电路，即便LTPS晶体管的阈值电压偏移量较大(阈值电压偏 移
Figure PCTCN2023070297-appb-000004
)，驱动信号输出端OUT仍旧可以输出比较稳定的波形，为工艺提供一定的容限误差。
为详细说明该有益效果，下面通过与相关技术进行对比来说明。
图20均示出了相关技术与本申请实施例的对比仿真图，其中，横坐标为时间，纵坐标为仿真时驱动信号输出端OUT输出的信号。
图20中的四个仿真结果由上到下依次为：相关技术的LTPS晶体管的阈值电压偏移0V时，驱动信号输出端OUT的信号；相关技术的LTPS晶体管的阈值电压偏移-2.5V时，驱动信号输出端OUT的信号；本申请实施例的LTPS晶体管的阈值电压偏移0V时，驱动信号输出端OUT的信号；本申请实施例的的LTPS晶体管的阈值电压偏移-2.5V时，驱动信号输出端OUT的信号。由图20可知，当相关技术和本申请实施例的LTPS晶体管的阈值电压均偏移0V时，相关技术和本申请实施例驱动信号输出端的输出的信号均正常，但是，当相关技术和本申请实施例的LTPS晶体管的阈值电压均偏移-2.5V时，相关技术输出的信号异常，即相关技术的移位寄存器失效，而本申请实施例输出的信号仍然正常。
由此可见，本申请实施例提供的包括IGZO晶体管的栅极驱动电路在LTPS阈值电压偏移
Figure PCTCN2023070297-appb-000005
时，电路作为第一扫描驱动电路仍旧可以输出比较稳定的波形，为工艺提供一定的容限误差。
以上是以某批次的晶体管特性为例说明，旨在表述本提案可以容忍的阈值电压偏移范围更强，留给工艺窗口的容忍度更高。实际可容忍的偏移值不局限于此。
同样，当栅极驱动电路为第一扫描驱动电路时，第一扫描驱动电路的移位寄存器ASG支撑脉宽调制。
以上所述，以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (16)

  1. 一种移位寄存器，其特征在于，包括：
    节点控制模块，与第一电平信号接收端、第二电平信号接收端、第一时钟信号端、第二时钟信号端、第一节点和第二节点电连接；
    输入模块，与所述第二时钟信号端、触发信号输入端和所述第二节点电连接；
    稳压模块，与所述第二节点、所述第二时钟信号端和第三节点电连接；
    输出模块，与所述第一电平信号接收端、所述第二电平信号接收端、所述第一节点、所述第三节点和驱动信号输出端电连接；
    所述输入模块用于接收所述触发信号输入端的输入信号，并响应于所述第二时钟信号端接收的第二时钟信号而控制所述第二节点的信号；
    所述节点控制模块用于接收所述第一电平信号接收端接收的第一电平信号和所述第二电平信号接收端接收的第二电平信号，并响应于所述第二节点的信号、所述第一时钟信号端接收的第一时钟信号和所述第二时钟信号端接收的第二时钟信号，控制所述第一节点的信号；
    所述输出模块用于接收所述第二电平信号接收端接收的第二电平信号，并响应于所述第一节点的信号，控制所述驱动信号输出端输出的信号；或者，所述输出模块用于接收所述第一电平信号接收端的第一电平信号，并响应于所述第三节点的信号，控制所述驱动信号输出端输出的信号；
    所述稳压模块用于接收所述第二节点的信号，并响应于所述第二时钟信号端接收的所述第二时钟信号，控制所述第三节点的信号；
    其中，所述第一电平信号为低电平信号，所述第二电平信号为高电平信号；当所述驱动信号输出端输出的信号为低电平信号时，所述第三节点的信号的电位小于所述第一电平信号接收端接收的第一电平信号的电位；
    所述节点控制模块包括至少一个有源层为氧化物半导体的晶体管；所述输入模块、所述稳压模块和所述输出模块中的至少一者中包括至少一个有源层为硅的晶体管。
  2. 根据权利要求1所述的移位寄存器，其特征在于，所述节点控制模块包括：
    第一控制单元，与所述第一电平信号接收端、所述第一时钟信号端、所述第二时钟信号端、所述第一节点和所述第二节点电连接；
    第二控制单元，与所述第二电平信号接收端、所述第一节点和所述第二节点电连接；
    所述第一控制单元用于接收所述第一电平信号接收端的第一电平信号，并响应于所述第二节点的信号、所述第一时钟信号端接收的第一时钟信号和所述第二时钟信号端接收的所述第二时钟信号，控制所述第一节点的信号；或者，所述第二控制单元用于接收所述第二电平信号接收端接收的第二电平信号，并响应于所述第二节点的信号，控制所述第一节点的信号。
  3. 根据权利要求2所述的移位寄存器，其特征在于，所述第一控制单元包括至少一个有源层为氧化物半导体的晶体管。
  4. 根据权利要求1所述的移位寄存器，其特征在于，所述移位寄存器还包括：
    保护模块，位于所述第二节点和所述第三节点之间，以及位于所述第二节点与所述稳压模块之间，且与所述第一电平信号接收端电连接；
    所述保护模块用于阻止所述第三节点的信号传输至所述第二节点。
  5. 根据权利要求1所述的移位寄存器，其特征在于，所述输入模块包括第一晶体管；所述第一晶体管的栅极与所述第二时钟信号端电连接，所述第一晶体管的第一极与所述触发信号输入端电连接，所述第一晶体管的第二极与所述第二节点电连接。
  6. 根据权利要求3所述的移位寄存器，其特征在于，所述第一控制单元包括第二晶体管、第三晶体管和第四晶体管；
    所述第二晶体管的栅极与所述第一时钟信号端电连接，所述第二晶体管的第一极与所述第一电平信号接收端电连接，所述第二晶体管的第二极、所述第四晶体管的栅极以及所述第三晶体管的第二极耦合于第四节点；
    所述第三晶体管的栅极与所述第二节点电连接，所述第三晶体管的第一极与所述第二时钟信号端电连接；
    所述第四晶体管的第一极与所述第一电平信号接收端电连接，所述第四晶体管的第二极与所述第一节点电连接。
  7. 根据权利要求6所述的移位寄存器，其特征在于，所述第二晶体管、所述第三晶体管和所述第四晶体管均为有源层为氧化物半导体的晶体管。
  8. 根据权利要求2所述的移位寄存器，其特征在于，所述第二控制单元包括第五晶体管；所述第五晶体管的栅极与第二节点电连接，所述第五晶体管的第一极与所述第二电平信号接收端电连接，所述第五晶体管的第二极与所述第一节点电连接。
  9. 根据权利要求4所述的移位寄存器，其特征在于，所述保护模块包括第六晶体管；所述第六晶体管的第一极与所述第二节点电连接，所述第六晶体管的栅极与所述第一电平信号接收端电连接，所述第六晶体管的第二极分别与所述第三节点和所述稳压模块电连接。
  10. 根据权利要求1所述的移位寄存器，其特征在于，所述稳压模块包括第七晶体管和第一电容；
    所述第七晶体管的栅极与所述第三节点电连接，所述第七晶体管的第一极与所述第一时钟信号端电连接，所述第七晶体管的第二极与所述第一电容的第二极电连接，所述 第一电容的第一极分别与所述第三节点和所述第二节点电连接。
  11. 根据权利要求1所述的移位寄存器，其特征在于，所述输出模块包括第二电容、第八晶体管和第九晶体管；
    所述第八晶体管的栅极、所述第二电容的第一极均与所述第一节点电连接，所述第八晶体管的第一极、所述第二电容的第二极均与所述第二电平信号接收端电连接，所述第八晶体管的第二极、所述第九晶体管的第二极均与所述驱动信号输出端电连接，所述第九晶体管的栅极与所述第三节点电连接，所述第九晶体管的第一极与所述第一电平信号接收端电连接。
  12. 根据权利要求1所述的移位寄存器，其特征在于，所述有源层为氧化物半导体的晶体管为N型晶体管；所述有源层为硅的晶体管为P型晶体管。
  13. 一种栅极驱动电路，其特征在于，包括相互级联的N个如权利要求1-12任一项所述的移位寄存器，N≥2。
  14. 一种显示面板，其特征在于，包括至少一个如权利要求13所述的栅极驱动电路。
  15. 根据权利要求14所述的显示面板，其特征在于，包括至少两个栅极驱动电路，其中一个栅极驱动电路为发光控制驱动电路，另一个栅极驱动电路为扫描驱动电路；
    所述发光控制驱动电路电连接的时钟信号线复用为所述扫描驱动电路的时钟信号线。
  16. 一种电子设备，其特征在于，包括如权利要求14或15所述的显示面板。
PCT/CN2023/070297 2022-04-27 2023-01-04 移位寄存器、栅极驱动电路、显示面板及电子设备 WO2023207216A1 (zh)

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160217870A1 (en) * 2015-01-26 2016-07-28 Everdisplay Optronics (Shanghai) Limited Shift register unit, gate drive circuit and display panel
CN110689848A (zh) * 2019-12-10 2020-01-14 京东方科技集团股份有限公司 显示装置和驱动方法
CN110739020A (zh) * 2019-10-28 2020-01-31 昆山国显光电有限公司 移位寄存器和显示面板
CN112397008A (zh) * 2020-11-11 2021-02-23 武汉华星光电半导体显示技术有限公司 Goa电路及显示面板
CN112838109A (zh) * 2020-08-28 2021-05-25 京东方科技集团股份有限公司 显示基板及其制作方法、显示装置
CN113889022A (zh) * 2021-10-27 2022-01-04 合肥维信诺科技有限公司 移位寄存器、显示面板和显示装置
CN113920924A (zh) * 2021-10-19 2022-01-11 京东方科技集团股份有限公司 显示基板及其驱动方法、显示装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10395612B2 (en) * 2015-12-03 2019-08-27 Innolux Corporation Driver circuit
CN109616056A (zh) * 2018-08-24 2019-04-12 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路和显示装置
CN113096607A (zh) * 2019-12-23 2021-07-09 深圳市柔宇科技股份有限公司 像素扫描驱动电路、阵列基板与显示终端
CN111754915B (zh) * 2020-06-29 2022-10-11 昆山国显光电有限公司 移位寄存器、发光控制电路和显示面板
CN113421604A (zh) * 2021-06-22 2021-09-21 京东方科技集团股份有限公司 移位寄存器、控制方法、栅极驱动电路和显示装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160217870A1 (en) * 2015-01-26 2016-07-28 Everdisplay Optronics (Shanghai) Limited Shift register unit, gate drive circuit and display panel
CN110739020A (zh) * 2019-10-28 2020-01-31 昆山国显光电有限公司 移位寄存器和显示面板
CN110689848A (zh) * 2019-12-10 2020-01-14 京东方科技集团股份有限公司 显示装置和驱动方法
CN112838109A (zh) * 2020-08-28 2021-05-25 京东方科技集团股份有限公司 显示基板及其制作方法、显示装置
CN112397008A (zh) * 2020-11-11 2021-02-23 武汉华星光电半导体显示技术有限公司 Goa电路及显示面板
CN113920924A (zh) * 2021-10-19 2022-01-11 京东方科技集团股份有限公司 显示基板及其驱动方法、显示装置
CN113889022A (zh) * 2021-10-27 2022-01-04 合肥维信诺科技有限公司 移位寄存器、显示面板和显示装置

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