WO2023197373A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2023197373A1
WO2023197373A1 PCT/CN2022/088972 CN2022088972W WO2023197373A1 WO 2023197373 A1 WO2023197373 A1 WO 2023197373A1 CN 2022088972 W CN2022088972 W CN 2022088972W WO 2023197373 A1 WO2023197373 A1 WO 2023197373A1
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WO
WIPO (PCT)
Prior art keywords
layer
base substrate
area
display panel
opening
Prior art date
Application number
PCT/CN2022/088972
Other languages
English (en)
French (fr)
Inventor
周坤
钟平
吴绍静
Original Assignee
武汉华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to KR1020227026260A priority Critical patent/KR20230147515A/ko
Priority to JP2023514107A priority patent/JP2024518208A/ja
Priority to US17/779,813 priority patent/US20230329049A1/en
Publication of WO2023197373A1 publication Critical patent/WO2023197373A1/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/50—OLEDs integrated with light modulating elements, e.g. with electrochromic elements, photochromic elements or liquid crystal elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks

Definitions

  • the present application relates to the field of display technology, and in particular, to a display panel and a display device.
  • FIAA Fan-out in AA, fan-out wiring is located in the display area
  • FIAA technology is a new layout method that can effectively reduce the lower border of the panel.
  • multi-layer connection wiring design is introduced to squeeze out wiring space for fan-out wiring.
  • the metal wiring density in the fan-out display area is easily different from that in the normal display area.
  • Embodiments of the present application provide a display panel and a display device to solve the problem that in existing display panels and display devices, the metal wiring density in the fan-out display area is different from the metal wiring density in the normal display area, resulting in fan-out display. There is a technical problem with the visual display mura phenomenon in the normal display area and the normal display area.
  • the present application provides a display panel, which includes a normal display area and a fan-out display area.
  • the fan-out display area is located on one side of the normal display area.
  • the fan-out display area includes a display panel pointing from the normal display area to the
  • the direction of the fan-out display area is a first area and a second area arranged in sequence; the display panel includes:
  • a driving circuit layer is provided on one side of the base substrate.
  • the driving circuit layer includes a plurality of pixel driving circuit units and a plurality of fan-out lines.
  • the pixel driving circuit units are located in the normal display area and the first area, the fan-out wiring is located in the second area, wherein the density of the pixel driving circuit units located in the first area is greater than the density of the pixel driving circuit units located in the normal display area;
  • connection wiring layer is provided on the side of the driving circuit layer away from the base substrate, and each of the connection wiring layers includes a plurality of connection wirings;
  • a plurality of anodes are provided on a side of the connection wiring layer away from the base substrate, and the pixel driving circuit unit is electrically connected to the corresponding anode through the connection wiring;
  • a pixel definition layer is provided on a side of the connection wiring layer away from the base substrate, the pixel definition layer includes a plurality of first openings, and the first openings expose at least part of the anode;
  • a luminescent layer disposed in the first opening
  • the display panel further includes a shielding layer, the pixel definition layer and the shielding layer are made of the same kind of light-shielding material, and the shielding layer is disposed on a side of the pixel definition layer away from the base substrate, and the The shielding layer includes a plurality of second openings, and the second openings are arranged corresponding to the first openings.
  • the orthographic projection of the second opening on the base substrate covers the orthographic projection of the first opening on the base substrate.
  • the ratio of the orthographic projection area of the second opening on the base substrate to the orthographic projection area of the first opening on the base substrate ranges from 1 to 1.5.
  • the orthographic projection of the first opening on the base substrate covers the orthographic projection of the second opening on the base substrate.
  • the ratio of the orthographic projection area of the second opening on the base substrate to the orthographic projection area of the first opening on the base substrate ranges from 0.8 to 1.
  • the luminescent layer covers the side walls and bottom of the second opening.
  • the thickness of the shielding layer in a direction perpendicular to the base substrate is 1 micron to 1.5 micron.
  • the material of the shielding layer includes a black matrix.
  • the display panel further includes a cathode, and the blocking layer is disposed between the cathode and the pixel definition layer.
  • the present application provides a display panel, which includes a normal display area and a fan-out display area.
  • the fan-out display area is located on one side of the normal display area.
  • the fan-out display area includes a display panel pointing from the normal display area to the
  • the direction of the fan-out display area is a first area and a second area arranged in sequence; the display panel includes:
  • a driving circuit layer is provided on one side of the base substrate.
  • the driving circuit layer includes a plurality of pixel driving circuit units and a plurality of fan-out lines.
  • the pixel driving circuit units are located in the normal display area and the first area, the fan-out wiring is located in the second area, wherein the density of the pixel driving circuit units located in the first area is greater than the density of the pixel driving circuit units located in the normal display area;
  • connection wiring layer is provided on the side of the driving circuit layer away from the base substrate, and each of the connection wiring layers includes a plurality of connection wirings;
  • a plurality of anodes are provided on a side of the connection wiring layer away from the base substrate, and the pixel driving circuit unit is electrically connected to the corresponding anode through the connection wiring;
  • a pixel definition layer is provided on a side of the connection wiring layer away from the base substrate, the pixel definition layer includes a plurality of first openings, and the first openings expose at least part of the anode;
  • a luminescent layer disposed in the first opening
  • the display panel further includes a shielding layer, the shielding layer is disposed on a side of the pixel definition layer away from the base substrate, the shielding layer includes a plurality of second openings, the second openings are connected to the The first opening is provided correspondingly.
  • the orthographic projection of the second opening on the base substrate covers the orthographic projection of the first opening on the base substrate.
  • the ratio of the orthographic projection area of the second opening on the base substrate to the orthographic projection area of the first opening on the base substrate ranges from 1 to 1.5.
  • the orthographic projection of the first opening on the base substrate covers the orthographic projection of the second opening on the base substrate.
  • the ratio of the orthographic projection area of the second opening on the base substrate to the orthographic projection area of the first opening on the base substrate ranges from 0.8 to 1.
  • the luminescent layer covers the side walls and bottom of the second opening.
  • the thickness of the shielding layer in a direction perpendicular to the base substrate is 1 micron to 1.5 micron.
  • the material of the shielding layer includes a black matrix.
  • the display panel further includes a cathode, and the blocking layer is disposed between the cathode and the pixel definition layer.
  • connection wiring layers includes a first connection wiring layer and a second connection wiring layer
  • the display panel further includes a third connection wiring layer that is sequentially stacked in a direction away from the base substrate. a flat layer, a second flat layer and a third flat layer;
  • the first flat layer covers the side of the driving circuit layer away from the base substrate, and the first connection wiring layer is provided between the first flat layer and the second flat layer, so The second connection wiring layer is provided between the second planar layer and the third planar layer;
  • the driving circuit layer is electrically connected to the connection wiring in the first connection wiring layer through a via hole penetrating the first flat layer, and the first connection wiring layer passes through the second flat layer.
  • the via hole of the layer is electrically connected to the connection trace in the second connection trace layer, and the second connection trace layer is electrically connected to the anode through the via hole penetrating the third flat layer.
  • the present application provides a display device, including a display panel.
  • the display panel includes a normal display area and a fan-out display area.
  • the fan-out display area is located on one side of the normal display area.
  • the fan-out display area includes a The normal display area points to the first area and the second area arranged in sequence in the direction of the fan-out display area; the display panel includes:
  • a driving circuit layer is provided on one side of the base substrate.
  • the driving circuit layer includes a plurality of pixel driving circuit units and a plurality of fan-out lines.
  • the pixel driving circuit units are located in the normal display area and the first area, the fan-out wiring is located in the second area, wherein the density of the pixel driving circuit units located in the first area is greater than the density of the pixel driving circuit units located in the normal display area;
  • connection wiring layer is provided on the side of the driving circuit layer away from the base substrate, and each of the connection wiring layers includes a plurality of connection wirings;
  • a plurality of anodes are provided on a side of the connection wiring layer away from the base substrate, and the pixel driving circuit unit is electrically connected to the corresponding anode through the connection wiring;
  • a pixel definition layer is provided on a side of the connection wiring layer away from the base substrate, the pixel definition layer includes a plurality of first openings, and the first openings expose at least part of the anode;
  • a luminescent layer disposed in the first opening
  • the display panel further includes a shielding layer, the shielding layer is disposed on a side of the pixel definition layer away from the base substrate, the shielding layer includes a plurality of second openings, the second openings are connected to the The first opening is provided correspondingly.
  • a shielding layer is provided on the side of the pixel definition layer away from the base substrate, and the plurality of second openings of the shielding layer correspond to the first openings of the pixel definition layer Setting, the shielding layer can be used to block the light reflected by the metal traces, so that the light reflected from the metal traces in the fan-out display area and the normal display area is more uniform, which is beneficial to improving the screen-off and screen-on states due to the fan-out display area.
  • the density of metal traces is different from that of the normal display area, causing visibility mura in the fan-out display area and the normal display area.
  • Figure 1 is a schematic plan view of a display panel provided by an embodiment of the present application.
  • Figure 2 is a first cross-sectional structural diagram of the display panel along A-A in Figure 1;
  • Figure 3 is a partial top structural schematic view of the first opening and the second opening in the display panel in Figure 2;
  • Figure 4 is a second cross-sectional structural schematic diagram along A-A of the display panel in Figure 1;
  • Figure 5 is a partial top structural schematic view of the first opening and the second opening in the display panel in Figure 4;
  • Figure 6 is a third cross-sectional structural schematic diagram along A-A of the display panel in Figure 1;
  • Figure 7 is a partial top structural schematic view of the first opening and the second opening in the display panel in Figure 6;
  • Figure 8 is a schematic diagram of the fourth cross-sectional structure along A-A of the display panel in Figure 1;
  • Figure 9 is a partial top structural schematic view of the first opening and the second opening in the display panel in Figure 8;
  • FIG. 10 is a schematic diagram of the fifth cross-sectional structure along A-A of the display panel in FIG. 1 .
  • 100a normal display area
  • 100b fan-out display area
  • 1001b first area
  • 1002b second area
  • 104a Pixel driving circuit unit; 104b. Fan-out wiring; 1041. Active layer; 1042. First gate insulation layer; 1043. First gate layer; 1044. Second gate insulation layer; 1045. Second gate pole layer; 1046, the first interlayer dielectric layer; 1047, the second interlayer dielectric layer; 1048, the first source and drain metal layer; 1049, the fourth flat layer; 1050, the second source and drain metal layer;
  • V1 the first opening
  • V2 the second opening
  • FIG. 1 is a schematic plan view of a display panel provided by an embodiment of the present application.
  • FIG. 2 is a schematic cross-sectional structural view of a display panel provided by an embodiment of the present application.
  • the display panel provided by the embodiment of the present application includes a normal display area 100a and a fan-out display area 100b.
  • the fan-out display area 100b is provided on one side of the normal display area 100a.
  • the fan-out display area 100b includes a The normal display area 100a points to the first area 1001b and the second area 1002b arranged in sequence in the direction of the fan-out display area 100b; the display panel includes a base substrate 101, a driving circuit layer 104, a connecting wiring layer, a plurality of Anode 110, pixel definition layer 111 and light emitting layer 113.
  • the fan-out display area 100b is arranged adjacent to the normal display area 100a, and the fan-out display area 100b can be arranged at the edge of the display panel. Further, in the embodiment of the present application, the fan-out display Area 100b is provided on the lower edge of the display panel.
  • the drive circuit layer 104 is disposed on one side of the base substrate 101.
  • the drive circuit layer 104 includes a plurality of pixel drive circuit units 104a and a plurality of fan-out traces 104b.
  • the pixel drive circuit unit 104a is located on the normal The display area 100a and the first area 1001b, the fan-out trace 104b is located in the second area 1002b.
  • At least one layer of the connection wiring layer is disposed on the side of the driving circuit layer 104 away from the base substrate 101 , and each layer of the connection wiring layer includes a plurality of connection wirings 1081 .
  • a plurality of anodes 110 are disposed on a side of the top connection wiring layer away from the base substrate 101 , and the pixel driving circuit unit 104a is electrically connected to the corresponding anode 110 through the connection wiring 1081 .
  • the pixel definition layer 111 is disposed on a side of the connection wiring layer away from the base substrate 101.
  • the pixel definition layer 111 includes a plurality of first openings V1, and the first openings V1 expose at least part of the pixel definition layer 111.
  • the anode 110 is described.
  • the light-emitting layer 113 is disposed in the first opening V1.
  • the display panel further includes a shielding layer 112.
  • the shielding layer 112 is disposed on a side of the pixel definition layer 111 away from the base substrate 101.
  • the shielding layer 112 includes a plurality of second openings V2, so The second opening V2 is provided corresponding to the first opening V1.
  • the spacing between two adjacent light-emitting pixels in the display area of the display panel in the prior art is equal, that is, the pixel density everywhere in the display area is equal, because each light-emitting pixel is driven by the corresponding pixel
  • the circuit units 104a are electrically connected correspondingly. Therefore, the density of the pixel driving circuit units 104a in the display area of the display panel in the related art is equal, and the spacing between two adjacent pixel driving circuit units 104a is equal.
  • the display panel of the present application includes a normal display area 100a and a fan-out display area 100b.
  • the position of each luminescent pixel in the fan-out display area 100b and the spacing between two adjacent luminescent pixels are different from those in the normal display area 100a. are consistent, that is, the pixel density of the fan-out display area 100b is the same as the pixel density of the normal display area 100a.
  • the pixel driving circuit unit 104a located in the fan-out display area 100b is electrically connected to the corresponding anode 110 through the connecting wire 1081, so as to To drive the corresponding light-emitting pixels located in the fan-out display area 100b to emit light, the arrangement of the connection wiring layer can be used without changing the original position of the light-emitting pixels in the fan-out display area 100b.
  • the pixel driving circuit units 104a in the fan-out display area 100b are all concentrated in the first area 1001b of the fan-out display area 100b, and the second area 1002b is not provided with any pixel driving The circuit unit 104a, therefore, the second area 1002b can be used to place the fan-out trace 104b.
  • the fan-out traces 104b in the application can be placed in the display area, so that the area of the display area is increased and the area of the non-display area is reduced, which is conducive to further realizing narrow borders and full-screen technology.
  • the distance between two adjacent pixel driving circuit units 104a located in the fan-out display area 100b can be compressed, or by reducing the pixels located in the fan-out display area 100b.
  • the size of the driving circuit unit 104a reduces the overall space occupied by all the pixel driving circuit units 104a located in the fan-out display area 100b, so that in the fan-out display area 100b, the driving circuit layer 104 can Part of the space is squeezed out for placing the fan-out trace 104b.
  • other methods can also be used, and this application does not limit this.
  • the pixel driving circuit units 104a in the fan-out display area 100b in the present application are all concentrated in the first area 1001b of the fan-out display area 100b, resulting in that they are located in the first area.
  • the density of the pixel driving circuit unit 104a of 1001b is greater than the density of the pixel driving circuit unit 104a located in the normal display area 100a, and because the pixel driving circuit unit 104a includes a plurality of metal wirings, the The metal wiring density of the first area 1001b is greater than the metal wiring density of the normal display area 100a.
  • the fan-out trace 104b is a metal trace and is newly introduced to the fan-out display.
  • the metal traces in the area 100b secondly, due to the arrangement space limitation, the density of the connection traces 1081 in the fan-out display area 100b is greater than that of the connection traces 1081 in the normal display area 100a. Density, the connection traces 1081 are transparent metal traces. Therefore, the metal wiring density of the fan-out display area 100b in this application is greater than the metal wiring density of the normal display area 100a. The difference in metal wiring density may easily cause the fan-out display area 100b to be different from the normal display area 100a. The visibility mura phenomenon occurs in the display area 100a.
  • the shielding layer 112 is provided on the side of the pixel definition layer 111 away from the base substrate 101 , and the plurality of second openings V2 of the shielding layer 112 are in contact with the pixel definition layer 112 .
  • the first opening V1 of the layer 111 is provided correspondingly, and the blocking layer 112 can be used to block the light reflected by the metal traces, so that the fan-out display area 100b and the normal display area 100a are separated from the metal traces.
  • the light reflected by the line is relatively uniform, which is beneficial to improving the fan-out problem caused by the difference between the metal wiring density of the fan-out display area 100b and the metal wiring density of the normal display area 100a in the screen-off and screen-on states.
  • the visibility mura phenomenon occurs in the out-display area 100b and the normal display area 100a.
  • the display area of the display panel is composed of the normal display area 100a and the fan-out display area 100b. Both the normal display area 100a and the fan-out display area 100b have display functions.
  • the fan-out trace 104b is provided in the fan-out display area 100b.
  • the display panel also includes a non-display area (not shown in the figure), and the fan-out display area 100b is disposed on one side of the normal display area 100a. Specifically, the fan-out display area 100b is disposed on one side of the normal display area 100a. between the display area 100a and the non-display area.
  • the display panel further includes a driver chip.
  • the driver chip can also be disposed in the fan-out display area 100b. In this case, the non-display area can be omitted, so the display panel can realize Borderless and full screen.
  • the base substrate 101 is a flexible substrate, and the flexible substrate is generally an organic polymer material such as polyimide or polyethylene terephthalate.
  • a barrier layer 102 and a buffer layer 103 are arranged sequentially in a direction away from the base substrate 101 and are disposed between the base substrate 101 and the driving circuit layer 104.
  • the barrier layer 102 is used to block water and oxygen to prevent external water vapor or oxygen from corroding the display panel.
  • the material used in the barrier layer 102 includes one or more of silicon oxide, silicon nitride, silicon oxynitride and amorphous silicon. kind.
  • the buffer layer 103 mainly plays a role of buffering and protection.
  • the material used in the buffer layer 103 includes one or both of silicon nitride and silicon oxide.
  • the pixel driving circuit unit 104a includes a plurality of thin film transistors.
  • the thin film transistors may be thin film transistors with a dual-gate structure.
  • the thin film transistors include a thin film transistor along an edge away from the base substrate 101
  • the first source-drain metal layer 1048 passes through the second interlayer dielectric layer 1047, the first interlayer dielectric layer 1046, the second gate insulating layer 1044 and the first gate electrode.
  • the thin film transistor may also be a thin film transistor containing only one gate layer.
  • the thin film transistor may also have a top gate or bottom gate structure, which is not covered in this application. limit.
  • the anode 110 may adopt a laminated structure of ITO (Indium tin oxide, indium tin oxide)/Ag (silver)/ITO, where ITO has good water-blocking properties and can prevent water vapor or oxygen from passing through.
  • the anode 110 is diffused into the light-emitting layer 113, thereby preventing the light-emitting layer 113 from being corroded by water vapor or oxygen and causing black spots to appear on the display panel, thereby improving the display effect of the display panel.
  • the pixel definition layer 111 defines a plurality of first openings V1, and the first openings V1 are pixel openings.
  • the first openings V1 refer to effective light-emitting pixels.
  • the orthographic projection area of the first opening V1 on the base substrate 101 is the orthographic projection area of the light-emitting layer 113 on the base substrate 101 .
  • connection wiring layer includes two layers of connection wiring layers, specifically including a first connection wiring layer 106 and a second connection wiring layer 108.
  • the display panel also includes a A first flattening layer 105 , a second flattening layer 107 and a third flattening layer 109 are sequentially stacked in the direction of the base substrate 101 .
  • the first flat layer 105 covers the side of the driving circuit layer 104 away from the base substrate 101 , and the first connection wiring layer 106 is disposed on the first flat layer 105 and the second flat layer 105 .
  • the second connection wiring layer 108 is disposed between the second planarization layer 107 and the third planarization layer 109 .
  • the driving circuit layer 104 is electrically connected to the connection wiring 1081 in the first connection wiring layer 106 through a via hole that penetrates the first planar layer 105 , and the first connection wiring layer 106 passes through a through hole.
  • the via holes of the second flat layer 107 are electrically connected to the connection wires 1081 in the second connection wire layer 108 , and the second connection wire layer 108 passes through the third flat layer 109
  • the via hole is electrically connected to the corresponding anode 110 .
  • connection wiring layer is a transparent conductive layer
  • connection wiring 1081 is a transparent wiring
  • the material of the connection wiring 1081 is a transparent conductor material
  • the transparent conductor material includes indium tin oxide, indium oxide, oxide Any of indium zinc and silver nanowires.
  • connection wiring layer can also be three layers, four layers, five layers... or even more layers. This application does not limit this.
  • the display panel also needs A corresponding number of flat layers are provided for disposing between two adjacent layers of the connection wiring layers; specifically, the material of the flat layers includes transparent organic materials, and the transparent organic materials include polyimide and photoresist materials.
  • the thin film transistor can also adopt a double-layer source and drain metal layer design to reduce impedance.
  • the thin film transistor also includes a second source and drain metal layer 1050 and a fourth flat layer 1049.
  • Four flat layers 1049 cover the side of the first source-drain metal layer 1048 away from the base substrate 101, and the second source-drain metal layer 1050 is disposed on the fourth flat layer 1049 away from the substrate.
  • the first flat layer 105 covers the side of the second source and drain metal layer 1050 away from the base substrate 101, and the first source and drain metal layer 1048 passes through the
  • the via hole of the fourth planar layer 1049 is electrically connected to the second source and drain metal layer 1050, and the second source and drain metal layer 1050 is connected to the first source and drain metal layer 1050 through the via hole penetrating the first planar layer 105.
  • the connection traces 1081 in the connection trace layer 106 are electrically connected.
  • the fan-out wiring 104b is provided in the same layer as the first gate layer 1043 or the second gate layer 1045, and the fan-out wiring 104b and the first gate layer 1043 Or the second gate layer 1045 is prepared through the same process.
  • the thickness of the shielding layer 112 in the direction perpendicular to the base substrate 101 is 1 micron to 1.5 microns.
  • the thickness of the shielding layer 112 should not be too large or too small. Excessive thickness will cause The increase in the overall thickness of the display panel is contrary to the current trend of thinner and lighter displays. If it is too small, the light-shielding effect will be poor, which is not conducive to improving the visibility mura phenomenon.
  • the thickness of the shielding layer 112 in the direction perpendicular to the base substrate 101 may be 1 micron, 1.1 micron, 1.2 micron, 1.3 micron, 1.4 micron and 1.5 micron.
  • the thickness of the shielding layer 112 along the direction perpendicular to the base substrate 101 is 1.2 microns.
  • the material of the shielding layer 112 includes a black matrix.
  • the material of the shielding layer 112 may also be other light-shielding materials, which is not limited by this application.
  • the shielding layer 112 can be prepared and formed by plasma enhanced chemical vapor deposition (PECVD). In other embodiments, the shielding layer 112 may also be formed by chemical vapor deposition or atomic layer deposition.
  • PECVD plasma enhanced chemical vapor deposition
  • the shielding layer 112 may also be formed by chemical vapor deposition or atomic layer deposition.
  • Figure 3 is a partial top view structural diagram of the first opening and the second opening in the display panel in Figure 2;
  • Figure 4 is a display panel provided by an embodiment of the present application.
  • the second schematic cross-sectional structural diagram of FIG. 5 is a partial top structural schematic diagram of the first opening and the second opening in the display panel in FIG. 4 .
  • the orthographic projection of the second opening V2 on the base substrate 101 covers the orthographic projection of the first opening V1 on the base substrate 101 .
  • the shielding layer 112 can shield part of the lower metal traces, because the orthographic projection of the shielding layer 112 on the base substrate 101 and the light-emitting layer 113 on the base substrate 101 There is no overlapping of the orthographic projections on the luminescent layer 113 . Therefore, in this embodiment, the visibility mura phenomenon is significantly improved without affecting the luminous effect of the luminescent layer 113 .
  • the orthographic projection shape of the second opening V2 on the base substrate 101 is the same as the orthographic projection shape of the corresponding first opening V1 on the base substrate 101 , that is, , the orthographic projection shape of the second opening V2 on the base substrate 101 is the same as the corresponding orthographic projection shape of the light-emitting layer 113 on the base substrate 101 .
  • Each pixel unit 115 is arranged in a Peral (pearl) type arrangement as an example for illustration.
  • Each pixel unit 115 includes two red luminescent pixels, two blue luminescent pixels and four green luminescent pixels.
  • the shape of the red light-emitting pixel and the blue light-emitting pixel is an octagon, and the shape of the green light-emitting pixel is an ellipse. Then, in the embodiment of the present application, the second opening V2 is in the base substrate 101
  • the orthographic projection shape on is an octagon or ellipse.
  • the pixel units 115 can also be arranged in other ways, and the orthographic projection shape of the light-emitting layer 113 on the base substrate 101 can also be rectangular, circular, or other polygonal shapes, etc.
  • the shape of the second opening V2 may also be different from the shape of the first opening V1. This application does not limit this.
  • the second opening V2 may be configured according to the arrangement and shape of the first opening V1. Two openings V2 are designed.
  • the ratio of the orthographic projection area of the second opening V2 on the base substrate 101 to the orthographic projection area of the first opening V1 on the base substrate 101 ranges from 1 to 1.5.
  • this embodiment includes two situations.
  • the first situation is that, please refer to FIG. 2 and FIG. 3 , the orthographic projection edge of the second opening V2 on the substrate 101 and the There is a gap in the orthographic projection edge of the first opening V1 on the base substrate 101 , that is to say, the orthographic projection area of the second opening V2 on the base substrate 101 is larger than the orthographic projection area of the first opening V1 on the base substrate 101 .
  • the orthographic projection area on the base substrate 101 that is, the orthographic projection area of the second opening V2 on the base substrate 101 and the orthographic projection area of the first opening V1 on the base substrate 101
  • the ratio is greater than 1 and less than or equal to 1.5.
  • the second opening V2 is on the base substrate 101.
  • the orthographic projection edge of the first opening V1 on the base substrate 101 completely overlaps with the orthographic projection edge of the second opening V2 on the base substrate 101. That is to say, the orthographic projection area of the second opening V2 on the base substrate 101 is equal to the The orthographic projection area of the first opening V1 on the base substrate 101, that is, the orthographic projection area of the second opening V2 on the base substrate 101 is the same as the orthographic projection area of the first opening V1 on the substrate.
  • the ratio of the orthogonal projected areas on the substrate 101 is equal to 1. It can be understood that in the second case, compared with the first case, the area of the lower metal trace blocked by the shielding layer 112 is larger, which has a better effect on improving visibility mura.
  • FIG. 6 is a schematic diagram of the third cross-sectional structure of the display panel provided by the embodiment of the present application.
  • FIG. 7 is a first opening and a third opening in the display panel in FIG. 6 .
  • the shielding layer 112 can block almost all lower metal traces, because the orthographic projection of the shielding layer 112 on the base substrate 101 is different from the orthographic projection of the shielding layer 112 on the base substrate 101.
  • the ratio of the orthographic projection area of the second opening V2 on the base substrate 101 to the orthographic projection area of the first opening V1 on the base substrate 101 ranges from 0.8 to 1.
  • the orthographic projection area of the second opening V2 on the base substrate 101 cannot be too small, otherwise the luminous effect of the luminescent layer 113 of the fan-out display area 100b will be greatly reduced, resulting in the fan-out display area
  • the display effect difference between 100b and the normal display area 100a is too large, resulting in reduced display uniformity.
  • FIG. 8 is a schematic diagram of the fourth cross-sectional structure of the display panel provided by the embodiment of the present application.
  • FIG. 9 is the first schematic diagram of the display panel in FIG. 8 .
  • the luminescent layer 113 covers the sidewalls and bottom of the second opening V2, that is, the blocking layer 112 is equivalent to playing the role of the pixel definition layer 111, and the second opening V2 is equivalent to a pixel opening.
  • the The light-emitting layer 113 completely covers the sidewalls and bottom of the second opening V2. Since the height of the blocking layer 112 is greater than the height of the pixel definition layer 111, that is, the height of the second opening V2 is greater than the height of the second opening V2. The height of an opening V1. Therefore, in this embodiment, the luminescent layer 113 is disposed in the second opening V2, which is equivalent to increasing the effective luminescent area of the luminescent layer 113, which is beneficial to improving the luminescent layer 113. The light-emitting effect of the light-emitting layer 113 is not affected, thereby achieving the purpose of improving the visibility mura.
  • Figure 10 is a schematic diagram of the fifth cross-sectional structure of a display panel provided by an embodiment of the present application; the difference between Figure 10 and Figure 2 is that the pixel definition layer 111 and the The shielding layer 112 uses the same kind of light-shielding material.
  • the material of the pixel definition layer 111 is also a black matrix. It can be understood that the pixel definition layer 111 not only plays a role in defining the light-emitting layer 113, but also plays the same role as the blocking layer 112.
  • the pixel definition layer 111 can block most of the The pixel driving circuit unit 104a, the fan-out wiring 104b and the connecting wiring 1081 can further improve visibility mura; in addition, compared with Figure 2, the thickness of the shielding layer 112 in this embodiment
  • the shielding layer 112 can be set smaller or even does not need to be set, which can solve the technical problem of the present application and help achieve the thinning and lightness of the display panel.
  • the display panel further includes a cathode 114, and the shielding layer 112 is disposed between the cathode 114 and the pixel definition layer 111.
  • the cathode 114 covers The pixel definition layer 111, the shielding layer 112 and the luminescent layer 113; in Figures 4, 6 and 8, the cathode 114 covers the shielding layer 112 and the luminescent layer 113.
  • the display panel further includes an electron injection layer, an electron transport layer, a hole transport layer and a hole injection layer that are sequentially arranged in a direction away from the base substrate 101.
  • the electron injection layer, The electron transport layer, the hole transport layer and the hole injection layer are provided in the first opening V1, and the electron injection layer and the electron transport layer are provided in the light emitting layer 113 and the Between the anode 110 , the hole transport layer and the hole injection layer are disposed between the light emitting layer 113 and the cathode 114 .
  • the display panel further includes an encapsulation layer, which covers the side of the cathode 114 away from the base substrate 101 and is used to encapsulate the light-emitting layer 113 to avoid exposure to the external environment. Water vapor and oxygen intrude into the light-emitting layer 113 and cause damage.
  • the encapsulation layer may be film encapsulated, and the encapsulation layer may be a single layer or a multi-layer encapsulation stack.
  • the encapsulation layer adopts an inorganic/organic/inorganic multi-layer encapsulation stack, which is beneficial to improving the encapsulation effect.
  • the display panel further includes a touch layer.
  • the touch layer is disposed on a side of the encapsulation layer away from the base substrate 101.
  • the touch type of the touch layer may be: Self-capacitance or mutual capacitance.
  • the touch type of the touch layer can be selected according to actual conditions, and this application does not limit this.
  • the display panel further includes a polarizer and a cover plate.
  • the polarizer and the dry plate are stacked in sequence and disposed on the side of the touch layer away from the base substrate 101.
  • the polarizer The cover plate is attached to the side surface of the touch layer away from the base substrate 101 through optical glue.
  • the cover plate is attached to the side surface of the polarizer away from the base substrate 101 through optical glue.
  • An embodiment of the present application also provides a display device, which includes the display panel in the above embodiment.
  • the display device includes fixed terminals such as televisions and desktop computers, mobile terminals such as mobile phones and notebook computers, and wearable terminals.
  • Equipment such as bracelets, VR (virtual display) equipment, AR (augmented display) equipment.
  • An embodiment of the present application also provides a method for preparing a display panel.
  • the display panel includes a normal display area 100a and a fan-out display area 100b.
  • the fan-out display area 100b is disposed on one side of the normal display area 100a.
  • the fan-out display area 100b includes a first area 1001b and a second area 1002b sequentially arranged in the direction from the normal display area 100a to the fan-out display area 100b; the preparation method includes the following steps:
  • a driving circuit layer 104 is formed on one side of the base substrate 101.
  • the driving circuit layer 104 includes a plurality of pixel driving circuit units 104a and a plurality of fan-out lines 104b.
  • the plurality of pixel driving circuit units 104a are disposed on the The normal display area 100a and the first area 1001b, the plurality of fan-out traces 104b are provided in the second area 1002b, and the density of the pixel driving circuit unit 104a located in the first area 1001b is greater than that located in the normal display area 100a.
  • connection wiring layer is formed on the side of the driving circuit layer 104 away from the base substrate 101, and each connection wiring layer includes a plurality of connection wirings;
  • An anode 110 is formed on the side of the connection wiring layer away from the base substrate 101;
  • a pixel definition layer 111 is formed on the side of the connection wiring layer away from the base substrate 101.
  • the pixel definition layer 111 includes a plurality of first openings V1, and the first openings V1 expose at least part of the anode. 110;
  • the shielding layer 112 is formed on the side of the pixel definition layer 111 away from the base substrate 101 .
  • the shielding layer 112 includes a plurality of second openings V2 .
  • the second openings V2 and the first openings V1 Corresponding settings;
  • the light-emitting layer 113 is formed in the first opening V1.
  • a shielding layer is provided on the side of the pixel definition layer away from the base substrate, and a plurality of second openings of the shielding layer are provided corresponding to the first openings of the pixel definition layer.
  • the shielding layer can be used to block the light reflected by the metal traces, so that the light reflected from the metal traces in the fan-out display area and the normal display area is more uniform, which is beneficial to improving the problem of the fan-out display area in the screen-off and screen-on states.
  • the difference between the density of metal traces and the density of metal traces in the normal display area causes visibility mura in the fan-out display area and the normal display area.

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Abstract

一种显示面板及显示装置，显示面板包括正常显示区（100a）和扇出显示区（100b），扇出显示区（100b）包括第一区（1001b）和第二区（1002b）；显示面板的像素驱动电路单元（104a）位于正常显示区（100a）和第一区（1001b），扇出走线（104b）位于第二区（1002b）；在像素定义层（111）远离衬底基板（101）的一侧设置遮挡层（112），遮挡层（112）的第二开口（V2）与像素定义层（111）的第一开口（V1）对应设置，有利于改善可视性显示不均。

Description

显示面板及显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板及显示装置。
 背景技术
随着OLED面板技术发展，窄边框技术成为吸引用户群体的差异化技术。FIAA（Fanout in AA，扇出走线位于显示区）技术作为一种新的layout方式，可有效减小面板下边框。在FIAA技术中，引入多层连接走线设计来为扇出走线挤出布线空间，但在连接走线布线过程中，由于布线空间限制容易造成扇出显示区的金属走线密度与正常显示区的金属走线密度存在差异，密度不同容易导致从金属走线反射的光线不均匀，从而造成熄屏和亮屏状态下，扇出显示区和正常显示区出现可视性显示不均（mura）现象。
 技术问题
本申请实施例提供一种显示面板及显示装置，以解决现有的显示面板及显示装置中，扇出显示区的金属走线密度与正常显示区的金属走线密度存在差异，导致扇出显示区和正常显示区出现可视性显示mura现象的技术问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请提供一种显示面板，包括正常显示区和扇出显示区，所述扇出显示区位于所述正常显示区一侧，所述扇出显示区包括沿自所述正常显示区指向所述扇出显示区的方向依次排列的第一区和第二区；所述显示面板包括：
衬底基板；
驱动电路层，设置于所述衬底基板一侧，所述驱动电路层包括多个像素驱动电路单元及多条扇出走线，所述像素驱动电路单元位于所述正常显示区和所述第一区，所述扇出走线位于所述第二区，其中，位于所述第一区的所述像素驱动电路单元的密度大于位于所述正常显示区的所述像素驱动电路单元的密度；
至少一连接走线层，设置于所述驱动电路层远离所述衬底基板的一侧，每一所述连接走线层包括多条连接走线；
多个阳极，设置于所述连接走线层远离所述衬底基板的一侧，所述像素驱动电路单元通过所述连接走线与对应的所述阳极电连接；
像素定义层，设置于所述连接走线层远离所述衬底基板的一侧，所述像素定义层包括多个第一开口，所述第一开口裸露出至少部分所述阳极；以及
发光层，设置于所述第一开口内；
其中，所述显示面板还包括遮挡层，所述像素定义层和所述遮挡层采用同种遮光材料，所述遮挡层设置于所述像素定义层远离所述衬底基板的一侧，所述遮挡层包括多个第二开口，所述第二开口与所述第一开口对应设置。
根据本申请提供的显示面板，所述第二开口在所述衬底基板上的正投影覆盖所述第一开口在所述衬底基板上的正投影。
根据本申请提供的显示面板，所述第二开口在所述衬底基板上的正投影面积与所述第一开口在所述衬底基板上的正投影面积的比值范围为1~1.5。
根据本申请提供的显示面板，所述第一开口在所述衬底基板上的正投影覆盖所述第二开口在所述衬底基板上的正投影。
根据本申请提供的显示面板，所述第二开口在所述衬底基板上的正投影面积与所述第一开口在所述衬底基板上的正投影面积的比值范围为0.8~1。
根据本申请提供的显示面板，所述发光层覆盖所述第二开口的侧壁和底部。
根据本申请提供的显示面板，所述遮挡层沿垂直于所述衬底基板方向的厚度为1微米~1.5微米。
根据本申请提供的显示面板，所述遮挡层的材料包括黑矩阵。
根据本申请提供的显示面板，所述显示面板还包括阴极，所述遮挡层设置于所述阴极和所述像素定义层之间。
本申请提供一种显示面板，包括正常显示区和扇出显示区，所述扇出显示区位于所述正常显示区一侧，所述扇出显示区包括沿自所述正常显示区指向所述扇出显示区的方向依次排列的第一区和第二区；所述显示面板包括：
衬底基板；
驱动电路层，设置于所述衬底基板一侧，所述驱动电路层包括多个像素驱动电路单元及多条扇出走线，所述像素驱动电路单元位于所述正常显示区和所述第一区，所述扇出走线位于所述第二区，其中，位于所述第一区的所述像素驱动电路单元的密度大于位于所述正常显示区的所述像素驱动电路单元的密度；
至少一连接走线层，设置于所述驱动电路层远离所述衬底基板的一侧，每一所述连接走线层包括多条连接走线；
多个阳极，设置于所述连接走线层远离所述衬底基板的一侧，所述像素驱动电路单元通过所述连接走线与对应的所述阳极电连接；
像素定义层，设置于所述连接走线层远离所述衬底基板的一侧，所述像素定义层包括多个第一开口，所述第一开口裸露出至少部分所述阳极；以及
发光层，设置于所述第一开口内；
其中，所述显示面板还包括遮挡层，所述遮挡层设置于所述像素定义层远离所述衬底基板的一侧，所述遮挡层包括多个第二开口，所述第二开口与所述第一开口对应设置。
根据本申请提供的显示面板，所述第二开口在所述衬底基板上的正投影覆盖所述第一开口在所述衬底基板上的正投影。
根据本申请提供的显示面板，所述第二开口在所述衬底基板上的正投影面积与所述第一开口在所述衬底基板上的正投影面积的比值范围为1~1.5。
根据本申请提供的显示面板，所述第一开口在所述衬底基板上的正投影覆盖所述第二开口在所述衬底基板上的正投影。
根据本申请提供的显示面板，所述第二开口在所述衬底基板上的正投影面积与所述第一开口在所述衬底基板上的正投影面积的比值范围为0.8~1。
根据本申请提供的显示面板，所述发光层覆盖所述第二开口的侧壁和底部。
根据本申请提供的显示面板，所述遮挡层沿垂直于所述衬底基板方向的厚度为1微米~1.5微米。
根据本申请提供的显示面板，所述遮挡层的材料包括黑矩阵。
根据本申请提供的显示面板，所述显示面板还包括阴极，所述遮挡层设置于所述阴极和所述像素定义层之间。
根据本申请提供的显示面板，至少一所述连接走线层包括第一连接走线层和第二连接走线层，所述显示面板还包括沿远离所述衬底基板方向依次层叠设置的第一平坦层、第二平坦层和第三平坦层；
所述第一平坦层覆于所述驱动电路层远离所述衬底基板的一侧，所述第一连接走线层设置于所述第一平坦层和所述第二平坦层之间，所述第二连接走线层设置于所述第二平坦层和所述第三平坦层之间；
所述驱动电路层通过贯穿所述第一平坦层的过孔与所述第一连接走线层中的所述连接走线电连接，所述第一连接走线层通过贯穿所述第二平坦层的过孔与所述第二连接走线层中的所述连接走线电连接，所述第二连接走线层通过贯穿所述第三平坦层的过孔与所述阳极电连接。
本申请提供一种显示装置，包括显示面板，所述显示面板包括正常显示区和扇出显示区，所述扇出显示区位于所述正常显示区一侧，所述扇出显示区包括沿自所述正常显示区指向所述扇出显示区的方向依次排列的第一区和第二区；所述显示面板包括：
衬底基板；
驱动电路层，设置于所述衬底基板一侧，所述驱动电路层包括多个像素驱动电路单元及多条扇出走线，所述像素驱动电路单元位于所述正常显示区和所述第一区，所述扇出走线位于所述第二区，其中，位于所述第一区的所述像素驱动电路单元的密度大于位于所述正常显示区的所述像素驱动电路单元的密度；
至少一连接走线层，设置于所述驱动电路层远离所述衬底基板的一侧，每一所述连接走线层包括多条连接走线；
多个阳极，设置于所述连接走线层远离所述衬底基板的一侧，所述像素驱动电路单元通过所述连接走线与对应的所述阳极电连接；
像素定义层，设置于所述连接走线层远离所述衬底基板的一侧，所述像素定义层包括多个第一开口，所述第一开口裸露出至少部分所述阳极；以及
发光层，设置于所述第一开口内；
其中，所述显示面板还包括遮挡层，所述遮挡层设置于所述像素定义层远离所述衬底基板的一侧，所述遮挡层包括多个第二开口，所述第二开口与所述第一开口对应设置。
 有益效果
本申请的有益效果为：本申请提供的显示面板及显示装置，通过在像素定义层远离衬底基板的一侧设置遮挡层，遮挡层的多个第二开口与像素定义层的第一开口对应设置，遮挡层可用于遮挡经金属走线反射的光线，使得扇出显示区与正常显示区从金属走线反射的光线较为均匀，有利于改善熄屏和亮屏状态下，因扇出显示区的金属走线密度与正常显示区的金属走线密度存在差异而造成扇出显示区和正常显示区出现可视性mura现象。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的显示面板的平面结构示意图；
图2是图1中的显示面板沿A-A的第一种截面结构示意图；
图3是图2中的显示面板中的第一开口和第二开口的局部俯视结构示意图；
图4是图1中的显示面板沿A-A的第二种截面结构示意图；
图5是图4中的显示面板中的第一开口和第二开口的局部俯视结构示意图；
图6是图1中的显示面板沿A-A的第三种截面结构示意图；
图7是图6中的显示面板中的第一开口和第二开口的局部俯视结构示意图；
图8是图1中的显示面板沿A-A的第四种截面结构示意图；
图9是图8中的显示面板中的第一开口和第二开口的局部俯视结构示意图；
图10是图1中的显示面板沿A-A的第五种截面结构示意图。
附图标记说明：
100a、正常显示区；100b、扇出显示区；1001b、第一区；1002b、第二区；
101、衬底基板；102、阻隔层；103、缓冲层；104、驱动电路层；105、第一平坦层；106、第一连接走线层；107、第二平坦层；108、第二连接走线层；1081、连接走线；109、第三平坦层；110、阳极；111、像素定义层；112、遮挡层；113、发光层；114、阴极；115、像素单元；
104a、像素驱动电路单元；104b、扇出走线；1041、有源层；1042、第一栅极绝缘层；1043、第一栅极层；1044、第二栅极绝缘层；1045、第二栅极层；1046、第一层间介质层；1047、第二层间介质层；1048、第一源漏极金属层；1049、第四平坦层；1050、第二源漏极金属层；
V1、第一开口；V2、第二开口。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。此外，应当理解的是，此处所描述的具体实施方式仅用于说明和解释本申请，并不用于限制本申请。在本申请中，在未作相反说明的情况下，使用的方位词如“上”和“下”通常是指装置实际使用或工作状态下的上和下，具体为附图中的图面方向；而“内”和“外”则是针对装置的轮廓而言的。
请参阅图1和图2，图1是本申请实施例提供的显示面板的平面结构示意图；图2是本申请实施例提供的显示面板的第一种截面结构示意图。本申请实施例提供的显示面板，包括正常显示区100a和扇出显示区100b，所述扇出显示区100b设置于所述正常显示区100a一侧，所述扇出显示区100b包括沿自所述正常显示区100a指向所述扇出显示区100b的方向依次排列的第一区1001b和第二区1002b；所述显示面板包括衬底基板101、驱动电路层104、连接走线层、多个阳极110、像素定义层111和发光层113。
所述扇出显示区100b与所述正常显示区100a相邻设置，所述扇出显示区100b可以设置于所述显示面板的边缘，进一步地，在本申请实施例中，所述扇出显示区100b设置于所述显示面板的下边缘。
所述驱动电路层104设置于所述衬底基板101一侧，所述驱动电路层104包括多个像素驱动电路单元104a及多条扇出走线104b，所述像素驱动电路单元104a位于所述正常显示区100a和所述第一区1001b，所述扇出走线104b位于所述第二区1002b。至少一层所述连接走线层设置于所述驱动电路层104远离所述衬底基板101的一侧，每一层所述连接走线层包括多条连接走线1081。多个阳极110设置于位于顶层的所述连接走线层远离所述衬底基板101的一侧，所述像素驱动电路单元104a通过所述连接走线1081与对应的所述阳极110电连接。所述像素定义层111设置于所述连接走线层远离所述衬底基板101的一侧，所述像素定义层111包括多个第一开口V1，所述第一开口V1裸露出至少部分所述阳极110。所述发光层113设置于所述第一开口V1内。
其中，所述显示面板还包括遮挡层112，所述遮挡层112设置于所述像素定义层111远离所述衬底基板101的一侧，所述遮挡层112包括多个第二开口V2，所述第二开口V2与所述第一开口V1对应设置。
可以理解的是，现有技术中的显示面板的显示区中的相邻两个发光像素之间的间距相等，即，显示区各处的像素密度相等，由于每一发光像素与对应的像素驱动电路单元104a对应电连接，因此，现有技术中的显示面板的显示区的各处的所述像素驱动电路单元104a的密度相等，相邻两个像素驱动电路单元104a之间的间距相等。
本申请的显示面板包括正常显示区100a和扇出显示区100b，所述扇出显示区100b中的每一发光像素的位置及相邻两个发光像素之间的间距与所述正常显示区100a均保持一致，即，所述扇出显示区100b的像素密度与所述正常显示区100a的像素密度相同。而本申请与现有技术的不同之处在于，本申请中位于所述扇出显示区100b的所述像素驱动电路单元104a通过所述连接走线1081与对应的所述阳极110电连接，以驱动位于所述扇出显示区100b中的对应的发光像素发光，所述连接走线层的设置，能够在不改变所述扇出显示区100b中的所述发光像素的原本位置的情况下，将所述扇出显示区100b中的所述像素驱动电路单元104a全部集中在所述扇出显示区100b的所述第一区1001b，而所述第二区1002b未设置有任何所述像素驱动电路单元104a，因此，所述第二区1002b可用于放置所述扇出走线104b，相较于现有技术中的将所述扇出走线104b设置于所述显示面板的非显示区，由于本申请中的所述扇出走线104b可放置于显示区，使得所述显示区的面积增大，所述非显示区的面积减小，从而有利于进一步实现窄边框和全面屏技术。
具体地，可通过压缩位于所述扇出显示区100b中的相邻两个所述像素驱动电路单元104a之间的间距，或者，通过减小位于所述扇出显示区100b中的所述像素驱动电路单元104a的尺寸，使得位于所述扇出显示区100b中的所有所述像素驱动电路单元104a所占据的整体空间缩小，从而在所述扇出显示区100b，所述驱动电路层104能够挤出部分空间用于放置所述扇出走线104b。当然地，也可采用其他方式，本申请对此不做限定。
由上可知，由于本申请中的所述扇出显示区100b中的所述像素驱动电路单元104a全部集中在所述扇出显示区100b的所述第一区1001b，导致位于所述第一区1001b的所述像素驱动电路单元104a的密度大于位于所述正常显示区100a的所述像素驱动电路单元104a的密度，又由于所述像素驱动电路单元104a包括多条金属走线，因此，所述第一区1001b的金属走线密度大于所述正常显示区100a的金属走线密度。
进一步地，第一，由于所述扇出走线104b设置于所述扇出显示区100b的所述第二区1002b，所述扇出走线104b为金属走线且为新引入至所述扇出显示区100b的金属走线；第二，由于排布空间限制，导致所述扇出显示区100b中的所述连接走线1081的密度大于所述正常显示区100a中的所述连接走线1081的密度，所述连接走线1081为透明金属走线。因此，本申请中的所述扇出显示区100b的金属走线密度大于所述正常显示区100a的金属走线密度，金属走线密度差则容易导致所述扇出显示区100b和所述正常显示区100a出现可视性mura现象。
有鉴于此，本申请通过在所述像素定义层111远离所述衬底基板101的一侧设置所述遮挡层112，所述遮挡层112的多个所述第二开口V2与所述像素定义层111的所述第一开口V1对应设置，所述遮挡层112可用于遮挡经所述金属走线反射的光线，使得所述扇出显示区100b与所述正常显示区100a从所述金属走线反射的光线较为均匀，有利于改善熄屏和亮屏状态下，因所述扇出显示区100b的金属走线密度与所述正常显示区100a的金属走线密度存在差异而造成所述扇出显示区100b和所述正常显示区100a出现可视性mura现象。
在本申请实施例中，所述显示面板的显示区由所述正常显示区100a和所述扇出显示区100b构成，所述正常显示区100a和所述扇出显示区100b均具有显示功能，所述扇出走线104b设置于所述扇出显示区100b。所述显示面板还包括非显示区（图中未示出），所述扇出显示区100b设置于所述正常显示区100a一侧，具体的，所述扇出显示区100b设置于所述正常显示区100a和非显示区之间。
进一步的，所述显示面板还包括驱动芯片，所述驱动芯片也可设置于所述扇出显示区100b内，此种情况下，所述非显示区可省去，故所述显示面板能够实现无边框和全面屏。
在本申请实施例中，所述衬底基板101为柔性衬底，所述柔性衬底一般为聚酰亚胺、聚对苯二甲酸乙二醇酯等有机聚合物材料。
在本申请实施例中，所述衬底基板101和所述驱动电路层104之间还设置有沿远离所述衬底基板101的方向上依次层叠设置的阻隔层102和缓冲层103，所述阻隔层102用于阻隔水氧，防止外部的水汽或者氧气侵蚀所述显示面板，所述阻隔层102所用的材料包括氧化硅、氮化硅、氮氧化硅和非晶硅中的一种或几种。所述缓冲层103主要起到缓冲和保护的作用，所述缓冲层103所用的材料包括氮化硅和氧化硅中的一种或两种。
所述像素驱动电路单元104a包括多个薄膜晶体管，在本申请实施例中，所述薄膜晶体管可以为双栅极结构的薄膜晶体管，具体的，所述薄膜晶体管包括沿远离所述衬底基板101的方向依次设置的有源层1041、第一栅极绝缘层1042、第一栅极层1043、第二栅极绝缘层1044、第二栅极层1045、第一层间介质层1046、第二层间介质层1047和第一源漏极金属层1048。其中，所述第一源漏极金属层1048通过贯穿所述第二层间介质层1047、所述第一层间介质层1046、所述第二栅极绝缘层1044和所述第一栅极绝缘层1042的过孔与所述有源层1041电连接。当然的，在一些实施例中，所述薄膜晶体管也可以为仅含有一层栅极层的薄膜晶体管，此外，所述薄膜晶体管也可以为顶栅或者是底栅结构，本申请对此不做限制。
在本申请实施例中，所述阳极110可采用ITO（Indium tin oxide，氧化铟锡）/Ag（银）/ITO的叠层结构，其中ITO具有良好的阻水性能，可以防止水汽或氧气通过所述阳极110扩散至所述发光层113，从而避免所述发光层113被水汽或氧气侵蚀导致所述显示面板出现黑点的情况发生，从而改善所述显示面板的显示效果。
需要说明的是，所述像素定义层111定义出多个所述第一开口V1，所述第一开口V1为像素开口，在本申请实施例中，所述第一开口V1是指有效发光像素开口，所述第一开口V1在所述衬底基板101上的正投影面积即为所述发光层113在所述衬底基板101上的正投影面积。
在本申请实施例中，至少一层所述连接走线层包括两层连接走线层，具体包括第一连接走线层106和第二连接走线层108，所述显示面板还包括沿远离所述衬底基板101方向依次层叠设置的第一平坦层105、第二平坦层107和第三平坦层109。所述第一平坦层105覆于所述驱动电路层104远离所述衬底基板101的一侧，所述第一连接走线层106设置于所述第一平坦层105和所述第二平坦层107之间，所述第二连接走线层108设置于所述第二平坦层107和所述第三平坦层109之间。所述驱动电路层104通过贯穿所述第一平坦层105的过孔与所述第一连接走线层106中的所述连接走线1081电连接，所述第一连接走线层106通过贯穿所述第二平坦层107的过孔与所述第二连接走线层108中的所述连接走线1081电连接，所述第二连接走线层108通过贯穿所述第三平坦层109的过孔与对应的所述阳极110电连接。
具体的，所述连接走线层为透明导电层，所述连接走线1081为透明走线，所述连接走线1081的材料为透明导体材料，透明导体材料包括氧化铟锡、氧化铟、氧化铟锌和银纳米线中的任意一种。
当然的，在其他实施例中，所述连接走线层还可为三层、四层、五层……甚至更多层，本申请对此不做限制，相应的，所述显示面板还需设置相应数量的平坦层，用于设置于相邻两层所述连接走线层之间；具体的，所述平坦层的材质包括透明有机材料，透明有机材料包括聚酰亚胺和光阻材料。
进一步的，所述薄膜晶体管还可采用双层源漏极金属层设计，以降低阻抗，具体的，所述薄膜晶体管还包括第二源漏极金属层1050和第四平坦层1049，所述第四平坦层1049覆于所述第一源漏极金属层1048远离所述衬底基板101的一侧，所述第二源漏极金属层1050设置于所述第四平坦层1049远离所述衬底基板101的一侧，所述第一平坦层105覆于所述第二源漏极金属层1050远离所述衬底基板101的一侧，所述第一源漏极金属层1048通过贯穿所述第四平坦层1049的过孔与所述第二源漏极金属层1050电连接，所述第二源漏极金属层1050通过贯穿所述第一平坦层105的过孔与所述第一连接走线层106中的连接走线1081电连接。
在本申请实施例中，所述扇出走线104b与所述第一栅极层1043或所述第二栅极层1045同层设置，所述扇出走线104b与所述第一栅极层1043或所述第二栅极层1045通过同一道制程制备而成。
在本申请实施例中，所述遮挡层112沿垂直于所述衬底基板101方向的厚度为1微米~1.5微米，所述遮挡层112的厚度不宜过大或过小，厚度过大会使所述显示面板的整体厚度增大，与当前显示器轻薄化的趋势相违背，过小则遮光效果较差，不利于改善可视性mura现象。
可选的，所述遮挡层112沿垂直于所述衬底基板101方向的厚度可以为1微米、1.1微米、1.2微米、1.3微米、1.4微米和1.5微米，在本申请实施例中，所述遮挡层112沿垂直于所述衬底基板101方向的厚度为1.2微米。
在本申请实施例中，所述遮挡层112的材料包括黑矩阵，当然的，在一些实施例中，所述遮挡层112的材料可也选用其它遮光材料，本申请对此不做限制。
在本申请实施例中，可通过等离子化学气相沉积法（Plasma enhanced chemicalvapor deposition，PECVD）制备形成所述遮挡层112。在其他一些实施例中，也可以通过化学气相沉积或者原子层沉积等方法制备形成所述遮挡层112。
在一种实施例，请继续参阅图2~图5，图3是图2中的显示面板中的第一开口和第二开口的局部俯视结构示意图；图4是本申请实施例提供的显示面板的第二种截面结构示意图；图5是图4中的显示面板中的第一开口和第二开口的局部俯视结构示意图。
在本申请实施例中，所述第二开口V2在所述衬底基板101上的正投影覆盖所述第一开口V1在所述衬底基板101上的正投影。在此种实施例中，所述遮挡层112可遮挡部分下层金属走线，由于所述遮挡层112在所述衬底基板101上的正投影与所述发光层113在所述衬底基板101上的正投影未发生重叠，因此，本实施例在不影响所述发光层113的发光效果的前提下，使得可视性mura现象得到明显改善。
在本申请实施例中，所述第二开口V2在所述衬底基板101上的正投影形状与相对应的所述第一开口V1在所述衬底基板101上的正投影形状相同，即，所述第二开口V2在所述衬底基板101上的正投影形状与相对应的所述发光层113在所述衬底基板101上的正投影形状相同。以每一像素单元115排布为Peral（珍珠）型排布为例进行说明，每一所述像素单元115包括两个红色发光像素、两个蓝色发光像素和四个绿色发光像素，所述红色发光像素和所述蓝色发光像素的形状为八边形，所述绿色发光像素的形状为椭圆形，则，在本申请实施例中，所述第二开口V2在所述衬底基板101上的正投影形状为八边形或椭圆形。
当然的，在其它实施例中，所述像素单元115还可采用其他排布方式，所述发光层113在所述衬底基板101上的正投影形状也可为矩形、圆形或者其他多边形等其他形状，所述第二开口V2的形状也可以与所述第一开口V1的形状不相同，本申请对此不作限制，可根据所述第一开口V1的排布方式和形状对所述第二开口V2进行设计。
具体的，所述第二开口V2在所述衬底基板101上的正投影面积与所述第一开口V1在所述衬底基板101上的正投影面积的比值范围为1~1.5。
详细地说，此种实施例包含两者情况，其中，第一种情况为，请参阅图2和图3，所述第二开口V2在所述衬底基板101上的正投影边缘与所述第一开口V1在所述衬底基板101上的正投影边缘存在间隙，也就是说，所述第二开口V2在所述衬底基板101上的正投影面积大于所述第一开口V1在所述衬底基板101上的正投影面积，即，所述第二开口V2在所述衬底基板101上的正投影面积与所述第一开口V1在所述衬底基板101上的正投影面积的比值大于1，且小于或等于1.5。
第二种情况为，请参阅图4和图5，图4与图2的不同之处在于，图5与图3的不同之处在于，所述第二开口V2在所述衬底基板101上的正投影边缘与所述第一开口V1在所述衬底基板101上的正投影边缘完全重叠，也就是说，所述第二开口V2在所述衬底基板101上的正投影面积等于所述第一开口V1在所述衬底基板101上的正投影面积，即，所述第二开口V2在所述衬底基板101上的正投影面积与所述第一开口V1在所述衬底基板101上的正投影面积的比值等于1。可以理解的是，第二种情况相较于第一种情况，所述遮挡层112遮挡的下层金属走线的面积较大，对于可视性mura的改善效果更好。
在一种实施例中，请参阅图6和图7，图6是本申请实施例提供的显示面板的第三种截面结构示意图；图7是图6中的显示面板中的第一开口和第二开口的局部俯视结构示意图；图6与图2、图7与图3的不同之处在于，所述第一开口V1在所述衬底基板101上的正投影覆盖所述第二开口V2在所述衬底基板101上的正投影，在此种实施例中，所述遮挡层112可遮挡几乎全部下层金属走线，由于所述遮挡层112在所述衬底基板101上的正投影与所述发光层113在所述衬底基板101上的正投影存在部分重叠，所述发光层113的有效发光面积减小，因此，相较于图2和图4，本实施例对于可视性mura的改善效果进一步增加，但牺牲了述发光层113的发光效果。
具体的，所述第二开口V2在所述衬底基板101上的正投影面积与所述第一开口V1在所述衬底基板101上的正投影面积的比值范围为0.8~1，所述第二开口V2在所述衬底基板101上的正投影面积不能过小，否则会使所述扇出显示区100b的所述发光层113的发光效果大幅度降低，导致所述扇出显示区100b与所述正常显示区100a的显示效果差异过大，导致显示均一性降低。
进一步的，在一种实施例中，请参阅图8和图9，图8是本申请实施例提供的显示面板的第四种截面结构示意图；图9是图8中的显示面板中的第一开口和第二开口的局部俯视结构示意图；图8与图6、图9与图7的不同之处在于，为了改善本申请实施例中的所述发光层113的发光效果降低的弊端，所述发光层113覆盖所述第二开口V2的侧壁和底部，即所述遮挡层112相当于起到所述像素定义层111的作用，所述第二开口V2相当于像素开口，优选的，所述发光层113完全覆盖所述第二开口V2的侧壁和底部，由于所述遮挡层112的高度大于所述像素定义层111的高度，即，所述第二开口V2的高度大于所述第一开口V1的高度，因此，本实施例将所述发光层113设置于所述第二开口V2内，相当于增大了所述发光层113的有效发光面积，有利于改善所述发光层113的发光效果，从而在不影响所述发光层113的发光效果的前提下，实现改善可视性mura的目的。
在一种实施例中，请参阅图10，图10是本申请实施例提供的显示面板的第五种截面结构示意图；图10与图2的不同之处在于，所述像素定义层111和所述遮挡层112采用同种遮光材料，可选的，所述像素定义层111的材料同样为黑矩阵。可以理解的是，所述像素定义层111不仅起到限定所述发光层113的作用，还与所述遮挡层112起到同样的作用，因此，所述像素定义层111可遮挡所述大部分所述像素驱动电路单元104a、所述扇出走线104b和所述连接走线1081，可进一步改善可视性mura；此外，相较于图2，本实施例中的所述遮挡层112的厚度可设置较小，甚至无需设置所述遮挡层112，即可解决本申请的技术问题，有利于实现所述显示面板的轻薄化。
在本申请实施例中，所述显示面板还包括阴极114，所述遮挡层112设置于所述阴极114和所述像素定义层111之间，在图2和图10中，所述阴极114覆盖所述像素定义层111、所述遮挡层112和所述发光层113；在图4、图6和图8中，所述阴极114覆盖所述遮挡层112和所述发光层113。
在本申请实施例中，所述显示面板还包括沿远离所述衬底基板101的方向依次设置的电子注入层、电子传输层、空穴传输层和空穴注入层，所述电子注入层、所述电子传输层、所述空穴传输层和所述空穴注入层设置于所述第一开口V1内，所述电子注入层和所述电子传输层设置于所述发光层113和所述阳极110之间，所述空穴传输层和所述空穴注入层设置于所述发光层113和所述阴极114之间。
在本申请实施例中，所述显示面板还包括封装层，所述封装层覆于所述阴极114远离所述衬底基板101的一侧，用于封装所述发光层113，避免外界环境中的水汽和氧气侵入所述发光层113被损坏的情况发生。所述封装层可采用薄膜封装，所述封装层可为单层或多层封装叠构，优选地，所述封装层采用无机/有机/无机的多层封装叠构，有利于提升封装效果。
在本申请实施例中，所述显示面板还包括触控层，所述触控层设置于所述封装层远离所述衬底基板101的一侧，所述触控层的触控类型可以为自电容式或者互电容式。所述触控层的触控类型可以根据实际情况进行选择，本申请对此不做限制。
在本申请实施例中，显示面板还包括偏光片和盖板，所述偏光片和所述干板依次层叠设置于所述触控层远离所述衬底基板101的一侧，所述偏光片通过光学胶贴合于所述触控层远离所述衬底基板101的一侧表面上，所述盖板通过光学胶贴合于所述偏光片远离所述衬底基板101的一侧表面上。
本申请实施例还提供一种显示装置，所述显示装置包括上述实施例中的所述显示面板，所述显示装置包括固定终端如电视、台式电脑，移动终端如手机、笔记本电脑，以及可穿戴设备如手环、VR(虚拟显示)设备、AR(增强显示)设备。
本申请实施例还提供一种显示面板的制备方法，所述显示面板包括正常显示区100a和扇出显示区100b，所述扇出显示区100b设置于所述正常显示区100a一侧，所述扇出显示区100b包括沿自所述正常显示区100a指向所述扇出显示区100b的方向依次排列的第一区1001b和第二区1002b；所述制备方法包括以下步骤：
提供一衬底基板101；
在所述衬底基板101一侧形成驱动电路层104，所述驱动电路层104包括多个像素驱动电路单元104a和多条扇出走线104b，所述多个像素驱动电路单元104a及设置于所述正常显示区100a和第一区1001b，所述多条扇出走线104b设置于所述第二区1002b，位于所述第一区1001b的所述像素驱动电路单元104a的密度大于位于所述正常显示区100a的所述像素驱动电路单元104a的密度；
在所述驱动电路层104远离所述衬底基板101的一侧形成至少一连接走线层，每一所述连接走线层包括多条连接走线；
在所述连接走线层远离所述衬底基板101的一侧形成阳极110；
在所述连接走线层远离所述衬底基板101的一侧形成像素定义层111，所述像素定义层111包括多个第一开口V1，所述第一开口V1裸露出至少部分所述阳极110；
在所述像素定义层111远离所述衬底基板101的一侧形成所述遮挡层112，所述遮挡层112包括多个第二开口V2，所述第二开口V2与所述第一开口V1对应设置；以及
在所述第一开口V1内形成发光层113。
有益效果为：本申请实施例提供的显示面板及显示装置，通过在像素定义层远离衬底基板的一侧设置遮挡层，遮挡层的多个第二开口与像素定义层的第一开口对应设置，遮挡层可用于遮挡经金属走线反射的光线，使得扇出显示区与正常显示区从金属走线反射的光线较为均匀，有利于改善熄屏和亮屏状态下，因扇出显示区的金属走线密度与正常显示区的金属走线密度存在差异而造成扇出显示区和正常显示区出现可视性mura现象。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种显示面板，包括正常显示区和扇出显示区，所述扇出显示区位于所述正常显示区一侧，所述扇出显示区包括沿自所述正常显示区指向所述扇出显示区的方向依次排列的第一区和第二区；所述显示面板包括：
    衬底基板；
    驱动电路层，设置于所述衬底基板一侧，所述驱动电路层包括多个像素驱动电路单元及多条扇出走线，所述像素驱动电路单元位于所述正常显示区和所述第一区，所述扇出走线位于所述第二区，其中，位于所述第一区的所述像素驱动电路单元的密度大于位于所述正常显示区的所述像素驱动电路单元的密度；
    至少一连接走线层，设置于所述驱动电路层远离所述衬底基板的一侧，每一所述连接走线层包括多条连接走线；
    多个阳极，设置于所述连接走线层远离所述衬底基板的一侧，所述像素驱动电路单元通过所述连接走线与对应的所述阳极电连接；
    像素定义层，设置于所述连接走线层远离所述衬底基板的一侧，所述像素定义层包括多个第一开口，所述第一开口裸露出至少部分所述阳极；以及
    发光层，设置于所述第一开口内；
    其中，所述显示面板还包括遮挡层，所述像素定义层和所述遮挡层采用同种遮光材料，所述遮挡层设置于所述像素定义层远离所述衬底基板的一侧，所述遮挡层包括多个第二开口，所述第二开口与所述第一开口对应设置。
  2. 根据权利要求1所述的显示面板，其中，所述第二开口在所述衬底基板上的正投影覆盖所述第一开口在所述衬底基板上的正投影。
  3. 根据权利要求2所述的显示面板，其中，所述第二开口在所述衬底基板上的正投影面积与所述第一开口在所述衬底基板上的正投影面积的比值范围为1~1.5。
  4. 根据权利要求1所述的显示面板，其中，所述第一开口在所述衬底基板上的正投影覆盖所述第二开口在所述衬底基板上的正投影。
  5. 根据权利要求4所述的显示面板，其中，所述第二开口在所述衬底基板上的正投影面积与所述第一开口在所述衬底基板上的正投影面积的比值范围为0.8~1。
  6. 根据权利要求5所述的显示面板，其中，所述发光层覆盖所述第二开口的侧壁和底部。
  7. 根据权利要求1所述的显示面板，其中，所述遮挡层沿垂直于所述衬底基板方向的厚度为1微米~1.5微米。
  8. 根据权利要求1所述的显示面板，其中，所述遮挡层的材料包括黑矩阵。
  9. 根据权利要求1所述的显示面板，其中，所述显示面板还包括阴极，所述遮挡层设置于所述阴极和所述像素定义层之间。
  10. 一种显示面板，包括正常显示区和扇出显示区，所述扇出显示区位于所述正常显示区一侧，所述扇出显示区包括沿自所述正常显示区指向所述扇出显示区的方向依次排列的第一区和第二区；所述显示面板包括：
    衬底基板；
    驱动电路层，设置于所述衬底基板一侧，所述驱动电路层包括多个像素驱动电路单元及多条扇出走线，所述像素驱动电路单元位于所述正常显示区和所述第一区，所述扇出走线位于所述第二区，其中，位于所述第一区的所述像素驱动电路单元的密度大于位于所述正常显示区的所述像素驱动电路单元的密度；
    至少一连接走线层，设置于所述驱动电路层远离所述衬底基板的一侧，每一所述连接走线层包括多条连接走线；
    多个阳极，设置于所述连接走线层远离所述衬底基板的一侧，所述像素驱动电路单元通过所述连接走线与对应的所述阳极电连接；
    像素定义层，设置于所述连接走线层远离所述衬底基板的一侧，所述像素定义层包括多个第一开口，所述第一开口裸露出至少部分所述阳极；以及
    发光层，设置于所述第一开口内；
    其中，所述显示面板还包括遮挡层，所述遮挡层设置于所述像素定义层远离所述衬底基板的一侧，所述遮挡层包括多个第二开口，所述第二开口与所述第一开口对应设置。
  11. 根据权利要求10所述的显示面板，其中，所述第二开口在所述衬底基板上的正投影覆盖所述第一开口在所述衬底基板上的正投影。
  12. 根据权利要求11所述的显示面板，其中，所述第二开口在所述衬底基板上的正投影面积与所述第一开口在所述衬底基板上的正投影面积的比值范围为1~1.5。
  13. 根据权利要求10所述的显示面板，其中，所述第一开口在所述衬底基板上的正投影覆盖所述第二开口在所述衬底基板上的正投影。
  14. 根据权利要求13所述的显示面板，其中，所述第二开口在所述衬底基板上的正投影面积与所述第一开口在所述衬底基板上的正投影面积的比值范围为0.8~1。
  15. 根据权利要求14所述的显示面板，其中，所述发光层覆盖所述第二开口的侧壁和底部。
  16. 根据权利要求10所述的显示面板，其中，所述遮挡层沿垂直于所述衬底基板方向的厚度为1微米~1.5微米。
  17. 根据权利要求10所述的显示面板，其中，所述遮挡层的材料包括黑矩阵。
  18. 根据权利要求10所述的显示面板，其中，所述显示面板还包括阴极，所述遮挡层设置于所述阴极和所述像素定义层之间。
  19. 根据权利要求10所述的显示面板，其中，至少一所述连接走线层包括第一连接走线层和第二连接走线层，所述显示面板还包括沿远离所述衬底基板方向依次层叠设置的第一平坦层、第二平坦层和第三平坦层；
    所述第一平坦层覆于所述驱动电路层远离所述衬底基板的一侧，所述第一连接走线层设置于所述第一平坦层和所述第二平坦层之间，所述第二连接走线层设置于所述第二平坦层和所述第三平坦层之间；
    所述驱动电路层通过贯穿所述第一平坦层的过孔与所述第一连接走线层中的所述连接走线电连接，所述第一连接走线层通过贯穿所述第二平坦层的过孔与所述第二连接走线层中的所述连接走线电连接，所述第二连接走线层通过贯穿所述第三平坦层的过孔与所述阳极电连接。
  20. 一种显示装置，包括显示面板，所述显示面板包括正常显示区和扇出显示区，所述扇出显示区位于所述正常显示区一侧，所述扇出显示区包括沿自所述正常显示区指向所述扇出显示区的方向依次排列的第一区和第二区；所述显示面板包括：
    衬底基板；
    驱动电路层，设置于所述衬底基板一侧，所述驱动电路层包括多个像素驱动电路单元及多条扇出走线，所述像素驱动电路单元位于所述正常显示区和所述第一区，所述扇出走线位于所述第二区，其中，位于所述第一区的所述像素驱动电路单元的密度大于位于所述正常显示区的所述像素驱动电路单元的密度；
    至少一连接走线层，设置于所述驱动电路层远离所述衬底基板的一侧，每一所述连接走线层包括多条连接走线；
    多个阳极，设置于所述连接走线层远离所述衬底基板的一侧，所述像素驱动电路单元通过所述连接走线与对应的所述阳极电连接；
    像素定义层，设置于所述连接走线层远离所述衬底基板的一侧，所述像素定义层包括多个第一开口，所述第一开口裸露出至少部分所述阳极；以及
    发光层，设置于所述第一开口内；
    其中，所述显示面板还包括遮挡层，所述遮挡层设置于所述像素定义层远离所述衬底基板的一侧，所述遮挡层包括多个第二开口，所述第二开口与所述第一开口对应设置。
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