WO2022237017A1 - 显示面板及其制作方法、显示装置 - Google Patents

显示面板及其制作方法、显示装置 Download PDF

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Publication number
WO2022237017A1
WO2022237017A1 PCT/CN2021/117253 CN2021117253W WO2022237017A1 WO 2022237017 A1 WO2022237017 A1 WO 2022237017A1 CN 2021117253 W CN2021117253 W CN 2021117253W WO 2022237017 A1 WO2022237017 A1 WO 2022237017A1
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WO
WIPO (PCT)
Prior art keywords
layer
auxiliary electrode
display panel
pixel definition
opening
Prior art date
Application number
PCT/CN2021/117253
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English (en)
French (fr)
Inventor
王超
Original Assignee
Tcl华星光电技术有限公司
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Publication date
Application filed by Tcl华星光电技术有限公司 filed Critical Tcl华星光电技术有限公司
Priority to US17/600,402 priority Critical patent/US20240049564A1/en
Publication of WO2022237017A1 publication Critical patent/WO2022237017A1/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8052—Cathodes
    • H10K59/80522—Cathodes combined with auxiliary electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/82—Cathodes
    • H10K50/824—Cathodes combined with auxiliary electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass

Definitions

  • the present application relates to the field of display technology, in particular to a display panel, a manufacturing method thereof, and a display device having the display panel.
  • OLED Organic Light-Emitting Diode
  • LCD Liquid Crystal Display
  • advantages of display color and display viewing angle have been widely concerned by everyone. In recent years, its development has been changing rapidly. Not only can it make curved displays, but it is also gradually developing to large sizes.
  • the cathode on the transparent surface is generally made thinner, resulting in poor conductivity.
  • the screen size is large, the light-emitting point in the center of the screen is far away from the electrode interface, and the long-distance current transmission causes a large increase in the driving voltage.
  • the driving voltage gap between the inner edge of the screen close to the electrode interface area and the center area of the screen is too large, and there is a voltage drop (IR The problem of drop) occurs, which makes the peripheral brightness of the display panel brighter, while the middle display is darker, resulting in uneven display.
  • Embodiments of the present application provide a display panel, a manufacturing method thereof, and a display device, which can solve the technical problem that the voltage drop of the cathode layer of the OLED display panel is prone to occur, thereby causing uneven display on the display panel.
  • An embodiment of the present application provides a display panel, which includes:
  • a pixel definition layer including a plurality of opening areas and a non-opening area surrounding each of the opening areas;
  • the cathode layer is disposed on the pixel definition layer and the auxiliary electrode, and connected in parallel with the auxiliary electrode.
  • the pixel definition layer further includes a retaining wall structure disposed in the non-opening area, the auxiliary electrode is disposed on the retaining wall structure, and the cathode layer continuously covers The pixel definition layer is overlapped with the auxiliary electrode.
  • the display panel further includes a spacer disposed on the retaining wall structure and the auxiliary electrode, the spacer includes at least one opening, and the cathode layer covers the The spacer is overlapped with the auxiliary electrode through at least one of the openings.
  • a tank is formed on the side of the retaining wall structure facing the cathode layer, the auxiliary electrode is located in the tank, and the cathode layer covers the retaining wall structure and on the auxiliary electrode.
  • the depth of the groove body is equal to the thickness of the auxiliary electrode.
  • the orthographic projection of the auxiliary electrode on the pixel definition layer is outside the coverage of the anode's orthographic projection on the pixel definition layer.
  • the display panel includes a plurality of auxiliary electrodes, and each of the auxiliary electrodes is set corresponding to at least one of the opening regions, and each of the auxiliary electrodes is corresponding to at least one of the opening regions.
  • the opening areas are arranged adjacent to each other.
  • the display panel includes a display area and a non-display area surrounding the display area, and the distribution density of the plurality of auxiliary electrodes is directed from the non-display area to that of the display area.
  • the direction is increasing.
  • a method for manufacturing a display panel which includes the following steps:
  • the pixel definition layer includes a plurality of opening regions and non-opening regions surrounding each of the opening regions;
  • the electrode layer includes an anode formed in the opening area, and an auxiliary electrode formed in the non-opening area;
  • a cathode layer is formed on the pixel definition layer and the auxiliary electrode, and the cathode layer is connected in parallel with the auxiliary electrode.
  • a display device includes a display panel, and the display panel includes:
  • a pixel definition layer including a plurality of opening areas and a non-opening area surrounding each of the opening areas;
  • the cathode layer is disposed on the pixel definition layer and the auxiliary electrode, and connected in parallel with the auxiliary electrode.
  • the pixel definition layer further includes a retaining wall structure disposed in the non-opening area, the auxiliary electrode is disposed on the retaining wall structure, and the cathode layer continuously covers The pixel definition layer is overlapped with the auxiliary electrode.
  • the display panel further includes a spacer disposed on the retaining wall structure and the auxiliary electrode, the spacer includes at least one opening, and the cathode layer covers the The spacer is overlapped with the auxiliary electrode through at least one of the openings.
  • a tank is formed on the side of the retaining wall structure facing the cathode layer, the auxiliary electrode is located in the tank, and the cathode layer covers the retaining wall structure and on the auxiliary electrode.
  • the depth of the groove body is equal to the thickness of the auxiliary electrode.
  • the orthographic projection of the auxiliary electrode on the pixel definition layer is outside the coverage of the anode's orthographic projection on the pixel definition layer.
  • the display panel includes a plurality of auxiliary electrodes, and each of the auxiliary electrodes is set corresponding to at least one of the opening regions, and each of the auxiliary electrodes is corresponding to at least one of the opening regions.
  • the opening areas are arranged adjacent to each other.
  • the display panel includes a display area and a non-display area surrounding the display area, and the distribution density of the plurality of auxiliary electrodes is directed from the non-display area to that of the display area.
  • the direction is increasing.
  • the present application can effectively reduce the surface resistance of the cathode layer by setting the auxiliary electrode in the non-opening area to overlap the cathode layer, and can improve the voltage drop phenomenon of the display panel, thereby improving the display panel display.
  • the uniformity improves the display effect of the display panel.
  • the auxiliary electrode and the anode are formed in the same process, which can reduce the process steps and save the process cost.
  • FIG. 1 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • FIG. 2 is a flowchart of a method for manufacturing a display panel provided in an embodiment of the present application
  • FIG. 3 is a schematic structural diagram of another display panel provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of another display panel provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a planar distribution structure of a pixel definition layer provided by an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a planar distribution structure of another pixel definition layer provided by an embodiment of the present application.
  • FIGS. 7A to 7E are schematic structural diagrams of the manufacturing process of the display panel provided by the embodiment of the present application.
  • FIG. 8 is a schematic diagram of a planar distribution structure of an auxiliary electrode provided in an embodiment of the present application.
  • FIG. 9 is a schematic diagram of a planar distribution structure of another auxiliary electrode provided in an embodiment of the present application.
  • first and second are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, a feature defined as “first” or “second” may explicitly or implicitly include one or more of said features.
  • “plurality” means two or more, unless otherwise specifically defined.
  • the cathode on the transparent surface is generally made thinner, resulting in poor conductivity.
  • the screen size is large, the light-emitting point in the center of the screen is far away from the electrode interface, and the long-distance current transmission causes a large increase in the driving voltage.
  • the driving voltage gap between the inner edge of the screen close to the electrode interface area and the center area of the screen is too large, and there is a voltage drop (IR The problem of drop) occurs, which makes the peripheral brightness of the display panel brighter, while the middle display is darker, resulting in uneven display.
  • the display panel includes a pixel definition layer 10, a cathode layer 21 and an electrode layer, wherein the pixel definition layer 10 includes a plurality of opening areas A and a non-opening area B surrounding each opening area A.
  • the electrode layer is disposed on the pixel definition layer 10 , and the electrode layer is at least used for forming the anode 22 in the opening area A and for forming the auxiliary electrode 30 in the non-opening area B.
  • the cathode layer 21 is disposed on the pixel definition layer 10 and the auxiliary electrode 30 , and the cathode layer 21 and the auxiliary electrode 30 are connected in parallel.
  • the embodiment of the present application arranges the auxiliary electrode 30 in the non-opening area B of the pixel definition layer 10, and the auxiliary electrode 30 is connected in parallel with the cathode layer 21, so that the resistance of the cathode layer 21 can be effectively reduced, and the display can be improved.
  • the voltage drop phenomenon of the panel can further improve the display uniformity of the display panel.
  • the auxiliary electrode 30 is disposed in the non-opening area B, so as not to affect the occupied area and space of the opening area A, which increases the aperture ratio of the display panel and further improves the display effect of the display panel.
  • the auxiliary electrode 30 and the anode 22 are formed in the same process, which can reduce the process steps and save the process cost.
  • the display panel includes a substrate 40, a thin film transistor array layer 50 disposed on the substrate 40, an interlayer insulating layer 60 disposed on the thin film transistor array layer 50, and an interlayer insulating layer 60 disposed on the interlayer insulating layer 60.
  • the substrate 40 may be a glass rigid substrate, or a flexible substrate, and the material of the flexible substrate includes an organic resin material, which is not limited herein.
  • the thin film transistor array layer 50 includes thin film transistor devices distributed in an array and a spacer layer covering the thin film transistor devices, and the interlayer insulating layer 60 covers the thin film transistor array layer 50 to further cover the thin film transistor devices.
  • the flat layer 70 is covered on the interlayer insulating layer 60 , and the side of the flat layer 70 facing away from the interlayer insulating layer 60 is a flat surface, so as to reduce film level differences and improve process yield.
  • the pixel definition layer 10 includes a plurality of opening areas A and a non-opening area B surrounding the opening area A. Further, the pixel definition layer 10 includes a retaining wall structure 11, and the retaining wall structure 11 defines a plurality of opening areas A and is located in the non-opening area. in zone B. Wherein, the opening area A is formed by an opening penetrating through the pixel definition layer 10 .
  • the display panel also includes an electrode layer disposed on the pixel definition layer 10, and the electrode layer is at least used to form the anode 22 in the opening area A, and is used to form the auxiliary electrode 30 in the non-opening area B, that is, the anode 22 and the The auxiliary electrode 30 is formed on the pixel definition layer 10 in the same process.
  • the display panel also includes an organic light-emitting layer 23 disposed in the opening area A and on the anode 22, wherein the anode 22 passes through the flat layer 70 and the interlayer insulating layer 60 through the via hole and the thin film transistor in the thin film transistor array layer.
  • the devices are electrically connected to realize the transmission of electrical signals.
  • the display panel also includes a cathode layer 21 continuously covering the pixel definition layer 10, the cathode layer 21 continuously covering a plurality of opening regions A and non-opening regions B, and the cathode layer 21 covering the upper surface of the organic light-emitting layer 23, so that It is overlapped with the organic light-emitting layer 23, and the cathode layer 21 is formed on the entire surface of the pixel definition layer 10.
  • the edge area of the cathode layer 21 is connected to the signal terminal, and the electrical signal is output through the signal terminal. A voltage is applied to both sides of the layer 23 to realize the light emitting function of the organic light emitting layer 23 .
  • the auxiliary electrode 30 is connected in parallel with the cathode layer 21, thereby reducing the resistance of the cathode layer 21, effectively improving the voltage drop phenomenon of the display panel, and improving the display uniformity of the display panel.
  • the auxiliary electrode 30 is disposed on the barrier structure 11, and the cathode layer 21 continuously covers the organic light-emitting layer 23, the barrier structure 11 and the auxiliary electrode 30, so as to realize overlapping with the auxiliary electrode 30, and the auxiliary electrode 30 can pass through
  • the signal wires are connected to the signal terminals so as to be connected in parallel with the cathode layer 21 .
  • the orthographic projection of the signal wiring on the pixel definition layer 10 is located in the non-aperture region B, thereby increasing the aperture ratio of the display panel and improving the display effect of the display panel.
  • the orthographic projection of the auxiliary electrode 30 on the pixel definition layer 10 is located outside the coverage of the orthographic projection of the anode 22 on the pixel definition layer 10, so as to avoid the generation of parasitic capacitance between the auxiliary electrode 30 and the anode 22, and improve the display effect of the display panel .
  • the embodiment of the present application also provides a manufacturing method of the display panel described in the above embodiments, please refer to FIG. 2 , the manufacturing method includes the following steps:
  • the pixel definition layer 10 includes a plurality of opening regions A and non-opening regions B surrounding each opening region A.
  • the electrode layer includes an anode 22 formed in the opening area A, and an auxiliary electrode 30 formed in the non-opening area B.
  • the material of the auxiliary electrode 30 is the same as that of the anode 22 .
  • both the auxiliary electrode 30 and the anode 22 can have a laminated structure of ITO/Ag/ITO.
  • auxiliary electrode 30 and the anode 22 are formed in the same process, and further, on the basis of reducing the resistance of the cathode layer 21, the process process can be reduced, and the process time and cost can be saved.
  • the display panel includes a substrate 40, a thin film transistor array layer 50 disposed on the substrate 40, an interlayer insulating layer 60 disposed on the thin film transistor array layer 50, and a thin film transistor array layer 50 disposed on the The planar layer 70 on the interlayer insulating layer 60 and the pixel definition layer 10 disposed on the planar layer 70 .
  • the pixel definition layer 10 includes a plurality of opening areas A and a non-opening area B surrounding the opening area A, and the pixel definition layer 10 includes a wall structure 11, the wall structure 11 defines a plurality of opening areas A and is located in the non-opening area B .
  • the display panel also includes an electrode layer disposed on the pixel definition layer 10, and the electrode layer is at least used to form the anode 22 in the opening area A, and is used to form the auxiliary electrode 30 in the non-opening area B, that is, the anode 22 and the The auxiliary electrode 30 is formed on the pixel definition layer 10 in the same process.
  • the display panel further includes an organic light emitting layer 23 disposed in the opening area A and on the anode 22 .
  • the auxiliary electrode 30 is disposed on the upper surface of the retaining wall structure 11 and protrudes from the upper surface of the retaining wall structure 11 .
  • the display panel further includes a cathode layer 21 continuously covering the organic light-emitting layer 23 , the wall structure 11 and the auxiliary electrode 30 , and the cathode layer 21 covers the auxiliary electrode 30 to achieve overlapping with the auxiliary electrode 30 .
  • the manufacturing method of the display panel includes:
  • a substrate 40 is provided, the substrate 40 includes a glass rigid substrate or a flexible substrate, and the material of the flexible substrate includes an organic resin material.
  • the thin film transistor array layer 50 is prepared on the substrate 40, and the thin film transistor array layer 50 includes thin film transistor devices and a spacer layer covering the thin film transistor devices.
  • An interlayer insulating layer 60 is prepared on the thin film transistor array layer 50 to further cover the thin film transistor devices.
  • the flat layer 70 is prepared on the interlayer insulating layer 60 , and the side of the flat layer 70 facing away from the interlayer insulating layer 60 is a flat surface.
  • the pixel definition layer 10 is prepared on the flat layer 70, the pixel definition layer 10 includes a retaining wall structure 11, the retaining wall structure 11 defines a plurality of opening areas A, and the retaining wall structure 11 is located in the non-opening area B, and the non-opening area B surrounds The opening area A is set.
  • the material of the retaining wall structure 11 includes an organic photoresist material.
  • Via holes penetrating through the planar layer 70 and the interlayer insulating layer 60 are formed by photolithography, dry etching, photoresist stripping and other processes.
  • a metal layer is prepared on the pixel definition layer 10, and the metal layer is patterned by processes such as yellow light and etching to form a patterned electrode layer, and the electrode layer includes an anode 22 formed in the opening area A, and a The auxiliary electrode 30 in the non-opening area B.
  • the metal layer includes a stacked structure of ITO/Ag/ITO.
  • the anode 22 is electrically connected to the TFT devices in the TFT array layer 50 through via holes.
  • the organic light emitting layer 23 is prepared in the opening area A, and the organic light emitting layer 23 is located on the anode 22 .
  • the cathode layer 21 on the pixel definition layer 10 Prepare the cathode layer 21 on the pixel definition layer 10, and the cathode layer 21 continuously covers the organic light-emitting layer 23, the barrier structure 11 and the auxiliary electrode 30, and overlaps with the auxiliary electrode 30, so as to realize the parallel connection between the cathode layer 21 and the auxiliary electrode 30 .
  • the display panel includes a substrate 40, a thin film transistor array layer 50 disposed on the substrate 40, an interlayer insulating layer 60 disposed on the thin film transistor array layer 50, and a The planar layer 70 on the interlayer insulating layer 60 and the pixel definition layer 10 disposed on the planar layer 70 .
  • the pixel definition layer 10 includes a plurality of opening areas A and a non-opening area B surrounding the opening area A, and the pixel definition layer 10 includes a wall structure 11, the wall structure 11 defines a plurality of opening areas A and is located in the non-opening area B .
  • the display panel also includes an electrode layer disposed on the pixel definition layer 10, and the electrode layer is at least used to form the anode 22 in the opening area A, and is used to form the auxiliary electrode 30 in the non-opening area B, that is, the anode 22 and the The auxiliary electrode 30 is formed on the pixel definition layer 10 in the same process.
  • the display panel further includes an organic light emitting layer 23 disposed in the opening area A and on the anode 22 .
  • the auxiliary electrode 30 is disposed on the retaining wall structure 11 .
  • the display panel further includes a cathode layer 21 continuously covering the organic light-emitting layer 23 , the wall structure 11 and the auxiliary electrode 30 , and the cathode layer 21 covers the auxiliary electrode 30 to achieve overlapping with the auxiliary electrode 30 .
  • a tank body 101 is disposed on a side of the retaining wall structure 11 facing the cathode layer 21 , and the auxiliary electrode 30 is disposed in the tank body 101 .
  • the depth of the groove body 101 is equal to the thickness of the auxiliary electrode 30 . In order to reduce the step difference of the film layer and improve the yield of the process.
  • the manufacturing method of the display panel includes:
  • a substrate 40 is provided, the substrate 40 includes a glass rigid substrate or a flexible substrate, and the material of the flexible substrate includes an organic resin material.
  • the thin film transistor array layer 50 is prepared on the substrate 40, and the thin film transistor array layer 50 includes thin film transistor devices and a spacer layer covering the thin film transistor devices.
  • An interlayer insulating layer 60 is prepared on the thin film transistor array layer 50 to further cover the thin film transistor devices.
  • the flat layer 70 is prepared on the interlayer insulating layer 60 , and the side of the flat layer 70 facing away from the interlayer insulating layer 60 is a flat surface.
  • the pixel definition layer 10 is prepared on the flat layer 70, the pixel definition layer 10 includes a retaining wall structure 11, the retaining wall structure 11 defines a plurality of opening areas A, and the retaining wall structure 11 is located in the non-opening area B, and the non-opening area B surrounds The opening area A is set.
  • the material of the retaining wall structure 11 includes an organic photoresist material.
  • Via holes penetrating through the planar layer 70 and the interlayer insulating layer 60 are formed by photolithography, dry etching, photoresist stripping and other processes.
  • a groove body 101 is formed on a side of the retaining wall structure 11 facing away from the flat layer 70 .
  • a metal layer is prepared on the pixel definition layer 10, and the metal layer is patterned by processes such as yellow light and etching to form a patterned electrode layer, and the electrode layer includes an anode 22 formed in the opening area A, and a The auxiliary electrode 30 inside the tank body 101 .
  • the metal layer includes a stacked structure of ITO/Ag/ITO.
  • the anode 22 is electrically connected to the TFT devices in the TFT array layer 50 through via holes.
  • the organic light emitting layer 23 is prepared in the opening area A, and the organic light emitting layer 23 is located on the anode 22 .
  • the cathode layer 21 on the pixel definition layer 10 Prepare the cathode layer 21 on the pixel definition layer 10, and the cathode layer 21 continuously covers the organic light-emitting layer 23, the barrier structure 11 and the auxiliary electrode 30, and overlaps with the auxiliary electrode 30, so as to realize the parallel connection between the cathode layer 21 and the auxiliary electrode 30 .
  • the display panel includes a substrate 40, a thin film transistor array layer 50 disposed on the substrate 40, an interlayer insulating layer 60 disposed on the thin film transistor array layer 50, and The planar layer 70 on the interlayer insulating layer 60 and the pixel definition layer 10 disposed on the planar layer 70 .
  • the pixel definition layer 10 includes a plurality of opening areas A and a non-opening area B surrounding the opening area A, and the pixel definition layer 10 includes a wall structure 11, the wall structure 11 defines a plurality of opening areas A and is located in the non-opening area B .
  • the display panel also includes an electrode layer disposed on the pixel definition layer 10, and the electrode layer is at least used to form the anode 22 in the opening area A, and is used to form the auxiliary electrode 30 in the non-opening area B, that is, the anode 22 and the The auxiliary electrode 30 is formed on the pixel definition layer 10 in the same process.
  • the display panel further includes an organic light emitting layer 23 disposed in the opening area A and on the anode 22 .
  • the auxiliary electrode 30 is disposed on the retaining wall structure 11 .
  • the display panel is also disposed on the spacer 12 on the barrier structure 11 and the auxiliary electrode 30 , and the spacer 12 is formed with at least one opening to expose part of the upper surface of the auxiliary electrode 30 .
  • the display panel further includes a cathode layer 21 continuously covering the organic light emitting layer 23 , the wall structure 11 and the spacer 12 , and the cathode layer 21 overlaps with the auxiliary electrode 30 through at least one opening.
  • At least one opening includes two through holes 31, and the two through holes 31 are located at both ends of the auxiliary electrode 30.
  • the shape of the through holes 31 is not limited. In the example, a circle is taken as an example for illustration.
  • At least one opening includes a strip-shaped hole 32 , and the strip-shaped holes 32 are arranged along the extending direction of the auxiliary electrode 30 to achieve a maximum contact area between the auxiliary electrode 30 and the cathode layer 21 .
  • the manufacturing method of the display panel includes:
  • a substrate 40 is provided, the substrate 40 includes a glass rigid substrate or a flexible substrate, and the material of the flexible substrate includes an organic resin material.
  • the thin film transistor array layer 50 is prepared on the substrate 40, and the thin film transistor array layer 50 includes thin film transistor devices and a spacer layer covering the thin film transistor devices.
  • An interlayer insulating layer 60 is prepared on the thin film transistor array layer 50 to further cover the thin film transistor devices.
  • the flat layer 70 is prepared on the interlayer insulating layer 60 , and the side of the flat layer 70 facing away from the interlayer insulating layer 60 is a flat surface.
  • the pixel definition layer 10 is prepared on the flat layer 70, the pixel definition layer 10 includes a retaining wall structure 11, the retaining wall structure 11 defines a plurality of opening areas A, and the retaining wall structure 11 is located in the non-opening area B, and the non-opening area B surrounds The opening area A is set.
  • Via holes penetrating through the planar layer 70 and the interlayer insulating layer 60 are formed by photolithography, dry etching, photoresist stripping and other processes.
  • a metal layer is prepared on the pixel definition layer 10, and the metal layer is patterned by processes such as yellow light and etching to form a patterned electrode layer.
  • the electrode layer includes the anode 22 formed in the opening area A, and The auxiliary electrode 30 in the opening area B.
  • the auxiliary electrode 30 is located on the upper surface of the retaining wall structure 11 , and optionally, the metal layer includes a stacked structure of ITO/Ag/ITO.
  • the anode 22 is electrically connected to the TFT devices in the TFT array layer 50 through via holes.
  • the spacer 12 is prepared on the retaining wall structure 11 , and the spacer 12 covers the auxiliary electrode 30 .
  • the material of the spacers 12 is the same as that of the wall structure 11 , and may be an organic photoresist material.
  • At least one opening is defined on a side of the spacer 12 facing away from the retaining wall structure 11 , and at least one opening exposes part of the upper surface of the auxiliary electrode 30 .
  • the organic light emitting layer 23 is prepared in the opening area A, and the organic light emitting layer 23 is located on the anode 22 .
  • the cathode layer 21 is prepared on the pixel definition layer 10, and the cathode layer 21 continuously covers the organic light-emitting layer 23, the wall structure 11 and the spacer 12, and the cathode layer 21 overlaps with the auxiliary electrode 30 through at least one opening to realize the cathode Layer 21 is connected in parallel with auxiliary electrode 30 .
  • the auxiliary electrode 30 in the non-opening area B of the pixel definition layer 10, and the auxiliary electrode 30 is connected in parallel with the cathode layer 21, the resistance of the cathode layer 21 can be effectively reduced, and the voltage of the display panel can be improved. drop phenomenon, thereby improving the display uniformity of the display panel.
  • the auxiliary electrode 30 is disposed in the non-opening area B, so as not to affect the occupied area and space of the opening area A, which increases the aperture ratio of the display panel and further improves the display effect of the display panel.
  • the auxiliary electrode 30 and the anode 22 are formed in the same process, which can reduce the process steps and save the process cost.
  • the display panel includes a plurality of auxiliary electrodes 30 , and each auxiliary electrode 30 is disposed corresponding to at least one opening area A, and each auxiliary electrode 30 is disposed adjacent to at least one opening area A corresponding thereto.
  • auxiliary electrodes 30 are provided in one-to-one correspondence with a plurality of opening regions A, so that each opening region A is provided with an auxiliary electrode 30 adjacent to it, that is, for each pixel
  • An auxiliary electrode 30 is provided in parallel with the cathode layer 21 to effectively reduce the resistance of the cathode layer 21, improve the voltage drop phenomenon, and improve the display uniformity of the display panel.
  • one auxiliary electrode 30 is provided corresponding to each opening area A, specifically, one auxiliary electrode 30 can be provided corresponding to two opening areas A, and the auxiliary electrode 30 is located between two opening areas A; An auxiliary electrode 30 is correspondingly provided in the area A, and the auxiliary electrode 30 is adjacent to an opening area A in the middle. Moreover, the number of opening regions A corresponding to each auxiliary electrode 30 is not limited.
  • the display panel includes a display area C and a non-display area D surrounding the display area C, and a plurality of auxiliary electrodes 30 are evenly distributed in the display area C.
  • the display panel includes a display area C and a non-display area D surrounding the display area C.
  • the distribution density of the plurality of auxiliary electrodes 30 increases gradually.
  • the distribution of the plurality of auxiliary electrodes 30 can also be that the distribution density of the auxiliary electrodes 30 at the place where the resistance of the cathode layer 21 is relatively large is greater than the distribution density of the auxiliary electrodes 30 at the place where the resistance of the cathode layer 21 is small, which is not described here. limited.
  • an embodiment of the present application further provides a display device, which includes the display panel described in the above-mentioned embodiments, and its structure and manufacturing method are the same as those in the above-mentioned embodiments, and will not be repeated here.
  • Display devices include smart bracelets, smart watches, virtual reality (Virtual Reality, VR) and other wearable devices; display devices also include mobile phones, e-books, e-newspapers, TVs, personal portable computers, foldable and rollable OLEDs and other flexible display and lighting equipment.
  • VR Virtual Reality

Abstract

本申请公开了一种显示面板及其制作方法、显示装置。显示面板包括：像素定义层，包括多个开口区以及围绕各开口区的非开口区；电极层，设置于像素定义层上，且电极层至少用于形成位于开口区内的阳极，以及用于形成位于非开口区内的辅助电极；以及阴极层，设置于像素定义层与辅助电极上，并与辅助电极并联。

Description

显示面板及其制作方法、显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板及其制作方法、及具有该显示面板的显示装置。
 背景技术
有机发光二极管(Organic Light-Emitting Diode，OLED)显示面板因具有超越液晶显示器(Liquid Crystal Display，LCD)的显示特性与品质，例如：轻薄化、短的反应时间、低的驱动电压、更好的显示色彩以及显示视角等优点，受到大家广泛的关注，近些年其发展日新月异，不仅可以制作曲面显示，同时也逐渐向大尺寸发展。
目前，对于顶发射OLED器件，由于要兼顾透过率，透明面阴极一般做得较薄，导致其导电能力较差。在屏幕尺寸较大时，在屏幕中心的发光点，由于离电极接口较远，长距离的电流传输使其驱动电压上升较大。造成屏幕内边缘靠近电极接口区域与屏幕中心区域驱动电压差距过大，有电压降(IR drop)的问题产生，进而使得显示面板的周边亮度较亮，而中间显示较暗，导致显示不均。
 技术问题
本申请实施例提供一种显示面板及其制作方法、显示装置，能够解决OLED显示面板由于阴极层容易产生电压降的现象，进而导致显示面板显示不均的技术问题。
 技术解决方案
本申请实施例提供一种显示面板，其包括：
像素定义层，包括多个开口区以及围绕各所述开口区的非开口区；
电极层，设置于所述像素定义层上，且所述电极层至少用于形成位于所述开口区内的阳极，以及用于形成位于所述非开口区内的辅助电极；以及
阴极层，设置于所述像素定义层与所述辅助电极上，并与所述辅助电极并联。
在本申请的一种实施例中，所述像素定义层还包括设置于所述非开口区内的挡墙结构，所述辅助电极设置于所述挡墙结构上，所述阴极层连续地覆盖所述像素定义层，并与所述辅助电极搭接。
在本申请的一种实施例中，所述显示面板还包括设置于所述挡墙结构与所述辅助电极上的间隔部，所述间隔部包括至少一开孔，所述阴极层覆盖所述间隔部，并通过至少一所述开孔与所述辅助电极搭接。
在本申请的一种实施例中，所述挡墙结构朝向所述阴极层的一侧形成有槽体，所述辅助电极位于所述槽体内，所述阴极层覆盖于所述挡墙结构以及所述辅助电极上。
在本申请的一种实施例中，所述槽体的深度等于所述辅助电极的厚度。
在本申请的一种实施例中，所述辅助电极在所述像素定义层上的正投影位于所述阳极在所述像素定义层上的正投影的覆盖范围之外。
在本申请的一种实施例中，所述显示面板包括多个所述辅助电极，且每一所述辅助电极对应至少一所述开口区设置，且每一所述辅助电极与其对应的至少一所述开口区相邻设置。
在本申请的一种实施例中，所述显示面板包括显示区以及围绕所述显示区的非显示区，且多个所述辅助电极的分布密度由所述非显示区指向所述显示区的方向递增。
根据本申请的上述目的，提供一种显示面板的制作方法，其包括以下步骤：
形成像素定义层，且所述像素定义层包括多个开口区以及围绕各所述开口区的非开口区；
形成电极层于所述像素定义层上，且所述电极层包括形成于所述开口区内的阳极，以及形成于所述非开口区内的辅助电极；以及
形成阴极层于所述像素定义层与所述辅助电极上，且所述阴极层与所述辅助电极并联。
根据本申请的上述目的，提供一种显示装置，所述显示装置包括显示面板，所述显示面板包括：
像素定义层，包括多个开口区以及围绕各所述开口区的非开口区；
电极层，设置于所述像素定义层上，且所述电极层至少用于形成位于所述开口区内的阳极，以及用于形成位于所述非开口区内的辅助电极；以及
阴极层，设置于所述像素定义层与所述辅助电极上，并与所述辅助电极并联。
在本申请的一种实施例中，所述像素定义层还包括设置于所述非开口区内的挡墙结构，所述辅助电极设置于所述挡墙结构上，所述阴极层连续地覆盖所述像素定义层，并与所述辅助电极搭接。
在本申请的一种实施例中，所述显示面板还包括设置于所述挡墙结构与所述辅助电极上的间隔部，所述间隔部包括至少一开孔，所述阴极层覆盖所述间隔部，并通过至少一所述开孔与所述辅助电极搭接。
在本申请的一种实施例中，所述挡墙结构朝向所述阴极层的一侧形成有槽体，所述辅助电极位于所述槽体内，所述阴极层覆盖于所述挡墙结构以及所述辅助电极上。
在本申请的一种实施例中，所述槽体的深度等于所述辅助电极的厚度。
在本申请的一种实施例中，所述辅助电极在所述像素定义层上的正投影位于所述阳极在所述像素定义层上的正投影的覆盖范围之外。
在本申请的一种实施例中，所述显示面板包括多个所述辅助电极，且每一所述辅助电极对应至少一所述开口区设置，每一所述辅助电极与其对应的至少一所述开口区相邻设置。
在本申请的一种实施例中，所述显示面板包括显示区以及围绕所述显示区的非显示区，且多个所述辅助电极的分布密度由所述非显示区指向所述显示区的方向递增。
 有益效果
相较于现有技术，本申请通过在非开口区设置辅助电极与阴极层搭接，进而可以有效地降低阴极层的面电阻，可以改善显示面板的电压降现象，进而提高了显示面板的显示均一性，提高了显示面板的显示效果。此外，辅助电极与阳极在同一制程中形成，进而可以缩减工艺工序，节省工艺成本。
 附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1为本申请实施例提供的一种显示面板的结构示意图；
图2为本申请实施例提供的显示面板的制作方法流程图；
图3为本申请实施例提供的另一种显示面板的结构示意图；
图4为本申请实施例提供的另一种显示面板的结构示意图；
图5为本申请实施例提供的一种像素定义层的平面分布结构示意图；
图6为本申请实施例提供的另一种像素定义层的平面分布结构示意图；
图7A至图7E为本申请实施例提供的显示面板的制作流程结构示意图；
图8为本申请实施例提供的一种辅助电极的平面分布结构示意图；
图9为本申请实施例提供的另一种辅助电极的平面分布结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
下文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本申请。此外，本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本申请提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
目前，对于顶发射OLED器件，由于要兼顾透过率，透明面阴极一般做得较薄，导致其导电能力较差。在屏幕尺寸较大时，在屏幕中心的发光点，由于离电极接口较远，长距离的电流传输使其驱动电压上升较大。造成屏幕内边缘靠近电极接口区域与屏幕中心区域驱动电压差距过大，有电压降(IR drop)的问题产生，进而使得显示面板的周边亮度较亮，而中间显示较暗，导致显示不均。
为解决上述技术问题，本申请实施例提供一种显示面板，请参照图1，所述显示面板包括像素定义层10、阴极层21以及电极层，其中，像素定义层10包括多个开口区A以及围绕各开口区A的非开口区B。
电极层设置于像素定义层10上，且电极层至少用于形成位于开口区A内的阳极22，以及用于形成位于非开口区B内的辅助电极30。
阴极层21设置于像素定义层10与辅助电极30上，且阴极层21与辅助电极30并联。
在实施应用过程中，本申请实施例通过在像素定义层10的非开口区B内设置辅助电极30，且辅助电极30与阴极层21并联，可以有效地降低阴极层21的电阻，可以改善显示面板的电压降现象，进而可以提高显示面板的显示均一性。辅助电极30设置于非开口区B内，进而不会影响占用开口区A的面积和空间，提高了显示面板的开口率，进一步地提高了显示面板的显示效果。此外，辅助电极30与阳极22在同一制程中形成，进而可以缩减工艺工序，节省工艺成本。
进一步地，请继续参照图1，显示面板包括基板40、设置于基板40上的薄膜晶体管阵列层50、设置于薄膜晶体管阵列层50上的层间绝缘层60、设置于层间绝缘层60上的平坦层70以及设置于平坦层70上的像素定义层10。
可选的，基板40可为玻璃刚性基板，或柔性基板，且柔性基板的材料包括有机树脂材料，在此不作限定。
薄膜晶体管阵列层50包括阵列分布的薄膜晶体管器件以及包覆薄膜晶体管器件的间隔层，且层间绝缘层60覆盖于薄膜晶体管阵列层50上，以进一步覆盖薄膜晶体管器件。平坦层70覆盖于层间绝缘层60上，且平坦层70背向层间绝缘层60的一侧为平坦的表面，以减小膜层段差，提高制程良率。
像素定义层10包括多个开口区A以及围绕开口区A的非开口区B，进一步地，像素定义层10包括挡墙结构11，且挡墙结构11限定出多个开口区A并位于非开口区B内。其中，开口区A为贯穿像素定义层10的开口所形成。
显示面板还包括设置于像素定义层10上的电极层，且电极层至少用于形成位于开口区A内的阳极22，以及用于形成位于非开口区B内的辅助电极30，即阳极22与辅助电极30在同一制程中形成于像素定义层10上。
此外，显示面板还包括设置于开口区A内且位于阳极22上的有机发光层23，其中，阳极22通过贯穿平坦层70以及层间绝缘层60的过孔与薄膜晶体管阵列层中的薄膜晶体管器件电性连接，以实现电信号的传输。
显示面板还包括连续地覆盖于像素定义层10上的阴极层21，阴极层21连续地覆盖多个开口区A以及非开口区B，且阴极层21覆盖于有机发光层23的上表面，以与有机发光层23搭接，且阴极层21为整面形成于像素定义层10上，阴极层21的边缘区域连接于信号端子，通过信号端子输出电信号，与阳极22相配合，在有机发光层23两侧施加电压，以实现有机发光层23的发光功能。
在本申请实施例中，辅助电极30与阴极层21并联，进而可以降低阴极层21的电阻，可以有效地改善显示面板的电压降现象，提高显示面板的显示均一性。
进一步地，辅助电极30设置于挡墙结构11上，且阴极层21连续地覆盖有机发光层23、挡墙结构11以及辅助电极30，以实现与辅助电极30搭接，且辅助电极30可通过信号走线与信号端子相连接，以实现与阴极层21并联。且信号走线在像素定义层10上的正投影位于非开口区B内，进而可以提高显示面板的开口率，提高显示面板的显示效果。
辅助电极30在像素定义层10上的正投影位于阳极22在像素定义层10上的正投影的覆盖范围之外，以避免辅助电极30与阳极22之间产生寄生电容，提高显示面板的显示效果。
另外，本申请实施例还提供一种上述实施例所述的显示面板的制作方法，请参照图2，该制作方法包括以下步骤：
S10、形成像素定义层10，且像素定义层10包括多个开口区A以及围绕各开口区A的非开口区B。
S20、形成电极层于像素定义层10上，且电极层包括形成于开口区A内的阳极22，以及形成于非开口区B内的辅助电极30。
S30、形成阴极层21于像素定义层10与辅助电极30上，且阴极层21与辅助电极30并联。
在本申请实施例中，辅助电极30的材料与阳极22的材料相同，可选的，辅助电极30与阳极22均可为ITO/Ag/ITO的层叠结构。
进一步地，辅助电极30与阳极22在同一道制程中形成，进而在降低阴极层21电阻的基础上，还可以缩减工艺制程，节省工艺时间以及成本。
在本申请的一种实施例中，请参照图1，显示面板包括基板40、设置于基板40上的薄膜晶体管阵列层50、设置于薄膜晶体管阵列层50上的层间绝缘层60、设置于层间绝缘层60上的平坦层70以及设置于平坦层70上的像素定义层10。
像素定义层10包括多个开口区A以及围绕开口区A的非开口区B，且像素定义层10包括挡墙结构11，挡墙结构11限定出多个开口区A并位于非开口区B内。
显示面板还包括设置于像素定义层10上的电极层，且电极层至少用于形成位于开口区A内的阳极22，以及用于形成位于非开口区B内的辅助电极30，即阳极22与辅助电极30在同一制程中形成于像素定义层10上。此外，显示面板还包括设置于开口区A内且位于阳极22上的有机发光层23。其中，辅助电极30设置于挡墙结构11的上表面，并突出于挡墙结构11的上表面。
显示面板还包括连续地覆盖有机发光层23、挡墙结构11以及辅助电极30的阴极层21，且阴极层21覆盖辅助电极30以实现与辅助电极30搭接。
在本实施例中，显示面板的制作方法包括：
提供基板40，基板40包括玻璃刚性基板或柔性基板，且柔性基板的材料包括有机树脂材料。
制备薄膜晶体管阵列层50于基板40上，且薄膜晶体管阵列层50包括薄膜晶体管器件以及包覆薄膜晶体管器件的间隔层。
制备层间绝缘层60于薄膜晶体管阵列层50上，以进一步地覆盖薄膜晶体管器件。
制备平坦层70于层间绝缘层60上，且平坦层70背向层间绝缘层60的一侧为平坦的表面。
制备像素定义层10于平坦层70上，像素定义层10包括挡墙结构11，挡墙结构11限定出多个开口区A，且挡墙结构11位于非开口区B内，非开口区B围绕开口区A设置。可选的，挡墙结构11的材料包括有机光阻材料。
通过黄光、干刻、光阻剥离等制程形成贯穿平坦层70以及层间绝缘层60的过孔。
制备金属层于像素定义层10上，并通过黄光、蚀刻等工艺对金属层进行图案化处理，以形成图案化的电极层，且电极层包括形成位于开口区A内的阳极22，以及位于非开口区B内的辅助电极30。可选的，金属层包括ITO/Ag/ITO的层叠结构。其中，阳极22通过过孔与薄膜晶体管阵列层50中的薄膜晶体管器件电性连接。
制备有机发光层23于开口区A内，且有机发光层23位于阳极22上。
制备阴极层21于像素定义层10上，且阴极层21连续地覆盖有机发光层23、挡墙结构11以及辅助电极30，并与辅助电极30搭接，以实现阴极层21与辅助电极30并联。
在本申请的另一种实施例中，请参照图3，显示面板包括基板40、设置于基板40上的薄膜晶体管阵列层50、设置于薄膜晶体管阵列层50上的层间绝缘层60、设置于层间绝缘层60上的平坦层70以及设置于平坦层70上的像素定义层10。
像素定义层10包括多个开口区A以及围绕开口区A的非开口区B，且像素定义层10包括挡墙结构11，挡墙结构11限定出多个开口区A并位于非开口区B内。
显示面板还包括设置于像素定义层10上的电极层，且电极层至少用于形成位于开口区A内的阳极22，以及用于形成位于非开口区B内的辅助电极30，即阳极22与辅助电极30在同一制程中形成于像素定义层10上。此外，显示面板还包括设置于开口区A内且位于阳极22上的有机发光层23。其中，辅助电极30设置于挡墙结构11上。
显示面板还包括连续地覆盖有机发光层23、挡墙结构11以及辅助电极30的阴极层21，且阴极层21覆盖辅助电极30以实现与辅助电极30搭接。
在本实施例中，挡墙结构11朝向阴极层21的一侧设置槽体101，且辅助电极30设置于槽体101内。
优选的，槽体101的深度等于辅助电极30的厚度。以减小膜层段差，提高制程良品率。
在本实施例中，显示面板的制作方法包括：
提供基板40，基板40包括玻璃刚性基板或柔性基板，且柔性基板的材料包括有机树脂材料。
制备薄膜晶体管阵列层50于基板40上，且薄膜晶体管阵列层50包括薄膜晶体管器件以及包覆薄膜晶体管器件的间隔层。
制备层间绝缘层60于薄膜晶体管阵列层50上，以进一步地覆盖薄膜晶体管器件。
制备平坦层70于层间绝缘层60上，且平坦层70背向层间绝缘层60的一侧为平坦的表面。
制备像素定义层10于平坦层70上，像素定义层10包括挡墙结构11，挡墙结构11限定出多个开口区A，且挡墙结构11位于非开口区B内，非开口区B围绕开口区A设置。可选的，挡墙结构11的材料包括有机光阻材料。
通过黄光、干刻、光阻剥离等制程形成贯穿平坦层70以及层间绝缘层60的过孔。
于挡墙结构11背向平坦层70的一侧形成槽体101。
制备金属层于像素定义层10上，并通过黄光、蚀刻等工艺对金属层进行图案化处理，以形成图案化的电极层，且电极层包括形成位于开口区A内的阳极22，以及位于槽体101内的辅助电极30。可选的，金属层包括ITO/Ag/ITO的层叠结构。其中，阳极22通过过孔与薄膜晶体管阵列层50中的薄膜晶体管器件电性连接。
制备有机发光层23于开口区A内，且有机发光层23位于阳极22上。
制备阴极层21于像素定义层10上，且阴极层21连续地覆盖有机发光层23、挡墙结构11以及辅助电极30，并与辅助电极30搭接，以实现阴极层21与辅助电极30并联。
在本申请的另一种实施例中，请参照图4，显示面板包括基板40、设置于基板40上的薄膜晶体管阵列层50、设置于薄膜晶体管阵列层50上的层间绝缘层60、设置于层间绝缘层60上的平坦层70以及设置于平坦层70上的像素定义层10。
像素定义层10包括多个开口区A以及围绕开口区A的非开口区B，且像素定义层10包括挡墙结构11，挡墙结构11限定出多个开口区A并位于非开口区B内。
显示面板还包括设置于像素定义层10上的电极层，且电极层至少用于形成位于开口区A内的阳极22，以及用于形成位于非开口区B内的辅助电极30，即阳极22与辅助电极30在同一制程中形成于像素定义层10上。此外，显示面板还包括设置于开口区A内且位于阳极22上的有机发光层23。其中，辅助电极30设置于挡墙结构11上。
在本实施例中，显示面板还设置于挡墙结构11与辅助电极30上的间隔部12，且间隔部12形成有至少一开孔，以暴露辅助电极30的部分上表面。
显示面板还包括连续地覆盖有机发光层23、挡墙结构11以及间隔部12的阴极层21，且阴极层21通过至少一开孔与辅助电极30搭接。
可选的，请参照图5，至少一开孔包括两个通孔31，且两个通孔31位于辅助电极30的两端，在本实施例中，通孔31的形状不作限定，本实施例中以圆形为例，进行说明。
可选的，请参照图6，至少一开孔包括一条形孔32，且条形孔32沿辅助电极30的延伸方向进行排布，以实现辅助电极30与阴极层21具有最大的接触面积。
另外，请参照图4、图7A、图7B、图7C、图7D以及图7E，在本实施例中，显示面板的制作方法包括：
提供基板40，基板40包括玻璃刚性基板或柔性基板，且柔性基板的材料包括有机树脂材料。
制备薄膜晶体管阵列层50于基板40上，且薄膜晶体管阵列层50包括薄膜晶体管器件以及包覆薄膜晶体管器件的间隔层。
制备层间绝缘层60于薄膜晶体管阵列层50上，以进一步地覆盖薄膜晶体管器件。
制备平坦层70于层间绝缘层60上，且平坦层70背向层间绝缘层60的一侧为平坦的表面。
制备像素定义层10于平坦层70上，像素定义层10包括挡墙结构11，挡墙结构11限定出多个开口区A，且挡墙结构11位于非开口区B内，非开口区B围绕开口区A设置。
通过黄光、干刻、光阻剥离等制程形成贯穿平坦层70以及层间绝缘层60的过孔。
制备金属层于像素定义层10上，并通过黄光、蚀刻等工艺对金属层进行图案化处理，以形成图案化的电极层，电极层包括形成位于开口区A内的阳极22，以及位于非开口区B内的辅助电极30。辅助电极30位于挡墙结构11上表面，可选的，金属层包括ITO/Ag/ITO的层叠结构。其中，阳极22通过过孔与薄膜晶体管阵列层50中的薄膜晶体管器件电性连接。
制备间隔部12于挡墙结构11上，且间隔部12覆盖辅助电极30。可选的，间隔部12的材料与挡墙结构11的材料相同，可为有机光阻材料。
于间隔部12背向挡墙结构11的一侧开设至少一开孔，且至少一开孔暴露辅助电极30的部分上表面。
制备有机发光层23于开口区A内，且有机发光层23位于阳极22上。
制备阴极层21于像素定义层10上，且阴极层21连续地覆盖有机发光层23、挡墙结构11以及间隔部12，阴极层21通过至少一开孔与辅助电极30搭接，以实现阴极层21与辅助电极30并联。
承上，本申请实施例通过在像素定义层10的非开口区B内设置辅助电极30，且辅助电极30与阴极层21并联，可以有效地降低阴极层21的电阻，可以改善显示面板的电压降现象，进而可以提高显示面板的显示均一性。辅助电极30设置于非开口区B内，进而不会影响占用开口区A的面积和空间，提高了显示面板的开口率，进一步地提高了显示面板的显示效果。此外，辅助电极30与阳极22在同一制程中形成，进而可以缩减工艺工序，节省工艺成本。
在本申请实施例中，显示面板包括多个辅助电极30，且每一辅助电极30对应至少一开口区A设置，且每一辅助电极30与其对应的至少一开口区A相邻设置。
可选的，请参照图5以及图6，多个辅助电极30与多个开口区A一一对应设置，以对应每个开口区A均设置一个辅助电极30与其相邻，即针对每个像素均设置一辅助电极30与阴极层21并联，以有效地降低阴极层21的电阻，改善电压降现象，提高显示面板的显示均一性。
可选的，每多个开口区A对应设置一个辅助电极30，具体地，可2个开口区A对应设置一个辅助电极30，且辅助电极30位于两个开口区A之间；可3个开口区A对应设置一个辅助电极30，且辅助电极30与位于中间一个开口区A相邻设置。且每个辅助电极30对应的开口区A的数量不作限定。
可选的，请参照图8，显示面板包括显示区C以及围绕显示区C的非显示区D，且多个辅助电极30均匀分布于显示区C内。
可选的，请参照图9，显示面板包括显示区C以及围绕显示区C的非显示区D，在沿非显示区D指向显示区C的方向上，多个辅助电极30的分布密度递增。
进一步地，多个辅助电极30的分布情况，还可以为阴极层21的电阻较大处的辅助电极30的分布密度大于阴极层21的电阻较小处的辅助电极30的分布密度，在此不作限定。
另外，本申请实施例还提供一种显示装置，该显示装置包括上述实施例所述的显示面板，其结构以及制作方法均与上述实施例中相同，在此不再赘述。
显示装置包括智能手环、智能手表、虚拟现实（Virtual Reality，VR）等可穿戴设备；显示装置还包括移动电话机、电子书、电子报纸、电视机、个人便携电脑、可折叠以及可卷曲OLED等柔性显示及照明设备。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例所提供的一种显示面板及其制作方法、显示装置进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (17)

  1. 一种显示面板，其包括：
    像素定义层，包括多个开口区以及围绕各所述开口区的非开口区；
    电极层，设置于所述像素定义层上，且所述电极层至少用于形成位于所述开口区内的阳极，以及用于形成位于所述非开口区内的辅助电极；以及
    阴极层，设置于所述像素定义层与所述辅助电极上，并与所述辅助电极并联。
  2. 根据权利要求1所述的显示面板，其中，所述像素定义层还包括设置于所述非开口区内的挡墙结构，所述辅助电极设置于所述挡墙结构上，所述阴极层连续地覆盖所述像素定义层，并与所述辅助电极搭接。
  3. 根据权利要求2所述的显示面板，其中，所述显示面板还包括设置于所述挡墙结构与所述辅助电极上的间隔部，所述间隔部包括至少一开孔，所述阴极层覆盖所述间隔部，并通过至少一所述开孔与所述辅助电极搭接。
  4. 根据权利要求2所述的显示面板，其中，所述挡墙结构朝向所述阴极层的一侧形成有槽体，所述辅助电极位于所述槽体内，所述阴极层覆盖于所述挡墙结构以及所述辅助电极上。
  5. 根据权利要求4所述的显示面板，其中，所述槽体的深度等于所述辅助电极的厚度。
  6. 根据权利要求1所述的显示面板，其中，所述辅助电极在所述像素定义层上的正投影位于所述阳极在所述像素定义层上的正投影的覆盖范围之外。
  7. 根据权利要求1所述的显示面板，其中，所述显示面板包括多个所述辅助电极，且每一所述辅助电极对应至少一所述开口区设置，每一所述辅助电极与其对应的至少一所述开口区相邻设置。
  8. 根据权利要求7所述的显示面板，其中，所述显示面板包括显示区以及围绕所述显示区的非显示区，且多个所述辅助电极的分布密度由所述非显示区指向所述显示区的方向递增。
  9. 一种显示面板的制作方法，其包括以下步骤：
    形成像素定义层，且所述像素定义层包括多个开口区以及围绕各所述开口区的非开口区；
    形成电极层于所述像素定义层上，且所述电极层包括形成于所述开口区内的阳极，以及形成于所述非开口区内的辅助电极；以及
    形成阴极层于所述像素定义层与所述辅助电极上，且所述阴极层与所述辅助电极并联。
  10. 一种显示装置，所述显示装置包括显示面板，所述显示面板包括：
    像素定义层，包括多个开口区以及围绕各所述开口区的非开口区；
    电极层，设置于所述像素定义层上，且所述电极层至少用于形成位于所述开口区内的阳极，以及用于形成位于所述非开口区内的辅助电极；以及
    阴极层，设置于所述像素定义层与所述辅助电极上，并与所述辅助电极并联。
  11. 根据权利要求10所述的显示装置，其中，所述像素定义层还包括设置于所述非开口区内的挡墙结构，所述辅助电极设置于所述挡墙结构上，所述阴极层连续地覆盖所述像素定义层，并与所述辅助电极搭接。
  12. 根据权利要求11所述的显示装置，其中，所述显示面板还包括设置于所述挡墙结构与所述辅助电极上的间隔部，所述间隔部包括至少一开孔，所述阴极层覆盖所述间隔部，并通过至少一所述开孔与所述辅助电极搭接。
  13. 根据权利要求11所述的显示装置，其中，所述挡墙结构朝向所述阴极层的一侧形成有槽体，所述辅助电极位于所述槽体内，所述阴极层覆盖于所述挡墙结构以及所述辅助电极上。
  14. 根据权利要求13所述的显示装置，其中，所述槽体的深度等于所述辅助电极的厚度。
  15. 根据权利要求10所述的显示装置，其中，所述辅助电极在所述像素定义层上的正投影位于所述阳极在所述像素定义层上的正投影的覆盖范围之外。
  16. 根据权利要求10所述的显示装置，其中，所述显示面板包括多个所述辅助电极，且每一所述辅助电极对应至少一所述开口区设置，每一所述辅助电极与其对应的至少一所述开口区相邻设置。
  17. 根据权利要求16所述的显示装置，其中，所述显示面板包括显示区以及围绕所述显示区的非显示区，且多个所述辅助电极的分布密度由所述非显示区指向所述显示区的方向递增。
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CN114188495A (zh) * 2021-12-10 2022-03-15 惠州华星光电显示有限公司 显示面板及其制备方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107565048A (zh) * 2017-08-24 2018-01-09 京东方科技集团股份有限公司 一种阵列基板的制备方法、阵列基板和显示装置
US20180233703A1 (en) * 2015-10-13 2018-08-16 Samsung Display Co., Ltd. Organic light emitting display panel and method of manufacturing the same
CN112164757A (zh) * 2020-09-24 2021-01-01 深圳市华星光电半导体显示技术有限公司 显示面板及其制作方法
CN113270558A (zh) * 2021-05-13 2021-08-17 Tcl华星光电技术有限公司 显示面板及其制作方法、显示装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007157662A (ja) * 2005-12-08 2007-06-21 Seiko Epson Corp 有機発光装置の製造方法、有機発光装置および電子機器
CN106992204B (zh) * 2017-04-25 2019-12-20 京东方科技集团股份有限公司 一种oled阵列基板及其制备方法、显示装置
KR20230117645A (ko) * 2017-04-26 2023-08-08 오티아이 루미오닉스 인크. 표면의 코팅을 패턴화하는 방법 및 패턴화된 코팅을포함하는 장치
CN108649060B (zh) * 2018-05-16 2020-06-05 京东方科技集团股份有限公司 Oled器件及其制备方法、显示装置
CN110168736A (zh) * 2019-03-29 2019-08-23 京东方科技集团股份有限公司 发光基板及其制作方法、电子装置
CN110212007A (zh) * 2019-06-21 2019-09-06 京东方科技集团股份有限公司 显示基板、显示装置以及制作显示基板的方法
CN112420943A (zh) * 2020-11-09 2021-02-26 深圳市华星光电半导体显示技术有限公司 显示面板及其制作方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180233703A1 (en) * 2015-10-13 2018-08-16 Samsung Display Co., Ltd. Organic light emitting display panel and method of manufacturing the same
CN107565048A (zh) * 2017-08-24 2018-01-09 京东方科技集团股份有限公司 一种阵列基板的制备方法、阵列基板和显示装置
CN112164757A (zh) * 2020-09-24 2021-01-01 深圳市华星光电半导体显示技术有限公司 显示面板及其制作方法
CN113270558A (zh) * 2021-05-13 2021-08-17 Tcl华星光电技术有限公司 显示面板及其制作方法、显示装置

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